2017 International Siberian Conference on Control and Communications (SIBCON) Broadband Differential 1.5-5 GHz LO Buffer Based On SiGe BiCMOS Technology

A.A. Kokolov, F.I. Sheyerman, L.I. Babak Department of Computer Systems Tomsk State University of Control Systems and Radioelectronics 40, Lenin Ave., Tomsk, Russia, 634050 [email protected]

Abstract— This paper presents the design of the monolithic higher power , low reverse transmission and low input pseudo-differential buffer amplifier based on 0.25 um SiGe capacitance. BiCMOS technology for mixer local oscillator (LO) input. LO In this paper, we report on the analysis, design and buffer amplifier is implemented using pseudo-differential experimental investigation of a SiGe BiCMOS BA for the circuit with voltage parallel feedback circuit. Buffer mixer LO input. The LO BA architecture has been designed amplifier designed for 1.5-5 GHz frequency band and has power using cascode topology with negative feedback circuit and a gain GT = 15 dB with 0.5 dB ripple, 1-dB compression point P1dB is more than 15 dBm, chip size is 1.2×2.1 mm2. pseudo-differential structure. With proposed configuration BA has 1.5-4.5 GHz frequency band with 15 dB power gain GT and Index Terms— MMIC; SiGe; differential amplifier; buffer 1-dB compression point P1dB in one channel more than 15 dBm amplifier; local oscillator; cascode. while consuming voltage and current were VCC = 5 V and IC = 53 mA. The chip is fabricated using the 0.25 um SiGe I. INTRODUCTION BiCMOS process (IHP, Germany). Die area of the LO BA is 2 The design of modern electronic circuits is a compromise 1.2×2.1 mm (including the pads). between technical and economical performances. A broad II. STURUCTURE AND CIRCUIT DESIGN frequency band allows expanding the range of possible applications of the designed circuits. A number of wireless A. Strucutre and requrements for LO BA protocols (mobile communications, wireless Internet, global The overall structure of the mixer with LO BA is illustrated navigation systems, etc.) works in the frequency band up to in the Fig. 1. The BA is located between balun and DBM to 5 GHz. Therefore, design of universal broadband electronic exclude the losses of LO power. It was decided to design the circuits that can overlap several frequency bands becomes differential BA without baluns at the input and output ports actual. because of more simple measurement interpretation and chip Mixer is the key component that defines performance of the size economy. Mixer is the key component that defines performances of the many microwave systems. Passive double balanced mixer (DBM) offers excellent performances in terms of frequency band, port isolation, and intermodulation characteristics. The disadvantages of such mixers are negative conversion gain and high level of the required LO power [1]. One of the common way to overcome the latter problem is the using of the LO buffer amplifier (BA) [2]. This solution has an additional advantage of higher LO isolation from RF and IF ports. Nowadays, modern SiGe technology offers the advantage of being low cost and having a high integration level. However, the main problems are poor RF output power and significant losses in transmission lines and elements. The major factor that Fig. 1. Structure of the mixer with LO BA. limits the output power of the standard SiGe process is the The LO BA requirements are as follows: breakdown voltage. The combination of the • frequency band: 1.5-5 GHz; common-base (CB) and common-emitter (CE) stage • configuration, which is called “cascode”, provides the differential input and output port; • increasing of the breakdown voltage and output power, because power gain GT: 15±1 dB; • the total DC voltage drop on each transistor [3–6]. Also, output power Pout: more than 15 dBm. compared to the standard CE configuration, cascode has a In addition, the each input differential port must be matched to 50 Ohm; output differential ports must be matched 2017 International Siberian Conference on Control and Communications (SIBCON) to the mixer LO . It is reasonable to have a 2-3 The usage of several in parallel may lead to the dB margin in output power Pout to prevent nonlinear stability problems at high frequencies [5]. The reason is the of the LO signal. Besides, BA must be unconditionally stable parasitic inductance, which appears when the parallel transistor in the whole frequency band. are connected with common microstrip line. To prevent the possible unstability the series resistance R (Fig. 2) can be B. Cascode circuit stab introduced. The value of the resistance Rstab should be enough One of the major factor that limits the output power of SiGe to compensate the influence of the parasitic inductance, as technology process is the transistor breakdown voltages. usual Rstab is about 3-10 Ω. Also, the values of bias resistors Because generally the high values of fT and fMAX (and power Rbias1 and Rbias2 were optimized for supply voltage Vcc = 5 V. gain GT) are obtained due to breakdown voltage sacrificing [7]. The used 0.25 um SiGe BiCMOS technology offers three C. Circuit design different types of the HBT NPN transistors: standard, high- As usual, the differential structure in increases performance and high-voltage. Despite the facts that high- the output voltage swing and reduces sensitivity to the parasitic voltage transistors have breakdown voltage VBR > 7 V and effects of the bonding wires and packaging [8]. Unfortunately, high-performance transistors have higher fT =80 GHz, the the tail current source of the differential structure will affect the standard NPN configuration was chosen as a compromise performance of the amplifier, such as gain and efficiency. between power gain and output power density. Therefore, the pseudo-differential structure was chosen for The breakdown voltage VBR for standard NPN transistor is designing the LO BA as presented in Fig. 3. 4 V, which limits the bias voltage VCC to the 2–2.5 V. The cascode, a combination of the CB and CE configurations, as Out+ Out- shown in Fig. 2, allows higher supply voltage VCC in the range of 4-5 V. Moreover, cascode is more unilateral, hence more VCC C6 C9 unconditionally stable than CE device, also it has higher L2 L3 maximum achievable gain GMAX, that allows to design only one-stage amplifier to fulfill the requirements. C7

C5 C10 VB2

R4 T2 T4 R2 R6 C2 C13 R5 C11 R1 C3 C8 R8 T1 T3

L1 L4 R3 R7 C4 C12

VB1

C1 C14 In+ In- Fig. 3. Circuit schematic of the pseudo-differential LO BA.

The input matching networks consist of parallel RC-circuits (R1, C2 and R8, C13) with DC blocking capacitors (C11, C13), Fig. 2. Parallel HBT in the cascode with bias and stabilizing circuits. that stabilize the BA introducing the losses at low frequencies, and parallel LC elements (L1, L4, C1 and C14), that match input Muli-finger NPN HBT transistor configuration is used for of each amplifier to the 50 Ω. The resistors R3, R4 and R7 are both cascode to increase collect current IC. The transistors T1 used for biasing the cascode. and T2 in Fig 2 are built with N = 16 fingers of LE = 3.36 um The broadband cascode cell uses a negative voltage length. The additional boost of the output power can be feedback through series RC-circuit to improve the stability and reached by paralleling 4 transistors as shown in Fig. 2, which to obtain the flat gain in the desired frequency band. The output leads to the increase of the output collector current IC. The matching network consist of shunt inductances L2 and L3, that cascode transistors are biased with total collector current used as a power supply, and series DC blocking capacitors C6 IC = 50 mA (12.5 mA per each HBT) and supply voltage VCC = and C9. 5 V. Differential structure of the LO BA will additionally The models of the passive elements and microstrip lines increases the output power as well as collector current up to provided by the foundry were used for the LO BA performance IC = 100 mA. simulation, except the output inductances. The output 2017 International Siberian Conference on Control and Communications (SIBCON) inductances (L2 and L3) were modeled by the EM simulator software such as Momentum from Keysight Technologies.

III. MEASUREMENT RESULTS The chip microphotograph of the cascode LO BA fabricated on the 0.25 um SiGe BiCMOS technology is shown in Fig. 4. The pseudo-differential LO BA chip occupies the area of 1.2×2.1 mm (2.52 mm2) including the pads.

Fig. 5. Measured and simulated differential S-parameters of the pseudo-differential LO BA.

The measured and simulated Rollett’s stability factor K is illustrated in Fig. 6. The K-factor is greater than 1 in the whole frequency band that means unconditionally stability. The difference between measured and simulated stability factors caused by the inaccuracy of the active and passive PDK models.

Fig. 4. Fabricated pseudo-differential LO BA.

The chip was measured on-wafer using GSGSG probes with pitch 150 um both at the input and at the output ports. Keysight PNA-X network analyzer was used to measure the mixed-mode 4-port S-parameters matrix [9] in the frequency range up to 10 GHz. The supply voltages of the LO BA were VB1=4.1 V and VB2 = VCC = 5 V while total output current was IC = 101 mA. Fig. 5 compares with good agreement the simulated and measured differential S-parameters (the first quadrant of the mixed-mode 4-port S-matrix). The measured input return loss Fig. 6. Measured and simulated differential S-parameters of the pseudo-differential LO BA. (|S11|) is better than -10 dB from 1.5 to 5 GHz. Over this frequency range, output return loss (|S22|) is better than -5.5 dB. The variation of the power gain GT from bias current is The amplifier achieves power gain GT about 15.5 dB with shown in Fig. 7. As it could be seen, the impact of the collector ripple about 0.5 dB from 1 to 5 GHz. current IC on the amplifier gain is not very high, mostly bias The output matching of the LO BA is a compromise point will influence on the output power (Fig. 8). between delivered output power Pout, return losses and The 1-dB compression point P1dB of the pseudo-differential amplifier size. A little difference between measured and LO BA was measured on-wafer using GSGSG probes, DC simulated output return loss |S22| and power gain GT can be probes and Keysight PNA-X network analyzer. Due to caused by the EM modeled output inductances and nonlinear differential structure of the LO BA and lack of broadband HBT models inaccuracy. Although it is not shown in the balun the P1dB measurement were performed only for half of measurement results, reverse isolation (|S12|) is better than the LO BA using the In+ and Out+ ports (Fig. 4). The rest two -41 dB in the whole frequency range due to cascode features. ports (In- and Out-) were terminated by 50 Ω loads. However, due to the common bias circuits, the LO BA will consume as a full amplifier. So, one need to divide the total collector current IC_total by 2, to get current in one channel IC_half. 2017 International Siberian Conference on Control and Communications (SIBCON) technology have been presented in this paper. The BA will be used at mixer differential input LO port to decrease the required LO power. To achieve a higher output power and flat gain the LO BA architecture has been designed using cascode topology with negative voltage feedback circuit and the pseudo-differential structure. Proposed configuration of the LO BA has 1.5–4.5 GHz frequency band with 15 dB power gain GT and 1-dB compression point P1dB more than 15 dBm in one channel while consuming voltage and current were VCC = 5 V and IC = 53 mA. The chip is fabricated using the 0.25 um SiGe BiCMOS process (IHP, Germany). The die area of the LO BA is 1.2×2.1 mm2 including the pads.

ACKNOWLEDGMENT The project was carried out with financial support of Fig. 7. Measured and simulated differential S-parameters Ministry of Education and Science of the Russian Federation. of the pseudo-differential LO BA. The unique project identifier is RFMEFI57715X0179.

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