Empirical CPU Power Modelling and Estimation in the gem5 Simulator Basireddy Karunakar Reddy∗, Matthew J. Walker∗, Domenico Balsamo∗, Stephan Diestelhorsty, Bashir M. Al-Hashimi∗ and Geoff V. Merrett∗ ∗University of Southampton yARM Ltd. Southampton, UK Cambridge, UK fkrb1g15,mw9g09,db2a12,bmah,
[email protected] [email protected] Abstract—Power modelling is important for modern CPUs The bottom-up power models take a CPU specification (e.g. to inform power management approaches and allow design cache size, number of pipelines) and attempt to estimate the space exploration. Power simulators, combined with a full-system power by first estimating the CPU complexity, number of architectural simulator such as gem5, enable power-performance trade-offs to be investigated early in the design of a system components and area and then the amount of switching activity with different configurations (e.g number of cores, cache size, required to perform different tasks. Wattch is a framework for etc.). However, the accuracy of existing power simulators, such architectural-level power simulation. CACTI is a modelling as McPAT, is known to be low due to the abstraction and tool for estimating cache and memory access time, cycle specification errors, and this can lead to incorrect research time, area, leakage, and dynamic power using device models conclusions. In this paper, we present an accurate power model, built from measured data, integrated into gem5 for estimating based on the industry-standard ITRS roadmap. McPAT is an the power consumption of a simulated quad-core ARM Cortex- integrated power, area, and timing modelling framework. In A15. A power modelling methodology based on Performance particular, McPAT has gained popularity due to its ease-of-use Monitoring Counters (PMCs) is used to build and evaluate the and readiness, as it needs a single configuration file with activ- integrated model in gem5.