DOCSLIB.ORG

Accuracy Evaluation of GEM5 Simulator System

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Accuracy Evaluation of GEM5 Simulator System Accuracy Evaluation of GEM5 Simulator System Anastasiia Butko, Rafael Garibotti, Luciano Ost and Gilles Sassatelli LIRMM, CNRS/University of Montpellier II – 161 rue Ada, Cedex05 34095 Montpellier, France {last_name}@lirmm.fr Abstract - Design space exploration (DSE) of complex embedded claim to be fast and flexible. While the simulation speed is systems that combine a number of CPUs, dedicated hardware trivially observed, the claimed level of accuracy of such and software is a tedious task for which a broad range of systems remains often unclear. This paper contributes by approaches exists, from the use of high-level models to hardware evaluating the accuracy of one popular framework, GEM5, prototyping. Each of these entails different simulation when compared to a real hardware platform. speed/accuracy tradeoffs, and thereby enables exploring a certain subset of the design space in a given time. Some simulation frameworks devoted to CPU-centric systems have been developed over the past decade, that either feature near real-time simulation speed or moderate to high speed with quasi-cycle level accuracy, often by means of instruction-set simulators or binary translation techniques. This paper presents an evaluation in term of accuracy in modeling real systems using the GEM5 simulator that belong to the first class. Performance figures of a wide range of benchmarks (e.g. in domains such as scientific computing and media applications) are captured and compared to results obtained on real hardware. Keywords: embedded system, GEM5, modeling and full-system simulation, etc. I. INTRODUCTION Embedded computing systems are found in a wide range of products; they become more and more complex and the main feature are always performance, power consumption and cost. With a large number of existing solutions, developers must decide the best-suited configuration while meeting time-to- Figure 1 – Pyramid of abstraction levels that comprise a system design from market. the specification to a possible optimal solution. Figure extracted from [2]. There exist different approaches to design space This paper is organized as follows. Section II describes exploration. The golden point design is an approach to specify related work on full-system simulation. Section III describes architectures in a very detailed level using hardware GEM5, the chosen simulator. Reference Model, Environment description languages like VHDL or Verilog [1]. This limited configuration and benchmarks are presented in Section IV. abstraction gives high accuracy, but in turn poses severe Section V describes the experiments. Finally, Section VI draws limitations on design space exploration and is also extremely conclusions and gives directions for future work. time consuming. Employed methodologies often lie in higher- level models. II. RELATED WORK Following this direction, there are cycle-accurate models, This section provides an abstract survey of the most abstract executable models and others high-level abstraction popular full-system simulators, according to different criteria: models as shown in Figure 1, which result in faster simulation (i) accuracy, (ii) supported processor architectures, (iii) compared to RTL, at the cost of a loss of accuracy. licensing and (iv) development activity. Furthermore, these models facilitate analysis iterations around various architectural options as well as software execution, Simics is a functionally-accurate full-system simulator that which gives flexibility to explore more features than in a low- enables unmodified target software (e.g. operating system, level abstraction model. applications) to run on the virtual platform similar to the physical hardware [3]. Simics supports a wide range of According to this scenario, to maintain a reasonable processor architectures (e.g. Alpha, ARM, MIPS, PowerPC, balance between simulation time and accuracy, we put focus on SPARC, x86), as well as operating systems (e.g. Linux, full-system simulators, which are software programs that VxWorks, Solaris, FreeBSD, QNX, RTEMS). Simics is simulate hardware, making target software believe that it is composed of an instruction-set simulator, memory- running on physical hardware. Moreover, these simulators management units models, as well as all memories and devices found in the memory map of the processors. Simics has two GEM5 is a modular discrete event driven full-system main disadvantages, it is not claimed to be cycle-accurate and a simulator, under BSD license. This simulator supports different commercial license is required (marketed by Wind River instruction set architectures, such as Alpha, ARM, x86, Systems). SPARC, PowerPC and MIPS [6]. Moreover, this simulator has an active development and support team. PTLsim is a cycle accurate full-system x86 microprocessor simulator that has an out of order pipelined model. PTLsim Table I summarizes the reviewed work according to the also supports modeling of multi-processor or simultaneous four criteria mentioned before. Excluding PTLSim that only multithreading (SMT) machines [4]. PTLsim presents two supports x86, reviewed simulators are composed of several main drawbacks, only x86 architectures are supported and the processor architectures. For instance, OVPsim has the largest tool suite is not actively maintained anymore. number of processor architectures among them, but unfortunately does not target simulation accuracy but rather SimpleScalar is an open source infrastructure for simulation application development, while Simics has a private license. and architectural modeling. It supports several processor Further, SimpleScalar does not provide support or architectures including Alpha, ARM, PowerPC and x86. development anymore. In turn, GEM5 covers all four features, Moreover, it features a large range of CPU models, which justifying our choice. varies from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level To the best of our knowledge there exist no published memory hierarchies [5]. SimpleScalar features were widely material that reports and discusses GEM5 accuracy in terms of improved in the past, but it seems that both development and performance estimation. For instance in [7], authors evaluate support have slowed down significantly, once the last update the accuracy of the M5 full-system simulator for TCP/IP based was more than a year ago at the time of this writing. network-intensive workloads, using only two benchmarks that OVPsim is a dynamic linked library marketed by Imperas, were executed on a single Alpha CPU model. Differing from which simulates complex multiprocessor platforms containing the previous work, this paper evaluates the accuracy of GEM5, arbitrary local and shared-memory topologies [1]. An which combines both M5 [8] and GEMS [9] into one important feature of this simulator is the dynamic binary simulator. Further, several workload belonging to different translation that improves simulation speed. OVPsim domains are employed to stress a dual-core ARM v7 ISA advantages are extensive documentation and excellent support (Cortex-A9), which is widely used in today high-performance for different processor architectures. However, OVPsim does embedded systems. not models cycle-accurate processors but rather instruction accurate processors. TABLE I. RELATED WORKS ON FULL-SYSTEM SIMULATION Development Reference Simulator Accuracy Supported processor architectures License /Support activity WindRiver [3] Simics Functionally-accurate Alpha, ARM, MIPS, PowerPC, SPARC and x86 Private Yes Yourst [4] PTLsim Cycle-accurate x86 Open Yes Austin et al. [5] SimpleScalar Cycle-accurate Alpha, ARM, PowerPC and x86 Open No Open Cores Open RISC, ARM, Synopsys ARC, Imperas [1] OVPsim Instruction-accurate Open and Private Yes MIPS, PowerPC, Xilinx MicroBraze and others Binkert et al. [6] GEM5 Cycle-accurate Alpha, ARM, x86, SPARC, PowerPC and MIPS Open Yes III. GEM5: THE SIMULATION FRAMEWORK A. System Modes This section presents the simulator chosen. GEM5 was Two different system modes are supported in GEM5: (i) created with the best features of two projects, one focused on a system emulation (SE) and (ii) full system (FS) mode. The SE full-system simulator (M5 [8]) and another in memory systems emulates most operating system-level services through stubs on (GEMS [9]). GEM5 simulator provides a flexible, modular the simulation workstation, which include the Operating simulation system that makes it possible exploring System services and devices, resulting in a significant multiprocessor architecture features by offering a diverse set of simulation speedup at the cost of limited support for some CPU models, system execution modes, and memory system functionalities such as multithreading. On the other hand, the models [6]. FS mode performs complete system simulation, including the OS, thread scheduler and devices that runs on both user-level GEM5 is an event-driven simulation framework that has and kernel-level instructions, making the simulation accuracy, different abstraction levels, balancing simulation speed and penalizing the simulation time. accuracy. Furthermore, GEM5 has an open source license, a good object-oriented infrastructure and a very active mailing B. CPU Models list. GEM5 supports four different CPU models: (i) AtomicSimple, (ii) TimingSimple, (iii) In-Order, and (iv) Out- Of-Order (O3), which differ in speed/accuracy trade-offs. IV. EXPERIMENTAL SETUP AtomicSimple is the simplest scalar one cycle-per- instruction/ideal memory model,
Load more

Recommended publications
  • Imperas Tools Overview
    Imperas Tools Overview This document provides an overview of the OVP and Imperas tools environment. Imperas Software Limited Imperas Buildings, North Weston, Thame, Oxfordshire, OX9 2HA, UK [email protected] Author: Imperas Software Limited Version: 2.0.2 Filename: Imperas_Tools_Overview.doc Project: Imperas Tools Overview Last Saved: January 22, 2021 Keywords: Imperas Tools Overview © 2021 Imperas Software Limited www.OVPworld.org Page 1 of 20 Imperas Tools Overview Copyright Notice Copyright © 2021 Imperas Software Limited All rights reserved. This software and documentation contain information that is the property of Imperas Software Limited. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Imperas Software Limited, or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Imperas permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer IMPERAS SOFTWARE LIMITED., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
    [Show full text]
  • Ibex Documentation Release 0.1.Dev50+G873e228.D20211001
    Ibex Documentation Release 0.1.dev50+g873e228.d20211001 lowRISC Oct 01, 2021 CONTENTS 1 Introduction to Ibex 3 1.1 Standards Compliance..........................................3 1.2 Synthesis Targets.............................................4 1.3 Licensing.................................................4 2 Ibex User Guide 5 2.1 System and Tool Requirements.....................................5 2.2 Getting Started with Ibex.........................................6 2.3 Core Integration.............................................6 2.4 Examples.................................................9 3 Ibex Reference Guide 11 3.1 Pipeline Details.............................................. 11 3.2 Instruction Cache............................................. 13 3.3 Instruction Fetch............................................. 17 3.4 Instruction Decode and Execute..................................... 19 3.5 Load-Store Unit............................................. 22 3.6 Register File............................................... 24 3.7 Control and Status Registers....................................... 27 3.8 Performance Counters.......................................... 36 3.9 Exceptions and Interrupts........................................ 38 3.10 Physical Memory Protection (PMP)................................... 41 3.11 Security Features............................................. 42 3.12 Debug Support.............................................. 43 3.13 Tracer................................................... 44 3.14 Verification...............................................
    [Show full text]
  • OVP Debugging Applications with Eclipse User Guide
    OVP Debugging Applications with Eclipse User Guide Imperas Software Limited Imperas Buildings, North Weston, Thame, Oxfordshire, OX9 2HA, UK [email protected] Author: Imperas Software Limited Version: 1.3 Filename: OVPsim_Debugging_Applications_with_Eclipse_User_Guide.doc Project: OVP Debugging Applications with Eclipse User Guide Last Saved: Monday, 13 January 2020 Keywords: © 2020 Imperas Software Limited www.OVPworld.org Page 1 of 39 OVP Debugging Applications with Eclipse User Guide Copyright Notice Copyright © 2020 Imperas Software Limited All rights reserved. This software and documentation contain information that is the property of Imperas Software Limited. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Imperas Software Limited, or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Imperas permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the reader’s responsibility to determine the applicable regulations and to comply with them. Disclaimer IMPERAS SOFTWARE LIMITED, AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
    [Show full text]
  • Gem5, INTEROPERABILITY, and IMPROVING SIMULATOR METHODOLOGY
    gem5, INTEROPERABILITY, AND IMPROVING SIMULATOR METHODOLOGY Jason Lowe-Power [email protected] @jlowepower Outline What is gem5? Recent gem5 features gem5’s future My vision Big news Features coming soon Created at Michigan by students of Steve Reinhardt, principally Nate Binkert. “A tool for simulating systems” 3 4 Created at Michigan by students of Steve Reinhardt, principally Nate Binkert. “A tool for simulating systems” Created at Wisconsin by students of Mark Hill and David Wood. Detailed memory system 5 6 Today today gem5 2011 paper cited over 3000 times 15-20% of ISCA/MICRO/HPCA papers use gem5 Thriving community project Average of 70-ish commits per month About 100 unique contributors over last 2 years 7 Today today Over 400 “models” Over 4000 parameters! 3 timing-based CPU models (simple, in order, out of order) 8 ISAs (ARM, RISC-V, x86, Alpha, Power, SPARC, MIPS, GCN3) 12 memory models (DDR3, DDR4, HBM, HMC, etc.) 42 devices (PCI, Arm platform, x86 platform, storage) AMD GPGPU 12 cache coherence protocols Network on chip (Garnet) 8 Today Programmatic configuration 9 Today Programmatic configuration 10 11 Today today Support for complex ML stacks See https://github.com/KyleRoarty/gem5_docker/ Support for ARM SVE instructions Integration with other simulators DRAMSim2 SST DSENT SystemC McPAT GPGPU-Sim 12 Simulator integration Choose a driver Choose an interface 13 gem5 + SST Multiple implementations SST used as driver for gem5 But two event queues Interface is memory requests Separate setup for each simulator 14 gem5 + SystemC
    [Show full text]
  • Lost in Abstraction: Pitfalls of Analyzing Gpus at the Intermediate Language Level
    2018 IEEE International Symposium on High Performance Computer Architecture Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level Anthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, John Kalamatianos, Onur Kayiran, Michael LeBeane, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, Xianwei Zhang, Akshay Jain†, Timothy G. Rogers† AMD Research, Advanced Micro Devices, Inc. †School of Electrical and Computer Engineering, Purdue University {anthony.gutierrez, brad.beckmann, alexandru.dutu, joe.gross, john.kalamatianos, onur.kayiran, michael.lebeane, matthew.poremba, brandon.potter, sooraj.puthoor, matthew.sinclair, mark.wyse, jieming.yin, xianwei.zhang}@amd.com {jain156, timrogers}@purdue.edu Abstract—Modern GPU frameworks use a two-phase handful of open-source simulators, such as GPGPU-Sim compilation approach. Kernels written in a high-level [11], gem5 [14], and Multi2Sim [35]. language are initially compiled to an implementation- Simulating a GPU is especially challenging because of agnostic intermediate language (IL), then finalized to the two-phase compilation flow typically used to generate the machine ISA only when the target GPU hardware GPU kernel binaries. To maintain portability between dif- is known. Most GPU microarchitecture simulators ferent generations of GPU hardware, GPU kernels are first available to academics execute IL instructions because compiled to an intermediate language (IL). Prior to launch- there is substantially less functional state associated ing a kernel, low-level software, such as the GPU driver or with the instructions, and in some situations, the ma- runtime, finalizes the IL into the machine instruction set chine ISA’s intellectual property may not be publicly architecture (ISA) representation that targets the GPU disclosed.
    [Show full text]
  • Virtualized Hardware Environments for Supporting Digital I&C Verification
    VIRTUALIZED HARDWARE ENVIRONMENTS FOR SUPPORTING DIGITAL I&C VERIFICATION Frederick E. Derenthal IV, Carl R. Elks, Tim Bakker, Mohammadbagher Fotouhi Department of Electrical and Computer Engineering, Virginia Commonwealth University (VCU) 601 West Main Street, Richmond, Virginia 23681 [email protected]; [email protected]; [email protected]; [email protected] ABSTRACT The technology of virtualized hardware testing platforms within the nuclear context in order to provide a framework for evaluating virtualized hardware/software approaches is discussed. To understand the applicability of virtualized hardware approaches, we have developed a virtual hardware model of an actual smart sensor using the Imperas product OVPsim development environment, as is seen in [1]. An evaluation of the modeling effort required to create the digital I&C smart sensor is provided, followed by an analysis and findings on the various tools in the OVPsim environment for supporting testing, evidence collecting, and analysis. The analyzed tools include traditional input/output testing, model-based testing, mutation testing, and fault injection techniques. Finally, the goal of this research effort is to analyze virtual hardware platforms and present findings to the nuclear community on the efficacy and viability of this technology as a complementary means to actual hardware-in-the-loop testing Factory Acceptance Testing for Nuclear Power Plant (NPP) digital I&C systems. Key Words: Virtual Hardware, Virtual Modeling, Verification, Validation 1 INTRODUCTION Much of the instrumentation and control (I&C) equipment in operating U.S. NPPs is based on very mature, primarily analog technology that is steadily trending toward obsolescence. The use of digital I&C systems for plant upgrades, particularly in NPP safety systems, has been slow primarily due to the fact that uncertainties, such as (e.g.
    [Show full text]
  • OVP Guide to Using Processor Models
    OVP Guide to Using Processor Models Model specific information for RISC-V RVB64I Imperas Software Limited Imperas Buildings, North Weston Thame, Oxfordshire, OX9 2HA, U.K. [email protected] Author Imperas Software Limited Version 20210408.0 Filename OVP Model Specific Information riscv RVB64I.pdf Created 5 May 2021 Status OVP Standard Release Imperas OVP Fast Processor Model Documentation for RISC-V RVB64I Copyright Notice Copyright (c) 2021 Imperas Software Limited. All rights reserved. This software and documentation contain information that is the property of Imperas Software Limited. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Imperas Software Limited, or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Imperas permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them. Disclaimer IMPERAS SOFTWARE LIMITED, AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
    [Show full text]
  • Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration Amir Charif, Gabriel Busnot, Rania Mameesh, Tanguy Sassolas, Nicolas Ventroux
    Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration Amir Charif, Gabriel Busnot, Rania Mameesh, Tanguy Sassolas, Nicolas Ventroux To cite this version: Amir Charif, Gabriel Busnot, Rania Mameesh, Tanguy Sassolas, Nicolas Ventroux. Fast Virtual Pro- totyping for Embedded Computing Systems Design and Exploration. RAPIDO2019 - 11th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan 2019, Valence, Spain. pp.1-8, 10.1145/3300189.3300192. hal-02023805 HAL Id: hal-02023805 https://hal.archives-ouvertes.fr/hal-02023805 Submitted on 18 Feb 2019 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Fast Virtual Prototyping for Embedded Computing Systems Design and Exploration Amir Charif, Gabriel Busnot, Rania Mameesh, Tanguy Sassolas and Nicolas Ventroux Computing and Design Environment Laboratory CEA, LIST Gif-sur-Yvette CEDEX, France [email protected] ABSTRACT 2.0 standard [1], which, in addition to offering interoper- Virtual Prototyping has been widely adopted as a cost- ability and reusability of SystemC models, provides several effective solution for early hardware and software co-validation. abstraction levels to cope with varying needs in accuracy and However, as systems grow in complexity and scale, both the speed.
    [Show full text]
  • Imperas Platform User Guide
    Imperas Virtual Platform Documentation for ghs-multi Imperas Guide to using Virtual Platforms Platform / Module Specific Information for renesas.ovpworld.org / ghs-multi Imperas Software Limited Imperas Buildings, North Weston Thame, Oxfordshire, OX9 2HA, U.K. [email protected]. Author Imperas Software Limited Version 20210408.0 Filename Imperas_Platform_User_Guide_ghs-multi.pdf Created 05 May 2021 Status OVP Standard Release Copyright (c) 2021 Imperas Software Limited www.imperas.com OVP License. Release 20210408.0 Page 1 of 14 Imperas Virtual Platform Documentation for ghs-multi Copyright Notice Copyright 2021 Imperas Software Limited. All rights reserved. This software and documentation contain information that is the property of Imperas Software Limited. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Imperas Software Limited, or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Imperas permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them.
    [Show full text]
  • QEMU As a Platform for PLC Virtualization an Analysis from a Cyber Security Perspective
    QEMU as a platform for PLC virtualization An analysis from a cyber security perspective HANNES HOLM, MATS PERSSON FOI Swedish Defence Research Agency Phone: +46 8 555 030 00 www.foi.se FOI-R--4576--SE SE-164 90 Stockholm Fax: +46 8 555 031 00 ISSN 1650-1942 April 2018 Hannes Holm, Mats Persson QEMU as a platform for PLC virtualization An analysis from a cyber security perspective Bild/Cover: Hannes Holm FOI-R--4576--SE Titel QEMU as a platform for PLC virtualization Title Virtualisering av PLC:er med QEMU Rapportnr/Report no FOI-R--4576--SE Månad/Month April Utgivningsår/Year 2018 Antal sidor/Pages 36 ISSN 1650-1942 Kund/Customer MSB Forskningsområde 4. Informationssäkerhet och kommunikation FoT-område Projektnr/Project no E72086 Godkänd av/Approved by Christian Jönsson Ansvarig avdelning Ledningssytem Detta verk är skyddat enligt lagen (1960:729) om upphovsrätt till litterära och konstnärliga verk, vilket bl.a. innebär att citering är tillåten i enlighet med vad som anges i 22 § i nämnd lag. För att använda verket på ett sätt som inte medges direkt av svensk lag krävs särskild överenskommelse. This work is protected by the Swedish Act on Copyright in Literary and Artistic Works (1960:729). Citation is permitted in accordance with article 22 in said act. Any form of use that goes beyond what is permitted by Swedish copyright law, requires the written permission of FOI. FOI-R--4576--SE Sammanfattning IT-säkerhetsutvärderingar är ofta svåra att genomföra inom operativa industriella informations- och styrsystem (ICS) då de medför risk för avbrott, vilket kan få mycket stor konsekvens om tjänsten som ett system realiserar är samhällskritisk.
    [Show full text]
  • OVP Guide to Using Processor Models
    OVP Guide to Using Processor Models Model specific information for RISC-V RV64G Imperas Software Limited Imperas Buildings, North Weston Thame, Oxfordshire, OX9 2HA, U.K. [email protected] Author Imperas Software Limited Version 20210408.0 Filename OVP Model Specific Information riscv RV64G.pdf Created 5 May 2021 Status OVP Standard Release Imperas OVP Fast Processor Model Documentation for RISC-V RV64G Copyright Notice Copyright (c) 2021 Imperas Software Limited. All rights reserved. This software and documentation contain information that is the property of Imperas Software Limited. The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement. No part of the software and documentation may be reproduced, transmitted, or translated, in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without prior written permission of Imperas Software Limited, or as expressly provided by the license agreement. Right to Copy Documentation The license agreement with Imperas permits licensee to make copies of the documentation for its internal use only. Each copy shall include all copyrights, trademarks, service marks, and proprietary rights notices, if any. Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals of other countries contrary to United States law is prohibited. It is the readers responsibility to determine the applicable regulations and to comply with them. Disclaimer IMPERAS SOFTWARE LIMITED, AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
    [Show full text]
  • An OVP Simulator for the Evaluation of Cluster
    MPSoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures Maria Méndez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat, Philipp Wehner, Jens Rettkowski, Diana Göhringer To cite this version: Maria Méndez Real, Vincent Migliore, Vianney Lapotre, Guy Gogniat, Philipp Wehner, et al.. MP- SoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures. 4rd Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), Jul 2016, Samos, Greece. hal-01347188 HAL Id: hal-01347188 https://hal.archives-ouvertes.fr/hal-01347188 Submitted on 26 Feb 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. MPSoCSim extension: An OVP Simulator for the Evaluation of Cluster-based Multicore and Many-core architectures Maria Mendez´ Real, Vincent Migliore, Vianney Lapotre, Philipp Wehner, Jens Rettkowski, Diana Gohringer¨ Guy Gogniat Ruhr-University Bochum, Germany Univ. Bretagne-Sud, UMR 6285, Lab-STICC, fphilipp.wehner, jens.rettkowski, [email protected] F-56100 Lorient, France [email protected] Abstract—In this paper, an extension of the OVP based MPSoC MPSoCSim allows the modeling of heterogeneous MPSoCs simulator MPSoCSim is presented.
    [Show full text]