Sii9687a Port Processor and Sii9617 MHL 2 Bridge with HDMI Receiver

Programmer’s Reference

SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver

Programmer’s Reference

Document # SiI-PR-1078-A SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc.

December 2012

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Further Information To request other materials, documentation, and information, contact your local Silicon Image, Inc. sales office or visit the Silicon Image, Inc. web site at www.siliconimage.com. Revision History Revision Date Comment A 12/2012 First release.

Table of Contents Introduction ...... 1 Register Map ...... 2 Notes and Conventions ...... 3 How to Read a Register Description Table...... 4 Glossary ...... 5 Register Summary Tables ...... 6 SiI9687A/SiI9617 General Control and Status ...... 17 System Registers...... 17 Device Identification Register Group ...... 17 System Reset Register Group ...... 17 Slave Address Selection ...... 19 Slave Address Register Group ...... 19 External Pin Control ...... 20 General Purpose I/O (GPIO) Register Group ...... 20 GPIO Interrupt Configuration Register Group ...... 22 TPWR Pin Control Register Group ...... 24 TMDS Pipe Status ...... 25 TMDS Pipe Status Register Group ...... 25 TMDS Control Register Group ...... 26 Interrupt Control and Status...... 27 Interrupt Control and Group Status Register Group ...... 27 General Interrupt Enable and Status Register Group ...... 29 InstaPort Switch and HDMI Receiver (SiI9687A Only) ...... 30 InstaPort ...... 30 InstaPort Auto Port Control Enable Register Group ...... 30 InstaPort HPE Sequence Timing Control Register Group ...... 32 HDMI Input Port Control ...... 33 InstaPort Viewing Technology ...... 33 Port Control with System Off or in Standby ...... 34 Port Control on Exit from Standby ...... 34 VGA Port Controls ...... 34 Hot Plug Event (HPE) Control Register Group ...... 34 Receiver Termination Value Register Group ...... 38 InstaPort Background Authentication Control Registers ...... 39 TMDS Video Sources ...... 39 Internal Pattern Generator Video Source ...... 39 Input Port Selection Register Group ...... 39 Receiver HDCP Registers...... 40 HDCP Status and Control Register Group ...... 40 HDCP Link Shadow Register Group ...... 43 Receiver InfoFrame Capture ...... 44 Main and Subpipe Packet Extraction Register Group ...... 44 Miscellaneous Audio InfoFrame Register Group ...... 46 Main Pipe Video Input Format ...... 48 Main Pipe Video Input Format Register Group ...... 48 Select Port Video Input Format ...... 49 EDID SRAM Control ...... 51 EDID Read/Write Register Group ...... 51 NVRAM Interface ...... 52 NVRAM Power-up Load Sequence ...... 52 NVRAM Programming Procedure ...... 54 NVRAM Control Register Group ...... 55

Switch/Receiver Interrupt Control and Status ...... 58 Port Status Interrupt Enable and Status Register Group ...... 58 InstaPort Interrupt Enable and Status Register Group ...... 59 Packet Interrupt Enable and Status Register Group ...... 60 InstaPrevue ...... 62 InstaPrevue Basics ...... 62 Supported Video Modes ...... 62 Display Modes ...... 62 All and Active Display Modes ...... 62 Selected Port (PIP) Display Mode ...... 63 InstaPrevue Programming (SiI9687A Only) ...... 63 Preview Window Size and Position ...... 63 Main Video Resolution Changes ...... 63 InstaPrevue Control Register Group ...... 64 InstaPrevue Width and Height Register Group ...... 66 InstaPrevue X/Y Position Register Group ...... 68 InstaPrevue Window Color Register Group ...... 70 InstaPrevue Window Border Control and Color Register Group ...... 71 InstaPrevue Window Animation Control ...... 73 MHL Receiver ...... 75 MHL Sideband Channel ...... 75 MSC Commands Error Codes ...... 76 Remote Control Protocol (RCP) ...... 76 Request Action Protocol (RAP) ...... 76 MHL/CBUS Programming ...... 77 CBUS Control Registers Register Group...... 78 CBUS Protocol Virtual Register Group ...... 81 MHL Discovery Status Register Group ...... 82 MHL Interrupt Enable and Status Register Group ...... 83 Audio Return Channel ...... 84 ARC Control and Status Registers ...... 84 Transmitter Programming Interface ...... 85 Video Pattern Generator ...... 86 Clock Sources ...... 86 Extended Patterns ...... 86 VPG Programming ...... 86 VPG Control Register Group ...... 87 Appendix A – Input Port HDCP DDC-Accessible Registers ...... 89 HDCP DDC Bus Registers ...... 90 Appendix B – NVRAM Boot Data Memory Layout ...... 93 Appendix C – Device Initialization ...... 95 Verifying POR ...... 95 Register Initialization ...... 95 References ...... 98 Standards Documents ...... 98 Silicon Image Documents ...... 98

List of Figures Figure 1. SiI9687A/SiI9617 Functional Block Diagram ...... 1 Figure 2. Reading a Register Description Table ...... 4 Figure 3. GPIO Pad Schematic ...... 21 Figure 4. INT Pulse on Event ...... 27 Figure 5. HPE Control Block Diagram ...... 35 Figure 6. Reading or Writing a Receiver Port SRAM ...... 51 Figure 7. Reading or Writing a Receiver Port SRAM ...... 52 Figure 8. Boot Time NVRAM/EDID SRAM Data Flow ...... 53 Figure 9. Enable InstaPrevue ALL mode ...... 64 Figure 10. Enable InstaPrevue Selected (PIP) mode ...... 64 Figure 11. Disable InstaPrevue Display ...... 64 Figure 12. Relationship between (Speed, Acceleration) and (Distance, Number of Frames) Representations ...... 73 Figure 13. Sending an MHL MSC_MSG Command (RCP Subcommand) ...... 77 Figure 14. Sending an MHL SET_INT Command ...... 77 Figure 15. Sending an MHL SET_HPD Command ...... 77 Figure 16. Sending an MHL WRITE_BURST Command ...... 78 Figure 17. Programming the VPG using the Main Pipe Clock Source ...... 86 Figure 18. Programming the VPG to Generate an Extended Pattern ...... 87

List of Tables Table 1. Register Address Groups ...... 2 Table 2. Control of Primary I2C Address with CI2CA Pin ...... 3 Table 3. Conventions and Usage ...... 3 Table 4. Slave Address 8 Map ...... 19 Table 5. Slave Address 8 Map Example ...... 19 Table 6. GPIO Pin Settings ...... 20 Table 7. Receiver Hot Plug Signal Control Modes ...... 37 Table 8. Receiver Termination Control Modes ...... 37 Table 9. Preview Window Size Example...... 67 Table 10. MHL CBUS Register Sets Accessible by an MHL-capable Peer Device ...... 75 Table 11. MSC Commands ...... 76 Table 12. Video Pattern Generator Clock Sources ...... 86 Table 13. Video Pattern Generator Extended Patterns ...... 86 Table 14. DDC Registers (0x74) ...... 89 Table 15. NVRAM Boot Data Memory Layout ...... 93 Table 16. Register Preinitialization Values...... 96 Table 17. MHL CBUS Register Preinitialization Values ...... 97 Table 18. Referenced Documents ...... 98 Table 19. Standards Groups Contact Information ...... 98 Table 20. Silicon Image Documents ...... 98

vi © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference . Introduction The 9687A device is a four-port HDMI port processor that offers innovative features such as InstaPrevue, InstaPort™ S, support for Mobile High-definition Link (MHL™ 2) technology, and Audio Return Channel (ARC) as described in the HDMI 1.4b Specification. The device supports video resolutions up to 1080p 3D, 60 Hz, 4K x 2K, 30 Hz. It also supports all mandatory and some optional 3D formats up to 300 MHz as described in the HDMI 1.4b Specification. Every input port supports the HDMI 1.4b standard and any one of the input ports can support the MHL™ 2 standard. The 9687A has a single unencrypted HDMI output port that is intended for connection to the TV SoC. The SiI9617 device is an MHL 2 bridge and HDMI receiver with two input ports. Both ports support the HDMI 1.4b standard with HDCP encryption, and any one of the two ports can support the MHL 2 standard. InstaPrevue and InstaPort™ S technologies are not available on this device.

Always - On Section

ARC SPDIF ARC Connect to one of input ports

CBUS Note: MHL input can be assigned to any port during design MHL Control but is hardwired and cannot be selected by software

Serial Ports

DDC 0 DDC DDC 1 DDC 2 NVRAM Booting Sequencer EDID SRAM DDC 3 DDC VGA Configuration, INT HDCP Status, and I2C OTP Local Registers Interrupt Control I2C Registers

Power- Down Section R0X TMDS Rx ( Port0 ) A

C R1X DPLL TMDS Rx Packet ( Port1 ) Analyzer MHL HDCP InstaPrevue Demux Authentication Processing Packet Analyzer

R2X B TMDS Rx ( Port2 ) D DPLL TX HDMI Data Path Video TMDS R3X and HDCP Unmask Mixer Tx TMDS Rx ( Port3 ) MHL Demux

Figure 1. SiI9687A/SiI9617 Functional Block Diagram

In Figure 1 on the previous page, callouts A and B refer to input multiplexers to select one input port. Multiplexer A selects one inactive input for the roving/subpipe, while multiplexer B selects the input for the main pipe. Callouts C and D select either the HDMI block or the MHL-to-HDMI converter. Block C transfers data from the roving pipe while block D transfers data from the main pipe. Note that only the two input ports, R0X and R1X, will be available in the SiI9617 device. This document provides the necessary information to program the SiI9687A/SiI9617 devices.

Register Map The registers in this document are described in groups according to function. Certain registers in each address range are reserved for future use. The reserved registers have no detailed definitions in this document. The registers belong to one of the two power domains as shown in Figure 1 on the previous page. The Always-on section (AON) and the Power-down section (PWD) can have power management and contain most of the registers together. The register descriptions in this document indicate which power section the register belongs to. The registers are accessible through one of the I2C ports on the HDMI receiver, either each of the DDC buses connecting to one source, or the local I2C interface. Table 1 lists the register address groups. Table 1. Register Address Groups I2C Port I2C Device Addr Device Access Address Range Register Purpose I2C Page DDC Local CI2CA = 0 CI2CA = 1 0x00–0x19 0 0xB0 0xB2 — X System Control and Status 0x1A–0x39 0 0xB0 0xB2 — X HDCP Registers 0x70–0x7E 0 0xB0 0xB2 — X Interrupt Registers 0x90–0xA0 0x80–0x89 0 0xB0 0xB2 — X TMDS Termination Control Registers 0x00–0x04 9 0xE0 0xE0 — X EDID Control Registers 0x05–0x31 9 0xE0 0xE0 — X NVRAM Interface Registers 0x40–0x43 9 0xE0 0xE0 — X InstaPort Control Registers1 0x78–0x7D 9 0xE0 0xE0 — X Extra Control and Status Registers 0xD0–0xD1 0xC0–0xCE 9 0xE0 0xE0 — X General Purpose I/O Registers 0xD7–0xE8 9 0xE0 0xE0 — X MHL Control and Status Registers 0xFF 9 0xE0 0xE0 — X Hard Reset Register 0x05–0xFF 12 0xE6 0xE6 — X CBUS Control registers 0x00–0xFF 10 0x64 0x64 — X Receiver TMDS Control 0x00, 0x02 11 0x90 0x90 — X Transmitter TMDS 0xB0–0xB1 11 0x90 0x90 — X ARC Control Registers 0xE0, 0xE5, 0xFF 11 0x90 0x90 — X VPG Control Registers 0x00–0xFF 5 0x50 0x50 — X Preauthentication Page #1 Registers 0x00–0xFF 6 0x52 0x52 — X Preauthentication Page #2 Registers 0x00–0xFF 7 0x54 0x54 — X Preauthentication Page #3 Registers 0x00–0xFF 3 0xFA 0xFA — X InstaPrevue Registers1 0x00–0xFF — 0x74 — X — DDC-Accessible Registers 0x00–0xFF — 0xA0 — X — EDID Accessible Registers Notes: 1. Not applicable to the SiI9617 device.

The local I2C interface registers are accessed through a set of device register pages, each with their own I2C device address. Page 0 is considered the primary device register set and can be configured to respond to one of two fixed addresses, set by the state of the CI2CA pin at reset. The remaining I2C device slave addresses are chosen based on the contents of the slave address configuration registers in the Slave Address Registers section on page 20. The primary I2C device slave address is set according to the state of the CI2CA pin, which is latched on the rising edge of the internal reset signal generated when the device is powered up. Registers in this document with the device address 0xB0 are equivalent to those using the device addresses 0xB2. These settings are fixed and cannot be changed. Table 2. Control of Primary I2C Address with CI2CA Pin CI2CA Pin Device Base Address LOW 0xB0 HIGH 0xB2 Important: Do not write to the SiI9687A/SiI9617 register addresses that are not described in this document unless instructed to do so by your Silicon Image representative. Modifications to undocumented registers can cause unintended errors in the chip function.

Notes and Conventions Table 3. Conventions and Usage Convention Usage Bit N Bits are numbered in little-endian format; the LSB of a byte or word is referred to as Bit 0. 0xNN Hex representation of base-16 numbers are represented using C language notation, preceded by 0x. NNN Binary (base-2) numbers. NN Decimal (base-10) numbers are represented using no additional prefixes or suffixes. R Read only. W Write only. R/W Read and write. R/C Read/Clear: Read, and write 1 to clear. RSVD A bit in a register that is reserved. Reads are indeterminate and writes are ignored. RSVD-W0 A bit in a register that is reserved. Any writes to these bits MUST be written as 0. RSVD-W1 A bit in a register that is reserved. Any writes to these bits MUST be written as 1. Notes: 1. Take special note of the RSVD-Wx conventions. These must be followed for proper operation of the device. 2. This document uses the term Selected Port to indicate the HDMI receiver and transmitter port that is currently selected. 3. The registers in Appendix C – Device Initialization on page 95 must be initialized when the SiI9687A/SiI9617 device is reset either through power-up of the always-on power domain or through a software hard reset. Most registers do not need to be altered during program operation. 4. In addition to these registers, other registers may require modification during the startup and operation of the port processor, depending on the system configuration. 5. By convention, the term set is used to indicate a logic 1 state and the terms clear and cleared are used to indicate a logic 0 state.

How to Read a Register Description Table Every SiI9687A/SiI9617 register description table in this document uses the same general format. Most tables describe only one register, but there are some that describes sets of related registers. Figure 2 shows a typical multi-register description table labeled with numbers in parenthesis that reference further description below. (2)Address:Offset (3)Name (4)Page (5)Type 0xB0:0x71 SHORT_NAME_1 0 AON (6)0xB0:0x75 SHORT_NAME_2 0 AON (7)Bi (9)R (11)Def (8)Bit Label (10)Description t /W ault 7:4 (12)RSVD — Reserved — 3 BIT_LABEL R/W Register description. 0 2:0 RSVD-W0 — Reserved — Figure 2. Reading a Register Description Table

(1) Long name of register or related registers. This name is listed in the Table of Contents. (2) This column lists the I2C address of the device page containing the register and the register offset within the page. Both values are in hexadecimal. (3) This column lists the register name. It is in character/underscore format to allow searching the Silicon Image reference source code for instances of these registers. The actual register name used in the source code adds the prefix ‘REG_ to each register name. This name is listed in numerical order in the Register Summary Table. (4) This column lists the internal device page containing the register. (5) This column lists the power type of the register. The choices are ‘AON’, meaning that the register is in the always on section of the device, and ‘PWD’, meaning the register is in the section of the device that is powered down in standby mode and is therefore unreadable during standby. (6) If there is more than 1 row in the section below the Address:Offset label, this table is a multiple register table. (7) This column indicates the bit or bits in the register bit field described on that row. This value is either a single digit or a range indicated by the [x:y] format, where x is the highest order bit of the range and y is the lowest order bit. The values are typically not larger than 7. If a value larger than 7 is shown in this column, it indicates that a bit field spans more than one register. (8) This column labels each bit field in the register or registers. (9) This column indicates the available access modes for the bit field as shown in Table 3 on page 3. (10) This column gives a long description of the bit field function. (11) This column shows the power-up/reset value for the bit field. A dash indicates an undefined value. (12) This label indicates a reserved bit field can be written as 0, written as 1, or either value; refer to Table 3 on page 3. The read value of a reserved bit field is undefined, although some may have defined power-up/reset values.

Glossary Term Definition AIF Audio InfoFrame AON Always-on Power AVI Auxiliary Video Information CKDT Clock Detect DDC Display Data Channel EDID Extended Display Identification HDCP High-bandwidth Digital Content Protection HPD Hot Plug Detect HPE Hot Plug Event HW Hardware IPV InstaPrevue MHL Mobile High-definition Link MSC MHL Side Band Channel MP Main Pipe/Primary Pipe PA Physical Address PWD Power-down Logic RP Roving Pipe/Subpipe SCDT Sync Detect SW Software TMDS Transition Minimized Differential Signaling TPI Transmitter Programming Interface VPG Video Pattern Generator VSI Vendor Specific InfoFrame

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 5 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Register Summary Tables Ref 0x50: Name 7 6 5 4 3 2 1 0 Page 0x01 59 INT_STATUS_IP1 RSVD-W0 HPE_RP RSVD-W0 HPE_MP RSVD-W0 0x03 60 PA_INTR3 RSVD MP_EVENT_END RSVD 0x05 60 INT_STATUS_IP2 AUTH_CHG_P3 AUTH_CHG_P2 AUTH_CHG_P1 AUTH_CHG_P0 MP_DECRYPT_CHG HDCP_GOOD_CHG RSVD-W0 0x06 61 INT_STATUS_P3 MP_NEW_VSI MP_NEW_AVI MP_NEW_AIF MP_NO_VSI MP_NO_AVI MP_NO_AIF RSVD-W0 0x07 61 INT_STATUS_P4 MP_UNMUTE MP_MUTE RSVD-W0 0x08 60 INT_STATUS_IP3 MP_MUTE_CHG RSVD-W0 MP_RES_STABLE_ RSVD-W0 RSVD-W0 0x09 60 INT_STATUS_IP4 CHG 0x15 59 INT_ENABLE_IP1 RSVD-W0 HPE_RP RSVD-W0 HPE_MP RSVD-W0 0x17 60 PA_INTR3_MASK RSVD MP_EVENT_END RSVD 0x19 60 INT_ENABLE_IP2 AUTH_CHG_P3 AUTH_CHG_P2 AUTH_CHG_P1 AUTH_CHG_P0 MP_DECRYPT_CHG HDCP_GOOD_CHG RSVD-W0 0x1A 61 INT_ENABLE_P3 MP_NEW_VSI MP_NEW_AVI MP_NEW_AIF MP_NO_VSI MP_NO_AVI MP_NO_AIF RSVD-W0 0x1B 61 INT_ENABLE_P4 MP_UNMUTE MP_MUTE RSVD-W0 0x1C 60 INT_ENABLE_IP3 MP_MUTE_CHG RSVD-W0 MP_RES_STABLE_ RSVD-W0 RSVD-W0 0x1D 60 INT_ENABLE_IP4 CHG 0x3A 26 PAUTH_CTRL MP_SWAP RSVD USE_AV_MUTE IGNORE_PA_HPD RSVD SKIP_NON_HDCP PORT_CH_ENABLE 0x3B 40 SELECTED_PORT_0 RP_PORT_BIT MP_PORT_BIT 0x3C 41 PAUTH_STAT1 P3_DECRYPT P2_DECRYPT P1_DECRYPT P0_DECRYPT P3_AUTH P2_AUTH P1_AUTH P0_AUTH 0x50 39 IP_AUTH_PORT_TIME_7_0 AUTH_ PORT_TIME 0x51 39 IP_AUTH_PORT_TIME_15_8 AUTH_ PORT_TIME 0x52 39 IP_AUTH_PORT_TIME_23_16 AUTH_ PORT_TIME 0x53 39 IP_AUTH_PORT_TIME_31_24 AUTH_ PORT_TIME AUDIO_MUTE_SYN VIDEO_MUTE_SYN USE_FRAME_ECC RI_RECOV_EN RSVD RST_ECC_ERR 0x63 26 MISC_CTRL0 C C 0x6F 41 HDCP_CLR RSVD-W0 CLR_BOTH_RI RSVD-W0 PACKET_RD_NO_ PACKET_RD_MASK RSVD RD_PIPE_SEL PACKET_RD_PORT_SEL 0x7C 50 PORT_SEL PWR _DVI RP_HPE_TRIG_OV MP_HPE_TRIG_OV RSVD RP_HPE_TRIG RSVD MP_HPE_TRIG 0x87 31 IP_HPE_TRIGGER R R PHYS_HPD_DIS_P PHYS_HPD_DIS_P PHYS_HPD_DIS_P PHYS_HPD_DIS_P RSVD-W0 RSVD-W1 0x88 30 PHYS_HPD_DISABLE 3 2 1 0 0x89 32 IP_TIMER_GRANULARITY RSVD HPE_TIMER_GRANULARITY 0x8A 32 IP_HPE_HPD_START HPE_HPD_START 0x8B 32 IP_HPE_HPD_END HPE_HPD_END 0x8C 33 IP_HPE_RXTERM_START HPE_RXTERM_START 0x8D 33 IP_HPE_RXTERM_END HPE_RXTERM_END

Ref 0x50: Name 7 6 5 4 3 2 1 0 Page 0x8E 33 IP_HPE_HDCP_DDC_START HPE_HDCP_DDC_START 0x8F 33 IP_HPE_HDCP_DDC_END HPE_HDCP_DDC_END 0x90 33 IP_HPE_EDID_DDC_START HPE_EDID_DDC_START 0x91 33 IP_HPE_EDID_DDC_END HPE_ EDID_DDC_END 0x9F 66 IP_CONFIG_43 BGND_DISABLE RSVD-W1 0xA3 66 IP_CONFIG_47 RSVD-W0 PORT_SELECT 0xCC 50 SP_H_RES_ACTIVEL SP_H_RES_ACTIVE 0xCD 50 SP_H_RES_ACTIVEH SP_H_RES_ACTIVE 0xCE 50 SP_H_RES_BLANKL SP_H_RES_BLANK 0xCF 50 SP_H_RES_BLANKH SP_H_RES_BLANK 0xD0 50 SP_V_RES_ACTIVEL SP_V_RES_ACTIVE 0xD1 50 SP_V_RES_ACTIVEH SP_V_RES_ACTIVE 0xD2 51 SP_V_RES_BLANK SP_V_RES_BLANK MP_GCP_CLEAR_ MP_GCP_SET_MU RSVD MP_RES_STABLE RSVD MP_NEW_GCP RSVD 0xE8 49 MP_GCP_STATUS MUTE TE

Ref 0x52: Name 7 6 5 4 3 2 1 0 Page 0x72 45 MP_AIF_CAPTURE_HEADER MP_AIF_CAPTURE_HEADER 0x73 46 MP_VSI_CAPTURE_HEADER MP_VSI_CAPTURE_HEADER 0xD9 48 MP_H_RES_ACTIVEL MP_H_RES_ACTIVE 0xDA 48 MP_H_RES_ACTIVEH MP_H_RES_ACTIVE 0xDB 48 MP_H_RES_BLANKL MP_H_RES_BLANK 0xDC 48 MP_H_RES_BLANKH MP_H_RES_BLANK 0xDD 48 MP_V_RES_ACTIVEL MP_V_RES_ACTIVE 0xDE 48 MP_V_RES_ACTIVEH MP_V_RES_ACTIVE 0xDF 49 MP_V_RES_BLANK MP_V_RES_BLANK 0xE0 49 MP_VFORMAT MP_VFORMAT RSVD 0xE2 49 MP_COLOR_DEPTH RSVD COLOR_DEPTH

Ref 0x54: Name 7 6 5 4 3 2 1 0 Page 0x20 44 MP_PACKET_BUFFER_CLR RSVD VSI_ID_CHK_EN VSI_ID_SWAP AIF_CLR_EN VSI_CLR_EN 0x21 47 SP_ACP_HEADERL SP_ACP_HEADERL 0x22 47 SP_ACP_HEADERH SP_ACP_HEADERH 0x23 47 SP_ACP_LENGTH SP_ACP_LENGTH 0x24 47 SP_ACP_PB0 SP_ACP_PB0–27

Ref 0x54: Name 7 6 5 4 3 2 1 0 Page 0x40 47 SP_SPD_HEADERL SP_SPD_HEADERL 0x41 47 SP_SPD_HEADERH SP_SPD_HEADERH 0x42 47 SP_SPD_LENGTH SP_SPD_LENGTH 0x43 47 SP_SPD_PB0 SP_SPD_PB0 0x44 47 SP_SPD_PB1 SP_SPD_PB1–27 0x5F 47 SP_ISRC1_HEADERL SP_ISRC1_HEADERL 0x60 47 SP_ISRC1_HEADERH SP_ISRC1_HEADERH 0x61 47 SP_ISRC1_LENGTH SP_ISRC1_LENGTH 0x62 47 SP_ISRC1_PB0 SP_ISRC1_PB0 0x72 48 SP_ISRC2_HEADERL SP_ISRC2_HEADERL 0x73 48 SP_ISRC1_HEADERH SP_ISRC2_HEADERH 0x74 48 SP_ISRC2_LENGTH SP_ISRC2_LENGTH 0x75 48 SP_ISRC2_PB1 SP_ISRC2_PB0 0x90 45 SP_AIF_HEADERL SP_AIF_HEADERL 0x91 45 SP_AIF_HEADERH SP_AIF_HEADERH 0x92 45 SP_AIF_LENGTH SP_AIF_LENGTH 0x93 45 SP_AIF_PB0 SP_AIF_PB0 0xAF 45 SP_AIF_VALID RSVD SP_AIF_VALID 0xB0 45 SP_AVI_HEADERL SP_AVI_HEADERL 0xB1 45 SP_AVI_HEADERH SP_AVI_HEADERH 0xB2 45 SP_AVI_LENGTH SP_AVI_LENGTH 0xB3 45 SP_AVI_PB0 SP_AVI_PB0 0xC1 46 SP_AVI_VALID RSVD SP_AVI_VALID 0xD0 46 SP_VSI_HEADERL SP_VSI_HEADERL 0xD1 46 SP_VSI_HEADERH SP_VSI_HEADERH 0xD2 46 SP_VSI_LENGTH SP_VSI_LENGTH 0xD3 46 SP_VSI_PB0 SP_VSI_PB0 0xEF 46 SP_VSI_VALID RSVD S/MP_VSI_VALID

Ref 0x74: Name 7 6 5 4 3 2 1 0 Page 0x00 90 BKSV1 BKSV 0x01 90 BKSV2 BKSV 0x02 90 BKSV3 BKSV 0x03 90 BKSV4 BKSV 0x04 90 BKSV5 BKSV

Ref 0x74: Name 7 6 5 4 3 2 1 0 Page 0x08 90 RI1 RI 0x09 90 RI2 RI 0x10 90 AKSV1 AKSV 0x11 90 AKSV2 AKSV 0x12 90 AKSV3 AKSV 0x13 90 AKSV4 AKSV 0x14 90 AKSV5 AKSV 0x18 91 AN1 AN 0x19 91 AN2 AN 0x1A 91 AN3 AN 0x1B 91 AN4 AN 0x1C 91 AN5 AN 0x1D 91 AN6 AN 0x1E 91 AN7 AN 0x1F 91 AN8 AN 0x40 91 BCAPS HDMI_C RPTR FIFORDY FAST RSVD 0x41 92 BSTATUS1 DEV_EXC DEV_COUNT 0x42 92 BSTATUS2 RSVD HDMI_MODE CAS_EXC DEV_DEPTH 0x43 92 KSV_FIFO KSV_FIFO 0xFB 89 SI_DEVICE_ID DEV_ID DEV_REV

Ref 0x90: Name 7 6 5 4 3 2 1 0 Page 0x00 85 TMDST_CTRL1 TMDST_OE3 TMDST_OE2 TMDST_OE1 TMDST_OE0 RSVD TMDST_EN 0xB0 84 I2C_ARC_MODE ARC_INT_SET ARC_DRV_EN ARC_DRV_MODE ARC_TERM_CTL 0xB1 84 I2C_ARC_TERM RSVD ARC_TERM_EN 0xE0 87 VPG_CTRL_1 RSVD-W0 VPG_EXT_EN RSVD 0xE5 87 VPG_CTRL_2 VPG_PATTERN RSVD VPG_TMDS_BIST_ VPG_FORMAT VPG_CLK_SEL VPG_EN 0xFF 88 VPG_CTRL_3 EN

Ref 0xB0: Name 7 6 5 4 3 2 1 0 Page 0x00 17 VND_IDL VND_ID 0x01 17 VND_IDH VND_ID 0x02 17 DEV_IDL_RX DEV_ID 0x03 17 DEV_IDH_RX DEV_ID

Ref 0xB0: Name 7 6 5 4 3 2 1 0 Page 0x04 17 DEV_REV MAJOR NUM MINOR NUM AUTO_RESET_ RSVD RSVD INSTAPORT_RESET GLOBAL_RESET 0x05 18 SYS_RESET_1 ENABLE PDD_POWER_ MHL_MODE RSVD RSVD PWR5V RSVD CKDT SCDT 0x06 25 STATE STATUS 0x07 18 SYS_RESET_3 RSVD NO_USE_SCDT RSVD HDCP_RST EN_HDCP_DDC_ EN_HDCP_DDC_ EN_HDCP_DDC_ EN_HDCP_DDC_ RSVD 0x09 36 RX_HDCP_DDC_EN P3 P2 P1 P0 0x0A 39 RX_PORT_SEL RSVD PWD_20MHZ_OSC RSVD DDC_DEL_EN PORT_SEL 0x0B 18 SYS_RESET_2 RSVD MHL_RESET RSVD STANDBY_TERM_ STANDBY_HDCP_ RSVD PWD_WAS_DOWN 0x0C 38 PWD_PORT_CTRL DISABLE DISABLE 0x10 36 RX_HP_CTRL1 HP_CTRL_P3 HP_CTRL_P2 HP_CTRL_P1 HP_CTRL_P0 0x11 20 SLAVE_ADDR6 SLAVE_ADDR_6 0x12 20 SLAVE_ADDR7 SLAVE_ADDR_7 0x13 20 SLAVE_ADDR8 SLAVE_ADDR_8 0x14 20 SLAVE_ADDR5 SLAVE_ADDR_5 0x15 20 SLAVE_ADDR4 SLAVE_ADDR_4 0x16 20 SLAVE_ADDR0 SLAVE_ADDR_0 0x17 20 SLAVE_ADDR1 SLAVE_ADDR_1 0x19 20 SLAVE_ADDR3 SLAVE_ADDR_3 0x1A 43 SHD_BKSV_1_RX HDCP_BKSV 0x1B 43 SHD_BKSV_2_RX HDCP_BKSV 0x1C 43 SHD_BKSV_3_RX HDCP_BKSV 0x1D 43 SHD_BKSV_4_RX HDCP_BKSV 0x1E 43 SHD_BKSV_5_RX HDCP_BKSV 0x1F 43 HDCP_SHD_RI1 HDCP_RI 0x20 43 HDCP_SHD_RI2 HDCP_RI 0x21 43 HDCP_SHD_AKSV1 HDCP_AKSV 0x22 43 HDCP_SHD_AKSV2 HDCP_AKSV 0x23 43 HDCP_SHD_AKSV3 HDCP_AKSV 0x24 43 HDCP_SHD_AKSV4 HDCP_AKSV 0x25 43 HDCP_SHD_AKSV5 HDCP_AKSV 0x26 44 HDCP_SHD_AN1 HDCP_AN 0x27 44 HDCP_ SHD_AN2 HDCP_AN 0x28 44 HDCP_ SHD_AN3 HDCP_AN 0x29 44 HDCP_ SHD_AN4 HDCP_AN 0x2A 44 HDCP_ SHD_AN5 HDCP_AN

Ref 0xB0: Name 7 6 5 4 3 2 1 0 Page 0x2B 44 HDCP_ SHD_AN6 HDCP_AN 0x2C 44 HDCP_ SHD_AN7 HDCP_AN 0x2D 44 HDCP_ SHD_AN8 HDCP_AN 0x30 42 HDCP_SHD_BSTAT2 BSTATUS2[7:5] MP_HDMI_MODE RSVD-W0 0x31 40 HDCP_WR_DEBUG CLEAR_RI RSVD 0x32 41 HDCP_STAT RSVD-W0 DECRYPT AUTHEN RSVD 0x3A 42 BCAPS_CTRL0 P3_HDMI P3_FAST P2_HDMI P2_FAST P1_HDMI P1_FAST P0_HDMI P0_FAST 0x40 20 SLAVE_ADDR11 SLAVE_ADDR_11 0x70 28 INT_GROUP_STATE_0 GRP6_INT GRP5_INT RSVD GRP_PA GRP1_INT GRP0_INT INT 0x71 29 INT_STATUS_1 RSVD PDD_PWR_CHG RSVD 0x72 58 INT_STATUS_2 HDMI_MODE RSVD-W0 SW_INT CKDT_INT SCDT_INT RSVD-W0 0x75 29 INT_ENABLE_1 RSVD PDD_PWR_CHG RSVD 0x76 58 INT_ENABLE_2 HDMI_MODE RSVD-W0 SW_INT CKDT_INT SCDT_INT RSVD-W0 SOFT_ OPEN_ RSVD POLARITY RSVD 0x79 28 INT_CTRL INTR DRAIN 0x7B 59 CH0_INTR5 P3_CKDT P2_CKDT P1_CKDT P0_CKDT R3PWR5V R2PWR5V R1PWR5V R0PWR5V 0x7C 59 CH0_INTR6 RSVD-W0 SPPWR5V 0x7D 59 CH0_INTR5_MASK P3_CKDT P2_CKDT P1_CKDT P0_CKDT R3PWR5V R2PWR5V R1PWR5V R0PWR5V 0x7E 59 CH0_INTR6_MASK RSVD-W0 SPPWR5V 0x80 38 RX_TERM_VAL_1 TERM_VAL_P2 RSVD TERM_VAL_P3 0x82 37 RX_TMDS_TERM_0 TERM_SEL_P3 TERM_SEL_P2 TERM_SEL_P1 TERM_SEL_P0 0x83 38 RX_TERM_VAL_0 TERM_VAL_P0 RSVD TERM_VAL_P1 0x90 29 INT_STATUS_7 RSVD BOOT_DONE RSVD 0x92 29 INT_ENABLE_7 RSVD BOOT_DONE RSVD 0x94 23 CH0_INTR9 RSVD INT_PIN[0] 0xA0 23 CH0_INTR9_MASK RSVD INT_PIN[0]

Ref 0xE0: Name 7 6 5 4 3 2 1 0 Page 0x00 36 RX_EDID_VER EDID_NVRAM_VERSION EN_EDID_DDC_VG RSVD EN_EDID_DDC_P3 EN_EDID_DDC_P2 EN_EDID_DDC_P1 EN_EDID_DDC_P0 0x01 36 RX_EDID_DDC_EN A 0x02 51 EDID_FIFO_ADDR FIFO_ADDR 0x03 52 EDID_FIFO_DATA FIFO_DATA 0x04 52 EDID_FIFO_SEL RSVD BOOT_DATA SEL_EDID_VGA SEL_EDID_CH3 SEL_EDID_CH2 SEL_EDID_CH1 SEL_EDID_CH0 0x05 55 NVM_COMMAND RSVD NVM_CMD NVM_COPYTO_VG RSVD NVM_COPYTO_3 NVM_COPYTO_2 NVM_COPYTO_1 NVM_COPYTO_0 0x06 55 NVM_COPYTO A

Ref 0xE0: Name 7 6 5 4 3 2 1 0 Page 0x07 56 NVM_STAT1 RSVD VGA_EDID_VGA VGA_EDID_P3 VGA_EDID_P2 VGA_EDID_P1 VGA_EDID_P0 RSVD NVM_CMD_DONE 0x08 56 BSM_INIT RSVD BSM_INIT 0x09 56 BSM_STAT RSVD BOOT_PROGRESS BOOT_DONE EDID_ERR BOOT_ERR 0x10 56 NVM_STAT RSVD NVM_BOOT_VALID NVM_EDID_VALID 0x12 57 NVM_STAT2 RSVD HDMI_EDID_VGA HDMI_EDID_P3 HDMI_EDID_P2 HDMI_EDID_P1 HDMI_EDID_P0 DIS_AUTO_HPD_ DIS_AUTO_HPD_ DIS_AUTO_HPD_ DIS_AUTO_HPD_ HPD_CTRL_P3 HPD_CTRL_P2 HPD_CTRL_P1 HPD_CTRL_P0 0x13 35 HPD_HW_CTRL P3 P2 P1 P0 0x1A 57 CECPA_ADDR CECPA_ADR 0x1C 57 CECPAD_L_CH0 CECPAD_CH0-4 0x1D 57 CECPAD_H_CH0 CECPAD_CH0-4 0x1E 57 CECPAD_L_CH1 CECPAD_CH0-4 0x1F 57 CECPAD_H_CH1 CECPAD_CH0-4 0x20 57 CECPAD_L_CH2 CECPAD_CH0-4 0x21 57 CECPAD_H_CH2 CECPAD_CH0-4 0x22 57 CECPAD_L_CH3 CECPAD_CH0-4 0x23 57 CECPAD_H_CH3 CECPAD_CH0-4 0x24 57 CECPAD_L_CH4 CECPAD_CH0-4 0x25 57 CECPAD_H_CH4 CECPAD_CH0-4 0x2C 58 CHECKSUM_CH0 CHECKSUM_CH0-4 0x2D 58 CHECKSUM_CH1 CHECKSUM_CH0-4 0x2E 58 CHECKSUM_CH2 CHECKSUM_CH0-4 0x2F 58 CHECKSUM_CH3 CHECKSUM_CH0-4 0x30 58 CHECKSUM_CH4 CHECKSUM_CH0-4 IP_TERM_CTRL_ IP_TERM_CTRL_ IP_TERM_CTRL IP_TERM_CTRL_ RSVD TERMCTRL_EN_P2 TERMCTRL_EN_P1 TERMCTRL_EN_P0 0x40 31 IP_TERM_CTRL P3 P2 _P1 P0 0x41 31 PH_HPD_CTRL RSVD IP_HPD_CTRL_P3 IP_HPD_CTRL_P2 IP_HPD_CTRL_P1 IP_HPD_CTRL_P0 RSVD TERMCTRL_EN_P3 0x42 32 IP_DDC_CTRL RSVD IP_DDC_CTRL_P3 IP_DDC_CTRL_P2 IP_DDC_CTRL_P1 IP_DDC_CTRL_P0 RSVD 0x43 32 IP_EDID_CTRL RSVD IP_EDID_CTRL_P3 IP_EDID_CTRL_P2 IP_EDID_CTRL_P1 IP_EDID_CTRL_P0 RSVD 0x71 26 HDMI_WAKEUP_SEL RSVD HDMI_WAKE_SEL 0x7D 24 TPWR_PIN_CONFIG RSVD TPWR_OEN TPWR_MODE TPWR_PAD_CTRL TPWR_WR_DATA GPIO_HW_OUT_ RSVD 0xC0 21 GPIO_OUT_EN EN_0 0xC2 21 GPIO_OUT_EN0 RSVD PIN_MODE0 0xC4 23 GPIO_RE_EN0 RSVD RE_EN[0] 0xC6 23 GPIO_FE_EN0 RSVD FE_EN[0] 0xC8 21 GPIO_WRDATA0 RSVD WD0 0xCA 22 GPIO_RDDATA0 RSVD RD[0]

Ref 0xE0: Name 7 6 5 4 3 2 1 0 Page 0xCC 22 GPIO_PUSEL0 RSVD PU_SEL[0] 0xCE 22 GPIO_PU_EN0 RSVD PU_EN[0] 0xD1 25 PWR5V_STATUS RSVD PWR5V_P3 PWR5V_P2 PWR5V_P1 PWR5V_P0 REG_MHL_OSC_ RSVD MOBILE_R3P MOBILE_R2P MOBILE_R1P MOBILE_R0P 0xD7 83 CP_PAD_STAT EN 0xE0 82 MHL_CBUS_CONNECTED RSVD MHL_CBUS_CONNECTED_PORT 0xE6 82 MHL_PORT_SEL_STATUS RSVD MHL_PORT 0xFF 19 SYS_RESET_4 HARD_RESET RSVD

Ref 0xE6: Name 7 6 5 4 3 2 1 0 Page 0x00 81 CBUS_DEVCAP_0 MHL_DEVCAP_REGISTER 0x01 81 CBUS_DEVCAP_1 MHL_DEVCAP_REGISTER 0x02 81 CBUS_DEVCAP_2 MHL_DEVCAP_REGISTER 0x03 81 CBUS_DEVCAP_3 MHL_DEVCAP_REGISTER 0x04 81 CBUS_DEVCAP_4 MHL_DEVCAP_REGISTER 0x05 81 CBUS_DEVCAP_5 MHL_DEVCAP_REGISTER 0x06 81 CBUS_DEVCAP_6 MHL_DEVCAP_REGISTER 0x07 81 CBUS_DEVCAP_7 MHL_DEVCAP_REGISTER 0x08 81 CBUS_DEVCAP_8 MHL_DEVCAP_REGISTER 0x09 81 CBUS_DEVCAP_9 MHL_DEVCAP_REGISTER 0x0A 81 CBUS_DEVCAP_A MHL_DEVCAP_REGISTER 0x0B 81 CBUS_DEVCAP_B MHL_DEVCAP_REGISTER 0x0C 81 CBUS_DEVCAP_C MHL_DEVCAP_REGISTER 0x0D 81 CBUS_DEVCAP_D MHL_DEVCAP_REGISTER 0x0E 81 CBUS_DEVCAP_E MHL_DEVCAP_REGISTER 0x0F 81 CBUS_DEVCAP_F MHL_DEVCAP_REGISTER 0x20 81 CBUS_MHL_INTR_0 LOCAL_MHL_INTR_REGISTER 0x21 81 CBUS_MHL_INTR_1 LOCAL_MHL_INTR_REGISTER 0x22 81 CBUS_MHL_INTR_2 LOCAL_MHL_INTR_REGISTER 0x23 81 CBUS_MHL_INTR_3 LOCAL_MHL_INTR_REGISTER 0x30 81 CBUS_MHL_STAT_0 MHL_STAT_REGISTER 0x31 81 CBUS_MHL_STAT_1 MHL_STAT_REGISTER 0x32 81 CBUS_MHL_STAT_2 MHL_STAT_REGISTER 0x33 81 CBUS_MHL_STAT_3 MHL_STAT_REGISTER 0x40 82 CBUS_SCRATCH_0 MHL_SCRATCHPAD_REGISTER 0x41 82 CBUS_SCRATCH_1 MHL_SCRATCHPAD_REGISTER

Ref 0xE6: Name 7 6 5 4 3 2 1 0 Page 0x42 82 CBUS_SCRATCH_2 MHL_SCRATCHPAD_REGISTER 0x43 82 CBUS_SCRATCH_3 MHL_SCRATCHPAD_REGISTER 0x44 82 CBUS_SCRATCH_4 MHL_SCRATCHPAD_REGISTER 0x45 82 CBUS_SCRATCH_5 MHL_SCRATCHPAD_REGISTER 0x46 82 CBUS_SCRATCH_6 MHL_SCRATCHPAD_REGISTER 0x47 82 CBUS_SCRATCH_7 MHL_SCRATCHPAD_REGISTER 0x48 82 CBUS_SCRATCH_8 MHL_SCRATCHPAD_REGISTER 0x49 82 CBUS_SCRATCH_9 MHL_SCRATCHPAD_REGISTER 0x4A 82 CBUS_SCRATCH_A MHL_SCRATCHPAD_REGISTER 0x4B 82 CBUS_SCRATCH_B MHL_SCRATCHPAD_REGISTER 0x4C 82 CBUS_SCRATCH_C MHL_SCRATCHPAD_REGISTER 0x4D 82 CBUS_SCRATCH_D MHL_SCRATCHPAD_REGISTER 0x4E 82 CBUS_SCRATCH_E MHL_SCRATCHPAD_REGISTER 0x4F 82 CBUS_SCRATCH_F MHL_SCRATCHPAD_REGISTER 0x91 78 CBUS_STATUS RSVD CBUS_CONNECTED MSC_MSG_DONE_ WRITE_BURST_ WRITE_STAT_ SET_INT_RCVD MSC_MSG_RCVD RSVD MSC_CMD_DONE CONNECT_CHANGE 0x92 83 INT_STATUS_CBUS1 WITH_NACK RCVD RCVD MSC_MSG_DONE_ WRITE_BURST_RC WRITE_STAT_ SET_INT_RCVD MSC_MSG_RCVD RSVD MSC_CMD_DONE CONNECT_CHANGE 0x93 83 INT_ENABLE_CBUS1 WITH_NACK VD RCVD 0x94 83 INT_STATUS_CBUS2 RSVD MSC_CMD_ABORT — — — — — — 0x95 83 INT_ENABLE_CBUS2 RSVD MSC_CMD_ABORT — — — — — — 0x98 78 CBUS_DDC_ABORT DDC_ABORT RSVD DDC_TIMEOUT DDC_PROTO_ERR DDC_MAX_FAIL 0x9A 78 CBUS_XFR_ABORT PEER_ABORT RSVD XFR_UNDEF_CMD XFR_TIMEOUT XFR_PROTO_ERR XFR_MAX_FAIL FWR__MSC_MSG FWR_INVALID_OF PEER_ABORT — FWR_UNDEF_CMD FWR_TIMEOUT FWR_PROTO_ERR FWR_MAX_FAIL 0x9C 79 CBUS_FWR_ABORT _OV F 0xB8 79 CBUS_PRI_START RSVD WR_BURST WR _DATA RD_ DATA MSC_DATA XFER_DATA 0xB9 79 CBUS_CMD_OFST MSC_CMD_OFFSET 0xBA 79 CBUS_MSC_WR_DATA_1 CBUS_MSC_WR_DATA1 0xBB 79 CBUS_MSC_WR_DATA_2 CBUS_MSC_WR_DATA2 0xBC 80 CBUS_MSC_RD_DATA_1 CBUS_MSC_RD_DATA1 0xBF 80 MSC_MSG_SUBCMD MSC_MSG_SUBCMD 0xC0 80 MSC_MSG_OPCODE MSC_MSG_OPCODE 0xC6 80 CBUS_BURST_LEN RSVD CBUS_BURST_LEN

Ref 0xFA: Name 7 6 5 4 3 2 1 0 Page 0x03 64 IPV_WIN_ENABLE RSVD IPV_WIN_EN_2 IPV_WIN_EN_1 IPV_WIN_EN_0 0x04 65 IPV_MODE IPV_WIN_CNT RSVD IPV_MODE

Ref 0xFA: Name 7 6 5 4 3 2 1 0 Page 0x05 67 IPV_1WIN_16x9_WIDTH RSVD IPV_WIDTH_16x9 0x06 67 IPV_2WIN_16x9_WIDTH RSVD IPV_WIDTH_16x9 0x07 67 IPV_3WIN_16x9_WIDTH RSVD IPV_WIDTH_16x9 0x0A 67 IPV_1WIN_4x3_WIDTH RSVD IPV_WIDTH_4x3 0x0B 67 IPV_2WIN_4x3_WIDTH RSVD IPV_WIDTH_4x3 0x0C 67 IPV_3WIN_4x3_WIDTH RSVD IPV_WIDTH_4x3 0x0F 67 IPV_1WIN_HEIGHT RSVD IPV_HEIGHT 0x10 67 IPV_2WIN_HEIGHT RSVD IPV_HEIGHT 0x11 67 IPV_3WIN_HEIGHT RSVD IPV_HEIGHT 0x14 68 IPV_ACT_WIDTH_W0_L IPV_ACTUAL_WIDTH 0x15 68 IPV_ACT_WIDTH_W0_H IPV_ACTUAL_WIDTH 0x16 68 IPV_ACT_WIDTH_W1_L IPV_ACTUAL_WIDTH 0x17 68 IPV_ACT_WIDTH_W1_H IPV_ACTUAL_WIDTH 0x18 68 IPV_ACT_WIDTH_W2_L IPV_ACTUAL_WIDTH 0x19 68 IPV_ACT_WIDTH_W2_H IPV_ACTUAL_WIDTH 0x1E 68 IPV_ACT_HEIGHT IPV_ACTUAL_HEIGHT 0x1F 68 IPV_WIN_X0_L IPV_WIN_X 0x20 68 IPV_WIN_X0_H IPV_WIN_X 0x21 68 IPV_WIN_X1_L IPV_WIN_X 0x22 68 IPV_WIN_X1_H IPV_WIN_X 0x23 68 IPV_WIN_X2_L IPV_WIN_X 0x24 68 IPV_WIN_X2_H IPV_WIN_X 0x29 69 IPV_WIN_Y0_L IPV_WIN_Y 0x2A 69 IPV_WIN_Y0_L IPV_WIN_Y 0x2B 69 IPV_WIN_Y1_L IPV_WIN_Y 0x2C 69 IPV_WIN_Y1_L IPV_WIN_Y 0x2D 69 IPV_WIN_Y2_L IPV_WIN_Y 0x2E 69 IPV_WIN_Y2_L IPV_WIN_Y 0x33 69 IPV_ACT_X_W0_L IPV_ACTUAL_X 0x34 69 IPV_ACT_X_W0_H IPV_ACTUAL_X 0x35 69 IPV_ACT_X_W1_L IPV_ACTUAL_X 0x36 69 IPV_ACT_X_W1_H IPV_ACTUAL_X 0x37 69 IPV_ACT_X_W2_L IPV_ACTUAL_X 0x38 69 IPV_ACT_X_W2_H IPV_ACTUAL_X 0x3D 70 IPV_ALPHA_0 RSVD IPV_ALPHA 0x3E 70 IPV_ALPHA_1 RSVD IPV_ALPHA

Ref 0xFA: Name 7 6 5 4 3 2 1 0 Page 0x3F 70 IPV_ALPHA_2 RSVD IPV_ALPHA 0x42 69 IPV_WIN_3D_OFFSET0 IPV_3D_OFFSET 0x43 69 IPV_WIN_3D_OFFSET1 IPV_3D_OFFSET 0x44 69 IPV_WIN_3D_OFFSET2 IPV_3D_OFFSET IPV_FORCE_ RSVD IPV_WIN_VALID 0x47 65 IPV_WIN_STATUS BLANK 0x48 71 IPV_BORDER_CTRL RSVD USF_BORDER_EN NA_BORDER_EN ACT_BORDER_EN BORDER_EN IPV_RESTART_ IPV_RESTART_ RSVD-W1 0x4F 65 IPV_CTRL CTL1 CTL0 0x80 71 IPV_ALL_BORDER_CR ALL_BORDER_CR 0x81 71 IPV_ALL_BORDER_CB ALL_BORDER_CB 0x82 71 IPV_ALL_BORDER_Y ALL_BORDER_Y 0x83 72 IPV_ACT_BORDER_CR ACT_BORDER_CR 0x84 72 IPV_ACT_BORDER_CB ACT_BORDER_CB 0x85 72 IPV_ACT_BORDER_Y ACT_BORDER_Y 0x86 72 IPV_NA_BORDER_CR NA_BORDER_CR 0x87 72 IPV_NA_BORDER_CB NA_BORDER_CB 0x88 72 IPV_NA_BORDER_Y NA_BORDER_Y 0x89 72 IPV_USF_BORDER_CR USF_BORDER_CR 0x8A 72 IPV_USF_BORDER_CB USF_BORDER_CB 0x8B 72 IPV_USF_BORDER_Y USF_BORDER_Y 0x8C 74 IPV_ LOC_CTRL_X_SP SF_INIT_SPEED 0x8D 74 IPV_ LOC_CTRL_X_AC SF_ACCEL 0x8E 74 IPV_ LOC_CTRL_Y_SP SF_INIT_SPEED 0x8F 74 IPV_ LOC_CTRL_Y_AC SF_ACCEL 0x90 73 IPV_LOC_CTRL RSVD — — SF_ANIM_EN SF_MOVE_EN 0x93 70 IPV_USF_BGD_CR USF_BGD_CR 0x94 70 IPV_USF_BGD_CB USF_BGD_CB 0x95 70 IPV_USF_BGD_Y USF_BGD_Y

16 © 2011-2012 Silicon Image, Inc. All rights reserved SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. SiI9687A/SiI9617 General Control and Status The SiI9687A/SiI9617 device contains many registers that do not belong to a specific device feature. These include the ID registers and registers to map I2C addresses to internal device pages. In addition, there are some registers that perform functions for multiple feature modules. Some of these registers are included here, such as reset registers.

System Registers The SiI9687A/SiI9617 device requires some control that cannot be assigned specifically to one feature. This section describes the registers containing these control bits.

Device Identification Register Group This read only group of registers identifies the SiI9687A/SiI9617 device, including vendor ID, device type, and revision.

ID and Revision Registers Address:Offset Name Page Type 0xB0:0x00 VND_IDL 0 AON 0xB0:0x01 VND_IDH 0 AON 0xB0:0x02 DEV_IDL_RX 0 AON 0xB0:0x03 DEV_IDH_RX 0 AON 0xB0:0x04 DEV_REV 0 AON Bit Bit Label R/W Description Default 7:0 R 0x01 VND_ID Unique vendor identification through I2C. 15:8 R 0x00

7:0 R Device type identification. 0x87 DEV_ID 15:8 R Device type identification. 0x96

7:4 MAJOR NUM R Device revision, Major number. 0000 3:0 MINOR NUM R Device revision, Minor number. 0001

System Reset Register Group The SiI9687A/SiI9617 device provides software reset control bits for different features and subfeatures of the device. In general, these are for debug purposes only and are not used in normal operation. Some reset bits are used as feature enable/disable controls. The reset bit documentation is included here only for debugging purposes. None of these bits should be used unless directed by Silicon Image. Unless otherwise indicated, reset operations are not self clearing. The reset must be both set and cleared by the controlling software. The minimum hold time of these resets is shorter than the duration of the I2C transaction used to trigger them. As a result, unless otherwise indicated, no wait time is needed after issuing a reset. Note that not all resets have the same active polarity. Unless otherwise noted, none of the resets in this group will reset register values.

System Reset Register 1 Address:Offset Name Page Type 0xB0:0x05 SYS_RESET_1 0 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — Auto software reset of all internal logic when sync is lost (SCDT == 0) for the port connected to the main pipe. 4 AUTO_RESET_ENABLE R/W 0 0 – Manual software reset 1 – Reset internal logic whenever SCDT = 0 3:2 RSVD — Reserved — InstaPort authentication logic reset. 1 INSTAPORT_RESET R/W 0 – Normal operation 1 1 – Reset Global Reset. Resets all internal logic except register interface, ARC, HDCP and EEPROM interfaces. Silicon Image recommends waiting at least 120 ms after 0 GLOBAL_RESET R/W 0 releasing this reset before setting the PORT_CHG_ENABLE bit (0x50:0x3A[0]). 0 – Normal operation 1 – Reset

System Reset Register 2 Address:Offset Name Page Type 0xB0:0x0B SYS_RESET_2 0 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — MHL Control Bus Logic Reset. 4 MHL_RESET R/W 0 – Normal operation 0 1 – Reset 3:0 RSVD — Reserved —

System Reset Register 3 Address:Offset Name Page Type 0xB0:0x07 SYS_RESET_3 0 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — InstaPort Reset Generation with SCDT LOW Condition. 3 NO_USE_SCDT R/W 0 – Use SCDT to generate reset 0 1 – Do not use SDCT to generate reset 2:1 RSVD — Reserved — Reset HDCP Arbitration and OTP Interface. 0 HDCP_RST R/W 0 – Normal operation 0 1 – Reset

System Reset Register 4 Address:Offset Name Page Type 0xE0:0xFF SYS_RESET_4 9 AON Bit Bit Label R/W Description Default Assert Hard Reset. Restore the SiI9687A/SiI9617 default register values and resets most logic blocks in the device. 1 – Assert Reset 7 HARD_RESET R/W 0 Note: The SiI9687A/SiI9617 device does NOT send an ACK in response to setting this bit. A write of this bit MUST be followed with a dummy read from the same location. 0 – Clear Reset 6:0 RSVD — Reserved —

Slave Address Selection The SiI9687A/SiI9617 device divides its control and status registers into blocks of 256 8-Bit registers called pages. Each page is addressed separately over the local I2C device bus. The main page I2C address is fixed at either 0xB0 or 0xB2 (8-Bit notation) depending on the initial value of the CI2CA pin. Unlike previous Silicon Image port processors, this device does not mirror the 0xB0 and 0xB2 pages on addresses 0xB8 and 0xBA.

Slave Address Register Group The slave address registers allow the secondary pages to be relocated according to the needs of the OEM system design. Each slave address register specifies the base I2C address for one or more functional modules of the SiI9687A/SiI9617 device. On power up, the default values are used. If one or more of these address values conflicts with another device in the system, the SiI9687A/SiI9617 software can initialize the corresponding slave register address value to a nonconflicting address. The register description tables in this section describe the functional modules supported by each register. When changing a slave address register, use the 8-Bit I2C address convention. This means that the 7-Bit I2C address is in the most significant seven bits of the value, while Bit 0 is always set to 0. Slave Address register #8 (0xB0:0x13) does not contain an actual register page address. The bits of this register are combined in different ways to create three I2C page addresses of the SiI9687A/SiI9617 device, one each for pages 5, 6, and 7. When programming this register, ensure that none of the three page addresses conflict with each other or any of the other slave registers page addresses. The lower two bits must always be 0b10. Table 4 describes how Slave Address register #8 uses bits [7:0] to create the I2C addresses for pages 5, 6, and 7 of the SiI9687A/SiI9617 device. Table 5 is an example of how bits [7:0] of Slave Address register #8 map to device pages 5, 6, and 7. Table 4. Slave Address 8 Map Slave Map Bits Slave Addr Slave Addr Addr Page 8-Input Bits 8-Input Bits 8-Input 7 6 5 4 3 2 1 0 Bits 7:4 3:2 — 5 7 6 5 4 0 3 2 0 7:4 3:2 — 6 7 6 5 4 3 2 1 0 7:4 OR of 3:2 1:0 7 7 6 5 4 3 ORed 2 1 0 0

Table 5. Slave Address 8 Map Example Binary Hex Page 7 6 5 4 3 2 1 0 — Slave Register #8 0 1 0 1 0 0 1 0 0x52 Page 5 0 1 0 1 0 0 0 0 0x50 Page 6 0 1 0 1 0 0 1 0 0x52 Page 7 0 1 0 1 0 1 0 0 0x54

Slave Address Registers Address:Offset Name Page Type 0xB0:0x11 SLAVE_ADDR6 0 AON 0xB0:0x12 SLAVE_ADDR7 0 AON 0xB0:0x13 SLAVE_ADDR8 0 AON 0xB0:0x14 SLAVE_ADDR5 0 AON 0xB0:0x15 SLAVE_ADDR4 0 AON 0xB0:0x16 SLAVE_ADDR0 0 AON 0xB0:0x17 SLAVE_ADDR1 0 AON 0xB0:0x19 SLAVE_ADDR3 0 AON 0xB0:0x40 SLAVE_ADDR11 0 AON Bit Bit Label R/W Description Default I2C device slave address for receiver ports 2 and 3 Analog 7:0 SLAVE_ADDR_6 R/W 0x66 Control registers. 7:0 SLAVE_ADDR_7 R/W Reserved. Must be set to 0x00. 0x68 I2C device slave address for mapping to InstaPort pages 5, 6, and 7. If using the default of 0x52, access pages 5, 6, and 7 7:0 SLAVE_ADDR_8 R/W 0x52 using I2C addresses 0x50, 0x52, and 0x54. See Table 4 on page 19 for details. 7:0 SLAVE_ADDR_5 R/W I2C device slave address for Transmit Control registers. 0x90 I2C device slave address for receiver Port 0 and Port 1 Analog 7:0 SLAVE_ADDR_4 R/W 0x64 Control registers. 7:0 SLAVE_ADDR_0 R/W Reserved. Must be set to 0x00. 0x00 I2C device slave address for MHL Receivers 0, 1, 2, 3, and 4 7:0 SLAVE_ADDR_1 R/W 0xE6 Control registers. 7:0 SLAVE_ADDR_3 R/W I2C device slave address for EDID and NVRAM registers. 0xE0 7:0 SLAVE_ADDR_11 R/W I2C device slave address for InstaPrevue registers, page 3. 0xFA

External Pin Control The device provides registers to control the behavior of certain external pins. These controls allow the system software to configure the device for a specific system design. The external pins consist of the TPWR pin and one general purpose input/output (GPIO) pin, which are used to communicate the internal software state with, or receive information from, another device. The GPIO pin is shared with the MHL_CD pin.

General Purpose I/O (GPIO) Register Group The registers in this group provide very flexible options for the control of each GPIO pin. Each pin can be an input or an output. Each pin has an internal pull-up or pull-down resistor, which can trigger an interrupt on a rising edge, falling edge, or any edge input activity. Table 6. GPIO Pin Settings GPIO Pin SiI9687A/SiI9617 Pin Primary Function Secondary Function Power GPIO 0 MHL_CD/GPIO0 MHL Cable Detect 0 N/A AON

Registers PWR

pe & pu

Logic I GPIO

oen pe & !pu Internal en C

Figure 3. GPIO Pad Schematic

GPIO HW Out Enable Address:Offset Name Page Type 0xE0:0xC0 GPIO_OUT_EN 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — 0 – Disable internal signal from GPIO output 0 GPIO_HW_OUT_EN_0 R/W 0 1 – Enable internal signal to GPIO output

GPIO Direction Control Register Address:Offset Name Page Type 0xE0:0xC2 GPIO_OUT_EN0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Selects the input/output mode for the GPIO pin. 0 PIN_MODE0 R/W 0 – Pin in the output mode 0 1 – Pin in the input mode

GPIO Write Data Registers Address:Offset Name Page Type 0xE0:0xC8 GPIO_WRDATA0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Sets the output value for the GPIO pin if enabled for output (GPIO Output Enable Registers (0xE0:0xC2). 0 WD0 R/W 0 0 – Pin output LOW 1 – Pin output HIGH

GPIO Read Data Registers Address:Offset Name Page Type 0xE0:0xCA GPIO_RDDATA0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Contains the current state of the GPIO pin. Valid only when the corresponding GPIO_OUT_EN (0xE0:0xC2) register bit is set 0 RD[0] R to 1 (Input mode). 0 0 – Pin is LOW 1 – Pin is HIGH

GPIO Pull Up/Down Select Registers Address:Offset Name Page Type 0xE0:0xCC GPIO_PUSEL0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Determines whether the internal pull-up or pull-down resistor is selected for the corresponding GPIO pin. The corresponding bit in the GPIO Pull-up/down Enable registers (0xE0:0xCE) must 0 PU_SEL[0] R/W be set to enable either the pull-up or the pull-down resistor. 0 0 – Pull-down resistor is selected 1 – Pull-up resistor is selected

GPIO Pull Up/Down Enable Registers Address:Offset Name Page Type 0xE0:0xCE GPIO_PU_EN0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Enables or disables the internal pull-up or pull-down resistor for the GPIO pin. The corresponding bit in the GPIO Pull- up/down Select registers (0xE0:0xCC) determines if the 0 PU_EN[0] R/W 0 pull-up or pull-down resistor is selected. 0 – Pull-up/down resistor disabled 1 – Pull-up/down resistor enabled

GPIO Interrupt Configuration Register Group The registers in this group control the GPIO interrupt mode for the SiI9687A/SiI9617 GPIO pin. When the GPIO pin changes state as configured in the GPIO_RE_EN and GPIO_FE_EN registers (0xE0:0xC6 and 0xE0:0xC4), the corresponding bit in the GPIO_INT registers (0xB0:0x94) is set. If the corresponding bit in the GPIO_MSK registers (0xB0:0xA0) is set, the INT bit in the INTR_STATE register (0xB0:0x70[0]) is set, and the SiI9687A/SiI9617 interrupt pin level is changed to an active state. See the Interrupt Control and Status section on page 27 for more information on the SiI9687A/SiI9617 interrupt system.

GPIO Interrupt Rising Edge Trigger Enable Registers Address:Offset Name Page Type 0xE0:0xC4 GPIO_RE_EN0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Enables or disables the rising edge interrupt trigger for the GPIO pin. Together with the GPIO Interrupt Falling Edge Trigger Enable registers, each GPIO pin can be configured to 0 RE_EN[0] R/W interrupt on any change. 0 0 – Rising Edge Interrupt Trigger disabled 1 – Rising Edge Interrupt Trigger enabled

GPIO Interrupt Falling Edge Trigger Enable Registers Address:Offset Name Page Type 0xE0:0xC6 GPIO_FE_EN0 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Enables or disables the falling edge interrupt trigger for the GPIO pin. Together with the GPIO Interrupt Rising Edge Trigger Enable registers, each GPIO pin can be configured to 0 FE_EN[0] R/W interrupt on any change. 0 0 – Falling Edge Interrupt Trigger disabled 1 – Falling Edge Interrupt Trigger enabled

GPIO Interrupt Status Registers Address:Offset Name Page Type 0xB0:0x94 CH0_INTR9 0 AON 0xB0:0xA0 CH0_INTR9_MASK 0 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Indicates the interrupt status for each of the GPIO pins. 0 INT_PIN[0] R/W 0 – No interrupt activity since last clear 0 1 – An interrupt occurred Notes: 1. Write 1 to a bit location to clear the associated interrupt. 2. When an interrupt occurs, the INTR bit in the INTR_STATE register (0xB0:0x70[0]) is set (along with the corresponding group state bit in the same register). If the corresponding bit is set in this register, the SiI9687A/SiI9617 interrupt pin level is changed to an active state.

TPWR Pin Control Register Group The SiI9687A/SiI9617 TPWR pin, also known as the CI2C/TPWR pin, is a special general purpose output pin that is normally used to provide clock or power status for the currently selected input TMDS port. Alternatively, it can be used as a software-controlled output for general use.

TPWR PIN Configuration Register Address:Offset Name Page Type 0xE0:0x7D TPWR_PIN_CONFIG 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — TPWR Reset. 4 TPWR_OEN R/W 0 – TPWR is in the output mode after reset 0 1 – TPWR is in the input mode (high-impedance) after reset TPWR PAD outputs the status of the selected HDMI input port. If the specific status is active, TPWR PAD is 1 if configured as status and 0 if configured as inverted status. TPWR_OEN must be set to 0 for this function to operate properly. 3:2 TPWR_MODE R/W 00 00 – Power status (0xB0:0x06[3]) 01 – Inverted Power status 10 – CKDT status (0xB0:0x06[1]) 11 – Inverted Clock detection status TPWR PAD Control. 1 TPWR_PAD_CTRL R/W 0 – Hardware controls TPWR pad value as configured by 0 TPWR_MODE and TPWR_OEN 1 –TPWR pin value is set by TPWR_WR_DATA TPWR Pin Write Data. TPWR_OEN must be set to 1 for this function to operate 0 TPWR_WR_DATA R/W properly. 0 0 – TPWR pin is set to LOW 1 – TPWR pin is set to HIGH

TMDS Pipe Status

TMDS Pipe Status Register Group

Main Pipe Status Register Address:Offset Name Page Type 0xB0:0x06 STATE 0 AON Bit Bit Label R/W Description Default State of the MHL device detect logic, with similar function to the MP_PWR5V bit for HDMI devices. 7 MHL_MODE R 0 – MHL source device not presented on main pipe selected — port 1 – MHL source device presented on main pipe selected port 6 RSVD — Reserved — Power-down domain (PDD) Power-down State. 0 – PDD is powered down (standby mode) PDD_POWER_ 1 – PDD has full power 5 R 1 STATUS This bit will be reset (0) and the device will not operate if the SiI9687A/SiI9617 transmitter is not connected to a video processor receiver with termination enabled. 4 RSVD — Reserved — State of the selected port 5 V power detect pin. This bit is set HIGH when a powered-on source is connected to 3 PWR5V R the TMDS input port connector. The value of this bit can be 0 read externally on the TPWR pin if it is configured for this output (see 0xE0:0x7D). 2 RSVD — Reserved — Clock Detect Status. The CKDT bit is set to 1 if the device is receiving a clock signal on the TMDS input. It does not indicate that the clock is correct or stable. The value of this bit can be read externally on 1 CKDT R 0 the TPWR pin if it is configured for this output (see 0xE0:0x7D). 0 – No clock 1 – Active TMDS clock Data Enable (DE) Detect Status. The DE signal is decoded from the TMDS signal. It is set to 1 by the source during active data periods and set to 0 during both horizontal and vertical sync periods. The SCDT bit is set 0 SCDT R 0 to 1 to indicate that the TMDS DE signal is toggling. It does not indicate that the signal is correct or stable. 0 – No sync toggling detected 1 – Sync toggling detected

Input Port 5 V Power Pin Status Register Address:Offset Name Page Type 0xE0:0xD1 PWR5V_STATUS 9 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — 3 PWR5V_P3 R PWR5V pin status for the corresponding port. 1 2 PWR5V_P2 R See Pipe Status registers (0xB0:0x06[3]). 1 1 PWR5V_P1 R 1 0 PWR5V_P0 R 1

TMDS Control Register Group System control registers specify the general operating characteristics of the SiI9687A/SiI9617 device.

Miscellaneous Control Register 0 Address:Offset Name Page Type 0x50:0x63 MISC_CTRL0 5 PWD Bit Bit Label R/W Description Default 0 – Disable 7 USE_FRAME_ECC R/W 1 1 – Enable consecutive ECC error frame detect 0 – Disable 6 RI_RECOV_EN R/W 0 1 – Enable recovery from glitch in DVI decoder 0 – Normal operation 1 – Nullify data island packets Forces all data islands to 0 data. This can be used to mute audio 5 AUDIO_MUTE_SYNC R/W 0 during port transitions or other periods of signal instability. Upon detecting the NULL packets, the A/V processor must soft mute the audio data to avoid audio pops or clicks. 0 – Normal operation 1 – Force black video (0 data) output on TMDS lines 4 VIDEO_MUTE_SYNC R/W This is used to mute video during port transitions or other 0 periods of signal instability. For some color spaces, the output may produce a different color, such as green or magenta. 3:1 RSVD — Reserved — 0 – Normal operation 0 RST_ECC_ERR R/W 0 1 – Reset ECC error counter Note: Silicon Image does not recommend the use of the AUDIO_MUTE_SYNC and VIDEO_MUTE_SYNC bits, as they may not be compatible with some sink devices.

Miscellaneous Control Register 1 Address:Offset Name Page Type 0x50:0x3A PAUTH_CTRL 5 PWD Bit Bit Label R/W Description Default 7:4 RSVD-W0 W Reserved 0000 3 RSVD-W1 W Reserved 1 2 RSVD — Reserved — 1 RSVD-W1 W Reserved 1 Enable port change Finite State Machine activity. 0 PORT_CH_ENABLE R/W 0 – Disable. FSM goes to IDLE 1 1 – Enable

Miscellaneous Control Register 2 Address:Offset Name Page Type 0xE0:0x71 HDMI_WAKEUP_SEL 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Wake Up from Power-down Source Select. 0 HDMI_WAKE_SEL R/W 0 – CKDT will be used as Wake Up source 0 1 – SCDT will be used as Wake Up source

Interrupt Control and Status The SiI9687A/SiI9617 device provides a single interrupt output pin (INT) for the main system processor, triggered by one or more internal interrupt sources, each with its own status and mask (enable) bits. Once an interrupt is triggered, it remains set in the status register until cleared by writing a 1 to the bit. The interrupt pin is programmable with either active-HIGH or active-LOW polarity and push-pull or open-drain output. Figure 4 illustrates a typical interrupt sequence with the interrupt polarity set to active-LOW. Register Bit (0xB0:0x70[0]) reflects the current logical state of the external interrupt pin. This means that the bit is set to 1 whenever the SiI9687A/SiI9617 device has triggered an interrupt event, regardless of the setting of the INT pin output polarity.

INT event

INT (to Host) INT cleared (by writing 1 to status bit)

TINT_ACTIVE

Figure 4. INT Pulse on Event

In this example using the default interrupt pin polarity, the INT pin is HIGH until an interrupt event occurs, which forces the pin LOW. When the host clears the interrupt event (by writing 1 to the triggering Interrupt Status Register bit), the INT line will again go HIGH as long as there are no more active events. TINT_ACTIVE duration depends on the response time of the host and software. Before leaving the service routine, the host should poll for additional events that could have occurred after the host completed the initial service.

Interrupt Control and Group Status Register Group The physical properties of the external interrupt pin are controlled by the INT_CTRL (0xB0:0x79) register. It is possible to mask the external interrupt pin using INT_CTRL bit 0 (0xB0:0x79[0]). This allows polling of the global interrupt status bit (0xB0:0x70[0]) to determine if an interrupt has occurred without allowing an actual hardware interrupt to the system processor. System software may trigger its own interrupt by setting the SOFT_INT_TRIGGER bit (0xB0:0x79[3]) to 1. This triggers a SW_INT (0xB0:0x72[5]), and if the global interrupt is enabled, a hardware interrupt is sent to the system processor. Note that as long as the SOFT_INT_TRIGGER bit is set, the SW_INT bit cannot be cleared. Because of the large number of interrupt sources, the SiI9687A/SiI9617 device provides group interrupt state registers (0xB0:0x70, 0xB0:0x71) that are set when an individual interrupt bit is set in one of the status registers associated with each group status bit. This allows faster determination of the interrupting event.

When the system processor receives the SiI9687A/SiI9617 interrupt, it should read both interrupt state registers to determine the interrupt group that originated the interrupt, and then check the interrupt status registers in that group to determine which event caused the interrupt. The interrupt registers covered by each group status bit are specified in the comments section of the interrupt state register descriptions (0xB0:0x70, 0xB0:0x71). Group interrupt status bits are not cleared directly. They are cleared when all interrupts in the registers associated with the group have been cleared.

Interrupt Control Register Address:Offset Name Page Type 0xB0:0x79 INT_CTRL 0 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Set Software Interrupt (triggers interrupt until this bit is SOFT_ cleared). 3 R/W 0 INTR 0 – Clear interrupt 1 – Set interrupt INT Pin Output Type. OPEN_ 2 R/W 0 – Push-pull 1 DRAIN 1 – Open-drain INT Pin Assertion Polarity Level. 0 – INT pin is normally LOW, and becomes HIGH when an 1 POLARITY R/W interrupt is generated internally. 1 1 – INT pin is normally HIGH, and becomes LOW when an interrupt is generated internally. 0 RSVD — Reserved —

Interrupt Group State 0 Register Address:Offset Name Page Type 0xB0:0x70 INT_GROUP_STATE_0 0 AON Bit Bit Label R/W Description Default CBUS Interrupt Group (group 6) Status. 7 GRP6_INT R This status bit is a logical OR of all enabled interrupt status bits 0 in 0xB0:0x7C. CBUS Interrupt Group (group 5) Status. 6 GRP5_INT R This status bit is a logical OR of all enabled interrupt status bits 0 in 0xE6:0x08. 5:4 RSVD — Reserved — InstaPort Interrupt Group. 3 GRP_PA R This status bit is a logical OR of all enabled interrupt status bits 0 in the registers 0x50:0x05 through 0x50:0x08. General Control Interrupt Group (group 1) Status. 2 GRP1_INT R This status bit is a logical OR of all enabled interrupt status bits 0 in the registers 0xB0:0x7B, 0xB0:0x90, and 0xB0:0x94. General Control Interrupt Group (group 0) Status. 1 GRP0_INT R This status bit is a logical OR of all enabled interrupt status bits 0 in the registers 0xB0:0x71 and 0xB0:0x72. Global Interrupt State Bit Value. If any of the group interrupts are asserted AND the global 0 INT R interrupt mask (0xB0:0x79[0]) bit is set (enabled), this bit is 0 set. The INT pin output polarity does not affect this bit.

General Interrupt Enable and Status Register Group Several interrupt status bits are general in nature and are described in this section. All other interrupt status registers are described in the section devoted to the SiI9687A/SiI9617 subsystem that generates them. An interrupt bit is set when the associated SiI9687A/SiI9617 subsystem interrupt has been triggered. If the interrupt bit is clear, no interrupt occurred on that subsystem. Once an interrupt is triggered, it remains set in the status register until cleared by writing a 1 to the bit.

Interrupt Status Register 1 Address:Offset Name Page Type 0xB0:0x71 INT_STATUS_1 0 AON 0xB0:0x75 INT_ENABLE_1 0 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Set to 1 if Power-down domain power change detected. 3 PDD_PWR_CHG R/W See System Status Register (0xB0:0x06[5]) to check actual 0 power state. 2:0 RSVD — Reserved —

Interrupt Status Register 7 Address:Offset Name Page Type 0xB0:0x90 INT_STATUS_7 0 AON 0xB0:0x92 INT_ENABLE_7 0 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — Hardware Boot complete interrupt. Write 1 to clear. Set when EDID data has been transferred from the NVRAM to 6 BOOT_DONE R/W 0 one or more port SRAMS. See NVRAM Boot Status Register (0xE0:0x09). 5:0 RSVD — Reserved —

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 29 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. InstaPort Switch and HDMI Receiver (SiI9687A Only) The SiI9687A device contains a four-port TMDS switch and an integrated TMDS receiver. The receiver performs HDCP decoding of the selected TMDS input and converts it into an HDCP unencrypted TMDS stream at the output. Sufficient TMDS decoding is performed to allow the device to process timing and authentication information and to support the InstaPort and InstaPrevue features. Full decoding of the video is not available to the external pins of the device.

InstaPort The SiI9687A InstaPort feature begins the HDCP authentication on an upstream (input) port immediately after a source device is connected, regardless of whether the port is currently selected for output to the downstream sink device. When that port is selected, the authenticated content is immediately available because it does not have to reauthenticate HDCP. The SiI9687A device must physically manipulate input port access controls such as termination, DDC enable, and hot plug signaling to request reauthentication from the upstream source device. This is called a Hot Plug Event (HPE). In certain input port operational modes, such as MHL, physical signaling is not appropriate or possible. In these cases, InstaPort must be prevented from performing automatic control. The PHYS_HPD_DISABLE register (0x50:0x88) is used to inform InstaPort that it should not physically manipulate the input port. Instead, it issues an interrupt (0x50:0x01) to allow the software to send an appropriate CBUS message to the upstream device. When InstaPort must force a reauthentication by the upstream device, it triggers a timed sequence of disabling and reenabling the input port access controls. The timing of this sequence can be controlled using the InstaPort HPE Timing registers (0x50:0x89–0x50:0x91). If InstaPort is not used or the software requires a physical HPE at a specific time, the software can manipulate the input port control signals manually. The port processor provides two methods for manual input port control: the single trigger bit (0x50:0x87) and individual signal control bits for each port (see the Hot Plug Event (HPE) Control Register Group on page 34). If preventing InstaPort automatic control of individual port signals for one or more ports is required, the InstaPort Auto Enable registers (0xE0:0x40–0xE0:0x43) can be configured to enable or disable any combination of Termination, HPD signal, HDCP DDC access, and EDID DDC access control for each individual input port.

InstaPort Auto Port Control Enable Register Group This group of registers enables or disables automatic InstaPort control of individual ports and port signals. It is possible to disable all HPE automatic physical signal control for a port (0x50:0x88) or to selectively disable automatic control of one or more HPE signals on one or more input ports (0xE0:0x40–0xE0:0x43). When the software must trigger an HPE physical event manually on a port selected to either the main or roving pipes, the IP_HPE_TRIG register (0x50:0x87) can be used to initiate the same HPE sequence that is normally performed by the InstaPort logic.

InstaPort Physical Hot Plug Disable Register Address:Offset Name Page Type 0x50:0x88 PHYS_HPD_DISABLE 5 PWD Bit Bit Label R/W Description Default 7:6 RSVD-W0 — Reserved 00 5 PHYS_HPD_DIS_P3 R/W Enable or disable the use of physical HPD signal toggling when 0 the InstaPort logic detects a need for a Hot Plug Event (HPE). 4 PHYS_HPD_DIS_P2 R/W 0 When a port is in the MHL mode, an automatic hot plug toggle 3 PHYS_HPD_DIS_P1 R/W must be prevented. Instead, an interrupt is triggered 0 (0x50:0x01[5,3]) so that the software can send the appropriate message over CBUS. 2 PHYS_HPD_DIS_P0 R/W 0 – Perform physical HPD toggling when an HPE is required 0 1 – Send HPE interrupt when HPE is required 1:0 RSVD-W1 — Reserved 11

InstaPort Hot-plug Event Trigger Register Address:Offset Name Page Type 0x50:0x87 IP_HPE_TRIGGER 5 PWD Bit Bit Label R/W Description Default 7:5 RSVD — Reserved 1 Roving/Subpipe Manual HPE Trigger. The RP_HPE_TRIG_OVR bit must be set to 1. 4 RP_HPE_TRIG R/W 0 0 – Normal operation 1 – Trigger a physical HPE sequence Roving/Subpipe Manual HPE Trigger Enable. 3 RP_HPE_TRIG_OVR R/W 0 – Allow InstaPort logic to trigger HPE sequence 0 1 – Allow manual HPE sequence trigger using RP_HPE_TRIG 2 RSVD — Reserved. 0 Main Pipe Manual HPE Trigger. The MP_HPE_TRIG_OVR bit must be set to 1. 1 MP_HPE_TRIG R/W 0 0 – Normal operation 1 – Trigger a physical HPE sequence Main Pipe Manual HPE Trigger Enable. 0 MP_HPE_TRIG_OVR R/W 0 – Allow InstaPort logic to trigger HPE sequence 0 1 – Allow manual HPE sequence trigger using MP_HPE_TRIG

InstaPort Auto Termination Enable Register Address:Offset Name Page Type 0xE0:0x40 IP_TERM_CTRL 9 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 IP_TERM_CTRL_P3 R/W For each port, individually allow the reauthentication logic to 1 5 IP_TERM_CTRL_P2 R/W control the port termination if the TMDS link for that port fails. 1 4 IP_TERM_CTRL_P1 R/W 0 – Prevent 1 3 IP_TERM_CTRL_P0 R/W 1 – Allow 1 2 TERMCTRL_EN_P2 R/W 0 – Disable 0 1 TERMCTRL_EN_P1 R/W 1 – Enable automatic HDMI termination control by hardware 0 0 TERMCTRL_EN_P0 R/W (Not applicable for MHL) 0

InstaPort Auto HPD Enable Register Address:Offset Name Page Type 0xE0:0x41 PH_HPD_CTRL 9 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 IP_HPD_CTRL_P3 R/W For each port, individually allow the reauthentication logic to 1 5 IP_HPD_CTRL_P2 R/W control the port HPD signal if the TMDS link for that port fails. 1 4 IP_HPD_CTRL_P1 R/W 0 – Prevent 1 3 IP_HPD_CTRL_P0 R/W 1 – Allow 1 2:1 RSVD — Reserved — 0 – Disable 0 TERMCTRL_EN_P3 R/W 1 – Enable automatic HDMI termination control by hardware 0 (Not applicable for MHL)

InstaPort Auto HDCP DDC Enable Register Address:Offset Name Page Type 0xE0:0x42 IP_DDC_CTRL 9 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 IP_DDC_CTRL_P3 R/W For each port, individually allow the reauthentication logic to 1 5 IP_DDC_CTRL_P2 R/W control the port HDCP DDC enable if the TMDS link for that 1 4 IP_DDC_CTRL_P1 R/W port fails. 1 0 – Prevent 3 IP_DDC_CTRL_P0 R/W 1 – Allow 1 2:0 RSVD — Reserved —

InstaPort Auto EDID Enable Register Address:Offset Name Page Type 0xE0:0x43 IP_EDID_CTRL 9 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 IP_EDID_CTRL_P3 R/W For each port, individually allow the reauthentication logic to 1 5 IP_EDID_CTRL_P2 R/W control the port EDID enable if the TMDS link for that port 1 4 IP_EDID_CTRL_P1 R/W fails. 1 0 – Prevent 3 IP_EDID_CTRL_P0 R/W 1 – Allow 1 2:0 RSVD — Reserved —

InstaPort HPE Sequence Timing Control Register Group When InstaPort must force a reauthentication by the upstream device, it triggers a timed sequence of disabling and reenabling the input port access controls. This group of registers defines the sequence and duration of the individual signals that comprise an HPE. The IP_TIMER_GRANULARITY register (0x50:0x89) defines the duration of the timer steps used by the start and end counter registers.

InstaPort HPE Timer Granularity Register Address:Offset Name Page Type 0x50:0x89 IP_TIMER_GRANULARITY 5 PWD Bit Bit Label R/W Description Default 7 RSVD — Reserved — Granularity of the InstaPort HPE event timer. 6:0 HPE_TIMER_GRANULARITY R/W 1100010 Each step is approximately 1.0235 ms.

InstaPort HPE Sequence HPD Start Time Register Address:Offset Name Page Type 0x50:0x8A IP_HPE_HPD_START 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_HPD_START R/W Offset from trigger time of HPD signal deassertion. 0x00

InstaPort HPE Sequence HPD End Time Register Address:Offset Name Page Type 0x50:0x8B IP_HPE_HPD_END 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_HPD_END R/W Offset from trigger time of HPD signal reassertion. 0x0C

InstaPort HPE Sequence RX Term Start Time Register Address:Offset Name Page Type 0x50:0x8C IP_HPE_RXTERM_START 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_RXTERM_START R/W Offset from trigger time of receiver termination disable. 0x00

InstaPort HPE Sequence RX Term End Time Register Address:Offset Name Page Type 0x50:0x8D IP_HPE_RXTERM_END 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_RXTERM_END R/W Offset from trigger time of receiver termination reenable. 0x03

InstaPort HPE Sequence HDCP DDC Start Time Register Address:Offset Name Page Type 0x50:0x8E IP_HPE_HDCP_DDC_START 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_HDCP_DDC_START R/W Offset from trigger time of HDCP DDC access disable. 0x00

InstaPort HPE Sequence HDCP DDC End Time Register Address:Offset Name Page Type 0x50:0x8F IP_HPE_HDCP_DDC_END 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_HDCP_DDC_END R/W Offset from trigger time of HDCP DDC access reenable. 0x0C

InstaPort HPE Sequence EDID DDC Start Time Register Address:Offset Name Page Type 0x50:0x90 IP_HPE_EDID_DDC_START 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_EDID_DDC_START R/W Offset from trigger time of EDID DDC access disable. 0x00

InstaPort HPE Sequence EDID DDC End Time Register Address:Offset Name Page Type 0x50:0x91 IP_HPE_EDID_DDC_END 5 PWD Bit Bit Label R/W Description Default 7:0 HPE_ EDID_DDC_END R/W Offset from trigger time of EDID DDC access reenable. 0x00

HDMI Input Port Control Although the 9687A device normally controls upstream HPD signals automatically, as well as the access to the input port DDC control registers and receiver termination settings, there is an option for manual control should system designers need this option. This section describes how to control source device access to each 9687A input port EDID (DDC address 0xA0) and HDCP (DDC address 0x74) registers, enable or disable the receiver termination, and control how the HPD signal responds to the HDMI connector +5 V pin.

InstaPort Viewing Technology Silicon Image recommends that the SiI9687A InstaPort technology be used to control the receiver input ports at all times. This technology automatically controls EDID and HDCP DDC access, HPD, and receiver termination to preauthenticate sources that are not connected to the SiI9687A main pipe. It also reauthenticates a source that has lost authentication when switched to the main pipe.

Port Control with System Off or in Standby The HDMI Specification requires that EDID access and HPD be available even if the system is turned off (power is provided by the HDMI source device) or in the standby mode. After the hardware reset of the SiI9687A device, HPD, EDID, HDCP, and receiver termination are disabled by default. To meet the HDMI requirement, it provides settings in NVRAM that are loaded into the port control registers at reset time. Each port can be individually selected to enable EDID and HPD immediately after reset without the software control. Bits [3:0] of the HPD_HW_CTRL (0xE0:0x13) register are loaded from the NVRAM boot data section location 0x04 after the device reset. Each bit corresponds to a port. If set to 1, EDID access and HPD control are enabled for the corresponding port after the device boot operation is complete. HDCP access and receiver termination for each port remains disabled until the system power is ON and the software enables them.

Port Control on Exit from Standby The software must set up port access control after the system power is turned on, even if InstaPort control is being used. To set up port access, the NVRAM settings for the HPD signal and EDID access must be overridden. Before overriding the NVRAM settings, the manual control registers should be set to the desired state using the HP_CTRL registers (0xB0:0x10) and the RX_EDID_DDC_EN register (0xE0:0x01). The software should then enable HDCP access using the RX_HDCP_DDC_EN (0xB0:0x09) register and turn on receiver termination using the RX_TMDS_TERM0 (0xB0:0x82) register. Once port access is set up, InstaPort will be able to control the ports automatically or the software can manually control the ports using the HP_CTRL, RX_EDID_DDC_EN, RX_HDCP_DDC_EN, and RX_TMDS_TERM0 register.

VGA Port Controls The SiI9687A/SiI9617 device contains an additional EDID SRAM that can be assigned to a VGA port. It does not have its own HDMI/DVI port logic. It is a spare single block (128-Byte) EDID memory. The VGA port does not have HPD, HDCP, or receiver termination controls, but VGA EDID access can be controlled using the RX_EDID_DDC_EN (0xE0:0x01) register. The VGA EDID can be loaded automatically from NVRAM by setting the appropriate bits in the NVRAM Boot Data array (see Appendix B – NVRAM Boot Data Memory Layout on page 93 for details).

Hot Plug Event (HPE) Control Register Group The registers in this group provide control over the receiver input port control signals. Figure 5 on the next page shows a block diagram of the input port control signal logic and the registers that control the logic.

NVRAM Boot load to EDID SRAM in progress

HPE_HW_CTRL_MODE 0xE0:0x13[3:0]

HPE_HW_CTRL_OVR 0xE0:0x13[7:4]

RX_HDCP_DDC_EN 0xB0:0x09[7:4] HDCP 3:0

RX_EDID_DDC_EN EDID 3:0 0xE0:0x01[3:0]

RXPWR5V 01 HPD 3:0 10

Reserved 11

RX_HP_CTRLx 0xB0:0x10 (two bits per port)

Figure 5. HPE Control Block Diagram

Receiver Hot Plug Event Hardware Control Status/Override Register Address:Offset Name Page Type 0xE0:0x13 HPD_HW_CTRL 9 AON Bit Bit Label R/W Description Default 7 DIS_AUTO_HPD_P3 R/W HW HPD and EDID Access Override. 0 6 DIS_AUTO_HPD_P2 R/W 0 – Hardware control is not overridden 0 5 DIS_AUTO_HPD_P1 R/W 1 – Hardware control of HPD and EDID access for the 0 corresponding port is disabled (see bits [3:0]). The 4 DIS_AUTO_HPD_P0 R/W HP_CTRL and EN_EDID registers can be used for 0 software control when these bits are set. 3 HPD_CTRL_P3 R 0 – Port HPD and EDID access is controlled by the HP_CTRL 0 2 HPD_CTRL_P2 R and EN_EDID registers 0 1 – Port is set to hardware control of HPD and EDID access 1 HPD_CTRL_P1 R 0 upon initial device reset either by HDMI cable plug-in or full system startup. This control remains with the hardware 0 HPD_CTRL_P0 R until overridden by software, which should occur when the 0 full system startup completes. Note: Bits [3:0] of this register are loaded from NVRAM location 0x04 at boot time.

Receiver Port HDCP DDC Enable Register Address:Offset Name Page Type 0xB0:0x09 RX_HDCP_DDC_EN 0 AON Bit Bit Label R/W Description Default 7 EN_HDCP_DDC_P3 R/W Controls external HDCP DDC access to the corresponding 0 6 EN_HDCP_DDC_P2 R/W receiver port. 0 5 EN_HDCP_DDC_P1 R/W 0 – Disable HDCP DDC Port 0 4 EN_HDCP_DDC_P0 R/W 1 – Enable HDCP DDC Port 0 3:0 RSVD — Reserved — Notes: 1. For correct operation, the control bits in this register should be used only when HW HPD and EDID Access Override (0xE0:0x13[7:4]) are set. 2. Disabling any HDCP DDC port causes accesses of the corresponding HDCP DDC I2C slave device to return NACK. The EDID I2C slave device is still accessible. 3. This register enables HDCP register access for one or more input ports.

Receiver Port EDID Version Register Address:Offset Name Page Type 0xE0:0x00 RX_EDID_VER 9 AON Bit Bit Label R/W Description Default 7:0 EDID_NVRAM_VERSION R/W Defines the version of EDID in NVRAM. 0x10

Receiver Port EDID DDC Enable Register Address:Offset Name Page Type 0xE0:0x01 RX_EDID_DDC_EN 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — 4 EN_EDID_DDC_VGA R/W Controls external EDID and HDCP DDC access to the 0 3 EN_EDID_DDC_P3 R/W corresponding receive port. 0 2 2 EN_EDID_DDC_P2 R/W 0 – Disable access to DDC I C slave addresses 0xA0 and 0x74 0 1 – Enable access to DDC I2C slave addresses 0xA0 and 0x74 1 EN_EDID_DDC_P1 R/W 0 0 EN_EDID_DDC_P0 R/W 0 Notes: 1. Before disabling access to the EDID via this register, the hot plug signal should be deasserted for each port that will be disabled to prevent the source device from trying to read the EDID while it is disabled. Use registers 0xB0:0x10 to deassert the HPD signal. 2. Disabling any EDID DDC port causes accesses of the corresponding EDID DDC I2C and HDCP DDC I2C slave devices to return NACK.

Receiver HPD Control Register 1 Address:Offset Name Page Type 0xB0:0x10 RX_HP_CTRL1 0 AON Bit Bit Label R/W Description Default 7:6 HP_CTRL_P3 R/W Controls the behavior of the Hot Plug Detect outputs for the 01 corresponding port. 5:4 HP_CTRL_P2 R/W 00 – LOW (if manual control enabled, follows RPWR if auto) 01 01 – HIGH (follows RPWR) 3:2 HP_CTRL_P1 R/W 10 – High-impedance 01 11 – Reserved 1:0 HP_CTRL_P0 R/W 01

The receiver HPD control settings (0xB0:0x10) determine how the HPD output of the HDMI input connector will behave. Standard HDMI operation requires that the HPD connector pin follows the state of the PWR5V pin. In other words, if a source is connected to the sink device, the connector PWR5V pin will be connected to the HPD pin. When the source detects a high level on the HPD pin, it assumes that a sink device is connected and can begin authentication. The SiI9687A/SiI9617 device does not connect the PWR5V pin directly to the HPD pin. Instead, it provides optional control of the HPD output to allow the sink to determine when to indicate that it is connected to the source. Figure 5 on page 35 shows the HPD output multiplexer. Table 7 shows the different control options. Table 7. Receiver Hot Plug Signal Control Modes Two Bit HPD HPD Output Effect Control Value If the HPE override bit is set (0xE0:0x13) or the HPE_HW_CTRL_MODE bit 00 is cleared, the HPD output is LOW. Otherwise, HPD follows the PWR5V signal level on the corresponding port connector. 01 HPD follows the PWR5V signal level on the corresponding port connector pin. HPD is high-impedance. 10 This option is used when MHL is selected on the corresponding port to enable the MHL logic to use the HPD signal pin. 11 Reserved

Receiver TMDS Termination Select Register 0 Address:Offset Name Page Type 0xB0:0x82 RX_TMDS_TERM_0 0 AON Bit Bit Label R/W Description Default 7:6 TERM_SEL_P3 R/W Select TMDS termination mode for corresponding receiver 11 input port. 5:4 TERM_SEL_P2 R/W 00 – 50 Ω termination 11 01 – Data 50 Ω termination, clock 100 Ω termination 3:2 TERM_SEL_P1 R/W 10 – Approximately 3 k Ω clock and data termination for hot- 11 plug surge current protection 1:0 TERM_SEL_P0 R/W 11 – Not terminated 11

The receiver TMDS termination control settings (0xB0:0x82) determine how the receiver termination will behave. As an alternate to the HPD signal, many HDMI sources try to detect if their output is terminated to determine if they are connected to a sink device. In other words, if a source detects receiver termination, it assumes that it is connected to a sink device and can begin authentication, or at least start sending the TMDS clock. The SiI9687A/SiI9617 device provides optional control of the receiver termination to allow the sink to determine when to indicate that it is connected to the source. Table 8 shows the different receiver termination control options. Table 8. Receiver Termination Control Modes Two Bit Term Receiver Termination Effect Select Value 00 The Data and Clock TMDS pins are terminated with internal 50 Ω resistors. The Data TMDS pins are terminated with internal 50 Ω resistors. The Clock TMDS 01 pin is terminated with an internal 100 Ω resistor. Data and Clock are terminated with internal 3 kΩ resistor for hot plug surge 10 protection. 11 The Data and Clock TMDS pins are not terminated.

Power Down Port Control Register Address:Offset Name Page Type 0xB0:0x0C PWD_PORT_CTRL 0 AON Bit Bit Label R/W Description Default 7:3 RSVD — Reserved — PWD Section Power Lost Status. This status bit is set to1 whenever the PWD section of the device loses power. Clear by writing a 1 to this bit. 2 PWD_WAS_DOWN R/W 1 0 – Normal operation 1 – PWD section has lost power since the last time this bit was written. Select control of receiver termination during the standby mode (PWD section has no power). 1 STANDBY_TERM_DISABLE R/W 0 – RECEIVER_TMDS_TERM0 (0xB0:0x82) control receiver 0 termination. 1 – Receiver termination for all ports is disabled when power to the PWD section of the device is lost. Select control of HDCP DDC access during standby mode (PWD section has no power). This does not include EDID DDC access. 0 STANDBY_HDCP_DISABLE R/W 0 – RECEIVER_HDCP_DDC_EN (0xB0:0x09) controls 0 HDCP DDC access. 1 – HDCP access for all ports is disabled when power to the PWD section of the device is lost.

Receiver Termination Value Register Group The receiver TMDS signal termination can be controlled for optimum performance of the HDMI or MHL link. These registers select the termination resistance for each input port individually. The 0xB0:0x82 registers are used to control enabling and disabling of the TMDS termination.

Receiver Termination Value Register 0 Address:Offset Name Page Type 0xB0:0x83 RX_TERM_VAL_0 0 AON Bit Bit Label R/W Description Default TMDS Receiver Termination Value for Port 0. 000 – 60 Ω 001 – 55 Ω 010 – 50 Ω 7:5 TERM_VAL_P0 R/W 100 011 – 45 Ω 100 – 40 Ω 110 – 35 Ω All other values reserved. 4:3 RSVD — Reserved — TMDS Receiver Termination Value for Port 1. 2:0 TERM_VAL_P1 R/W 100 See TERM_VAL_P0 for bit values.

Receiver Termination Value Register 1 Address:Offset Name Page Type 0xB0:0x80 RX_TERM_VAL_1 0 AON Bit Bit Label R/W Description Default TMDS Receiver Termination Value for Port 2. 7:5 TERM_VAL_P2 R/W 100 See TERM_VAL_P0 for bit values. 4:3 RSVD — Reserved — TMDS Receiver Termination Value for Port 3. 2:0 TERM_VAL_P3 R/W 100 See TERM_VAL_P0 for bit values.

InstaPort Background Authentication Control Registers In most cases, InstaPort operates with little software interaction or tuning. When used with InstaPrevue, the time spent with each background port connected to the TMDS subpipe must be controlled. To ensure that InstaPrevue has time to capture at least one valid frame at any resolution, InstaPrevue requires additional time at each port.

InstaPort Authenticated Port Time Out Register Address:Offset Name Page Type 0x50:0x50 IP_AUTH_PORT_TIME_7_0 5 PWD 0x50:0x51 IP_AUTH_PORT_TIME_15_8 5 PWD 0x50:0x52 IP_AUTH_PORT_TIME_23_16 5 PWD 0x50:0x53 IP_AUTH_PORT_TIME_31_24 5 PWD Bit Bit Label R/W Description Default 31:24 R/W Length of time for an authenticated background port to stay 0x00 23:16 R/W connected to the subpipe. Granularity is 500 ns. 0x03 AUTH_ PORT_TIME When an authenticated background port is connected to the 15:8 R/W subpipe, the authentication status is checked and if InstaPrevue 0x0D 7:0 R/W mode is enabled, a snapshot frame is captured. 0x40

TMDS Video Sources The device contains two internal TMDS pipelines for video data: one for transmitter output and one for the InstaPort and InstaPrevue features. When InstaPort is active, only the main pipe selection bits (0xB0:0x0A[2:0]) are valid.

Internal Pattern Generator Video Source The SiI9687A/SiI9617 device can generate internal video pattern data to support testing (see the Video Pattern Generator section on page 86).

Input Port Selection Register Group These registers select the receiver port. The roving pipe port selection is handled automatically by the InstaPort logic. The Port Selection Status registers show a one-bit-active status for the main and roving pipe port selections. The main pipe is represented by register 0x50:0x3B[3:0] and the roving pipe by register 0x50:0x3B[7:4]. Only one port is active at any one time for each pipe.

Port Select Register Address:Offset Name Page Type 0xB0:0x0A RX_PORT_SEL 0 AON Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — Enable Power-down 20 MHz MHL Oscillator. 5 PWD_20MHZ_OSC R/W 0 – Disable power-down oscillator 0 1 – Enable power-down oscillator 4 RSVD — Reserved — Enable the DDC delay. 0 – Disable delay 1 – Enable delay 3 DDC_DEL_EN R/W 1 Enables a minimum of 300 ns delay between the rising edge of the SCL signal and the falling edge of the SDA signal to ensure proper I2C operation. Main Pipe TMDS Input Port Select. 0 – 3: Selects corresponding receiver port 2:0 PORT_SEL R/W 000 4 – 7: Reserved See register 0xB0:0x09 for additional port selection control.

Port Selection Status Register 0 Address:Offset Name Page Type 0x50:0x3B SELECTED_PORT_0 5 PWD Bit Bit Label R/W Description Default Roving/Subpipe Port Selection, Port 0 to Port 3. 7:4 RP_PORT_BIT R 0 – Corresponding port not connected to roving pipe 0x0 1 – Corresponding port connected to roving pipe Main Pipe Port Selection, Port 0 to Port 3. 3:0 MP_PORT_BIT R 0 – Corresponding port not connected to main pipe 0x0 1 – Corresponding port connected to main pipe

Receiver HDCP Registers The registers listed in this section are for HDCP receiver authentication. The port processor has no upstream HDCP repeater support.

HDCP Status and Control Register Group

HDCP Debug Register Address:Offset Name Page Type 0xB0:0x31 HDCP_WR_DEBUG 0 PWD Bit Bit Label R/W Description Default Notify the Source to Retry Authentication. 0 – Normal operation, decrypt when enabled by authentication. 1 – Clear the Ri´ value in the HDMI receiver so that the source retries authentication. When CLR_BOTH_RI (0x50:0x6F[5]) is enabled, both bytes of the Ri´ are cleared; otherwise only byte 0 of the Ri´ is cleared. 7 CLEAR_RI W This bit is cleared when the source reauthenticates the HDMI 0 receiver. When errors in decrypted content are detected, set this bit to force the Ri´ value to mismatch the Ri value in the HDMI transmitter. The HDMI receiver indicates in the Link Integrity Check that HDCP decryption has stopped. This bit is cleared by hardware when the AKSV is written to the DDC register. 6:0 RSVD — Reserved — Note: Operates on selected port only.

HDCP Status Register Address:Offset Name Page Type 0xB0:0x32 HDCP_STAT 0 PWD Bit Bit Label R/W Description Default 7:6 RSVD-W0 R/W Reserved 00 Used by the sink firmware to determine HDCP decryption status of the currently selected port. 0 – HDCP decryption is inactive 5 DECRYPT R 0 1 – HDCP decryption is active This bit is set only when decryption is active. It is updated once per frame by checking for an active VSYNC and a CTL3 pulse. Used by the sink firmware to determine HDCP authentication status of the currently selected port. 0 – HDCP authentication not attempted 1 – HDCP authentication attempted 4 AUTHEN R 0 If authentication is attempted, this bit is set (even if authentication does not complete). This bit is set after R0′ calculation is complete, but this does not indicate if R0′ equals R0 in the Source. Only the source knows that result. 3:0 RSVD — Reserved — Notes: The status of Bits 5 and 4 refers to the selected port only.

HDCP Authentication Status Register 1 Address:Offset Name Page Type 0x50:0x3C PAUTH_STAT1 5 PWD Bit Bit Label R/W Description Default 7 P3_DECRYPT R HDCP decryption status for Port 0 through Port 3. 0 Decryption status is updated once per frame by checking for an 6 P2_DECRYPT R active DE and a CTL3 pulse. 0 0 – HDCP decryption is inactive 5 P1_DECRYPT R 1 – HDCP decryption is active 0

4 P0_DECRYPT R 0

3 P3_AUTH R HDCP Authentication Status for Port 0 through Port 3. 0 If authentication is attempted, this bit is set (even if 2 P2_AUTH R authentication does not complete). This bit is set after the port 0 processor completes its R ′ calculation, but this does not 1 P1_AUTH R 0 0 indicate if R0′ equals R0 in the source. Only the source knows that result. 0 P0_AUTH R 0 – HDCP authentication not attempted 0 1 – HDCP authentication attempted

HDCP Authentication Clearing Mode Register Address:Offset Name Page Type 0x50:0x6F HDCP_CLR 5 PWD Bit Bit Label R/W Description Default 7:6 RSVD-W0 W Reserved 00 0 – HW ECC Error RI-Clear mechanism clears the first byte of the R ′ if the ECC error threshold is exceeded. 5 CLR_BOTH_RI R/W i 0 1 – HW ECC Error RI-Clear mechanism clears both bytes of the Ri′ if the ECC error threshold is exceeded. 4:0 RSVD-W0 W Reserved 00000

HDCP BCAPS Control Register 0 Address:Offset Name Page Type 0xB0:0x3A BCAPS_CTRL0 0 PWD Bit Bit Label R/W Description Default Set HDCP BCAPS Register Bit 7 for Port 3. 7 P3_HDMI R/W 0 – Do not support HDMI 1 1 – Support HDMI Set HDCP BCAPS Register Bit 4 for Port 3. 6 P3_FAST R/W 0 – Do not support fast I2C 0 1 – Support fast I2C Set HDCP BCAPS Register Bit 7 for Port 2. 5 P2_HDMI R/W 0 – Do not support HDMI 1 1 – Support HDMI Set HDCP BCAPS Register Bit 4 for Port 2. 4 P2_FAST R/W 0 – Do not support fast I2C 0 1 – Support fast I2C Set HDCP BCAPS Register Bit 7 for Port 1. 3 P1_HDMI R/W 0 – Do not support HDMI 1 1 – Support HDMI Set HDCP BCAPS Register Bit 4 for Port 1. 2 P1_FAST R/W 0 – Do not support fast I2C 0 1 – Support fast I2C Set HDCP BCAPS Register Bit 7 for Port 0. 1 P0_HDMI R/W 0 – Do not support HDMI 1 1 – Support HDMI Set HDCP BCAPS Register Bit 4 for Port 0. 0 P0_FAST R/W 0 – Do not support fast I2C 0 1 – Support fast I2C Note: I2C has two clock frequencies, one at 100 kHz for normal I2C and 400 kHz for fast I2C. Setting the above bits to support fast I2C will set the clock speed to 400 kHz.

HDCP BSTATUS2 Main Pipe Control Register Address:Offset Name Page Type 0xB0:0x30 HDCP_SHD_BSTAT2 0 PWD Bit Bit Label R/W Description Default 7:5 BSTATUS2[7:5] R/W Bstatus bits. 000 Main Pipe HDMI Mode Enabled Status. 4 MP_HDMI_MODE R 0 – DVI mode 0 1 – HDMI mode 3:0 RSVD-W0 R/W Reserved 0000 Notes: This register is a shadow of register 0x74:0x42.

HDCP Link Shadow Register Group These registers provide the current value of the standard HDCP register set. They are read-only duplicates of the DDC registers written by the source device and those supplied by the SiI9687A/SiI9617 HDCP key hardware.

HDCP Shadow BKSV Registers Address:Offset Name Page Type 0xB0:0x1A SHD_BKSV_1_RX 0 PWD 0xB0:0x1B SHD_BKSV_2_RX 0 PWD 0xB0:0x1C SHD_BKSV_3_RX 0 PWD 0xB0:0x1D SHD_BKSV_4_RX 0 PWD 0xB0:0x1E SHD_BKSV_5_RX 0 PWD Bit Bit Label R/W Description Default The Key Selection Vector (KSV). This value must always be available for reading and may be 39:0 HDCP_BKSV R — used to determine that the video receiver is HDCP capable. Valid KSVs contain 20 ones and 20 zeros. Note: These registers are equivalent to DDC registers 0x74:0x00–0x74:0x04.

HDCP Shadow Ri′ Registers Address:Offset Name Page Type 0xB0:0x1F HDCP_SHD_RI1 0 PWD 0xB0:0x20 HDCP_SHD_RI2 0 PWD Bit Bit Label R/W Description Default Selected Port Link Verification Response. Updated every 128 frames. Silicon Image recommends that the source protect against errors in the I2C transmission by rereading this value when unexpected values are received. This 15:0 HDCP_RI R — value must be available at all times between updates. R0′ is available at a maximum of 100 ms after AKSV is received. Subsequent Ri′ values are available at a maximum of 128 pixel clocks following the assertion of CTL3. Note: These registers are equivalent to DDC registers 0x74:0x08–0x74:0x09

HDCP Shadow AKSV Registers Address:Offset Name Page Type 0xB0:0x21 HDCP_SHD_AKSV1 0 PWD 0xB0:0x22 HDCP_SHD_AKSV2 0 PWD 0xB0:0x23 HDCP_SHD_AKSV3 0 PWD 0xB0:0x24 HDCP_SHD_AKSV4 0 PWD 0xB0:0x25 HDCP_SHD_AKSV5 0 PWD Bit Bit Label R/W Description Default 39:0 HDCP_AKSV R Selected Port Video Transmitter Key Selection Vector (KSV). — Note: These registers are equivalent to DDC registers 0x74:0x10–0x74:0x14.

HDCP Shadow AN Registers Address:Offset Name Page Type 0xB0:0x26 HDCP_SHD_AN1 0 PWD 0xB0:0x27 HDCP_ SHD_AN2 0 PWD 0xB0:0x28 HDCP_ SHD_AN3 0 PWD 0xB0:0x29 HDCP_ SHD_AN4 0 PWD 0xB0:0x2A HDCP_ SHD_AN5 0 PWD 0xB0:0x2B HDCP_ SHD_AN6 0 PWD 0xB0:0x2C HDCP_ SHD_AN7 0 PWD 0xB0:0x2D HDCP_ SHD_AN8 0 PWD Bit Bit Label R/W Description Default Selected Port Session Random Number. A 64-Bit pseudo-random value written from the transmitter during authentication process. Alternatively; this value may be 63:0 HDCP_AN R 0 generated by software or hardware; and then written here. This multi-byte value must be written by the source device before the KSV is written. Note: These registers are equivalent to DDC registers 0x74:0x18–0x74:0x1F.

Receiver InfoFrame Capture This set of registers contains video input format information for the port specified in the SP_PORT_SEL register. They are provided to extract the InfoFrame data from the device attached to the selected port so that the upstream device can be configured correctly. To get the InfoFrame data from either of the selected pipes AIF/AVI/VSIF, first write the SP_PORT_SEL register (0x50:0x7C[2:0]) with the desired port and select pipe by RD_PIPE_SEL bit (0x50:0x7C[5]). Then read the corresponding SP_VALID register for the valid bit (bit[0]) to be set. Clear the last four frames of the extracted packet data (0x54:0x20), and read the length value from the desired selected pipe InfoFrame. Then use that length to do a block read from the desired InfoFrame buffer. To get the InfoFrame data from either of the main pipe buffers (AIF/VSIF), first clear the buffer of the previously extracted four frames of data (0x54:0x20), then read the length value from the desired main pipe InfoFrame. Finally, use that length to do a block read from the desired InfoFrame buffer.

Main and Subpipe Packet Extraction Register Group This set of registers contains InfoFrame information for the port that is selected to the main or subpipe. To get the InfoFrame data from either of the main pipe buffers (AIF/VSIF), first clear the buffer of the previously extracted four frames of data (reg 0x54:0x20), then read the length value from the desired main pipe InfoFrame. Finally, use that length to do a block read from desired InfoFrame buffer.

Packet Buffer Clear Register Address:Offset Name Page Type 0x54:0x20 MP_PACKET_BUFFER_CLR 7 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — 3 VSI_ID_CHK_EN R/W Hardware-based VSI ID check enable. 0 2 VSI_ID_SWAP R/W Swap byte order of IEEE ID for 3D VSI. 0 0 – Buffer will not be cleared automatically 1 AIF_CLR_EN R/W 1 – Buffer content will be cleared automatically if no AIF 0 received 0 – Buffer will not be cleared automatically 0 VSI_CLR_EN R/W 1 – Buffer content will be cleared automatically if no VSI 0 received

Main Pipe Audio InfoFrame Type Code Register Address:Offset Name Page Type 0x52:0x72 MP_AIF_CAPTURE_HEADER 6 PWD Bit Bit Label R/W Description Default 7:0 MP_AIF_CAPTURE_HEADER R/W The type code for HDMI Audio InfoFrame Packet. 0x84 Note: The HDMI Specification defines the Audio InfoFrame Type code to be 0x84. Therefore this register should be initialized to 0x84.

Selected Pipe Audio InfoFrame Registers Address:Offset Name Page Type 0x54:0x90 SP_AIF_HEADERL 7 PWD 0x54:0x91 SP_AIF_HEADERH 7 PWD 0x54:0x92 SP_AIF_LENGTH 7 PWD 0x54:0x93 SP_AIF_PB0 7 PWD 0x54:0x94– 7 PWD SP_AIF_PB1–SP_AIF_PB27 0x54:0xAE Bit Bit Label R/W Description Default 7:0 SP_AIF_HEADERL R Audio InfoFrame Packet Type Code. 0x00 7:0 SP_AIF_HEADERH R Audio InfoFrame Packet Version Code. 0x00 7:0 SP_AIF_LENGTH R Audio InfoFrame Packet Length. 0x00 7:0 SP_AIF_PB0 R Audio InfoFrame Packet Checksum. 0x00 7:0 SP_AIF_PB1– SP_AIF_PB27 R Audio InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_AIF_HEADERL to be 0x84 and SP_AIF_HEADERH to be 0x01. Other values are from the HDMI Specification version 1.4 Table 8-8. The SP_AIF_LENGTH field indicates the CEA-861D data payload length of 10 bytes (0x0A). The device can receive up to 27 bytes. It is up to the firmware to verify that the checksum matches the value in the AIF InfoFrame sent by the HDMI Transmitter.

Port AIF InfoFrame Valid Register Address:Offset Name Page Type 0x54:0xAF SP_AIF_VALID 7 PWD Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — 0 – Port AIF registers may not contain valid data 0 SP_AIF_VALID R 0 1 – Port AIF registers contain valid data

Selected Pipe AVI InfoFrame Registers Address:Offset Name Page Type 0x54:0xB0 SP_AVI_HEADERL 7 PWD 0x54:0xB1 SP_AVI_HEADERH 7 PWD 0x54:0xB2 SP_AVI_LENGTH 7 PWD 0x54:0xB3 SP_AVI_PB0 7 PWD 0x54:0xB4– 7 PWD SP_AVI_PB1–SP_AVI_PB13 0x54:0xC0 Bit Bit Label R/W Description Default 7:0 SP_AVI_HEADERL R AVI InfoFrame Packet Type Code. 0x00 7:0 SP_AVI_HEADERH R AVI InfoFrame Packet Version Code. 0x00 7:0 SP_AVI_LENGTH R AVI InfoFrame Packet Length. 0x00 7:0 SP_AVI_PB0 R AVI InfoFrame Packet Checksum. 0x00 7:0 SP_AVI_PB1–SP_AVI_PB13 R AVI InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_AVI_HEADERL to be 0x82 and SP_AVI_HEADERH to be 0x02. Other values are from the HDMI Specification version 1.4 Table 8-2. The SP_AVI_LENGTH field indicates the CEA-861D data payload length of 13 bytes (0x0D). It is up to the firmware to verify that the checksum matches the value in the AVI InfoFrame sent by the HDMI Transmitter.

Port AVI InfoFrame Valid Register Address:Offset Name Page Type 0x54:0xC1 SP_AVI_VALID 7 PWD Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — 0 – Port AVI registers may not contain valid data. 0 SP_AVI_VALID R 0 1 – Port AVI registers (0x54:0xB0) contain valid data

Main Pipe Vendor Specific InfoFrame Type Code Register Address:Offset Name Page Type 0x52:0x73 MP_VSI_CAPTURE_HEADER 6 PWD Bit Bit Label R/W Description Default 7:0 MP_VSI_CAPTURE_HEADER R/W The type code for HDMI Vendor Specific InfoFrame Packet. 0x81 Note: The HDMI Specification defines Vendor Specific InfoFrame Type code to be 0x81.

Selected Port Vendor Specific InfoFrame Registers Address:Offset Name Page Type 0x54:0xD0 SP_VSI_HEADERL 7 PWD 0x54:0xD1 SP_VSI_HEADERH 7 PWD 0x54:0xD2 SP_VSI_LENGTH 7 PWD 0x54:0xD3 SP_VSI_PB0 7 PWD 0x54:0xD4– 7 PWD SP_VSI_PB1–SP_AVI_PB27 0x54:0xEE Bit Bit Label R/W Description Default 7:0 SP_VSI_HEADERL R Vendor Specific InfoFrame Packet Type Code. 0x00 7:0 SP_VSI_HEADERH R Vendor Specific InfoFrame Packet Version Code. 0x00 7:0 SP_VSI_LENGTH R Vendor Specific InfoFrame Packet Length. 0x00 7:0 SP_VSI_PB0 R Vendor Specific InfoFrame Packet Checksum. 0x00 7:0 SP_VSI_PB1–SP_AVI_PB27 R Vendor Specific InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_VSI_HEADERL to be 0x81 and SP_VSI_HEADERH to be 0x01. Other values are from the HDMI Specification version 1.4 Table 8-10. It is up to the firmware to verify that the checksum matches the value in the VSI InfoFrame sent by the HDMI Transmitter.

Port Vendor Specific InfoFrame Valid Register Address:Offset Name Page Type 0x54:0xEF SP_VSI_VALID 7 PWD Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — 0 – Port VSIF registers may not contain valid data 0 S/MP_VSI_VALID R 0 1 – Port VSIF registers (0x54:0xD0) contain valid data

Miscellaneous Audio InfoFrame Register Group To get the InfoFrame data for ACP, SPD, ISRC1, and ISRC2 from either of the selected main or subpipes, write the RD_PIPE_SEL register (0x50:0x7C[5]). Clear the last four frames of the extracted packet data (0x54:0x20), read the length value from the desired selected pipe InfoFrame. Then using that length, perform a block read from desired InfoFrame buffer.

Selected Pipe ACP InfoFrame Registers Address:Offset Name Page Type 0x54:0x21 SP_ACP_HEADERL 7 PWD 0x54:0x22 SP_ACP_HEADERH 7 PWD 0x54:0x23 SP_ACP_LENGTH 7 PWD 0x54:0x24-0x3F SP_ACP_PB0 7 PWD Bit Bit Label R/W Description Default 7:0 SP_ACP_HEADERL R ACP InfoFrame Packet Type Code. 0x00 7:0 SP_ACP_HEADERH R ACP InfoFrame Packet ACP_Type. 0x00 7:0 SP_ACP_LENGTH R ACP InfoFrame Packet Length. 0x00 7:0 SP_ACP_PB0–27 R ACP InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_ACP_HEADERL to be 0x04 and SP_ACP_HEADERH to be ACP_Type. Other values are from the HDMI Specification version 1.4 Table 5-18. The SP_ACP_LENGTH field is reserved. The device can receive up to 27 bytes. It is up to the software to verify that the checksum matches the value in the ACP InfoFrame sent by the HDMI Transmitter.

Selected Pipe SPD InfoFrame Registers Address:Offset Name Page Type 0x54:0x40 SP_SPD_HEADERL 7 PWD 0x54:0x41 SP_SPD_HEADERH 7 PWD 0x54:0x42 SP_SPD_LENGTH 7 PWD 0x54:0x43 SP_SPD_PB0 7 PWD 0x54:0x44-0x5E SP_SPD_PB1 7 PWD Bit Bit Label R/W Description Default 7:0 SP_SPD_HEADERL R SPD InfoFrame Packet Type Code. 0x00 7:0 SP_SPD_HEADERH R SPD InfoFrame Packet Version Code. 0x00 7:0 SP_SPD_LENGTH R SPD InfoFrame Packet Length. 0x00 7:0 SP_SPD_PB0 R SPD InfoFrame Packet Checksum. 0x00 7:0 SP_SPD_PB1–27 R SPD InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_SPD_HEADERL to be 0x83 and SP_SPD_HEADERH to be 0x02. Other values are from HDMI Specification version 1.4 Table 8-2. The SP_SPD_LENGTH field indicates the CEA-861D data payload length of 1C bytes (0x1C). It is up to the software to verify that the checksum matches the value in the SPD InfoFrame sent by the HDMI Transmitter.

Selected Pipe ISRC1 InfoFrame Registers Address:Offset Name Page Type 0x54:0x5F SP_ISRC1_HEADERL 7 PWD 0x54:0x60 SP_ISRC1_HEADERH 7 PWD 0x54:0x61 SP_ISRC1_LENGTH 7 PWD 0x54:0x62-0x71 SP_ISRC1_PB0 7 PWD Bit Bit Label R/W Description Default 7:0 SP_ISRC1_HEADERL R ISRC1 InfoFrame Packet Type Code. 0x00 7:0 SP_ISRC1_HEADERH R ISRC1 InfoFrame Packet Version Code. 0x00 7:0 SP_ISRC1_LENGTH R ISRC1 InfoFrame Packet Length. 0x00 7:0 SP_ISRC1_PB0 R ISRC1 InfoFrame Packet Checksum. 0x00 7:0 SP_ISRC1_PB1–15 R ISRC1 InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_ISRC1_HEADERL to be 0x05. Other values are from the HDMI Specification version 1.4 Table 5-20. It is up to the software to verify that the checksum matches the value in the ISRC1 InfoFrame sent by the HDMI transmitter.

Selected Pipe ISRC2 InfoFrame Registers Address:Offset Name Page Type 0x54:0x72 SP_ISRC2_HEADERL 7 PWD 0x54:0x73 SP_ISRC1_HEADERH 7 PWD 0x54:0x74 SP_ISRC2_LENGTH 7 PWD 0x54:0x75-0x84 SP_ISRC2_PB1 7 PWD Bit Bit Label R/W Description Default 7:0 SP_ISRC2_HEADERL R ISRC2 InfoFrame Packet Type Code. 0x00 7:0 SP_ISRC2_HEADERH R ISRC2 InfoFrame Packet Version Code. 0x00 7:0 SP_ISRC2_LENGTH R ISRC2 InfoFrame Packet Length. 0x00 7:0 SP_ISRC2_PB0 R ISRC2 InfoFrame Packet Checksum. 0x00 7:0 SP_ISRC2_PB1–15 R ISRC2 InfoFrame Packet Data Bytes. 0x00 Note: The HDMI Specification defines SP_ISRC2_HEADERL to be 0x06. Other values are from the HDMI Specification version 1.4 Table 5-22. It is up to the software to verify that the checksum matches the value in the ISRC2InfoFrame sent by the HDMI Transmitter.

Main Pipe Video Input Format This set of registers contains video input format status information for the port that is selected as the main pipe. These registers should be read when the muted interrupt bit (0x50:0x07[6]) is detected.

Main Pipe Video Input Format Register Group

Main Pipe Video Horizontal Active Pixel Count Registers Address:Offset Name Page Type 0x52:0xD9 MP_H_RES_ACTIVEL 6 PWD 0x52:0xDA MP_H_RES_ACTIVEH 6 PWD Bit Bit Label R/W Description Default The width of the active display area. 12:0 MP_H_RES_ACTIVE R Measured by counting the pixel clocks from the video input to 0 the main pipe. The unit of measure is pixels.

Main Pipe Video Horizontal Blank Pixel Count Registers Address:Offset Name Page Type 0x52:0xDB MP_H_RES_BLANKL 6 PWD 0x52:0xDC MP_H_RES_BLANKH 6 PWD Bit Bit Label R/W Description Default The width of the display blanking measured from the video 11:0 MP_H_RES_BLANK R input to the main pipe. 0x000 The unit of measure is pixels.

Main Pipe Video Vertical Active Line Count Registers Address:Offset Name Page Type 0x52:0xDD MP_V_RES_ACTIVEL 6 PWD 0x52:0xDE MP_V_RES_ACTIVEH 6 PWD Bit Bit Label R/W Description Default The height of the active display area. 11:0 MP_V_RES_ACTIVE R Measured by counting lines from the video input to the main 0x000 pipe. The unit of measure is lines.

Main Pipe Video Vertical Blank Line Count Register Address:Offset Name Page Type 0x52:0xDF MP_V_RES_BLANK 6 PWD Bit Bit Label R/W Description Default The height of the display blanking measured from the video 7:0 MP_V_RES_BLANK R input to the main pipe. 0x00 The unit of measure is lines.

Main Pipe Video Format Register Address:Offset Name Page Type 0x52:0xE0 MP_VFORMAT 6 PWD Bit Bit Label R/W Description Default Main Pipe Video Format. 7 MP_VFORMAT R 0 – Noninterlaced 0 1 – Interlaced 6:0 RSVD — Reserved —

Main Pipe Color Depth Register Address:Offset Name Page Type 0x52:0xE2 MP_COLOR_DEPTH 6 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved. — Main input port Color Depth information extracted from AVI InfoFrame. 0100 – 8-bit 3:0 COLOR_DEPTH R 0101 – 10-bit 0000 0110 – 12-bit 0111 – 16-bit Other values are not valid.

Main Pipe General Control Packet (GCP) Status Register Address:Offset Name Page Type 0x50:0xE8 MP_GCP_STATUS 5 PWD Bit Bit Label R/W Description Default 7 RSVD — Reserved. — MP Resolution Stable. Any change in this bit sets interrupt bit 0x50:0x09[3]. 6 MP_RES_STABLE R — 0 – Not stable 1 – Stable 5 RSVD — Reserved — 4 MP_NEW_GCP R MP new GCP indicator. — 3 MP_GCP_CLEAR_MUTE R MP GCP CLEAR MUTE indicator. — 2 MP_GCP_SET_MUTE R MP GCP SET MUTE indicator. — 1:0 RSVD — Reserved — Note: Bit 6 is used by InstaPrevue to determine when the display resolution is stable so that the software can change the InstaPrevue register values. Select Port Video Input Format This set of registers contains video input format information for the port specified in the SP_PORT_SEL register. They are provided to extract the InfoFrame data from the device attached to selected port so that the upstream device can be configured correctly. To get the InfoFrame data from the AIF/AVI/VSIF of either of the selected pipes, first write the SP_PORT_SEL register (0x50:7C[2:0]) with the desired port. Then read the corresponding SP_VALID register for the valid bit (bit[0]) to be set. Clear the last 4 frames of the extracted packet data (0x54:0x20), read the length value from the desired selected pipe InfoFrame.Then using that length, perform a block read from the desired InfoFrame buffer.

Packet Capture Port Select Register Address:Offset Name Page Type 0x50:0x7C PORT_SEL 5 PWD Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — PIPE selection to read out ACP, SPD, ISRC1, and ISRC2 for either Main Pipe (MP) or Roving Pipe (SP). 5 RD_PIPE_SEL R/W 0 0 – Data comes from Main Pipe 1 – Data comes from Roving (Sub) Pipe 0 – No Clear; the previous value remains there 4 PACKET_RD_NO_PWR R/W 1 1 – Valid bit of AIF/AVI/VSI of unplugged port is cleared to 0 0 – No masking. In DVI mode, valid of AVI will be set due to no AVI for four frames event. The contents of AVI will be 3 PACKET_RD_MASK_DVI R/W all 0s including the header part. 1 1 – Valid bit of AIF/AVI/VSI of selected port is masked to 0 in DVI mode Chooses the InfoFrame capture port. 000 –Port 0 2:0 PACKET_RD_PORT_SEL R/W 001 – Port 1 000 010 – Port 2 011 – Port 3

Port Video Horizontal Active Line Count Registers Address:Offset Name Page Type 0x50:0xCC SP_H_RES_ACTIVEL 5 PWD 0x50:0xCD SP_H_RES_ACTIVEH 5 PWD Bit Bit Label R/W Description Default The width of the active display area. Measured by counting the TMDS clocks from the video input to the main pipe. The unit of measure is clocks. This is only accurate for 8-bit DVI and HDMI. For Deep Color use the 12:0 SP_H_RES_ACTIVE R formula: 0 Color depth 10-bit: (hres • 8) /5 Color depth 12-bit: (hres • 2) /3 Color depth 16-bit: (hres • 2)

Port Video Horizontal Blank Line Count Registers Address:Offset Name Page Type 0x50:0xCE SP_H_RES_BLANKL 5 PWD 0x50:0xCF SP_H_RES_BLANKH 5 PWD Bit Bit Label R/W Description Default The width of the display blanking measured from the video 11:0 SP_H_RES_BLANK R input to the main pipe. 0x000 The unit of measure is clocks.

Port Video Vertical Active Line Count Registers Address:Offset Name Page Type 0x50:0xD0 SP_V_RES_ACTIVEL 5 PWD 0x50:0xD1 SP_V_RES_ACTIVEH 5 PWD Bit Bit Label R/W Description Default The height of the active display area. 11:0 SP_V_RES_ACTIVE R Measured by counting lines from the video input to the main 0x000 pipe. The unit of measure is lines.

Port Video Vertical Blank Line Count Register Address:Offset Name Page Type 0x50:0xD2 SP_V_RES_BLANK 5 PWD Bit Bit Label R/W Description Default The height of the display blanking measured from the video 7:0 SP_V_RES_BLANK R input to the main pipe. 0x00 The unit of measure is lines.

EDID SRAM Control The SiI9687A/SiI9617 device contains Static Random Access Memory (SRAM) to contain the EDID for each receiver port. The SRAM is accessible externally through the EDID DDC lines of each receiver port. Each receiver port is connected to its own SRAM and therefore can contain a unique EDID. Generally, the EDID contents are the same, but it is possible to create truly separate EDIDs for each port if required. The SiI9687A/SiI9617 device also contains enough Non-Volatile Random Access Memory (NVRAM) to support a main HDMI EDID of 256 bytes (two blocks), and a separate VGA EDID of 128 bytes (one block). The NVRAM HDMI EDID is loaded into selected port SRAMs at the device boot time. During the load process, the CEC physical address locations and checksums for each individual port are loaded from values stored separately in another section of the NVRAM called the Boot Data section (64 bytes). This process allows a unique EDID with the same base HDMI capabilities for each receiver port.

EDID Read/Write Register Group The registers in this group are used to read and write individual port SRAMs. The same procedure is used for both standard and dual modes. Figure 6 illustrates the procedure for writing to SRAMs. When writing to these SRAMs, disable external DDC access for the duration of the write operation to prevent a source from reading incorrect data.

1. If writing, deassert HPD and disable EDID DDC access for the selected port to prevent the source from accessing the EDID using DDC. 2. Select the FIFO in the EDID_FIFO_SEL Select register (0xE0:0x04). 3. Write the starting address to the EDID_FIFO_ADDR register (0xE0:0x02). 4. Read from or write to the EDID_FIFO_DATA register (0xE0:0x03). The information is stored in the SRAM memory location specified by the EDID_FIFO_ADDR register. The address is automatically incremented. 5. The host can continue to read or write the EDID_FIFO_DATA register to sequentially access the SRAM data. 6. When finished writing a new EDID, enable EDID DDC access and reassert the HPD to force the source to reread the new EDID.

Figure 6. Reading or Writing a Receiver Port SRAM

FIFO Address Register Address:Offset Name Page Type 0xE0:0x02 EDID_FIFO_ADDR 9 AON Bit Bit Label R/W Description Default Address pointer for the EDID SRAM specified in register 0xE0:0x04. The value of the FIFO address register represents the currently addressed SRAM location. The SRAM has no default values 7:0 FIFO_ADDR R/W 0x00 and must be loaded with the appropriate data through the local I2C interface or from NVRAM. For every read or write from the data register (0xE0:0x03), the address is incremented by one and wraps around from 0xFF to 0x00. Note: Each time the host wants to access a different EDID SRAM, the new FIFO must be selected using 0xE0:0x04 prior to writing the FIFO address into this register.

FIFO Data Register Address:Offset Name Page Type 0xE0:0x03 EDID_FIFO_DATA 9 AON Bit Bit Label R/W Description Default This is the data register for the SRAM memory addressed by the FIFO_ADDR register. Write the starting address to the FIFO_ADDR register. 7:0 FIFO_DATA R/W Write data to the FIFO_DATA register. The address is 0x00 automatically incremented. The host can continue to write to the data register to sequentially load the EDID RAM.

FIFO Select Register Address:Offset Name Page Type 0xE0:0x04 EDID_FIFO_SEL 9 — Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — 5 BOOT_DATA R/W These bits control FIFO access to the EDID SRAM for each 0 4 SEL_EDID_VGA R/W port and the boot data SRAM. 0 3 SEL_EDID_CH3 R/W When the bit for a channel is set to 1, the corresponding SRAM 0 is selected for FIFO read/write operations. 2 SEL_EDID_CH2 R/W 0 1 SEL_EDID_CH1 R/W 0 0 SEL_EDID_CH0 R/W 0 Note: Only one bit in this register should be set at any one time.

NVRAM Interface

NVRAM Power-up Load Sequence When the SiI9687A/SiI9617 device is powered up (power applied to the always-on domain), the NVRAM can be used to initialize certain SiI9687A/SiI9617 registers and load the EDID SRAMs. Figure 7 enumerates the sequence performed by the device during a boot operation. Figure 8 on page 53 shows a block diagram of the relationship between NVRAM and EDID SRAMs.

1. Read offset 0x00 of the boot data NVRAM (extra 64 bytes). If the value is not 0xAA, no further action is taken. 2. Load device registers from the boot data. Note that the boot data SRAM is NOT loaded at this time, just the applicable registers. 3. Read offset 0x01 of the boot data NVRAM. If the value is not 0x55, no further action is taken. 4. Read register NVM_STAT2 (0xE0:0x12) to determine which EDID SRAMs to load with the NVRAM HDMI EDID. 5. Load each selected EDID SRAM (from register NVM_STAT2) with the NVRAM HDMI EDID. 6. Read register NVM_STAT1 (0xE0:0x07) to determine which EDID SRAMs to load with the NVRAM VGA EDID. 7. Load each selected EDID SRAM (from register NVM_STAT1) with the NVRAM VGA EDID. 8. The same sequence is performed for a BSM Init (0xE0:0x08[0]).

Figure 7. Reading or Writing a Receiver Port SRAM

Port SRAM Transfer Logic Register Storage NVRAM

Program EDID NVRAM PORT 0 EDID SRAM

Read NVRAM HDMI EDID PORT 1 NVRAM EDID HDMI SRAM EDID and Transfer Process VGA for each port. EDID PORT 2 EDID SRAM 1. Read EDID from NVRAM Read NVRAM VGA EDID

2. If HDMI EDID, substitute CEC PORT 3 Physical Address EDID SRAM 3. If HDMI EDID, substitute checksum CEC 4. Load into selected Address Port SRAM & Checksum Registers

Boot Load Select VGA Register EDID SRAM

NVRAM Other Boot BOOT DATA Loaded Registers

Read Boot Data NVRAM BOOT DATA SRAM Program Boot Data NVRAM

Loaded at Boot time (power on reset or command) NVRAM/EDID SRAM DATA FLOW Loaded at Boot time (power on reset or command) if selected

Figure 8. Boot Time NVRAM/EDID SRAM Data Flow

NVRAM Programming Procedure The SiI9687A/SiI9617 NVRAM is programmed from data contained in the EDID SRAM for Port 0. Use the following sequence to program the NVRAM.

Prepare a New HDMI EDID 1. Initialize an array of 64 bytes to 0. Name the array bootData. 2. Generate required EDID and HDMI EDID extension block (256 bytes total), including physical address field. 3. Save the EDID array offset of the physical address field in offset 0x0A of the bootData array. 4. Save physical address in offsets 0x0C and 0x0D of the bootData array. 5. Calculate checksum of the entire 256 bytes and place in location 255 of the EDID array. Save the checksum in offset 0x1C of the bootData array. 6. Repeat steps 4 and 5 four times. Change the physical address in the EDID array and increment the bootData array offsets appropriately. See Appendix B – NVRAM Boot Data Memory Layout on page 93 for the boot data block layout.

Prepare a New VGA EDID 1. Generate the required VGA EDID.

Prepare Boot Data Array 1. Determine which EDID SRAMs are to be loaded from the NVRAM at power up and set the corresponding bits in register 0xE0:0x12. Copy into offset 0x03 of the bootData array. 2. Determine which ports will have HPD controlled by the hardware and set the corresponding bits in register 0xE0:0x13. Copy into offset 0x04 of the bootData array. 3. Write 0x00 into offsets 0x05 and 0x06 of the bootData array. 4. Write 0xAA into offset 0x00 of the bootData array. 5. Write 0x55 into offset 0x01 of the bootData array.

Program Boot Data Array into NVRAM 1. Load the boot data SRAM with the bootData array following the steps described in the EDID Read/Write Register Group section on page 51. 2. Write 0x04 to the NVRAM Command Register (0xE0:0x05) to start the internal programming sequence. 3. Monitor the NVM_CMD_DONE bit of the NVRAM Command Status Register (0xE0:0x07). When this bit is set, the NVRAM programming operation is complete. This operation can take a maximum of 320 ms.

Optional BOOT DATA Verification Step 1. Write 0x06 to the NVRAM Command Register (0xE0:0x05) to read the boot data from the NVRAM into the boot data SRAM. 2. Monitor the NVM_CMD_DONE bit of the NVRAM Command Status Register (0xE0:0x07). When this bit is set, the NVRAM read operation is complete. This operation can take a maximum of 32 µs. 3. Read the boot data SRAM into the bootData array following the steps described in Figure 6 on page 51. 4. Compare bootData array to the source boot data information.

Program HDMI EDID into NVRAM 1. Load Port 0 EDID SRAM with the EDID table to be programmed into NVRAM following the steps described in Figure 6 on page 51. 2. Write 0x03 to the NVRAM Command Register (0xE0:0x05) to start the internal programming sequence. 3. Monitor the NVM_CMD_DONE bit of the NVRAM Command Status Register (0xE0:0x07). When this bit is set, the NVRAM programming operation is complete. This operation can take a maximum of 1280 ms.

Program VGA EDID into NVRAM 1. Load Port 0 EDID SRAM with the VGA EDID table to be programmed into NVRAM following the steps described in Figure 6 on page 51. 2. Write 0x13 to the NVRAM Command Register (0xE0:0x05) to start the internal programming sequence. 3. Monitor the NVM_CMD_DONE bit of the NVRAM Command Status Register (0xE0:0x07). When this bit is set, the NVRAM programming operation is complete. This operation can take a maximum of 640 ms.

Optional EDID Verification Step 1. Write 0x01 to the NVRAM Boot State Machine Initialization Register (0xE0:0x08). This function reads the boot data NVRAM contents into the appropriate SiI9687A/SiI9617 registers and then loads the port SRAMs selected by register (0xE0:0x12) from the NVRAM EDID data. During the load, the port processor substitutes the CEC physical address and EDID checksum for each port into the port SRAM. 2. Monitor the NVRAM Boot Status Register (0xE0:0x09) to determine when the operation is complete. This operation can take a maximum of (128 times the number of EDIDs loaded) µs. 3. Check the NVRAM Boot Status Register (0xE0:0x09) error bits to make sure the operation completed successfully. 4. Read the Port 0 SRAM following the steps described in Figure 6 on page 51 and compare to the original EDID source data. Note that there may be differences in the CEC physical address field and checksum field, depending on the values in the original EDID source data.

NVRAM Control Register Group

NVRAM Command Register Address:Offset Name Page Type 0xE0:0x05 NVM_COMMAND 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — NVRAM Command. 00011 – Program NVRAM HDMI EDID 00100 – Program Boot Data 00101 – Load NVRAM HDMI EDID into EDID SRAM(s) 00110 – Load NVRAM Boot Data into Boot Data SRAM 4:0 NVM_CMD R/W 00000 00111 – Load NVRAM VGA EDID into EDID SRAM(s) 10011 – Program NVRAM VGA EDID After writing to this register, wait for the command to complete by monitoring the NVRAM Command Status Register (0xE0:0x07).

NVRAM Load Select Register Address:Offset Name Page Type 0xE0:0x06 NVM_COPYTO 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — 4 NVM_COPYTO_VGA R/W These bits select which EDID SRAMs to update when the Load 0 3 NVM_COPYTO_3 R/W NVRAM EDID to EDID SRAM command (0xE0:0x05) is 0 written. Multiple EDIDs can be loaded simultaneously by 2 NVM_COPYTO_2 R/W 0 setting multiple bits. 1 NVM_COPYTO_1 R/W 0 0 NVM_COPYTO_0 R/W 0

NVRAM Boot State Machine Initialization Register Address:Offset Name Page Type 0xE0:0x08 BSM_INIT 9 AON Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Writing a 1 to this bit begins the NVRAM boot sequence which loads the EDID SRAMs and the boot data registers. This 0 BSM_INIT R/W 0 sequence is identical to that performed during power up. This bit clears automatically.

NVRAM Boot Status Register Address:Offset Name Page Type 0xE0:0x09 BSM_STAT 9 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — 3 BOOT_PROGRESS R 1 – NVRAM boot in progress 0 1 – NVRAM boot done. When set, this bit initiates a BOOT 2 BOOT_DONE R 1 DONE interrupt. See 0xB0:0x90[6] 1 – EDID Error (an ECC error occurred during an EDID copy 1 EDID_ERR R 0 operation) 1 – Boot Error (an ECC error occurred during the last boot 0 BOOT_ERR R 0 operation)

NVRAM Status Register Address:Offset Name Page Type 0xE0:0x10 NVM_STAT 9 AON Bit Bit Label R/W Description Default 7:2 RSVD — Reserved — Set to 1 if 0xAA was loaded from Boot Data NVRAM 1 NVM_BOOT_VALID R 0 location 0 at last boot. Set to 1 if 0x55 was loaded from Boot Data NVRAM 0 NVM_EDID_VALID R 0 location 1 at last boot.

NVRAM Status Register 1 Address:Offset Name Page Type 0xE0:0x07 NVM_STAT1 9 AON Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 VGA_EDID_VGA R NVRAM VGA EDID Boot information. 0 These bits indicate which SRAMs received a copy of the VGA 5 VGA_EDID_P3 R EDID in NVRAM during the last boot operation (power-up, 0 reset, or BSM_INIT command). 4 VGA_EDID_P2 R Selecting the SRAMs that will receive a copy of the NVRAM 0 VGA EDID at boot time is done by programming the NVRAM 3 VGA_EDID_P1 R boot data NVM_VGA_COPY location. One or all of these bits 0 may be set, but should not conflict with the HDMI_EDID_Px bits set in the NVM_STAT2 register. 2 VGA_EDID_P0 R 0 – NVRAM VGA EDID is NOT copied to this port SRAM 0 1 – NVRAM VGA EDID is copied to the corresponding port SRAM 1 RSVD — Reserved — NVM Command Status. 0 NVM_CMD_DONE R 0 – A NVRAM command is in progress 1 1 – The last NVRAM command written to the NVM_COMMAND register has completed Note: Bits 6:2 of this register are loaded from NVRAM at boot time from the NVRAM boot data NVM_VGA_COPY location.

NVRAM Status Register 2 Address:Offset Name Page Type 0xE0:0x12 NVM_STAT2 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — 4 HDMI_EDID_VGA R NVRAM HDMI EDID Boot Information. 0 These bits indicate which SRAMs received a copy of the 3 HDMI_EDID_P3 R HDMI EDID in NVRAM during the last boot operation 0 (power-up, reset, or BSM_INIT command). 2 HDMI_EDID_P2 R Selecting the SRAMs that will receive a copy of the NVRAM 0 HDMI EDID at boot time is done by programming the 1 HDMI_EDID_P1 R NVRAM boot data NVM_BOOT_COPY location. One or all 0 of these bits may be set, but should not conflict with the VGA_EDID_Px bits set in the NVM_STAT1 register. 0 HDMI_EDID_P0 R 1 – NVRAM HDMI EDID is copied to the corresponding port 0 SRAM Note: This register is loaded from NVRAM at boot time from the NVRAM boot data NVM_BOOT_COPY location.

NVRAM CEC Physical Address Offset Register Address:Offset Name Page Type 0xE0:0x1A CECPA_ADDR 9 AON Bit Bit Label R/W Description Default The offset into the EDID data where the CEC physical address is stored. The CEC physical address in the NVRAM EDID is replaced 7:0 CECPA_ADR R with a physical address from the CEC physical address 0x00 registers (0xE0:1C-25) whenever the EDID data is copied from NVRAM to the corresponding SRAM. This register contains the offset into the EDID of the data to be replaced. Notes: This register is loaded from NVRAM at boot time.

CEC Physical Address Registers Address:Offset Name Page Type 0xE0:0x1C CECPAD_L_CH0 9 AON 0xE0:0x1D CECPAD_H_CH0 9 AON 0xE0:0x1E CECPAD_L_CH1 9 AON 0xE0:0x1F CECPAD_H_CH1 9 AON 0xE0:0x20 CECPAD_L_CH2 9 AON 0xE0:0x21 CECPAD_H_CH2 9 AON 0xE0:0x22 CECPAD_L_CH3 9 AON 0xE0:0x23 CECPAD_H_CH3 9 AON Bit Bit Label R/W Description Default The 16-bit physical CEC address for corresponding EDID port. The physical address in the NVRAM EDID is replaced by this 15:0 CECPAD_CH0-3 R 0x0000 value whenever the EDID data is copied from NVRAM to the corresponding SRAM. Notes: These registers are loaded from NVRAM at boot time.

CEC Checksum Registers Address:Offset Name Page Type 0xE0:0x2C CHECKSUM_CH0 9 AON 0xE0:0x2D CHECKSUM_CH1 9 AON 0xE0:0x2E CHECKSUM_CH2 9 AON 0xE0:0x2F CHECKSUM_CH3 9 AON Bit Bit Label R/W Description Default The 8-bit checksum for the corresponding EDID port. The checksum in the EDID is replaced with this value whenever the 7:0 CHECKSUM_CH0-3 R 0x00 EDID data is copied from NVRAM to the corresponding SRAM. Notes: These registers are loaded from NVRAM at boot time.

Switch/Receiver Interrupt Control and Status The SiI9687A/SiI9617 switch and receiver feature supports the generation of interrupts for a large variety of conditions that help the software keep the system running smoothly. Although there is a large number of interrupts supported, most are not used in normal operation so the interrupt system will not get overloaded. There are three groups of interrupts. The Port Status group contains interrupts for changes in sync, clock, hot-plug, and other conditions. The InstaPort group contains interrupts associated with the InstaPort feature, such as authentication status, mute conditions, and Hot Plug Event (HPE) status. The Packet group contains interrupts for HDMI InfoFrame condition changes. An interrupt bit is set when the associated SiI9687A/SiI9617 feature interrupt has been triggered. If the interrupt bit is clear, no interrupt occurred on that subsystem. Once an interrupt is triggered, it remains set in the status register until cleared by writing a 1 to the bit.

Port Status Interrupt Enable and Status Register Group

Interrupt Status Register 2 Address:Offset Name Page Type 0xB0:0x72 INT_STATUS_2 0 AON 0xB0:0x76 INT_ENABLE_2 0 AON Bit Bit Label R/W Description Default Main Pipe HDMI Mode Change. 7 HDMI_MODE R/W Set to 1 when the main pipe selected input stream changes from 0 DVI to HDMI or HDMI to DVI. 6 RSVD-W0 W Reserved 0 Software-induced Interrupt. 5 SW_INT R/W 0 Set to 1 when 0xB0:0x79[3] is set by software. Main Pipe Clock Detect Change. 4 CKDT_INT R/W The state of the clock detect status for the selected pipe 0 changed. Main Pipe Sync Detect Change. 3 SCDT_INT R/W The state of the sync detect status for the selected pipe 0 changed. 2:0 RSVD-W0 W Reserved 000 Note: Interrupts in this register also set bit 1 of the Interrupt Group State 0 Register (0xB0:0x70[1]).

Interrupt Status Register 5 Address:Offset Name Page Type 0xB0:0x7B CH0_INTR5 0 AON 0xB0:0x7D CH0_INTR5_MASK 0 AON Bit Bit Label R/W Description Default 7 P3_CKDT R/W Set to 1 if Port 3 CKDT state changes. Write 1 to clear. 0 6 P2_CKDT R/W Set to 1 if Port 2 CKDT state changes. Write 1 to clear. 0 5 P1_CKDT R/W Set to 1 if Port 1 CKDT state changes. Write 1 to clear. 0 4 P0_CKDT R/W Set to 1 if Port 0 CKDT state changes. Write 1 to clear. 0 Set to 1 if R3PWR5V or CBUS3 connection changes. Write 1 3 R3PWR5V R/W 0 to clear. Set to 1 if R2PWR5V or CBUS2 connection changes. Write 1 2 R2PWR5V R/W 0 to clear. Set to 1 if R1PWR5V or CBUS1 connection changes. Write 1 1 R1PWR5V R/W 0 to clear. Set to 1 if R0PWR5V or CBUS0 connection changes. Write 1 0 R0PWR5V R/W 0 to clear. Note: Interrupts in this register also set bit 6 of the Interrupt Group State 0 Register (0xB0:0x70[6]).

Interrupt Status Register 6 Address:Offset Name Page Type 0xB0:0x7C CH0_INTR6 0 AON 0xB0:0x7E CH0_INTR6_MASK 0 AON Bit Bit Label R/W Description Default 7:1 RSVD-W0 W Reserved 0000000 Set to 1 if PWR5V or CBUS connection changes at selected 0 SPPWR5V R/W 0 port. Write 1 to clear. Note: Interrupts in this register also set bit 7 of the Interrupt Group State 0 Register (0xB0:0x70[7]).

InstaPort Interrupt Enable and Status Register Group InstaPort interrupts are triggered by changes in the state of authentication of a port or the state of the automatic hot plug event controller. Interrupts in this group also set bit 3 of the Interrupt Group State 0 Register (0xB0:0x70[3]).

InstaPort Interrupt Status Register 1 Address:Offset Name Page Type 0x50:0x01 INT_STATUS_IP1 5 PWD 0x50:0x15 INT_ENABLE_IP1 5 PWD Bit Bit Label R/W Description Default 7:6 RSVD-W0 W Reserved 00 Roving/Subpipe HPE Trigger Condition is Met. The port processor has determined that the port attached to the sub pipe requires a Hot Plug Event (HPE) and the port is configured for MHL. The software must send the appropriate 5 HPE_RP R/W MHL hot plug message instead of performing a physical hot 0 plug; see the InstaPort section on page 30 for details. If this interrupt is enabled and triggered, automatic monitoring of background ports will not continue until the software has cleared the interrupt. 4 RSVD-W0 W Reserved 0 Main Pipe HPE Trigger Condition is Met. The port processor has determined that the port attached to the main pipe requires a Hot Plug Event (HPE) and the port is 3 HPE_MP R/W 0 configured for MHL. The software must send the appropriate MHL hot plug message instead of performing a physical hot plug; see the InstaPort section on page 30 for details. 2:0 RSVD-W0 W Reserved 000

InstaPort Interrupt Status Register 2 Address:Offset Name Page Type 0x50:0x05 INT_STATUS_IP2 5 PWD 0x50:0x19 INT_ENABLE_IP2 5 PWD Bit Bit Label R/W Description Default 7 AUTH_CHG_P3 R/W HDCP AUTH State Change to 1 (active). 0 6 AUTH_CHG_P2 R/W There was an HDCP AUTH state change on the corresponding 0 5 AUTH_CHG_P1 R/W receiver port. 0 4 AUTH_CHG_P0 R/W 0 Main Pipe DECRYPT State Change. 3 MP_DECRYPT_CHG R/W There was a state change (active or inactive) on the port 0 connected to the main pipe. 2 HDCP_GOOD_CHG R/W The HDCP_GOOD status of the selected port has changed. 0 1:0 RSVD-W0 W Reserved 00 Note: Port 4 AUTH_CHG_P interrupts are located in register 0x50:0x06[1:0]

InstaPort Interrupt Status Register 3 Address:Offset Name Page Type 0x50:0x08 INT_STATUS_IP3 5 PWD 0x50:0x1C INT_ENABLE_IP3 5 PWD Bit Bit Label R/W Description Default 7 MP_MUTE_CHG R/W Main pipe mute status has changed. 0 6:0 RSVD-W0 W Reserved 0000000 Note: Main pipe un-mute and mute interrupts are located in register 0x50:07[7:6]

InstaPort Interrupt Status Register 4 Address:Offset Name Page Type 0x50:0x09 INT_STATUS_IP4 5 PWD 0x50:0x1D INT_ENABLE_IP4 5 PWD Bit Bit Label R/W Description Default 7:4 RSVD-W0 W Reserved 0000 3 MP_RES_STABLE_CHG R/W Main pipe resolution stable flag has changed. 0 2:0 RSVD-W0 W Reserved 000

Packet Interrupt Enable and Status Register Group Packet interrupts are triggered by various changes in the HDMI control packet traffic. Interrupts are triggered when a new (changed) packet of each type has been received, when certain packets have not been received for at least four frames, and also when certain packet specific content bits have changed, such as mute/unmute. Interrupts in this group also set Bit 3 of the Interrupt Group State 0 Register (0xB0:0x70[3]).

Packet Interrupt Status Register 2 Address:Offset Name Page Type 0x50:0x03 PA_INTR3 5 PWD 0x50:0x17 PA_INTR3_MASK 5 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — MP HPD event end time reaches. Asserted if set to 1. Write 1 3 MP_EVENT_END R/W 0 to clear. 2:0 RSVD — Reserved —

Packet Interrupt Status Register 3 Address:Offset Name Page Type 0x50:0x06 INT_STATUS_P3 5 PWD 0x50:0x1A INT_ENABLE_P3 5 PWD Bit Bit Label R/W Description Default 7 MP_NEW_VSI R/W The main pipe has received a new (changed) packet for the 0 6 MP_NEW_AVI R/W corresponding type. 0 5 MP_NEW_AIF R/W 0 4 MP_NO_VSI R/W The main pipe has not received a packet of the corresponding 0 3 MP_NO_AVI R/W type for at least four frames. 0 2 MP_NO_AIF R/W 0 1:0 RSVD-W0 W Reserved 00

Packet and InstaPort Interrupt Status Register 4 Address:Offset Name Page Type 0x50:0x07 INT_STATUS_P4 5 PWD 0x50:0x1B INT_ENABLE_P4 5 PWD Bit Bit Label R/W Description Default Main Pipe Unmute Condition is Met. 7 MP_UNMUTE R/W The InstaPort logic has determined that the port attached to the 0 main pipe is stable and can be unmuted. Main Pipe Unmute Condition is Met. 6 MP_MUTE R/W The InstaPort logic has determined that the port attached to the 0 main pipe is not stable and should be muted. 5:0 RSVD-W0 W Reserved 000000

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 61 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. InstaPrevue InstaPrevue provides previews of preauthenticated TMDS (HDMI/DVI/MHL) background input ports by overlaying small subframes on top of the selected main port video. The subfames can have size up to 256 x 144 pixels. With this feature, DTV makers can provide the end user with a more intuitive user interface for changing or selecting among various live sources. The update rate for each window is close to real time and offers a good preview of the sources not currently being viewed. The window animation feature can enhance user experience, allowing for a visual effect of smooth movement of subframes on the screen. In this section, the term window indicates an InstaPrevue subframe display window.

InstaPrevue Basics

Supported Video Modes InstaPrevue supports all 2D video formats defined in HDMI 1.3a and CEA-861-D Specifications, including variations in progressive/interlaced video and screen resolutions up to 1920 x 1080. The 4K x 2K resolution is not supported. Pixel repetition modes of 1 or 3 (2 or 4 pixels) are supported as well as Deep Color up to 12 bpp (Only the 8 MSBs are captured and displayed). InstaPrevue is compatible with RGB, YCbCr 4:4:4, and YCbCr 4:2:2 color formats. InstaPrevue 3D resolutions are supported in the frame packing mode only. When the main display is in 2D mode, background 3D sources are displayed using only the left field image. When the main display is in 3D mode, background 2D sources are displayed by reusing the 2D frame twice, one for the left 3D video frame and the other for the right 3D video frame. Background 3D sources are displayed on the 3D main display the same way as that of the 2D sources, using the left 3D frame. By controlling the horizontal offset of subframes in the left video frame and the right video frame, the 3D depth of the preview window image can be changed (see 0xFA:0x42–0xFA:0x46) to make the TV user feel more comfortable in manipulating preview images while watching a 3D video.

Display Modes InstaPrevue operates in one of the three modes:  The ALL preview mode displays one to three selectable background source windows regardless of the source status.  The ACTIVE mode displays only the windows for which there is an active, authenticated background video source.  The SELECTED mode displays a single window with a background source selected by the user and is intended as a picture-in-picture type preview.

All and Active Display Modes InstaPrevue operates using the InstaPort background authentication logic to sample video frames from each port in turn as it is visited to maintain or initiate port authentication. InstaPrevue window update is not at the full port video refresh rate. An InstaPrevue window is updated each time InstaPort visits its associated port, which may be at various intervals depending on how many ports are presented and authenticated. If InstaPrevue ACTIVE mode is chosen,, nonauthenticated, nonconnected, or unsupported format ports are not displayed and are skipped over in the update cycle of the window. The InstaPrevue ALL mode displays a blank window of a specified color (see 0xFA:0x93–0xFA:0x95) if the corresponding port is not authenticated, not connected, or its format is not supported. Because InstaPrevue must be able to capture at least one frame of video at each background port, the normal InstaPort background authentication speed must be slowed down to allow more time at each port. This is done by modifying the InstaPort Authenticated Port Time Out Register (0x50:0x50-0x50: 0x53) value from the default 100 ms to over 525 ms while InstaPrevue is active.

Selected Port (PIP) Display Mode The InstaPrevue Selected mode may be used to provide Picture-in-Picture (PIP) support for the TMDS inputs of the SiI9687A/SiI9617 device. Because the PIP display uses the same background logic used by the ALL and ACTIVE modes, background roving must be disabled to keep the PIP display constant. Therefore, InstaPort is not active when PIP mode is used. To display the PIP image, perform the following:  Stop the background roving action by setting the background pause bit.  Set the coordinates of all the preview windows to the same location on the main display.  Select the background port to display the same image as that of the PIP. Because only one image is displayed, a larger window size may be used.

InstaPrevue Programming (SiI9687A Only)

Preview Window Size and Position All InstaPrevue windows share a set of width and height registers. Depending on the number of active preview frames, the port processor automatically chooses one of the three sets of width and height registers, allowing the displayed windows to be larger if not all frames are active. In practice, all three sets are normally set to the same values for any number of active windows (frames) at any given time. Each set of width and height registers contains one width value for use when the SiI9687A device detects a 4:3 aspect ratio in the background video and a different width value for 16:9 aspect ratio images. Each set has only one height value that is used for both aspect ratios. Preview window size is limited by the number of active background sources and the main video resolution. The faster the main video frame rate, the less time that the port processor has to resize and merge preview video streams. See the InstaPrevue Width and Height Register Group on page 66 for register details and more programming information. Preview windows may be placed independently in any position on the main video image, with a few restrictions:  All windows can be placed starting on the same horizontal line (Y position). If they do not start on the same horizontal position, they should not overlap in the vertical range (even if the X dimension does not overlap).  For ALL or ACTIVE modes, preview windows must not overlap each other.  Ideally, preview windows should be aligned either horizontally or vertically.  Preview windows should not extend beyond the main horizontal or vertical display boundaries.  For YC422 video format, the X coordinate must be an even number.  For the SELECTED PORT (PIP) mode, the coordinates of all preview windows must be set to the same location. See the InstaPrevue X/Y Position Register Group on page 68 for register details and more programming information.

Main Video Resolution Changes When the main display resolution is changed, the software must change the window size and location registers to match the new display resolution. The SiI9687A device provides an interrupt (0x50:0x09[3]) to inform the software when the resolution has changed or become unstable. The SiI9687A device automatically disables the InstaPrevue windows, stops the internal compression engine, and freezes frame update if it detects an unstable main video signal. Therefore, the software must check this interrupt to update the size and location registers as necessary and reenable the InstaPrevue display.

InstaPrevue Control Register Group Figure 9 shows how to enter the InstaPrevue display mode from the InstaPort operation. Figure 10 illustrates how to enable PIP mode. Figure 11 shows how to return to the normal operation. All three examples assume that the width and height registers have been properly set. When changing the main video resolution, the image stream from the background port can be unstable. To avoid displaying invalid images to the main video, the software can set the SF_VLD_CLR bit (0xFA:0x47[7]) to freeze the preview window update and fill the displayed windows with the current background color. When the main pipe image is stable, this bit can be cleared to resume the normal operation.

1. 0x50:52 = 0x10 ; Slow down background authentication speed 2. 0xFA:48[0] = 1 ; Enable borders 3. 0xFA:04 = 0x00 ; Select ALL mode 4. 0xFA:4F[1:0] = 11 ; (Re)Start down scaler 5. 0xFA:47[7] = 0 ; Release InstaPrevue frame update 6. 0xFA:03[2:0] = 111 ; Enable all windows to display

Figure 9. Enable InstaPrevue ALL mode

1. 0x50:9F[7] = 1 ; Disable background roving 2. 0x50:A3[3:0] = port ; Select background port to display 3. 0xFA:48[0] = 1 ; Enable borders 4. 0xFA:04 = 0x03 ; Select PIP mode 5. 0xFA:4F[1:0] = 11 ; (Re)Start down scaler 6. 0xFA:47[7] = 0 ; Release InstaPrevue frame update 7. 0xFA:03[2:0] = 111 ; Enable all windows to display

All windows should be set to the same X/Y coordinates and size.

Figure 10. Enable InstaPrevue Selected (PIP) mode

1. 0xFA:03[2:0] = 0 ; Disable InstaPrevue window display 2. 0x50:9F[7] = 0 ; Enable background roving (if stopped) 3. 0xFA:47[7] = 1 ; Freeze InstaPrevue frame update 4. 0x50:52 = 0x03 ; Return background authentication to default speed

Figure 11. Disable InstaPrevue Display

InstaPrevue Window Enable Register Address:Offset Name Page Type 0xFA:0x03 IPV_WIN_ENABLE 3 PWD Bit Bit Label R/W Description Default 7:3 RSVD — Reserved — 2 IPV_WIN_EN_2 R/W Enable the corresponding preview window for display. 0 The actual decision to display a window depends on the 1 IPV_WIN_EN_1 R/W IPV_MODE value. 0 0 – Disable window display at all times 0 IPV_WIN_EN_0 R/W 1 – Enable window display depending upon IPV_MODE 0

InstaPrevue Mode Register Address:Offset Name Page Type 0xFA:0x04 IPV_MODE 3 PWD Bit Bit Label R/W Description Default 7:5 IPV_WIN_CNT R Number of InstaPrevue windows currently displayed. 000 4:2 RSVD — Reserved — InstaPrevue Display Mode. 00 – Display all subframes 1:0 IPV_MODE R/W 01 – Display active subframes 00 10 – Reserved 11 – Display only the selected subframe

InstaPrevue Window Status Register Address:Offset Name Page Type 0xFA:0x47 IPV_WIN_STATUS 3 PWD Bit Bit Label R/W Description Default Blank all Preview Windows. 7 IPV_FORCE_BLANK R/W 0 – Normal 0 1 – Force all preview windows to background color (0xFA:0x93 – 0xFA: 0x95) 6:5 RSVD — Reserved — Preview Window Status. 4:0 IPV_WIN_VALID R One bit for each window. If a bit is set, the corresponding — preview window contains active video.

InstaPrevue Control Register Address:Offset Name Page Type 0xFA:0x4F IPV_CTRL 3 PWD Bit Bit Label R/W Description Default 7:6 RSVD-W1 W Reserved 11 5:2 RSVD-W0 W Reserved 0000 Read: 0 – Normal operation 1 – Preview engine has stopped due to main display resolution change. 1 IPV_RESTART_CTL1 R/W Write: 0 0 – No action 1 – Restart the preview engine. This bit must be set after a main pipe resolution change has occurred. Must be written at the same time as the IPV_RESTART_CTL0 bit. Read: 0 – Error in scaler configuration 1 – Configured for proper scaling ratio 0 IPV_RESTART_CTL0 R/W Write: 1 0 – No action 1 – Restart the preview engine. This bit must be set after a main pipe resolution change has occurred. Must be written at the same time as the IPV_RESTART_CTL1 bit.

InstaPort Configuration Register 43 Address:Offset Name Page Type 0x50:0x9F IP_CONFIG_43 5 PWD Bit Bit Label R/W Description Default Disable Background Roving. This bit is intended to freeze the rotation of the subpipe between background ports for InstaPrevue Selected Port mode. 7 BGND_DISABLE R/W 0 It is not intended as a means of stopping InstaPort. 0 – Normal roving for RP 1 – Use RP as a second MP 6:0 RSVD-W1 W Reserved 1111111

InstaPort Configuration Register 47 Address:Offset Name Page Type 0x50:0xA3 IP_CONFIG_47 5 PWD Bit Bit Label R/W Description Default 7:4 RSVD-W0 W Reserved 0000 Input port selection when RP is used as a secondary pipe for InstaPrevue and roving is stopped. 0 – Port 0 3:0 PORT_SELECT R/W 0000 1 – Port 1 2 – Port 2 3 – Port 3

InstaPrevue Width and Height Register Group InstaPrevue maintains three sets of window size registers. The aspect ratio of the background input video affects the size of the preview video. For this reason, each set of size registers has two width registers, one for an aspect ratio of 16:9 and the other for an aspect ratio of 4:3. The SiI9687A device automatically selects the correct width register based on the incoming video aspect ratio. Each set of size registers contains only one height register, so the designer must choose the height value that best accommodates both aspect ratios. The three sets of window size registers represent the window size that will be used for the corresponding number of windows currently displayed. For example, if two windows out of the three contain active sources, they will be displayed using the values from window size set 2 (0xFA:0x06, 0xFA:0x0B, and 0xFA:0x10). If all background ports are active, window size set 3 will be used (0xFA:0x07, 0xFA:0x0C, and 0xFA:0x11). This feature allows the largest possible preview window size based on the number of sources in use. There is only one set of position registers for each window, so the location must be chosen carefully to ensure that no windows overlap in any of the three window sets. All the three sets of window size registers are needed for each main display resolution. To maintain appropriate window sizes for different main resolutions, all size registers must be reprogrammed every time the main resolution changes. The SiI9687A device provides an interrupt (0x50:0x09[3]) to inform the software when the resolution has changed. Table 9 on the next page shows an example of window sizes designed to produce the same size preview window no matter how many background sources are active and no matter what resolution the main display supports. Each set of values must be written into all the three window size register sets, using the appropriate values for the current main display resolution. The X/Y location registers must also be set appropriately for each resolution to maintain the same location on the display screen. Other values could be calculated to produce different results, such as large windows when only one or two background sources are active, and smaller windows if three sources are active.

Table 9. Preview Window Size Example Main Display Resolution Width 16 x 9 Width 4 x 3 Height 640 x 480 64 64 48 720 x 480 72 64 48 1280 x 720 128 96 72 1920 x 1080 192 104 98 The table width values must be divided by eight (shift right by three) before being written into the width registers, and the table height values must be divided by four (shift right by two) before writing to the height registers.

InstaPrevue Window 16:9 Width Registers Address:Offset Name Page Type 0xFA:0x05 IPV_1WIN_16x9_WIDTH 3 PWD 0xFA:0x06 IPV_2WIN_16x9_WIDTH 3 PWD 0xFA:0x07 IPV_3WIN_16x9_WIDTH 3 PWD Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — Width in pixels (divided by eight) of the preview window for 16:9 aspect ratio background sources. Each register specifies the width used when the corresponding number of preview 5:0 IPV_WIDTH_16x9 R/W 000000 windows are active. Usable range is 32 pixels to 256 pixels for a register range of 4 to 32.

InstaPrevue Window 4:3 Width Registers Address:Offset Name Page Type 0xFA:0x0A IPV_1WIN_4x3_WIDTH 3 PWD 0xFA:0x0B IPV_2WIN_4x3_WIDTH 3 PWD 0xFA:0x0C IPV_3WIN_4x3_WIDTH 3 PWD Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — Width in pixels (divided by eight) of the preview window for 4:3 aspect ratio background sources. Each register specifies the width used when the corresponding number of preview 5:0 IPV_WIDTH_4x3 R/W 000000 windows are active. Usable range is 32 pixels to 256 pixels for a register value range of 4 to 32.

InstaPrevue Window Height Registers Address:Offset Name Page Type 0xFA:0x0F IPV_1WIN_HEIGHT 3 PWD 0xFA:0x10 IPV_2WIN_HEIGHT 3 PWD 0xFA:0x11 IPV_3WIN_HEIGHT 3 PWD Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — Height in pixels (divided by four) of the preview window. Each register specifies the height used when the corresponding 5:0 IPV_HEIGHT R/W number of preview windows are active. 000000 Usable range is 24 lines to 144 lines for a register value range of 6 to 36.

InstaPrevue Window Actual Width Registers Address:Offset Name Page Type 0xFA:0x14 IPV_ACT_WIDTH_W0_L 3 PWD 0xFA:0x15 IPV_ACT_WIDTH_W0_H 3 PWD 0xFA:0x16 IPV_ACT_WIDTH_W1_L 3 PWD 0xFA:0x17 IPV_ACT_WIDTH_W1_H 3 PWD 0xFA:0x18 IPV_ACT_WIDTH_W2_L 3 PWD 0xFA:0x19 IPV_ACT_WIDTH_W2_H 3 PWD Bit Bit Label R/W Description Default Actual width in pixels of the corresponding InstaPrevue window. 8:0 IPV_ACTUAL_WIDTH R — A 9-bit value with bits [7:0] in registers with even offsets and Bit 8 in registers with odd offsets.

InstaPrevue Window Actual Height Register Address:Offset Name Page Type 0xFA:0x1E IPV_ACT_HEIGHT 3 PWD Bit Bit Label R/W Description Default Actual height in lines of the current InstaPrevue windows. The 7:0 IPV_ACTUAL_HEIGHT R — value is the same for all the preview windows.

InstaPrevue X/Y Position Register Group InstaPrevue maintains a set of window location registers for each preview window. Horizontal coordinates are 14-bit signed values ranging from –8192 to 8191, but only positive numbers should be used. Vertical coordinates are 13-bit signed values ranging from –4096 to 4095, but only positive numbers should be used. To maintain a preview window location for different main display resolutions, all position registers must be reprogrammed every time the main resolution changes. The SiI9687A device provides an interrupt (0x50:0x09[3]) to inform the software when the resolution has changed. The location must be set appropriately for each resolution to maintain the same approximate location on the display screen. Vertical location values must be divided by two when the main display is in the interlaced mode.

InstaPrevue Window Upper Left (X) Coordinate Registers Address:Offset Name Page Type 0xFA:0x1F IPV_WIN_X0_L 3 PWD 0xFA:0x20 IPV_WIN_X0_H 3 PWD 0xFA:0x21 IPV_WIN_X1_L 3 PWD 0xFA:0x22 IPV_WIN_X1_H 3 PWD 0xFA:0x23 IPV_WIN_X2_L 3 PWD 0xFA:0x24 IPV_WIN_X2_H 3 PWD Bit Bit Label R/W Description Default Horizontal (X) position of the upper left pixel of the corresponding InstaPrevue window. A 14-bit signed value with bits [7:0] in registers with odd offsets and bits [13:8] in registers with even offsets. Only 13:0 IPV_WIN_X R/W 0 positive values are valid. When determining this value, use the displayed image resolution instead of pixel counts that may include repeated pixels.

InstaPrevue Window Upper Left (Y) Coordinate Registers Address:Offset Name Page Type 0xFA:0x29 IPV_WIN_Y0_L 3 PWD 0xFA:0x2A IPV_WIN_Y0_L 3 PWD 0xFA:0x2B IPV_WIN_Y1_L 3 PWD 0xFA:0x2C IPV_WIN_Y1_L 3 PWD 0xFA:0x2D IPV_WIN_Y2_L 3 PWD 0xFA:0x2E IPV_WIN_Y2_L 3 PWD Bit Bit Label R/W Description Default Vertical (Y) position of the upper left pixel of the corresponding InstaPrevue window. A 13-bit signed value with bits [7:0] in registers with odd 12:0 IPV_WIN_Y R/W 0 offsets and bits [12:8] in registers with even offsets. Only positive values are valid. For interlaced resolutions, the vertical position must be divided by two.

InstaPrevue Window Actual X Coordinate Register Address:Offset Name Page Type 0xFA:0x33 IPV_ACT_X_W0_L 3 PWD 0xFA:0x34 IPV_ACT_X_W0_H 3 PWD 0xFA:0x35 IPV_ACT_X_W1_L 3 PWD 0xFA:0x36 IPV_ACT_X_W1_H 3 PWD 0xFA:0x37 IPV_ACT_X_W2_L 3 PWD 0xFA:0x38 IPV_ACT_X_W2_H 3 PWD Bit Bit Label R/W Description Default Actual horizontal (X) position of the upper left pixel of the corresponding InstaPrevue window. 12:0 IPV_ACTUAL_ X R — A 13-bit value having bits [7:0] in registers with odd offsets and bits [12:8] in registers with even offsets.

InstaPrevue 3D SubFrame Offset Registers Address:Offset Name Page Type 0xFA:0x42 IPV_WIN_3D_OFFSET0 3 PWD 0xFA:0x43 IPV_WIN_3D_OFFSET1 3 PWD 0xFA:0x44 IPV_WIN_3D_OFFSET2 3 PWD Bit Bit Label R/W Description Default InstaPrevue 3D frame offset value. For each corresponding window, this value specifies the depth 7:0 IPV_3D_OFFSET R/W 0x00 (offset) between the left and right subframes when the main video is in 3D mode.

InstaPrevue Window Color Register Group InstaPrevue windows can be displayed in 32 steps of opacity against the main display stream. Each window is independently controllable. In addition, the background color can be specified for preview windows in the following cases.  The associated TMDS port is HDCP protected and not authenticated yet, or it has failed authentication.  The associated TMDS port is a nonsupported format.  The associated TMDS port is not connected to a source (if in InstaPrevue ALL or Selected mode).

InstaPrevue Window Alpha Blend Level Registers Address:Offset Name Page Type 0xFA:0x3D IPV_ALPHA_0 3 PWD 0xFA:0x3E IPV_ALPHA_1 3 PWD 0xFA:0x3F IPV_ALPHA_2 3 PWD Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — Alpha blending level for the corresponding InstaPrevue window. 4:0 IPV_ALPHA R/W 00000 The alpha blending range is between 0 and 31; 0 is completely opaque and 31 is completely transparent.

InstaPrevue Window Background Color Registers Address:Offset Name Page Type 0xFA:0x93 IPV_USF_BGD_CR 3 PWD 0xFA:0x94 IPV_USF_BGD_CB 3 PWD 0xFA:0x95 IPV_USF_BGD_Y 3 PWD Bit Bit Label R/W Description Default 7:0 USF_BGD_CR R/W Background color for unsupported resolution/format or 0x80 7:0 USF_BGD_CB R/W nonauthenticated HDCP preview windows. The color is 0x80 7:0 USF_BGD_Y R/W specified as YCbCr color values. 0x00

InstaPrevue Window Border Control and Color Register Group These registers control the use of borders for InstaPrevue display windows. The border color is set using the 0xFA:0x80 –0xFA:0x82 registers to specify default YCbCr format values. Border display may be enabled or disabled with a single bit (0xFA:0x48[0]); however, the SiI9687A port processor provides several additional border color options that can be used while debugging the system.

InstaPrevue Border Control Register Address:Offset Name Page Type 0xFA:0x48 IPV_BORDER_CTRL 3 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Enable the use of the unsupported (USF) colors (0xFA:0x89– 0xFA:0x8B) for the InstaPrevue window border of ports that are sending an unsupported format status. If enabled, the USF 3 USF_BORDER_EN R/W border color will take precedence over any other enabled 0 border color. 0 – Disable USF color borders 1 – Enable USF color borders Enable the use of the HDCP-Bad (NA) colors (0xFA:0x86– 0xFA:0x88) for the InstaPrevue window border of ports that are HDCP but not authenticated. If enabled, the NA border 2 NA_BORDER_EN R/W color will take precedence over any other enabled border color 0 except USF. 0 – Disable NA color borders 1 – Enable NA color borders Enable the use of the Active Window (ACT) border colors (0xFA:0x83–0xFA:0x85) for the InstaPrevue windows when in the ACTIVE mode. If enabled and InstaPrevue is in the 1 ACT_BORDER_EN R/W ACTIVE mode, the ACT border color will take precedence 0 over the default ALL border color. 0 – Disable ACT color borders 1 – Enable ACT color borders Enable InstaPrevue window borders. The default color is specified in registers 0xFA:0x80–0xFA:0x82. When set, bits 0 BORDER_EN R/W 3:1 can override the default color under specific conditions. 0 0 – Disable InstaPrevue borders 1 – Enable InstaPrevue borders

InstaPrevue Default Border Color Registers Address:Offset Name Page Type 0xFA:0x80 IPV_ALL_BORDER_CR 3 PWD 0xFA:0x81 IPV_ALL_BORDER_CB 3 PWD 0xFA:0x82 IPV_ALL_BORDER_Y 3 PWD Bit Bit Label R/W Description Default 7:0 ALL_BORDER_CR R/W Border color for preview windows in InstaPrevue ALL mode. 0x80 7:0 ALL_BORDER_CB R/W The color is specified as YCbCr color values. 0x80 7:0 ALL_BORDER_Y R/W 0x40

InstaPrevue Active Mode Window Border Color Registers Address:Offset Name Page Type 0xFA:0x83 IPV_ACT_BORDER_CR 3 PWD 0xFA:0x84 IPV_ACT_BORDER_CB 3 PWD 0xFA:0x85 IPV_ACT_BORDER_Y 3 PWD Bit Bit Label R/W Description Default 7:0 ACT_BORDER_CR R/W Border color for preview windows in the InstaPrevue ACTIVE 0x80 7:0 ACT_BORDER_CB R/W mode. The color is specified as YCbCr color values. 0x80 7:0 ACT_BORDER_Y R/W 0xFF

InstaPrevue Not Available Window Border Color Registers Address:Offset Name Page Type 0xFA:0x86 IPV_NA_BORDER_CR 3 PWD 0xFA:0x87 IPV_NA_BORDER_CB 3 PWD 0xFA:0x88 IPV_NA_BORDER_Y 3 PWD Bit Bit Label R/W Description Default 7:0 NA_BORDER_CR R/W Border color for nonauthenticated HDCP preview windows. 0x1B 7:0 NA_BORDER_CB R/W This color overrides the InstaPrevue mode border color 0x1B 7:0 NA_BORDER_Y R/W registers. The color is specified as YCbCr color values. 0xAA

InstaPrevue Unsupported Format Window Border Color Registers Address:Offset Name Page Type 0xFA:0x89 IPV_USF_BORDER_CR 3 PWD 0xFA:0x8A IPV_USF_BORDER_CB 3 PWD 0xFA:0x8B IPV_USF_BORDER_Y 3 PWD Bit Bit Label R/W Description Default 7:0 USF_BORDER_CR R/W Border color for unsupported resolution/format preview 0x00 7:0 USF_BORDER_CB R/W windows. This color overrides the InstaPrevue mode border 0x80 7:0 USF_BORDER_Y R/W color registers. The color is specified as YCbCr color values. 0xFF

InstaPrevue Window Animation Control The SiI9687A port processor provides subframe window animation feature that can smoothly shift location of each subframe from current coordinate to the specified target coordinate with given initial speed and acceleration. The sequence of the steps below explains how to use the animation:  Enable animation feature (0xFA:0x90[1] = 1).  Set target coordinates of each subframe (see the InstaPrevue X/Y Position Register Group section on page 68).  Calculate and set desired animation speed and acceleration (see details below).  Trigger animation start (0xFA:0x90[0] = 1).  Wait until animation completes (0xFA:0x90[0] = 01). The animation feature can be enabled or disabled by writing 0xFA:0x90[1] = 1 or 0 respectively. If animation is disabled, the subframe location will be changed immediately following the change in coordinate registers. If the animation feature is enabled, writing to coordinate registers will take effect only after the animation is triggered by setting bit 0xFA:0x90[0]. Initial speed of subframe animation in horizontal and vertical dimensions can be set by writing to registers 0xFA:0x8C and 0xFA:0x8E respectively. Unit of speed value is pixels per frame. Acceleration of subframe animation in horizontal and vertical dimensions can be set by writing to registers 0xFA:0x8D and 0xFA:0x8F respectively. Acceleration value is a fixed point signed number in format 4.4 with values ranging from -8 to 7.9375 pixels per frame. There is a direct relationship between representation using speed and acceleration, and representation using distance from the current location to the target location and number of frames to complete animation movement. The following expression presents the relationship:

distance = ABS( current_position – target_position ) speed = distance * 2 / frames acceleration = 2 * (speed * frames – distance ) / (frames * frames)

Figure 12. Relationship between (Speed, Acceleration) and (Distance, Number of Frames) Representations

Animation is triggered by writing 1 to 0xFA:0x90[0] bit after writing target coordinates to coordinate registers. After starting the animation, bit 0xFA:0x90[0] will be reset and will remain 0 until the motion is fully completed. After that, the bit 0xFA:0x90[0] will be set to 1 by hardware. This can be used for synchronization of control actions by the software.

InstaPrevue Animation Control Register Address:Offset Name Page Type 0xFA:0x90 IPV_LOC_CTRL 3 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Enable Window Animation Feature. 1 SF_ANIM_EN R/W 0 – Disable animation feature 0 1 – Enable animation feature Triggers animation logic to begin moving the frames to target positions. This bit will be reset automatically when an animation has started and then will be set to 1 again when an animation is completed. All frames have reached their 0 SF_MOVE_EN R/W destination coordinates. 0 0 – Indicates ongoing animation (read). 1 – Triggers animation start (write). Indicates animation completion (read).

InstaPrevue Initial Speed Registers Address:Offset Name Page Type 0xFA:0x8C IPV_ LOC_CTRL_X_SP 3 PWD 0xFA:0x8E IPV_ LOC_CTRL_Y_SP 3 PWD Bit Bit Label R/W Description Default Initial speed of animation in horizontal (X) or vertical (Y) 7:0 SF_INIT_SPEED R/W 0xFF directions in units of pixels per frame.

InstaPrevue Acceleration Registers Address:Offset Name Page Type 0xFA:0x8D IPV_ LOC_CTRL_X_AC 3 PWD 0xFA:0x8F IPV_ LOC_CTRL_Y_AC 3 PWD Bit Bit Label R/W Description Default Acceleration of animation in horizontal (X) or vertical (Y) 7:0 SF_ACCEL R/W 0xFF directions. See Figure 12 on page 73 for details.

74 © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. MHL Receiver The SiI9687A/SiI9617 device features MHL support on any one of the ports of the receiver. Mobile High-definition Link (MHL) is a high-speed multimedia data transfer protocol intended to be used between mobile and display devices. For more information on MHL specifications, see the MHL Specification referenced in Table 18 on page 98. The SiI9687A/SiI9617 device supports version 1.0 of the MHL Specification as an MHL sink. MHL carries video, audio, auxiliary, control data, and power from a source to a sink across a cable consisting of five wires. The video, audio, and auxiliary data is multiplexed from several channels and sent to the sink across a differential signal pair (TMDS channel) using a fixed-ratio video clock. The control data is carried across on a single wire (CBUS) that provides configuration and status exchanges between the source and the sink devices. EDID data can be transferred between the source and the sink devices using the CBUS. Finally there are dedicated VBUS and ground pins that provide power between the sink and the source. CBUS (MHL Control Bus) is a software/hardware protocol that supports four types of packet transfers: Display Data Control (DDC), Vendor Specific, MHL Sideband Channel (MSC), and a reserved type.

MHL Sideband Channel The MHL Sideband Channel (MSC) is used to send commands between the MHL source and the sink devices. There are four types of MHL register sets defined by the CBUS protocol. These virtual registers are accessible only from the CBUS hardware bus using MHL Sideband Channel (MSC) commands. Table 10 describes these registers and their equivalent SiI9687A/SiI9617 I2C registers. Table 11 on the next page lists the MSC commands. Table 10. MHL CBUS Register Sets Accessible by an MHL-capable Peer Device CBUS virtual Local I2C on Name register offset SiI9687A/SiI9617 Description Offset Type Offset Type A peer device can read the SiI9687A/SiI9617 Device Capability Registers by sending a READ_DEVCAP 0xE6:0x00– command (Table 11). DEVCAP 0x00–0x0F R R/W 0xE6:0x0F For example, if the peer reads at CBUS offset 0x00, it reads the first DEVCAP register of the port processor at 0xE6:0x00. Trigger a virtual interrupt register interrupt on a peer device by setting the desired bit in one of the CBUS virtual interrupt registers and sending the SET_INT command 0xE6:0x20– (Table 11). For example, writing a bit in 0xE6:0x21 and Interrupt 0x20–0x23 W R/C 0xE6:0x23 sending the SET_INT command causes an interrupt on the peer device and sets the corresponding bit in virtual CBUS register 0x21 on the peer. See Figure 14 on page 77 for details. Set a status bit or bits on the peer device by setting the desired bit in one of the CBUS virtual status registers and 0xE6:0x30– sending the WRITE_STAT command (Table 11). Status 0x30–0x33 W R 0xE6:0x33 For example, writing a bit in 0xE6:0x31 and sending the WRITE_STAT command sets the corresponding bit in virtual CBUS status register 0x31 on the peer device. Write into the CBUS scratchpad of a peer device using the Scratch 0xE6:0x40– WRITE_BURST command (Table 11). Starting offset and 0x40–0x4F W R/W pad 0xE6:0x4F data length must be specified. See Figure 16 on page 78 for details.

Table 11. MSC Commands Command Command/ Code Control Packet Action Start Bit Offset Write to a peer virtual status register. WRITE_STAT WR_DATA(3) 0x30–0x33 MSC Command (0x60) is set by hardware. 0x60 Write one or more bits to a peer virtual SET_INT WR_DATA(3) interrupt register. 0x20–0x23 MSC Command (0x60) is set by hardware. Read one register from the virtual Device 0x61 READ_DEVCAP RD_DATA(2) Capability Registers of the peer. 0x00–0xFF MSC Command (0x61) is set by hardware. Send an HPD Detect notification to the source 0x64 SET_HPD XFER_DATA(0) 0x64 (sink only). Send an HPD Clear notification to the source. 0x65 CLR_HPD XFER_DATA(0) 0x65 (sink only). Send Remote Control Protocol (RCP) or 0x68 MSC_MSG SEND_VS_DATA(1) 0x68 Request Action Protocol (RAP) code. 0x6A GET_DDC_ERRORCODE XFER_DATA(0) Get DDC channel command error code. 0x6A 0x6B GET_ERRORCODE XFER_DATA(0) Get command error code. 0x6B Write 1 to 16 bytes to the peer virtual 0x6C WRITE_BURST WR_BURST(4) scratchpad registers; also requires length 0x40–0x4F written to (0xE6:0x20). Notes: 1. Command Start Bit refers to bits in register CBUS_PRI_START (0xE6:0xB8[4:0]). 2. Command/Offset refers to value written to register 0xE6:0xB9 before setting the Command Start Bit.

MSC Commands Error Codes When a command terminates with an error, it implies an ABORT on the host itself, or an ABORT was received from the peer, unless a NACK packet was sent by the peer that suggests the peer is busy and cannot attend to the transmission. (A retry might help, unless there is a programming error in the peer software and it has not cleared the interrupt registers.) Refer to latest MHL Specification for MSC commands related Error Codes.

Remote Control Protocol (RCP) The Remote Control Protocol (RCP) was developed for MHL-active devices. A source device gets a remote control command from the user and sends it to the peer device over the MHL Sideband Channel. This protocol uses the MSC_MSG command (see Table 11 on page 76). Data1 in register CBUS_MSC_WR_DATA_1 is for the RCP Command as described in the MHL Specification, and Data2 in register CBUS_MSC_WR_DATA_2 is for the RCP key code. RCP commands are confirmed by the RCPK (acknowledge) command or the RCPE (error response) command. An RCP command and its key code, when received and recognized by the follower, causes the follower to send an RCPK command with the same key code back to the initiator. An RCP command and its key code, when received but not recognized by the follower, causes the follower to send an RCPE command with an error code, and then an RCPK command with the original key code. Through this exchange, the original initiator recognizes that the key code has failed and confirms the actual value of the key code received by the follower by echoing it back to the initiator. The key codes used in RCP and RCPK subcommands are based upon the CEA-931C Specification. Refer to the MHL Specification for the definitions of RCP command and error codes.

Request Action Protocol (RAP) The Request Action Protocol (RAP) is a protocol that sends a request for action from a requester to a responder over the CBUS. RAP subcommands are confirmed by the RAPK (acknowledge) subcommand. This protocol uses the MSC_MSG command (see Table 11 on page 76). Data1 in register CBUS_MSC_WR_DATA_1 (0xE6:0xBA) is the RAP Command as described in the MHL Specification, and Data2 in register CBUS_MSC_WR_DATA_2 (0xE6:0xBB) is the RAP action code. Refer to the MHL Specification for the definitions of RAP command and error codes.

MHL/CBUS Programming The SiI9687A/SiI9617 device supports MHL on any one of the ports controlled by CBUS.. Registers start at I2C address 0xE6, offset 0x00. In the register description tables that follow, the Address:Offset column carries the values in the 0xAA:0xBB format, where AA is the CBUS I2C device page address, BB is the register offset. The initialization values of the CBUS registers can be found in Table 17 on page 97. Most CBUS commands operate on four sets of virtual registers defined by the CBUS protocol. These registers are accessible only from the CBUS hardware bus using MHL Sideband Channel (MSC) commands. Table 10 on page 75 maps the virtual CBUS protocol registers to the actual register locations of the SiI9687A/SiI9617 device. MSC commands are initiated by setting up the data, offset, and command registers and then setting the appropriate start bit in the CBUS_PRI_START (0xE6:0xB8[4:0]) register. Table 11 on page 76, shows the MSC command list and maps CBUS_PRI_START start bits to their corresponding MSC commands. CBUS_INT_STATUS is checked to determine if the command completed successfully or had an error. Figure 13, Figure 14, and Figure 15 illustrate sending MHL Sideband Commands to a peer device.

MSC_MSG: The MSC_MSG command can be sent and received by both the sink and the source.

1 0xE6:0xB9 = 0x68 ;MSC_MSG opcode 2 0xE6:0xBA = 0x10 ;RCP 3 0xE6:0xBB = 0x41 ;RCP key 4 0xE6:0xB8 = 0x02 ;Set START_MSC_MSG (Bit 1) 5 x = 0xE6:0x92[1] == 1? ;Check for command complete or error 6 0xE6:92 = x ;Clear the interrupt using the value read in Step 5

Figure 13. Sending an MHL MSC_MSG Command (RCP Subcommand)

SET_INT: The SET_INT command can be sent and received by both the sink and the source.

1 0xE6:0xB9 = 0x20 ; 0x20–0x23 depending upon which register to write 2 0xE6:0xBA = 0xAA ; Data to be written 3 0xE6:0xB8 = 0x08 ; Set Bit 3 to start command transmission 4 x = 0xE6:0x92[1] == 1? ; Check for command complete or error 5 0xE6:92 = x ; Clear the interrupt using the value read in Step 4

Figure 14. Sending an MHL SET_INT Command

SET_HPD: The SET_HPD command can be sent only by the sink.

1 0xE6:B9 = 0x64 ; SET_HPD opcode 2 0xE6:B8 = 0x01 ; Set Bit 0 to start command transmission 3 x = 0xE6:0x92[1] == 1? ;Check for command complete or error 4 0xE6:92 = x ;Clear the interrupt using the value read in Step 3

Figure 15. Sending an MHL SET_HPD Command

WRITE_BURST: The WRITE_BURST command can be sent and received by both the sink and the source. Sender should populate its own scratchpad registers prior to writing the send command.

1 0xE6:B9 = 0x40 – 0x4F ; Starting offset for scratchpad registers 2 0xE6:C6 = 0x00 – 0x0E ; Total # of registers to be written – 1 3 0xE6:B8 = 0x10 ; Set Bit 4 to start command transmission 4 x = 0xE6:0x92[1] == 1? ; Check for command complete or error 5 0xE6:92 = x ; Clear the interrupt using the value read in Step 4

Figure 16. Sending an MHL WRITE_BURST Command

CBUS Control Registers Register Group This section describes the MHL Control Bus (CBUS) registers of the SiI9687A/SiI9617 device. Information about the initialization of CBUS registers can be found in Table 17 on page 97.

CBUS Bus Status Register Address:Offset Name Page Type 0xE6:0x91 CBUS_STATUS 12 PWD Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — 0 – CBUS is not up and running 0 CBUS_CONNECTED R 0 1 – CBUS is up and running. Ready for MHL commands,

CBUS DDC ABORT Reason Register Address:Offset Name Page Type 0xE6:0x98 CBUS_DDC_ABORT 12 PWD Bit Bit Label R/W Description Default 7 DDC_ABORT R/W CBUS DDC transfer aborted by peer abort request. 0 6:3 RSVD — Reserved — 2 DDC_TIMEOUT R/W CBUS_DDC translation layer timeout happened. 0 1 DDC_PROTO_ERR R/W CBUS DDC translation layer protocol violated by peer. 0 CBUS DDC maximum number of transfers attempted 0 DDC_MAX_FAIL R/W 0 exceeded.

CBUS MHL Sideband Channel Transfer Abort Reason Register Address:Offset Name Page Type 0xE6:0x9A CBUS_XFR_ABORT 12 PWD Bit Bit Label R/W Description Default CBUS MHL Sideband Channel command aborted by peer 7 PEER_ABORT R/C 0 abort request. 6:4 RSVD — Reserved — CBUS MHL Sideband Channel Undefined Command initiated 3 XFR_UNDEF_CMD R/C 0 the interrupt. CBUS MHL Sideband Channel translation layer timeout 2 XFR_TIMEOUT R/C 0 occurred. CBUS MHL Sideband Channel translation layer protocol 1 XFR_PROTO_ERR R/C 0 violated by peer. CBUS MHL Sideband Channel maximum number of transfers 0 XFR_MAX_FAIL R/C 0 attempted exceeded.

CBUS Follower Abort Reason Register Address:Offset Name Page Type 0xE6:0x9C CBUS_FWR_ABORT 12 PWD Bit Bit Label R/W Description Default Peer initiated the CBUS MHL Sideband Channel command. 7 PEER_ABORT R/C The SiI9687A/SiI9617 device responded, but the peer aborted 0 the command. 6 RSVD — Reserved — 6 FWR__MSC_MSG_OV R/C Interrupt caused by MSC_MSG overflow. Peer initiated the CBUS MHL Sideband Channel command 4 FWR_INVALID_OFF R/C 0 with the wrong offset. Peer initiated the CBUS MHL Sideband Channel command and 3 FWR_UNDEF_CMD R/C 0 sent an undefined command. Peer initiated the CBUS MHL Sideband Channel command, 2 FWR_TIMEOUT R/C and a translation layer timeout occurred on the 0 SiI9687A/SiI9617 device side. Peer initiated the CBUS MHL Sideband Channel command 1 FWR_PROTO_ERR R/C 0 that violated the protocol. Peer initiated the CBUS MHL Sideband Channel command, 0 FWR_MAX_FAIL R/C and maximum number of transfer attempts while the 0 SiI9687A/SiI9617 device tried to respond.

CBUS Start Command Register Address:Offset Name Page Type 0xE6:0xB8 CBUS_PRI_START 12 PWD Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — 4 WR_BURST R/W Write 1 to start burst-writing peer’s scratchpad register. 0 3 WR _DATA R/W Write 1 to start writing peer’s Interrupts or Status registers. 0 2 RD_ DATA R/W Write 1 to start reading peer’s device capability registers 0 1 MSC_DATA R/W Write 1 to start sending MSC_MSG (0x68) to peer. 0 0 XFER_DATA R/W Write 1 to start transfer for all other MHL commands. 0

CBUS Command and Offset Register Address:Offset Name Page Type 0xE6:0xB9 CBUS_CMD_OFST 12 PWD Bit Bit Label R/W Description Default MSC Requester Command Opcode or Offset. 7:0 MSC_CMD_OFFSET R/W See Table 11 on page 76 for values written to this register for 0x00 each MSC command.

CBUS Write Data Registers Address:Offset Name Page Type 0xE6:0xBA CBUS_MSC_WR_DATA_1 12 PWD 0xE6:0xBB CBUS_MSC_WR_DATA_2 12 PWD Bit Bit Label R/W Description Default 7:0 CBUS_MSC_WR_DATA1 R/W MSC_MSG subcommand to be sent. 0x00 7:0 CBUS_MSC_WR_DATA2 R/W MSC_MSG opcode to be sent. 0x00

CBUS Read Data Register Address:Offset Name Page Type 0xE6:0xBC CBUS_MSC_RD_DATA_1 12 PWD Bit Bit Label R/W Description Default Response data received from peer after MHL command 7:0 CBUS_MSC_RD_DATA1 R 0x00 completed successfully.

CBUS MHL Sideband Channel Command Register Address:Offset Name Page Type 0xE6:0xBF MSC_MSG_SUBCMD 12 PWD Bit Bit Label R/W Description Default 7:0 MSC_MSG_SUBCMD R Received MSC_MSG subcommand from peer. 0x00

CBUS MHL Sideband Channel Data Register Address:Offset Name Page Type 0xE6:0xC0 MSC_MSG_OPCODE 12 PWD Bit Bit Label R/W Description Default 7:0 MSC_MSG_OPCODE R Received MSC_MSG opcode from peer. 0x00

CBUS MHL Sideband Channel Write Burst Data Length Register Address:Offset Name Page Type 0xE6:0xC6 CBUS_BURST_LEN 12 PWD Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Number of bytes to send to the peer scratchpad registers using 3:0 CBUS_BURST_LEN R/W 0000 the WRITE_BURST command.

CBUS Protocol Virtual Register Group This group contains the SiI9687A/SiI9617 registers that map to the CBUS protocol virtual register set. The virtual registers are accessible only from the CBUS hardware bus using MHL Sideband Channel (MSC) commands. Table 10 on page 75 maps the virtual CBUS protocol registers to the SiI9687A/SiI9617 registers in this group. The data in these registers is controlled by the registers of the CBUS Control Registers Register Group.

CBUS MHL Device Capability Registers Address:Offset Name Page Type 0xE6:0x00 CBUS_DEVCAP_0 12 PWD 0xE6:0x01 CBUS_DEVCAP_1 12 PWD 0xE6:0x02 CBUS_DEVCAP_2 12 PWD 0xE6:0x03 CBUS_DEVCAP_3 12 PWD 0xE6:0x04 CBUS_DEVCAP_4 12 PWD 0xE6:0x05 CBUS_DEVCAP_5 12 PWD 0xE6:0x06 CBUS_DEVCAP_6 12 PWD 0xE6:0x07 CBUS_DEVCAP_7 12 PWD 0xE6:0x08 CBUS_DEVCAP_8 12 PWD 0xE6:0x09 CBUS_DEVCAP_9 12 PWD 0xE6:0x0A CBUS_DEVCAP_A 12 PWD 0xE6:0x0B CBUS_DEVCAP_B 12 PWD 0xE6:0x0C CBUS_DEVCAP_C 12 PWD 0xE6:0x0D CBUS_DEVCAP_D 12 PWD 0xE6:0x0E CBUS_DEVCAP_E 12 PWD 0xE6:0x0F CBUS_DEVCAP_F 12 PWD Bit Bit Label R/W Description Default 7:0 MHL_DEVCAP_REGISTER R/W MHL defined Device Capability Registers. — Note: See the MHL Specification for register bit details. See Table 17 on page 97 for initialization values.

CBUS MHL Interrupt Registers Address:Offset Name Page Type 0xE6:0x20 CBUS_MHL_INTR_0 12 PWD 0xE6:0x21 CBUS_MHL_INTR_1 12 PWD 0xE6:0x22 CBUS_MHL_INTR_2 12 PWD 0xE6:0x23 CBUS_MHL_INTR_3 12 PWD Bit Bit Label R/W Description Default MHL Interrupt Registers. 7:0 LOCAL_MHL_INTR_REGISTER R/W The peer writes into these using MSC command SET_INT. 0x00 Write 1 to clear.

CBUS MHL Status Registers Address:Offset Name Page Type 0xE6:0x30 CBUS_MHL_STAT_0 12 PWD 0xE6:0x31 CBUS_MHL_STAT_1 12 PWD 0xE6:0x32 CBUS_MHL_STAT_2 12 PWD 0xE6:0x33 CBUS_MHL_STAT_3 12 PWD Bit Bit Label R/W Description Default MHL Status Registers. 7:0 MHL_STAT_REGISTER R The peer writes into these using MSC command 0x00 WRITE_STAT.

CBUS MHL Scratchpad Registers Address:Offset Name Page Type 0xE6:0x40 CBUS_SCRATCH_0 12 PWD 0xE6:0x41 CBUS_SCRATCH_1 12 PWD 0xE6:0x42 CBUS_SCRATCH_2 12 PWD 0xE6:0x43 CBUS_SCRATCH_3 12 PWD 0xE6:0x44 CBUS_SCRATCH_4 12 PWD 0xE6:0x45 CBUS_SCRATCH_5 12 PWD 0xE6:0x46 CBUS_SCRATCH_6 12 PWD 0xE6:0x47 CBUS_SCRATCH_7 12 PWD 0xE6:0x48 CBUS_SCRATCH_8 12 PWD 0xE6:0x49 CBUS_SCRATCH_9 12 PWD 0xE6:0x4A CBUS_SCRATCH_A 12 PWD 0xE6:0x4B CBUS_SCRATCH_B 12 PWD 0xE6:0x4C CBUS_SCRATCH_C 12 PWD 0xE6:0x4D CBUS_SCRATCH_D 12 PWD 0xE6:0x4E CBUS_SCRATCH_E 12 PWD 0xE6:0x4F CBUS_SCRATCH_F 12 PWD Bit Bit Label R/W Description Default MHL-defined Scratchpad Registers. 7:0 MHL_SCRATCHPAD_REGISTER R/W 0x00 See the MHL Specification for register bit details.

MHL Discovery Status Register Group

MHL Mode Default Port Status Register Address:Offset Name Page Type 0xE0:0xE6 MHL_PORT_SEL_STATUS 9 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Bits [3:0] represent Ports 0 to 3. 3:0 MHL_PORT R 0 – HDMI port 0000 1 – MHL port Note: This register is loaded from NVRAM boot data offset 0x24 at boot time. The boot data must be preprogrammed to enable the desired ports for MHL operation. The SiI9687A/SiI9617 device supports MHL on one of the HDMI input ports. The actual port selection is determined by the value in NVRAM offset 0x24.

MHL CBUS Connected Register Address:Offset Name Page Type 0xE0:0xE0 MHL_CBUS_CONNECTED 9 AON Bit Bit Label R/W Description Default 7:4 RSVD — Reserved — Bits [3:0] represent Ports 0 to 3. 3:0 MHL_CBUS_CONNECTED_PORT R 0 – MHL not connected on this port 0000 1 – MHL connected on this port

MHL Interrupt Enable and Status Register Group An interrupt bit is set when the associated SiI9687A/SiI9617 subsystem interrupt has been triggered. If the interrupt bit is clear, no interrupt occurred on that subsystem. Once an interrupt is triggered, it remains set in the status register until cleared by writing a 1 to the bit.

CBUS Interrupt Status Register 1 Address:Offset Name Page Type 0xE6:0x92 INT_STATUS_CBUS1 12 PWD 0xE6:0x93 INT_ENABLE_CBUS1 12 PWD Bit Bit Label R/W Description Default Set to 1 if NACK is received from peer in response to an MHL 7 MSC_MSG_DONE_WITH_NACK R/C 0 Sideband Channel command. 6 SET_INT_RCVD R/C Set to 1 if SET_INT command is received. 0 5 WRITE_BURST_RCVD R/C Set to 1 if WRITE_BURST command is received. 0 4 MSC_MSG_RCVD R/C Set to 1 if MSC_MSG CMD is received. 0 3 WRITE_STAT_RCVD R/C Set to 1 if WRITE_STAT command is received. 0 2 RSVD — Reserved — Set to 1 when MSC Command Transfer is done. Write 1 to 1 MSC_CMD_DONE R/C 0 clear. Set to 1 when CBUS connection changes from connected to 0 CONNECT_CHANGE R/C 0 disconnected or disconnected to connected. Write 1 to clear.

CBUS Interrupt Status Register 2 Address:Offset Name Page Type 0xE6:0x94 INT_STATUS_CBUS2 12 PWD 0xE6:0x95 INT_ENABLE_CBUS2 12 PWD Bit Bit Label R/W Description Default 7 RSVD — Reserved — 6 MSC_CMD_ABORT R/C MSC command was aborted. 0 4:5 RSVD — Reserved — 3 MSC_ABORT_RCVD R/C Peer sent an ABORT. 0 2 DDC_ABORT R/C DDC abort an interrupt. 0 1:0 RSVD — Reserved —

MHL Control Bus PAD Status Register Address:Offset Name Page Type 0xE0:0xD7 CP_PAD_STAT 9 AON Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — 4 REG_MHL_OSC_EN R 20 MHz oscillator power save control signal status. 1 3 MOBILE_R3P R Port 3 CBUS_HPD pad enables port status. 0 2 MOBILE_R2P R Port 2 CBUS_HPD pad enables port status. 0 1 MOBILE_R1P R Port 1 CBUS_HPD pad enables port status. 0 0 MOBILE_R0P R Port 0 CBUS_HPD pad enables port status. 0

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 83 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Audio Return Channel Audio Return Channel (ARC) is an extension of the HDMI 1.4 Specification that provides a separate path on the HDMI cable for audio. This path flows in the opposite direction of the audio/video signal traveling over the HDMI cable. Consider a DTV (sink) with an internal broadcast receiver and an AVR that is attached to one of its HDMI input ports. When playing a source from the AVR, it is possible to play the source audio through an amplifier in the AVR. However, when the broadcast receiver is in use, the audio must be routed to the AVR amplifier through a separate S/PDIF cable. ARC eliminates this second cable by allowing the DTV to route an S/PDIF signal through the HDMI cable to the AVR for playback. The SiI9687A/SiI9617 device contains one channel of ARC hardware that can be configured to operate as an ARC transmitter for use in HDMI sink devices.

ARC Control and Status Registers These registers control the operation of the Audio Return Channel (ARC) physical interface.

Audio Return Channel Mode Address:Offset Name Page Type 0x90:0xB0 I2C_ARC_MODE 11 PWD Bit Bit Label R/W Description Default 7:6 ARC_INT_SET R/W Internal 1 V Regulator Setting. 01 5 ARC_DRV_EN R/W ARC Driving Enable. 1 4 ARC_DRV_MODE R/W Driving Mode Setting (bleeding or not). 1 3:0 ARC_TERM_CTL R/W Termination Resistance Control. 1100

Audio Return Channel Termination Control Address:Offset Name Page Type 0x90:0xB1 I2C_ARC_TERM 11 PWD Bit Bit Label R/W Description Default 7:1 RSVD — Reserved — Termination Resistance Enable. 0 ARC_TERM_EN R/W 0 – Disable 1 1 – Enable

84 © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Transmitter Programming Interface The SiI9687A/SiI9617 device has an unencrypted output intended to be directly connected to the system video processor. It requires very little software setup and support.

TMDS Transmit Clock Control Register Address:Offset Name Page Type 0x90:0x00 TMDST_CTRL1 11 PWD Bit Bit Label R/W Description Default 0 – Disable R output 7 TMDST_OE3 R/W 0 1 – Enable R output 0 – Disable G output 6 TMDST_OE2 R/W 0 1 – Enable G output 0 – Disable B output 5 TMDST_OE1 R/W 0 1 – Enable B output 0 – Disable CLK output 4 TMDST_OE0 R/W 0 1 – Enable CLK output 3:1 RSVD — Reserved — 0 – Disable transmitter block 0 TMDST_EN R/W 0 1 – Enable transmitter block

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 85 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Video Pattern Generator The SiI9687A/SiI9617 Video Pattern Generator (VPG) sends one of eight predefined video patterns to the HDMI transmitter. The VPG can be used during product development for test purposes.

Clock Sources The VPG requires a video pixel clock for its operation. The clock is derived from one of the two sources (see Table 12). The Main pipe clock selection can be used when active HDMI or MHL inputs are connected, so that the VPG can use those clock signals without requiring an independent external clock. The other option is to use an internal 74.25 MHz clock oscillator. Table 12. Video Pattern Generator Clock Sources Clock Description 0x90:0xFF [2:1] 00 Main Pipe Clock 01 Internal Oscillator

Extended Patterns The basic pattern generator supports only a single pattern, an eight-color vertical bar pattern. Extended mode adds the additional seven patterns listed in Table 13. The video patterns can be generated in a wide range of resolutions and color depths (see the description of the bit VPG_FORMAT in register VPG_CTRL_3 (0x90:0xFF) below). The generated video color space is RGB. Table 13. Video Pattern Generator Extended Patterns No. Pattern Name No. Pattern Name No. Pattern Name No. Pattern Name 0 Solid Red 1 Solid Green 2 Solid Blue 3 Solid Black

4 Solid White 5 Ramp 6 Chessboard 7 Color Bars

VPG Programming Configuration of the video pattern generator begins with setting up the video clock source and the video format in register VPG_CTRL_3 (0x90:0xFF). The VPG_EN bit must be set to 0 to select the extended patterns and set to 1 for the basic pattern generator. Setting the VPG_EN to 1 enables the basic pattern generator immediately, because pattern selection is not needed in that case. In the case of extended patterns, the second step is needed to specify the pattern in the VPG_CTRL_2 (0x90:0xE5) register. Finally, the extended pattern generator must be enabled by setting the bit VPG_EXT_EN to 1. NVRAM Boot Data Memory location 0x28[0] should be set to 1 to enable all the patterns.

Configure VPG to use main pipe clock source and generate Chessboard pattern in 720p@60 Hz video format. 1. 0x90:0xFF = 0x08 ; Set 720p main pipe clock 2. 0x90:0xE5[7:4] = 0x6 ; Select Chessboard pattern 3. 0x90:0xE0[2] = 1 ; Enable extended VPG

Figure 17. Programming the VPG using the Main Pipe Clock Source

Configure VPG to use internal clock source and generate Chessboard pattern in 720p@60 Hz video format. 1. 0x90:0x00 = 0xF1 ; 2. 0x90:0x16 = 0x0D ; 3. 0x90:0x11 = 0x1A ; 4. 0x90:0x1D = 0x00 ; 5. 0x90:0x14 = 0x18 ; 6. 0xE0:0x7C = 0x30 ; 7. 0x90:0xFF = 0x0A ;Set 720p internal clock 8. 0x90:0xE5[7:4] = 0x6 ;Select Chessboard pattern 9. 0x90:0xE0[2] = 1 ;Enable extended VPG

Figure 18. Programming the VPG to Generate an Extended Pattern

VPG Control Register Group

Video Pattern Generator Control Register 1 Address:Offset Name Page Type 0x90:0xE0 VPG_CTRL_1 11 PWD Bit Bit Label R/W Description Default 7:3 RSVD-W0 W Reserved 00000 Enable Extended Pattern Set. Enables the use of the extended pattern set selected with 2 VPG_EXT_EN R/W 0x90:0xE5[7:4]. 0 0 – Use color bar pattern only (same as extended pattern #7) 1– Enable extended patterns 1:0 RSVD — Reserved 00

Video Pattern Generator Control Register 2 Address:Offset Name Page Type 0x90:0xE5 VPG_CTRL_2 11 PWD Bit Bit Label R/W Description Default Select the Video Pattern Generator Pattern. Choose the pattern generated by the VPG for display. Requires Extended Pattern Generator enable (0x90:0xE0[2] = 1. 0000– Full screen red (default) 0001 – Full screen green 0010 – Full screen blue 0011 – Full screen black 0100 – Full screen white 0101 – Ramp, from (0, 0, 0) to (255, 255, 255); each color 7:4 VPG_PATTERN R/W 0000 repeats for five pixels 0110 – Chessboard; see below 0111 – Color bar. Eight vertical stripes of 160 pixels in different colors In the chessboard pattern, the screen is divided into 8 x 6 blocks, with the size of 160 x 120. Black and white blocks alternate horizontally and vertically. This pattern is designed for the 1280 x 720 resolution, but will display on other resolutions with incomplete blocks. 3:0 RSVD — Reserved —

Video Pattern Generator Control Register 3 Address:Offset Name Page Type 0x90:0xFF VPG_CTRL_3 11 PWD Bit Bit Label R/W Description Default Select the Video Pattern Generator Format. The source clock must be set to match the format selected. 7:4 VPG_FORMAT R/W 0000 0000 – 720p @ 60 Hz All other are values reserved. 0 – Enable InstaPort data to go to TMDS encoder 3 VPG_TMDS_BIST_EN R/W 1 – Enable TMDS BIST data to go to TMDS encoder if 0 VPG_EN bit is set Select Clock Source for the Video Pattern Generator. 2:1 VPG_CLK_SEL R/W 00 – Main Pipe Clock 00 01 – Internal Clock Enable Color Bar Video Pattern Generator. 0 VPG_EN R/W 0 – Disable 0 1 – Enable

88 © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Appendix A – Input Port HDCP DDC-Accessible Registers A source (for example, a DVD player or a set-top box) is the only controller that accesses the HDCP-DDC-accessible registers. These registers are defined in the HDCP Specification. The software in the sink cannot interact with these registers. Table 14. DDC Registers (0x74) Ref 0x74 Name 7 6 5 4 3 2 1 0 Page 0xFB 89 DEVICE DEV_ID DEV_REV 0x00 90 BKSV1 BKSV1 0x01 90 BKSV2 BKSV2 0x02 90 BKSV3 BKSV3 0x03 90 BKSV4 BKSV4 0x04 90 BKSV5 BKSV5 0x08 90 RI1 RI1 0x09 90 RI2 RI2 0x10 90 AKSV1 AKSV1 0x11 90 AKSV2 AKSV2 0x12 90 AKSV3 AKSV3 0x13 90 AKSV4 AKSV4 0x14 90 AKSV5 AKSV5 0x18 91 AN1 AN1 0x19 91 AN2 AN2 0x1A 91 AN3 AN3 0x1B 91 AN4 AN4 0x1C 91 AN5 AN5 0x1D 91 AN6 AN6 0x1E 91 AN7 AN7 0x1F 91 AN8 AN8 FIFOR 0x40 92 BCAPS HDMI_C RPTR FAST RSVD DY DEV_ 0x41 92 BSTATUS1 DEV_COUNT EXC HDMI_ 0x42 92 BSTATUS2 RSVD CAS_EXC DEV_DEPTH MODE 0x43 92 KSV_FIFO KSV_FIFO

Silicon Image Device Identification Register Address:Offset Name Page Type 0x74:0xFB SI_DEVICE_ID DDC AON Bit Bit Label R/W Description Default 7:2 DEV_ID R DDC ID. 010101 1:0 DEV_REV R Device Revision. 00

HDCP DDC Bus Registers The following registers support High-bandwidth Digital Content Protection (HDCP) functionality. HDCP BKSV Registers Address:Offset Name Page Type 0x74:0x00 BKSV1 DDC AON 0x74:0x01 BKSV2 DDC AON 0x74:0x02 BKSV3 DDC AON 0x74:0x03 BKSV4 DDC AON 0x74:0x04 BKSV5 DDC AON Bit Bit Label R/W Description Default HDCP-capable receiver Key Selection Vector (KSV). 39:0 BKSV R An HDCP reset causes the HDCP keys to load every time 0 SCDT transitions from 0 to 1. Notes: 1. The BKSV register can also be read from a BKSV Shadow register (0xB0:0x1A–0xB0:0x1E). 2. HDCP initialization requires an active video stream into the HDMI receiver. The source should not read the HDCP BKSV value until it has been transmitting stable video to the HDMI receiver for a time period of at least TBKSVINIT. Refer to the associated data sheet (refer to Table 20 on page 98) for exact specifications. HDCP Ri Registers Address:Offset Name Page Type 0x74:0x08 RI1 DDC AON 0x74:0x09 RI2 DDC AON Bit Bit Label R/W Description Default The value of this register is read and compared in the software 15:0 RI R with the value of the Ri register from the HDCP-capable 0 transmitter. Notes: 1. The Ri register can also be read from the Ri Shadow registers (0xB0:0x1F–0xB0:0x20). 2. This value is updated every 128 frames when HDCP decryption is enabled and running. Silicon Image recommends that the source protect itself against errors in DDC/ I2C transmission by rereading this register. The value in the Ri register is always available. The initial value of R0′ is to be available at the maximum of 100 ms after the last byte of the source AKSV is written into the HDMI receiver (the actual calculation time depends on the frequency of the incoming TMDS clock). Subsequent values of Ri′ are available at the maximum of 128 pixel clocks after the HDMI receiver detects the assertion of the decoded CTL3 signal (as defined by HDCP). Refer to the HDCP Specification for more details.

HDCP AKSV Registers Address:Offset Name Page Type 0x74:0x10 AKSV1 DDC AON 0x74:0x11 AKSV2 DDC AON 0x74:0x12 AKSV3 DDC AON 0x74:0x13 AKSV4 DDC AON 0x74:0x14 AKSV5 DDC AON Bit Bit Label R/W Description Default 39:0 AKSV R/W HDCP-capable transmitter Key Selection Vector. 0 Notes: 1. The AKSV register can also be read from the AKSV Shadow registers (0xB0:0x21–0xB0:0x25). 2. Byte AKSV1 is written first. Byte AKSV5 must be written last, as it triggers the authentication logic in the HDMI receiver.

HDCP AN Registers Address:Offset Name Page Type 0x74:0x18 AN1 DDC PWD 0x74:0x19 AN2 DDC PWD 0x74:0x1A AN3 DDC PWD 0x74:0x1B AN4 DDC PWD 0x74:0x1C AN5 DDC PWD 0x74:0x1D AN6 DDC PWD 0x74:0x1E AN7 DDC PWD 0x74:0x1F AN8 DDC PWD Bit Bit Label R/W Description Default HDCP 64-bit pseudo-random value. This multi-byte value must 63:0 AN R/W be written before the AKSV bytes are written to the HDMI 0 receiver. Note: The AN register can also be read from the AN Shadow registers (0xB0:0x26–0xB0:0x2D).

BCAPS Register Address:Offset Name Page Type 0x74:0x40 BCAPS DDC PWD Bit Bit Label R/W Description Default HDMI Capability. Always reads 1 as an HDMI-capable device. 0 – Device supports DVI 1.0 but not HDMI 1 – Device supports HDMI This bit is available for diagnostic use only and should not be 7 HDMI_C R the indicator by the source to determine if the sink is used as an 1 HDMI sink. Consult the HDMI Specification for Vendor Specific Data Block (VSDB) in the EDID. This bit can be written to 0 after a hardware reset using the sink BCAPS_SET register. Because this bit defaults to 1, it may be read as 1 across the DDC channel until explicitly written by the sink software. Repeater Status. 0 – HDCP end point (receiver) 6 RPTR R 1 – Device is a repeater. 0 This bit can be written using the sink BCAPS_SET register. Always reads 0 for the SiI9687A/SiI9617 device. KSV FIFO Read Status. 0 – FIFO not ready for read 1 – FIFO ready for read This bit is set when the KSV FIFO is ready as part of the 5 FIFORDY R 0 HDCP standard register set. This function is needed for HDCP repeaters so that the source knows when to begin reading the KSV list. Refer to the HDCP Specification. Always reads 0 for the SiI9687A/SiI9617 device. I2C Transfer Speed Capability. 0 – Supports only up to 100 kbps speed 1 – Supports 400 kbps speed 4 FAST R 0 This bit should always be 0. The HDMI Specification requires the DDC bus to be used at 100 kHz speed or less (standard mode I2C). 3:0 RSVD — Reserved — Notes: 1. Bits RPTR and FIFORDY are for the currently selected port only. These bits can be read and written for each port individually using the corresponding bits in the HDCP_BCAPS_SET and HDCP_STAT registers device. 2. Bits HDMI_C and FAST are for the currently selected port only. These bits can be read and written for each port individually using the corresponding bits in the BCAPS_CTRL and HDCP_STAT registers device.

BSTATUS1 Register Address:Offset Name Page Type 0x74:0x41 BSTATUS1 DDC PWD Bit Bit Label R/W Description Default Device Count Exceeded. 7 DEV_EXC R 0 Always reads 0 for the SiI9687A/SiI9617 device. Device Count. 6:0 DEV_COUNT R 0000000 Always reads 0 for the SiI9687A/SiI9617 device.

BSTATUS2 Register Address:Offset Name Page Type 0x74:0x42 BSTATUS2 DDC PWD Bit Bit Label R/W Description Default 7:5 RSVD — Reserved — HDMI Mode (set or cleared by writing to local bus). 4 HDMI_MODE R 0 – Device is in the DVI mode 0 1 – Device is in the HDMI mode Cascade Depth Exceeded. 3 CAS_EXC R 0 Always reads 0 for the SiI9687A/SiI9617 device. Cascade Depth. 2:0 DEV_DEPTH R 000 Always reads 0 for the SiI9687A/SiI9617 device. Note: The BSTATUS2 register can also be read from the HDCP_SHD_BSTAT2 (0xB0:0x30) register.

KSV FIFO Register Address:Offset Name Page Type 0x74:0x43 KSV_FIFO DDC PWD Bit Bit Label R/W Description Default KSV Data. Read this address repeatedly without issuing an I2C Stop condition to retrieve the entire KSV list from the HDMI 7:0 KSV_FIFO R receiver. The FIFO pointer to the beginning of this FIFO is 0x00 reset to 0 by RESET# when the last byte of AN (0x1F) is written or by the next I2C Stop condition on the DDC bus. Always reads 0 for the SiI9687A/SiI9617 device.

92 © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Appendix B – NVRAM Boot Data Memory Layout This section describes the layout of the Boot Data area in the SiI9687A/SiI9617 NVRAM. This data is copied at boot time from the NVRAM to the corresponding SiI9687A/SiI9617 control register bits, but not into the Boot Data SRAM. To examine or program the boot data, use the Load NVRAM Boot Data to Boot Data SRAM command in the 0xE0:0x05 register. Table 15. NVRAM Boot Data Memory Layout Destination FW Default Offset Label Description Register Address Value 0xAA: Use NVRAM Contents during boot and set Bit 1 in NVRAM_STATUS register 0x00 NVRAM_CONFIG 0xE0:0x10[1] 0xAA (0xE0:0x10). Any other value in this register is ignored. 0x55: The NVRAM EDID is programmed and Bit 0 is set in NVRAM_STATUS register 0x01 EDID_VALID 0xE0:0x10[0] 0x55 (0xE0:0x10). All other values indicate the EDID is not programmed. 0x02 NVRAM_VERSION 0xE0:0x00 The version number of the NVRAM program. 0x06 Determines which EDID SRAMs are loaded 0x03 NVRAM_BOOT_COPY 0xE0:0x12 0x2F from the NVRAM HDMI EDID at power up. Determines which ports will have auto-HPD 0x04 HPD_HW_CTRL 0xE0:0x13 0x1F control enabled. RSVD-W0 Reserved (except Bit 5). 0x05 — Enable 300 ns delay on local I2C data line 0x00 CSDA_DEL_EN[5] (CSDA). 0x06 HDMI_WAKEUP_SRC 0xE0:0x71 Wake up chip based on CKDT or SKDT. 0x00 Determines which EDID SRAMs are loaded from the NVRAM VGA EDID at power up. 0x07 NVRAM_VGA_COPY 0xE0:0x07 0x10 NVRAM 0x07[3:0] are mapped to 0xE0:0x07 [5:2] respectively. 0x08– RSVD-W0 — Reserved 0x00 0x09 Offset of the CEC Physical Address within 0x0A CEC_PA_ADDR 0xE0:0x1A 0xA6 EDID. 0x0B RSVD-W0 — Reserved 0x00 0x10, 0x00, 0x0C– CEC Physical Address for port 0, 1, 2, 3 0x20, 0x00, CEC_PAD_x_CHx 0xE0:0x1C–0x23 0x13 respectively. 0x30, 0x00, 0x40, 0x00 0x14– RSVD-W0 — Reserved 0x00 0x1B 0x1C– EDID block 1 checksum for port 0, 1, 2, 3 0x2C, 0x1C, CHECKSUM_CHx 0xE0:0x2C–0x2F 0x1F respectively. 0x0C, 0xFC 0x20– RSVD-W0 — Reserved 0x00 0x23 0x24 MHL_PORT_EN 0xE0:0xE6 Select MHL Enable Port. 0x08 0x25 RSVD-W0 — Reserved 0x00 0x26 RSEN_VAL — HDMI and MHL RSEN Value. 0xC4 0x27 RSVD-W0 — Reserved 0x00 MHL auto termination control enable and 0x28 MHL_AUTO_TERM_ENABLE — 0x27 ETPG enable. 0x29– — — Not used (written as 0x00). 0x00 0x3F

MHL_TERM_CTRL NVRAM Offset Name Page Type 0x26 MHL_TERM_CTRL NVRAM PWD Bit Bit Label R/W Description Default MHL HPD. 7 MHL_HPD R/W 0 – Send SET_HPD packet when MHL is discovered 1 1 – Don’t send SET_HPD packet when MHL is discovered 6 RSVD-W1 — Reserved 1 5:4 RSVD — Reserved — 3:2 MHL_TERMINATION_VAL R/W MHL Termination Value for the port to be used in 0xB0:0x82. 01 1:0 HDMI_TERMINATION_VAL R/W HDMI Termination Value for the port to be used in 0xB0:0x82. 00

MHL_CTRL NVRAM Offset Name Page Type 0x28 MHL_ CTRL NVRAM PWD Bit Bit Label R/W Description Default 7:6 RSVD — Reserved — MHL Auto Termination. 0 – MHL termination is controlled by the firmware 5 MHL_AUTO_TERMINATION R/W 1 – MHL termination is controlled by the hardware 1 Termination value will be used as specified in NVRAM offset 0x07[3:2] 4:1 RSVD — Reserved — VPG Control. 0 ETPG_CTRL R/W 0 – Extended VPG disabled 1 1 – Extended VPG enabled

94 © 2011-2012 Silicon Image, Inc. All rights reserved. SiI-PR-1078-A CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. Appendix C – Device Initialization There are two phases in the operation of the SiI9687A/SiI9617 device, the initialization and the monitoring phases. Before initializing, the device must first be reset using the HARD_RESET register bit (0xE0:0xFF[7]).

Verifying POR Although the device has an internal Power-on Reset (POR) circuit to get AON and PWD to reset, Silicon Image recommends verifying that AON and PWD get reset properly as soon as the system boots up using the following sequence. 1. Perform a software hard reset by setting and clearing bit 0xE0:0xFF[7]. 2. Check if BOOT_DONE bit 0xE0:0x09[2] is set. If set, go to Step 5. 3. If BOOT_DONE is not set or local I2C does not respond, toggle RESET_N and wait for 300 ms. 4. Go to Step 1. 5. Initialize all the registers as described in the Register Initialization section below. Because asserting an external reset causes HPD toggling, Silicon Image recommends applying the external reset only when required.

Register Initialization The default values of certain SiI9687A/SiI9617 registers must be changed for proper operation of the device. Upon power-up, the registers listed in Table 16 on page 96 and Table 17 on page 97 must be written with the value from the appropriate column. For the best performance, Silicon Image recommends that these initialization values be written as early in the power-up cycle as possible, after the device has been reset. This is only an initialization list. Some of these registers may be controlled by the firmware during the normal operation and will deviate from the values listed here. Registers in this list that do not change during the operation are not described in this document; treat them as reserved registers and leave them in the state shown in the table. Silicon Image reserves the right to not disclose the meaning or operation of these registers as they may contain proprietary information. Silicon Image is constantly evaluating the default register values suggested in this table, and they are subject to change. Contact your Silicon Image representative for the latest values. Unless otherwise specified, the order of register initialization is not important. The highlighted registers at the beginning and the end of the register initialization list are intended to keep the device in reset until the other registers are properly initialized, and should be kept in place. Note: This initialization list leaves the transmitter output of the port processor disabled so that the rest of the device and system initialization may take place. When the system is ready to display, it must write 0xF1 to register 0x90:0x00 (TMDST_CTRL1) and unmute the device.

Table 16. Register Preinitialization Values Device Default Address Register Name SiI9687A/SiI9617 Comment Value Offset 0xE0:0xFF SPECIAL_PURPOSE 0x00 0x80 Force Hard Reset. 0xE0:0xFF SPECIAL_PURPOSE 0x00 0x00 Clear Hard Reset. ECC error check and 0x50:0x57 PAUTH_ECC_CTRL0 0x00 0x10 control Enable ECC Err 0x50:0x63 PAUTH_MISC_CTRL0 0x8E 0xCE detect, Enable recover glitch. HDCP stream ports 0x50:0x3A PAUTH_CTRL 0x00 0x0A from roving port. 0xB0:0x05 SRST 0x00 0x01 Hold in Reset. 0xB0:0x07 C0_HDCP_RST 0x00 0x01 Reset HDCP. 0xB0:0x07 C0_HDCP_RST 0x00 0x00 Clear Reset. Disable Auto-HPD 0xE0:0x13 NVM_HDP_HW_CTRL 0x00 0xF0 control on ports 0, 1, 2, 3. 0x64:0x8A *PLL0_VCOCAL 0x39 0x3C — 0x52:0xD0 *PAUTH_NUM_SAMPS 0x05 0x85 — 0x64:0x8B *TMDSRX_CTRL1 0x00 0x0C — 0x64:0x8C *TMDSRX_CTRL2 0x00 see comment Clear bit[5:4] 0x64:0x8D *TMDSRX_CTRL3 0x00 see comment Set bit[5:4] 0x64:0x8E *TMDSRX_CTRL4 0x00 see comment Bit[3:0] = 0x0A 0x50:0x59 *PA_INV_CTRL 0x7C 0x00 — 0x50:0x7F *PA_CONFIG_11 0x09 0x49 — 0x54:0x02 *PAUTH_MHL_IEEE_ID1 0x03 0x1D — 0x54:0x03 *PAUTH_MHL_IEEE_ID2 0x0C 0xA6 — 0x54:0x04 *PAUTH_MHL_IEEE_ID3 0x00 0x7C — 0x54:0x00 *PAUTH_MHL3D_CFG1 0x01 0x19 — 0x54:0x01 *PAUTH_MHL3D_CFG2 0x86 0x81 — 0x52:0x7D *PAUTH_ALT_ZONE4_CFG 0x80 0xE0 — 0x52:0xFA *PAUTH_MHL_TESTER_MODE 0x00 0x80 — 0x54:0x20 *PAUTH_CLR_BUFFER 0x00 0x01 — 0x52:0xAC *TMDS0_BW_I2C 0x0C 0x14 — 0x52:0x8E *TMDS1_BW_I2C 0x0C 0x14 — 0x50:0xAE *PA_MHL1X_CONF_REG_0 0x13 0x00 — Write 0x07 (3 bits) 0xB0:0x83 *TMDS_TERMCTRL1 0xC0 0x21 for MHL port. Write 0x07 (3 bits) 0xB0:0x80 *TMDS_TERMCTRL3 0xC0 0x21 for MHL port. 0x52:0xA4 *TMDS0_EQ_DATA0 0xDA 0x88 — 0x52:0xA5 *TMDS0_EQ_DATA1 0xDA 0x98 — 0x52:0xA6 *TMDS0_EQ_DATA2 0xDA 0xA8 — 0x52:0xA7 *TMDS0_EQ_DATA3 0xDA 0xB8 — 0x52:0xA8 *TMDS0_EQ_DATA4 0xDA 0xB9 — 0x52:0xA9 *TMDS0_EQ_DATA5 0xDA 0xC9 — 0x52:0xAA *TMDS0_EQ_DATA6 0xDA 0xBA — 0x52:0xAB *TMDS0_EQ_DATA7 0xDA 0xB8 — 0x52:0x86 *TMDS1_EQ_DATA0 0xDA 0x98 — 0x52:0x87 *TMDS1_EQ_DATA1 0xDA 0xB8 —

Device Default Address Register Name SiI9687A/SiI9617 Comment Value Offset 0x52:0x88 *TMDS1_EQ_DATA2 0xDA 0xB9 — 0x52:0x89 *TMDS1_EQ_DATA3 0xDA 0xBA — 0x90:0x01 *TMDST_CTRL2 0x01 0x41 — 0x52:0xC1 *DPLL_MULTZONE_CTRL 0xA0 0x50 — 0x52:0xC7 *MHL1X_EQ_DATA0 0x20 0x88 — 0x52:0xC8 *MHL1X_EQ_DATA1 0x40 0x98 — 0x52:0xC9 *MHL1X_EQ_DATA2 0x33 0xA8 — 0x52:0xCA *MHL1X_EQ_DATA3 0x43 0x98 — 0xE0:0x78 *REGUL_PWR_ENABLE 0x55 0x15 — 0xE0:0xE5 MHL_RST_CTRL 0x80 0x00 — OSC_CTRL_20MHz 0x0F see comment If 0xE0:0xFB ≤ 3, 0xE0:0xFA[4:0] = 0, else 0xE0:0xFA = 0xE0:0xFA (0xE0:0xFB[4:0] – 0x03). Set 0xE0:0xFA[7] = 1 0xB0:0x05 SRST 0x00 0x00 Clear Reset. Wait for 120 ms Enable FSM. Exclude 0x50:0x3A PAUTH_CTRL 0x00 0x0B non-HDCP stream ports from roving port. *Note: Initialization only. Not described in this document. See your Silicon Image representative for details. Table 17. MHL CBUS Register Preinitialization Values Device Default Register Name SiI9687A/SiI9617 Comment Address:Offset Value 0xE6:0x93 INT_ENABLE_CBUS1 0x00 0xFF Enable all bits. 0xE6:0x95 INT_ENABLE_CBUS2 0x00 0x4C — 0xE6:0x01 CBUS_DEVICE_CAP_1 0x10 0x20 MHL Version. 0xE6:0x02 CBUS_DEVICE_CAP_2 0x11 0x31 Device POW. 0xE6:0x03 CBUS_DEVICE_CAP_31 0x00 0x01 MHL Adopter ID (first byte). 0xE6:0x04 CBUS_DEVICE_CAP_41 0x00 0x42 MHL Adopter ID (second byte). 0xE6:0x05 CBUS_DEVICE_CAP_5 0x37 0x3F Video Link Mode. 0xE6:0x06 CBUS_DEVICE_CAP_6 0x00 0x03 Audio Link Mode. 0xE6:0x08 CBUS_DEVICE_CAP_8 0x00 0x41 Logical Device Map 0xE6:0x0A CBUS_DEVICE_CAP_A 0x07 0x1F Feature Support. Notes: 1. It is initialized to the Silicon Image MHL Adopter ID, but must be reset to the OEM Adopter ID. Do not leave as 0. 2. Initialization only. Not described in this document. See your Silicon Image Representative for details.

SiI-PR-1078-A © 2011-2012 Silicon Image, Inc. All rights reserved. 97 CONFIDENTIAL SiI9687A Port Processor and SiI9617 MHL 2 Bridge with HDMI Receiver Programmer’s Reference Silicon Image, Inc. References

Standards Documents Table 18 lists the standards abbreviations used in this document. Contact the responsible standards groups listed in Table 19 for more information on these specifications. Table 18. Referenced Documents Abbreviation Specification HDMI High-bandwidth Digital Multimedia Interface, Revision 1.4a, HDMI Consortium; March 2010 HDMI CTS HDMI Compliance Test Specification, Revision 1.4a, HDMI Consortium; March 2010 HDCP High-bandwidth Digital Content Protection, Revision 1.4, Digital Content Protection, LLC; July 2009 DVI Digital Visual Interface, Revision 1.0, Digital Display Working Group; April 1999 E-EDID Enhanced Extended Display Identification Data Standard, Release A Revision 1, (VESA); February 2000 CEA-861-E A DTV Profile For Uncompressed High Speed Digital Interfaces, EIA/CEA; March 2008 EDDC Enhanced Display Data Channel Standard, Version 1, VESA; September 1999 MHL MHL (Mobile High-definition Link) Specification, Version 1.0, MHL, LLC, June 2010

Table 19. Standards Groups Contact Information Standards Web URL e-mail Phone Group ANSI/EIA/CEA http://global.ihs.com [email protected] 800-854-7179 VESA http://www.vesa.org — 408-957-9270 HDCP http://www.digital-cp.com [email protected] — DVI http://www.ddwg.org [email protected] — HDMI http://www.hdmi.org [email protected] — MHL http://www.mhlconsortium.org [email protected] 408-962-4269

Silicon Image Documents Table 20 lists the documents available from your Silicon Image sales representative. Table 20. Silicon Image Documents Document Document Name SiI-DS-1140 SiI9687A Port Processor Data Sheet SiI-DS-1124 SiI9617 MHL Bridge and HDMI Receiver Data Sheet SiI-AN-0073 Handling EDID and CEA-861 Application Note SiI-SW-1137 SiI9687 Starter Kit Software SiI-SW-1168 SiI9617 Starter Kit Software

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