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Efficient Protocol Design Flow for Embedded Systems Daniel Dietterle

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Efficient Protocol Design Flow for Embedded Systems Daniel Dietterle Efficient Protocol Design Flow for Embedded Systems Von der Fakult¨atf¨ur Mathematik, Naturwissenschaften und Informatik der Brandenburgischen Technischen Universit¨atCottbus zur Erlangung des akademischen Grades Doktor der Ingenieurwissenschaften (Dr.-Ing.) genehmigte Dissertation vorgelegt von Dipl.-Inf. Daniel Dietterle geboren am 10. Februar 1978 in Eberswalde-Finow Gutachter: Prof. Dr.-Ing. Rolf Kraemer Gutachter: Prof. Dr.-Ing. J¨orgNolte Gutachter: Prof. Dr.-Ing. Adam Wolisz Tag der m¨undlichen Pr¨ufung: 25. Februar 2009 ii Abstract It is predicted that, in the next years, wireless sensor networks could be massively deployed in a wide variety of application areas, such as agriculture, logistics, au- tomation, or infrastructure monitoring. An extremely low power consumption, high dependability, and low cost are common requirements for sensor nodes in all these applications. This can be achieved only by tiny, power-efficient microcon- trollers and communication systems integrated on a single chip. Formal description techniques, such as SDL (Specification and Description Lan- guage), are suitable to formally prove properties of models designed in these lan- guages. Code generators facilitate the automatic transformation of SDL models into software implementations, while preserving the properties of the model and, thus, achieving high system dependability. The implementations consist of the translated state machine behavior and, additionally, require a run-time environ- ment for model execution. The objective of this work was to investigate an integrated design flow for embedded systems, which should allow the development of efficient and dependable system implementations from abstract SDL specifications. In this thesis, concepts for minimal SDL run-time environment have been devised and realized by an example implementation. Not only pure software implementations should be considered, but starting from these also the hardware/software (HW/SW) partitioning of the system should be supported. For this purpose, a cosimulation framework that allows the coupling of an instruction set simulator (ISS) with a functional SDL simulation has been investigated and prototypically implemented within the scope of this thesis. By shifting functionality to dedicated hardware components it is possible to take computational load from the microcontroller and to decrease the overall en- ergy consumption by reducing the clock frequency and lowering the supply voltage. Due to the use of SDL, the design flow lends itself particularly to the implementa- tion of communication protocols, and is limited to applications with soft real-time requirements. For an SDL-based design flow targeted to resource-constrained embedded sys- tems, concepts and real implementations of minimal SDL run-time environments were lacking. Available software tools, indeed, enable the transformation of SDL models into C code, however for an efficient implementation, an integration into existing real-time operating systems (RTOS) for small microcontrollers is essential. iii A prototypical implementation of a run-time library for the Reflex RTOS has been created to validate our general concepts. It is about 30 % faster and con- sumes less than half of the program memory compared to the operating system independent run-time environment of the tool vendor Telelogic. For simple SDL models, the application requires in total less than 8 kbytes program memory and 1 kbyte RAM. For the evaluation of design alternatives that realize different hardware/software partitionings, instruction set simulators are particularly suitable. They facilitate the identification of performance bottlenecks of the HW/SW system. Test stimuli are required in order to measure the performance and response time of systems under design. The development of an environment that generates such test signals can be a laborious task. Thus, it is reasonable, especially in the design of protocols, to use an SDL simulation of a communication network to generate these test stimuli. Such an SDL model already exists and is the basis for the implementation. The protocol implementation simulated by the ISS then becomes part of the network simulation. An efficient coupling of SDL simulations with instruction set simulators had to be investigated, and a solution is presented in this thesis. Based on the general concepts, a cosimulation framework for the ISS TSIM for the LEON2 processor was realized by the author. The joint SDL and instruction set simulation is very fast, which could be demonstrated by connecting a software implementation of the complex IEEE 802.15.3 medium access control (MAC) pro- tocol with an SDL simulation of a network consisting of four devices. The real execution time for 10 seconds of simulation time amounted to just 50 seconds. The overall design flow was validated by means of a HW/SW implementation of the IEEE 802.15.3 wireless MAC protocol. The author designed a complete SDL model of the protocol and integrated it into Reflex. By using our cosimulation environment for the TSIM simulator, the model was partitioned into hardware and software. For the hardware part, a dedicated protocol accelerator was designed by the author. This hardware component was integrated on a single chip with the LEON2 processor and, finally, manufactured. It could be shown that the presented methodology enables the design and implementation of efficient HW/SW systems. Consequently, it can be applied to the development of dependable and energy-efficient wireless sensor nodes and other embedded systems. Keywords: Model-based design, protocol engineering, cosimulation, IEEE 802.15.3. iv Zusammenfassung Es wird vorausgesagt, dass in einigen Jahren eine riesige Menge von drahtlos kom- munizierenden Sensorknoten in den verschiedensten Anwendungsgebieten, etwa der Landwirtschaft, Logistik, Automatisierung oder der Uberwachung¨ von Infra- struktur, Einzug halten k¨onnten. Diesen Ger¨atenist gemeinsam, dass sie einen ¨außerstgeringen Stromverbrauch, hohe Zuverl¨assigkeit und geringe Kosten auf- weisen m¨ussen. Dies ist nur mit kleinen, Strom sparenden Mikrocontrollern und auf einem einzigen Chip integrierten Kommunikationssystemen erreichbar. Formale Beschreibungssprachen, wie SDL (Specification and Description Lan- guage), eignen sich dazu, Eigenschaften von in dieser Sprache beschriebenen Modellen formal zu beweisen. Durch Code-Generatoren wird die automa- tische Umsetzung von SDL-Modellen in eine Software-Implementation unterst¨utzt, welche die Eigenschaften des Modells erhalten soll und somit eine hohe Zu- verl¨assigkeit des Systems erreicht. Neben der Umsetzung des Zustandsmaschinen- verhaltens wird auch eine Laufzeitumgebung zur Ausf¨uhrung ben¨otigt. Die Zielstellung dieser Arbeit war es, einen durchg¨angigenEntwurfsprozess f¨ur eingebettete Systeme auf der Basis von SDL zu untersuchen, der es erlaubt, von abstrakten Spezifikationen in SDL zu effizienten und zuverl¨assigen Systemimple- mentationen zu gelangen. Es wurden neue Konzepte f¨urminimale Laufzeitumge- bungen erarbeitet und beispielhaft umgesetzt. Es sollte jedoch nicht nur die Generierung von reinen Software-Imple- mentationen betrachtet werden, sondern von diesen ausgehend auch die Hardware/Software- (HW/SW-) Partitionierung der Systeme unterst¨utztwerden. Zu diesem Zweck wurde im Rahmen dieser Arbeit ein Cosimulations-Ansatz zur Kopplung eines Befehlssatzsimulators (Instruction Set Simulator, ISS) mit einer abstrakten SDL-Simulation untersucht und prototypisch implementiert. Durch die Verlagerung von Funktionen in eigens daf¨ur entworfene HW- Komponenten ist es m¨oglich, Last vom Mikrocontroller zu nehmen und den Gesamtenergieverbrauch des eingebetteten Systems durch das Absenken der Takt- frequenz und Versorgungsspannung zu verringern. Wegen der Verwendung von SDL eignet sich der Entwurfsprozess besonders f¨urdie Implementierung von Kom- munikationsprotokollen und ist auf Anwendungen mit weichen Echtzeitanforde- rungen beschr¨ankt. F¨ur eine SDL-basierte Entwurfsmethodik ausgerichtet auf extrem ressourcen- beschr¨ankte eingebettete Systeme fehlten bislang Konzepte und tats¨achliche Imple- v mentationen von minimalen SDL-Laufzeitumgebungen. Verf¨ugbare Werkzeuge er- lauben zwar die Ubersetzung¨ von SDL-Modellen in C-Code, f¨ur eine effiziente Implementation ist jedoch die Integration in vorhandene Mikrocontroller-Echtzeit- betriebssysteme (RTOS) erforderlich. Eine prototypische Implementation einer Laufzeitbibliothek f¨ur das RTOS Reflex wurde entwickelt, um die allgemeinen Konzepte zu validieren. Verglichen mit der betriebssystem-unabh¨angigen Laufzeitumgebung des Werkzeugherstellers Telelogic ist diese Implementation um ca. 30 % schneller und ben¨otigt weniger als die H¨alfte des Programmspeichers. Bei kleinen SDL-Systemen ben¨otigtdie gesamte Applikation weniger als 8 kB Programmspeicher und 1 kB RAM. Zur Bewertung von Entwurfsalternativen, die unterschiedliche HW/SW- Partitionierungen realisieren, eignen sich besonders Befehlssatzsimulatoren. Diese erlauben die taktgenaue Simulation der Ausf¨uhrung von Programmen auf einem Prozessor, h¨aufigauch von Modellen eigener HW-Komponenten, und sind um Gr¨oßenordnungen schneller als reine HW-Simulationen. Mit ihnen lassen sich zeitkritische Teile eines HW/SW-Systems identifizieren. Um Reaktionen des zu evaluierenden Systems hervorzurufen und dessen Per- formance messen zu k¨onnen, werden Teststimuli ben¨otigt.Die Entwicklung einer Umgebung, welche solche Testsignale erzeugt, kann sehr aufw¨andig sein. Daher ist es naheliegend, gerade im Bereich der
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