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Powerpc 64-Bit Kernel Internals

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Powerpc 64-Bit Kernel Internals PowerPC 64-bit Kernel Internals David Engebretsen, Mike Corrigan, Peter Bergner IBM Rochester, Minnesota engebret,mikejc,bergner @us.ibm.com f g Abstract 2 PowerPC-64 System Overview 2.1 Platforms Based on PowerPC-64 This paper describes the internals of a new imple- mentation of Linux∗ for IBM's 64-bit PowerPC∗∗ processors. This new kernel is based on the pre- existing PowerPC 32-bit kernel, with major changes The design of Linux/PPC64 has targeted execution to the memory management subsystem including a on all of IBM's recent platforms that use 64-bit Pow- new memory map, support for discontiguous real erPC processors, including both pSeries and iSeries memory, support for logical partitioning, and a new systems. mechanism for maintaining the coherency between the hardware hashed page table and the Linux soft- On pSeries systems, Linux runs directly on the hard- ware page table. ware and has been designed to support processors ranging from the POWER3∗∗ [OCW00], through the current generation of RS64 IV∗∗ (aka SStar) [BEK00], to the forthcoming POWER4∗∗ [DIE99]. On iSeries systems, multiple instances of Linux/PPC64 (as well as OS/400 and 1 Introduction Linux/PPC32) can be run in logical partitions of the system. See Figure 1. The new kernel implementation has been designed from the start to run in an iSeries logical partition, resulting in very little unique code for the two platforms. System platforms which are built around 64-bit PowerPC processors include both the pSeries∗∗ (formerly RS/6000∗∗) and iSeries∗∗ (formerly AS/400∗∗) brands. The pSeries platform typi- cally runs AIX∗∗ as its operating system, although OS/400 OS/400 Linux Linux Linux/PPC32 is also supported. The iSeries plat- V5R1 V4R5 PPC32 PPC64 Primary form runs OS/400∗∗ as its operating system. The new V5R1 release of OS/400 adds support for run- 0.25 1.0 0.75 2.0 CPU CPU CPU CPU ning Linux in a logical partition [AAN00]. Hypervisor Described in this paper is the implementation of a version of Linux designed to take full advantage of CPU CPU CPU CPU the underlying hardware and software on both the 0 1 2 3 pSeries and iSeries platforms. The kernel has been designed to minimize the code differences that are Figure 1: iSeries Partitioned System required to run in these widely different environ- ments. 2.2 Processor Architecture 3.1 Compiler Issues IBM's 64-bit implementations of the PowerPC pro- There are several interesting compiler and toolchain cessor architecture provide full 32-bit execution issues that have been introduced with the compatibility with no performance loss, a feature Linux/PPC64 kernel. that allows the Linux/PPC64 to provide excellent support of existing Linux/PPC32 applications. The first issue is that the 64-bit PowerPC ELF ABI was patterned after the 64-bit PowerOpen ABI used Although the various 64-bit processors all imple- by AIX, so its structure layout and calling conven- ment the same architecture and appear very similar tion rules are quite different than the 32-bit Pow- to operating system code, there are a few differ- erPC ELF ABI. By leveraging an existing 64-bit ences worth noting. All of the processors can toler- PPC ABI, less effort was required to port GCC to ate unaligned storage accesses, except the POWER3 the new architecture. which requires double word accesses to be at least word aligned. This fact led to complications in some The new ABI also has features some developers may places such as the token ring driver. not be familiar with, such as the Table Of Contents (TOC) which behaves in a fashion similar to the The RS64 IV provides hardware multithreading Global Offset Table (GOT). Because the TOC is (HMT) thereby presenting twice as many proces- accessed frequently, the 64-bit PowerPC ELF ABI sor contexts to the operating system as physically specifies that general purpose register R2 is to be exist. By enabling this feature, hardware contexts reserved for use as the TOC pointer. switch on certain long latency events such as an L2 cache miss, thus improving throughput. A second compiler issue of more practical impor- tance is that the PPC64 compiler is still under de- POWER4 adds a two core per chip design plus some velopment. Currently, it is able to build statically small changes to the address translation path. linked applications such as the Linux kernel. How- ever, it cannot build dynamically linked programs Both RS64 IV and POWER4 provide enablement due to unfinished work in the compiler and lack of a for logical partitioning. This includes features such PPC64 glibc implementation. This limitation pro- as a hypervisor state that is distinct from privi- vided a strong incentive for supporting unmodified leged state and the protection of critical processor PPC32 binary applications. resources such as the hardware page table pointer from code not running in the hypervisor state. 3.2 PowerPC Specific Data Structures 3 Kernel Internals The PPC64 kernel implementation has added two data structures which are used to store system wide and processor specific information. The first, the naca (node address communications area) is This section describes the features that have been used to hold system wide information such as the implemented to support 64-bit PowerPC processors number of processors in the system (or partition), where the kernel may be running natively on pSeries the size of real memory available to the kernel, hardware or in an iSeries logical partition. and cache characteristics. In addition, this data structure contains one field architected by the As is the case with all other operating systems used iSeries hypervisor which is initialized (at kernel on these platforms, Linux runs in big endian mode. build time) to point to the data area used by the The 64-bit PowerPC ELF ABI [TES01] dictates the hypervisor to communicate system configuration LP64 data model be used as it is in every other 64- data (vital product data or VPD) to the kernel. bit Linux implementation. This means that vari- The naca is always located at a fixed real address ables of type long and pointers are defined to be (0x4000) in order to facilitate debug. 64-bit, while an int is defined to be 32-bit. The second data structure is the paca (processor 3.3.2 iSeries LPAR address communications area). This structure con- tains information unique to each processor; there- Before the Linux kernel gets control, the iSeries hy- fore an array of paca's are created, one for each log- pervisor: ical processor. The biggest use of this data structure is as a save location during interrupt processing. Special Purpose Register 3 (SPRG3) of each proces- 1. Assigns memory to the partition as a 64 MB sor always points to the virtual address of the paca contiguous load area and the balance in 256 associated with that processor. Upon an interrupt, KB chunks. the value stored in SPRG3 is read and used as a base pointer to the paca where a small amount of proces- 2. Loads the Linux kernel into the load area. sor state is stored while relocation remains disabled 3. Provides system configuration data to the and a kernel stack is not yet available. Linux kernel via several data areas provided within the Linux kernel. 3.3 Initialization 4. Sets up hardware translations to the Linux ker- nel space address (0xC000. ) for the first 32 MB of the load area. The early phases of boot and initialization differ be- 5. Gives control to the Linux kernel with reloca- tween the pSeries and iSeries platforms. This sec- tion enabled at the System Reset interrupt vec- tion describes some of the differences. tor on each of the assigned processors. The Linux kernel continues the initialization as fol- 3.3.1 pSeries Native lows: Initially, the kernel is loaded by a bootloader (for 1. Builds an array (called msChunks) which is example Yaboot [Yab01]) into a contiguous block used to map the kernel's view of real addresses of real memory and given control with relocation to the actual hardware addresses. See Section disabled. Initialization code in the kernel interacts 3.4. with OpenFirmware (OF) [OF94] to accomplish the following tasks: 2. Builds an event queue which is used by the hy- pervisor to communicate system events (I/O in- terrupts) to the partition. 1. Determine the system configuration including 3. Opens a connection (via the hypervisor) to a real memory layout and the device tree. hosting partition for virtual I/O. 2. Instantiate the Run-Time Abstraction Services (RTAS), a firmware interface that shields the To provide partition isolation, the iSeries hypervisor operating system from many details of the requires (and enforces) that all code in an iSeries hardware platform. partition runs with relocation enabled. 3. Move secondary processors from spinning in OF to spinning in a kernel loop. 3.4 Address Space Layout The initialization code then relocates the kernel to The PowerPC architecture defines the address space real address 0x0. Next, an initial kernel stack is seen by an application to be the effective address. created, the TOC and naca pointers are initialized, This address is passed through a translation mecha- and an initial hardware page table (HPT) and seg- nism (for example a segment table) which produces ment table (STAB) are built to map real memory what is known as a virtual address. This address is from 0x0 through the HPT itself. Finally relocation then translated by the hardware page table to pro- is enabled and initialization continues through code duce an absolute address used by the hardware to common to both pSeries and iSeries.
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