COMPUTER CONTROLLED AUTOMATIC TEST SYSTEM FOR TESTING INTEGRATED CIRCUITS
Report an the abuue project as: part of the requirements for tfie award of The degree of
MASTER OF ENGINEERING SCIENCE in ELECTRICRL ENGINEERING b'j ROBIN LESLIE ARTHUR WALTON B. Sc.[Tech]
Superuiser Mr. F.Lewir.
MARCH 1972 UNIVERSITY OF N.S.W.
^ 5 OCT 1987
Library CONTENTS
List of Figures 3 Summary 5
Introduction 6 1 Philosophy of Automatic Testing 8 2 Example of Testing Problem 10 3 Selecting a Configuration 15 4 Selecting a Specification 17 5 System Specification 21 6 General Description 24 7 Details of Operation 28 8 Software 32 9 Programming Test Plans 35 10 Test Station 40 11 Multiplexer 47 12 Cross-point Matrix 50 13 Power Supplies 60 14 Measuring Unit 73 15 Controller 80 Conclusion 89 Acknowledgements 90
Bibliography 91 3
LIST OF FIGURES
Fiq. Title Page 1.1 Simplified Auto-Test System 8 2.1 TTL Inverter 10 2.2 TTL Example Test Set-up 10 2.3 TTL Example Flow Chart 12 2.4 TTL Example Test Program 13 2.5 TTL Example Test Program Without Comments 14 3.1 Expanded Auto-Test System 15 6.1 Complete Test Set and Computer. Photograph 24A 6.2 Complete Test Set Block Diagram 27 7.1 'Test System Operation Flow Chart 31 8.1 System Software Core Allocation, Table 34 10.1 Test Station No 1. Photograph 40A 10.2 Test Deck Logic Diagram 43 10.3 Test Deck and Control Logic Diagram 46 11.1 Test Station Multiplexer Logic Diagram 48 12.1 Cross-Point Matrix and Multiplexer Front Panel 50A 12.2 Underside of Cross-point Matrix and Multiplexer 50A 12.3 Reed Relay Circuit 51 12.4 Simplified Cross-Point Logic Diagram 52 12.5 Current Distribution In Clock and Data Lines 53 12.6 Cross-Point Matrix Control Logic Diagram 56 12.7 Reed Relay Card Circuit Diagram 57 12.8 Reed Relay Card. Photograph 58 13.1 Power Supply Front Panel. Photograph 60A 13.2 Buffer Cell Logic Diagram 61 13.3 Mode Register Allocation 62 13.4 Simplified Power Supply Logic Diagram 63 13.5 Constant Current Mode Configuration 64 13.6 Constant Voltage Mode Configuration 64 13.7 Power Controller Circuit Diagram 66 13.8 Power Controller. Photograph 67 13.8A Power Controller Component Layout 68 13.9 12-Bit Store and Gate Card Logic Diagram 69 13.10 12-Bit Buffer and Gate. Photograph 70 13.11 Power Supply Complete Logic Diagram 71 14.1 Measuring Unit Front Panel. Photograph 73A 4
Fiq. Title Page 14.2 Absolute Magnitude Converter Modes 74 14.3 Measuring Unit Logic Diagram 76 14.4 Absolute Magnitude Converter Circuit Diagram 77 14.5 Absolute Magnitude Converter. Photograph 78 14.6 Conversion Done Flag and Miscellanious Gate Card 79 15.1 Computer I/O Simulator Logic Diagram 85 ' 15.2 Computer I/O Level Converter Logic Diagram 86 15.3 Test Set Interface and Address Register Logic Diagram 87 15.4 Layout of Modules in Interface and Power Supplies 88 5
SUMMARY This report describes a computer controlled test system to screen integrated circuits in a manufacturing environment. Integrated circuits are tested three times during the manufacturing cycle and each requires a large number of tests to ensure it functions correctly.
The system provides a number of power - supplies, a measuring unit and a means of interconnecting these under external control. To facilitate the setting up of the various tests a software controller is used. This allows comparison of readings, conditional branching and data logging, to name a few features.
The controller is a PDP8/I computer operated in a foreground/background mode with testing as the foreground task and program preparation a background task. Data logging is punched out on paper tape and processed on a larger PDPQ/l configuration with a 340 line/minute printer.
The programmable power supplies provide plus and minus sixteen volts or plus or minus one hundred milliamps. The measurement unit measures voltages from twenty volts to two millivolt and currents from one hundred milliamps to twenty nanoamps.
The system is multiplexed to four test stations which can each be operating on the same test plan or completely different plans. 6
INTRODUCTION
The manufacture of integrated circuits produces wafers containing on average, 400 circuits. These circuits must be thoroughly tested before being separated and packaged because the cost of packaging is a major factor in the price of an I.C. This combined with, the fact that yields of 20/£ to 60/ are common, means accurate and complete wafer testing is essential.
To test a circuit completely can take scores of tests with a figure of 25 being about average. This means about ten thousand tests a wafer must be performed, and connection made to some 10 or more pads. In a manufacturing environment, which is concerned essentially with custom designs, elaborate test jigs are too time consuming and uneconomical.
For a stable processing line the D.C. parameters give an excellent measure of the circuits performance capabilities, thus 100^ D.C. testing with sample dynamic testing in a majority of cases will give good results.
It was decided at the A.W.A. Microelectronics facility to acquire a flexible general test system. To meet the requirement of quick change-over and ease of operation a computer controlled system was decided upon. A survey of the available commercial equipment revealed that a few very expensive (greater than. $100000) systems were available. On reviewing the specifications of these machines the author, in consultation with Dr G. Rigby,drew up a cost estimate of designing our own system. This showed the following advant ages in building our own system. 1) Low cost (approximately half equivalent overseas) 2) Our specifications to suit our usage 3) Expertese gained in the exercise useful for further system design 4) Local maintenance and modification greatly simplified 7
The author was thus given the job of specifying, designing and constructing the computer controlled Test System described in the following report.
The design is similar to most overseas units, as far as can be gathered from sales brochures. No detailed information on these proprietary systems is available, so any similarity is due to the similarity in goals.
The major difference between this system and say Teradyne is the emphasis on data logging and acquisition on our systems as against go/no-go on the other systems. Because of this a hardware analogue to digital converter is used and go/no-go decisions made in the computer software. This gives a conversion time of 10 us against 10 mS when data logging is required.
The Department of Supply, who have contracted A.W.A. to establish an integrated circuit facility, provided a PDP 8/l to run this test system. It was decided to use this machine, after careful consideration of those available. Factors taken into account include the precision required 10 - 12 bits, software back up, peripheral availability and the availability of similar modules to use in the Test Set proper.
A considerable number of Digital Equipment Modules were suitable for this system. The author was originally to do the software as well as the hardware, but due to lack of time and an offer from the Department of Supply to issue a software support contract for the facility, this was not the case. Mr R.N. Walker of Technical Computing and Graphics has developed the software from the requirements set out by the author in consultation with other design engineers in the facility. These are shown in the following report. 0
CHAPTER 1
PHILOSOPHY OF AUTOMATIC TESTING 1.1 ’ The basis of any automatic testing system is a controller, some stimuli, sensors and a means of connecting these to the device under test.
device STIMULI SWITCH - UNDER RND BOPRD TEST CONTROL
SYSTEM
SIMPLIFIED AUTO-TEST SYSTEM
1.2 The device under test (D.U.T.) is connected to the test svstsm via a switchboard. For each test this sets up the appropriate connections to the stimuli and sensors. This must be done without causing any significant change in the inherent properties of the D.U.T. or any loading or colouring of parameters being transmitted. The controller must be able to quickly alter this switchboard.
1.3 The stimuli must be such as to adequately exercise the D.U.T. in a way, that the sensors can measure the parameters desired, to ensure proper operation. These stimuli must be set in the correct mode and to the correct amplitude by the controller at a rate compatible with the overall testing speed required. The sensitivity and mode of the sensors must also be set by the controller.
1.4 At this stage a decision must be made as to whether the sensor readings are acceptable, and suitable action taken. In the case of a failure, this could be to abort or apply a different set of conditions, and re-test, or different limits. 9
1.5 If the sensors show a correct response, then the next test is initiated. This ability to make conditional variations in the test sequence is essential for classifying the devices under test into various categories. It also gives more realistic testing of overall operation, taking into account that it is generally the combination of parameters that determines the functional soundness of a device. 10
CHAPTER 2
EXAMPLE OF TESTING PROBLEM 2.1 Let us consider an example of a logic inverter, that has the following properties 1)
xccH>
FIG. 2.1 TTL INVERTER
If V. = 4.5, V = 5.5 Volts, Z is r< the I must be V. = 4.5, V =5.25 Volts, Z is the I must be ^ 4.3 mA l cc o cc FIG. 2.2 TTL EXAMPLE TEST SET-UP 2.2 To implement this, the device under test is connected as per Fig. 2.2 Pin 7 is connected to ground Pin 1 is connected to a stimula of + 4.5 volts Pin 14 is connected to a stimula of + 5.5 volts D Texas Instrument Catalogue 11 The current into pin 14 is sensed and checked to ensure it is less than 4.3 mA, if not a flag is set to say it is not a Class A device, and the stimulus on pin 14 is reduced to 5.25 Volts, and the current again sensed. If it is below, continue testing, if not fail the device and stop testing. 2.3 Setting this out more formally we can say Test 1 (Connect) Pin 7 Ground Pin 1 Stimuli 1 Pin 14 Stimuli 0 Set Stimuli 1 4.5 Volts Stimuli 0 5.5 Volts Turn on Stimuli Wait for conditions to reach equilibrium Read Current from stimuli 0 Check Is current <*4.3 mA Yes Go to test 2 No Fla^ A = 1 Set Stimuli 0 to 5.25 Volts Wait Read Check Is current < 4.3 mA Yes Go to test 2 No Fail Figure 2.3 is a flow chart of the above example Figure 2.4 is a typical program to execute the above Figure 2.5 is the same program with comments removed to show the essential statements. 12 TEST READY TO TEST? SET UP CONNECT IONS SET STIMULI NO. 0=S.SV NO. 1 = 4- .SV TURN ON ST IMULI WRIT FOR READ TEST OTHER CURRENT PRRRMETERS X - GO TO FLAG 1? N SET FLAG R= 1 NOT CLRSS R SHOW THAT DEVICE FRILED. GO TO FIG S 3 FLOW CHRRT FOR TEST EXAMPLE 15 /TFST A LOGIC INVERTER / /SET UP CONNECTIONS SXP PL 1 /SET UP SWITCH BOARD AS PEP TAPLF PL 1 / /SET UP STIMULI SPS SUSLM /SFT STIMULI 1 TO CONDITIONS as PER /TAPLF SL 1 1ST ENTRY SMU C 1 PM > SL 1 > P /STIMULI 0 IS COMBINED WITH SFNSOR /SET STIMULI C TO CONDITIONS AS PER /TABLE SL 1 PND ENTRY /SFT SENSOR RO READ CURRENT 0 >» 1PMA RANGE /TURN ON stimuli PWR ON! ALL DO DOL 1 > XK> \>P /MAY HAVE TO DO THIS TWICE / /WAIT FOR CONDITIONS TO SETTLE DLY 1 / /READ SENSOR RMU A A1 /READ SENSOR & GO TO AA1 IF UNSTABLF / /CHECK IF IN LIMITS LMT - 1 * AA?* AA?* AA 1 > /3P /<4*3MA GO TO. A A? /> A •3M A GO TO AA 1 / /FAILED LIMIT SET FLAG AA1 * CLP R1 /CLEARS PIN ) I-E. DEVICE NOT CLASS 1 SM U C 1 PM > SL 1 > 3 / ST I M UL l P TO /> • 5 VOLTS /AS PER TABLE SL1 3RD ENTRY DOL1> CNT /GO RACK AND TRY ANOTHER VOLTAGE / /EXIT FROM DO LOOP IF FAILED LIMIT TWICF /****** p a I l IJ R E ***** * ROT B1 3 /IF WE GET TO HERF WTHE DEVICE HAS FAILED /TURN ON REJECT PIN 13 LIGHT AND ADOPT /TESTING THIS DEClVE SHOW OPERATOR /IF WE GET HERE THE DEVICE IS GOOD SO FAR CONTINUE TESTING AAP, TEST ? / /LAST STATEMENT OF TEST ROUTINE END / /PI N L I PR API FS PL1, P7J0 /PIN 7 TO GROUND (REFERENCE) P-JPIA /PIN 1 A TO STIMULI 0 AND SENSOR PIJC /PIN l TO STIMULI 1 /NOTHING TO STIMULI P SL 1 » PSL VIO'ClPM /VOLTAGE RANGE X10 JCURRENT OVERLOAD !0MA A5C /A•5VOLTS 550 / 5 •5C VOLTS 5?5 /5•P 5 VOLTS $ FIG. 2.4 TTL EXAMPLE TEST PROGRAM /TEST A LOGIC INVERTER TEST 1 SXP PL 1 SPS SI> SL 1 , ] SML1 C 1 CM, SL 1 > ? PWR ON! ALL DO DOL LXKj 1, ? DLY 1 RMU AA1 LMT - \ r A A P > A A P > AA]a3 0 AA 1 * CLP PJ SMU C 1 0M > SL 1 > 3 DOL 1, CN T RJT PI 3 AA 2, TEST P END PL 1 > P7; 0 O; p l a P7; 0 0; 0 / SL 1 , PSL V10!C10M 4 50 550 5P5 $ FIG. 2.5 TTL EXAMPLE TEST PROGRAM WITHOUT COMMENTS 15 CHAPTER 3 SELECTING A CONFIGURATION 3.1 From the typical example we can expand Fig. 1.1 to Fig. 3.1 SPARES SWITCH - i SPflREl N ST 1 M H- BORRD T DEVICE ST X M S ------E>.. — ---- £>. ■ E AND R UNDER ST IM £ F ST I M 1 ------...... — ------R TEST CONTROL SENSOR ------, ------MULTI ------^--- C GROUND PLEXER E SYSTEM OPER -f RT OR PANEL] FIG. 3.1 EXPANDED AUTO-TEST SYSTEM 3.2 The device under test has to be connected to the switchboard in such a way that it is convenient to change devices and device types. The operator must be able to indicate to the controller that another device is ready to be tested. The controller must have a means of indicating to the operator the results of the test and that it has finished testing. (See Chapter 10). These observations can be done at an interface or test station. Generally the operator only requires to know the category of the device and not specific readings, but for more detailed evaluation, means must be provided to obtain the readings for each test. This can be done at a site other than the test station. (See Operation Chapter 7). 3.3 To provide efficient interface between the human operator and/or device handling machines the system should be capable of cycling round a number of test stations. This multiplexing must be as far down the chain towards the device under test as possible, so as to give best utilisation of hardware, without reducing through-put of tested devices or degrading operator convenience. 16 The switch board can be considered to contain two sections. 1) The cross-point matrix capable of connecting any combination of inputs to any combination of outputs (Chapter 12) and 2) a multiplexer to connect all outputs of cross-point matrix to the corresponding outputs of the test station. (Chapter 11) This switch-board should be capable of carrying fast changing D.C. voltages and currents. It should be preferably screened to minimize noise and cross talk and be suitable for four point or Kelvin probing (see Cross-Point Matrix - Chapter 12). The stimuli should be capable of supplying voltages and currents suitable for the class of device under test. They should have a means of storing the parameters to be supplied so that once set-up they remain in that state until again accessed by the controller. (See Power Supply Chapter 13). The sensor must be capable of measuring the full range of voltage and current available from the stimuli and convert this to a form which can be used to check the measurement obtained. (See Measurement Unit - Chapter 14). The controller determines the order of operations of each of the above units and determines the next operation on the basis of results obtained to that point in time. It should be easy to change the "test plan" for each device. Since multiplexing is advocated it should be possible to have a number of different "test plans" 'active' at once. Thus if each test station is testing a different device no appreciable time is lost in starting the test as each station is polled. These points are covered more fully in the chapter on the controller and inter face. (See Controller - Chapter 15). 17 CHAPTER 4 SELECTING A SPECIFICATION 4,1 As a compromise between a truly universal test system and an economic system it was decided to specify the test set for the most common uses envisaged. 4.2 The majority of the Integrated Circuits used are digital or non-linear devices. A review of those indicate a range of voltages as shown in table 1. DTL 0 5.5 0 60 mA TTL 0 5.5 0 80 mA RTL 0 4.0 ECL 0 -5.5 HLDTL 0 16 4,3 A review of available components D with which to make this system showed that _+ 18 volts could be achieved using off the shelf I.C. This was consistant with the specification in the advertising handouts for other commercial I.C. testers. 4.4 After discussing their requirements with the other design 2) engineers the following specification was drawn up. 4.4,1 Test Station 24 pin withKelvin point to the socket. Up to 16 lights to indicate results of test. A minimum of operator controls, preferably one push button * An indication that the device is being tested and that the system has received a request to test. 1) D.A.T.A. Linear Integrated Circuit Handbook 2) Dr G.A. Rigby - Chief Design Engineer; P.D. Lunsmann - Process & Planning; P.S. Smith, J.R. LeStrange, 3.R. McCluskey - Design Engineers and myself as Quality Control Engineer and Test systems designer. 18 4.4.2 Power Sources +_ 16 volts 100 mA Current overload programmable Constant current 100 mA 4.4.3 Measuring 100 mA F.S.. 100 pA resolution of lowest scale 16 volts 20 mV resolution better resolution for small voltages Fast data logging 4.4.4 Cross Point Fully addressable so that if necessary all or any cross-point may be set. A comparison with the specification in the next chapter for the completed test system shows these parameters were all satisfied. 4.4.5 Controller and Interface The requirements for the controller of the test system are briefly: 1 Step quickly through a number of test operations 2 Branch to alternative operations as the result of any particular test 3 Control the mode of all the components of the system 4 Quickly and easily change test plans for a large number of different devices 5 On the basis of tests passed and failed, indicate the classification of the oevice under test 6 Record selected readings of selected devices 7 Accumulate number of devices in each category 8 Cycle througn a given number of test stations and possible use of different plan for each. 19 4.4.5*1# To achieve some or all of these, a number of approaches are available. The two most commonly used in commercial systems are a multi-channel paper tape reader, eg Marconi "Auto Tester", 1 ) and a computer controlled* system. 4,4.5.2 Sequential Reader The paper tape system uses a loop of material - paper tape, mylar tape etc., - with operations coded as a sequence of holes. These characters are read and de-coded by the control hardware to perform the sequence of tests. This system can readily meet some requirements and others are extremely difficult, 1 This can readily be achieved up to 300 steps a second 2 This is difficult and can only be achieved by skipping past a series of tests. Any loops must be coded in full as addressing and searching would be slow and difficult 3 O.K. 4 An operator changes the tape 5 This can be achieved with a series of hardware flags and masks 6 Expensive on hardware if totals are accumulated in counters and the counters either manually read or multiplexed to a printer or punch 7 See above 8 Possible only if a separate reader for each test station is used 4.4.5.3 Mini Computer control The availability of small general purpose digital 2) computers for around $10,000 opens up a new avenue for general systems control. The ability 1) Marconi Auto Test Catalogue 2) (a) Digital Equipment (Aust) Pty Ltd (b) Hewlett Packard (c) Raytheon et al 20 to achieve the above aims is limited only by the ability of the programmer to develop suitable soft ware in the core available. The speed of set-up depends on complexity of the hardware but is better than an order of magnitude greater than the 'paper' tape method. 21 CHAPTER 5 SPECIFICATION 5#1 Power Supplies Constant Voltage Diode _+ 16 volts in 10 mV steps or .+ 2.0 volts .in 1.0 mV steps current overload can be set at ± 12 uA, _+ 120 uA, + 1.2 mA, +, 12 mA, .+ 120 mA Constant current mode ± 12 uA, _+ 120 uA, _+ 1.2 mA, +_ 12 mA, _+ 120 mA each current has a resolution of .1^ Note: There is a small offset of - 1.4 uA which can be significant at low current settings. 5.2 Measuring Unit _+ 20 volts 20 mV resolution _+ 2 volts 2 mV resolution _+ 100 mA .1 mA resolution _+ 10 mA 10 uA resolution + 1 mA 1 uA resolution +_ 100 uA 100 nA resolution _+ 10 uA 10 nA resolution Note: Offset also applies to this unit see Power Supplies above 5.3 Cross-Point 8 x 24 random (2 word) access matrix using three-wire connections with .1 uS latching time 2 mS settling time. 5.4 . Multiplexer 24 x 4 switch with some characteristics as the cross-point 5.5 Test Deck 16 binning indicator lights, 12 pass 4 failure; start button; status indicator, operating, finished and request not recognised; and a means of selecting the test plan required. A universal socket (up to 16 leads) and a 24 lead D.I.L. socket Interface A means of simulating computer data and pulses to allow fault diagnosis. Controller 'Mini-computer' with 12 bits or more per word, 8K words of core, high speed paper tape reader and punch, and at least 32K words of fixed head disk. 24A FIG. 6.1 COMPLETE TEST SET AND COMPUTER. PHOTOGRAPH 24 CHAPTER 6 GENERAL DESCRIPTION 6.1 This system is designed to test the D.C. parameters of integrated circuits (or module containing similar functions). It consists of a number of major components as shown in-the accompanying diagram (Figure 6,2). The complete system is shown in the Photograph Figure 6.1. The computer controls the whole of the testing, including setting up the connections, the power supplies, measurement and decision making. It is connected to the TEST SET by the TEST SET INTERFACE which converts signed levels, recog nizes and routes data destined for the TEST SET, and strobes results back to the computer, 6.2 Computer (Comp) The computer used is a PDP 8/1 with 8 thousand 12-bit words of core memory, a 32 thousand word disc, a high speed reader and punch. 1) These units are assembled in a single floor mounted cabinet 22" x 72" x 30". 6.3 Test Set (T.S.) The Test Set proper consists of the following: 6,3.1, An interface and controller to the PDP Q/l computer To minimize the number of I/O positions used on the computer, the test set has an address buffer which is up-dated by the computer and routes the data to and from the various units. The first 6-bits of the "ADDRES" word are de-coded to select the particular test system (first 3-bits) and the particular module in that system (second 3-bits), i.e. power supplies 1,2,3,4,5 measuring unit, test unit and croon-point matrix. The second 6-bits are used as control functions, which vary with, and are therefore supplied in an "ADDRES" D Digital Equipment Small Computer Handbook 1970 25 buss to each unit, A second buss, "DATIN'1 provides 12-bits of data to the unit selected by the "ADORES" buffer. For power supplies this is a "twos complement" magnitude word; for the cross-point it is the column points to be connected for each half row. The third buss "DATOUT" has data gated onto it, under control of "ADORES" buffer, for supply to the computer. This is read in via the first I/O slot to the computer accumulator for checking status and limits. The eight addressable units, one of which is four multiplexed devices, are described briefly below. 6.5.2. Cross-Point Matrix (X.P.M.) (Unit Address 0) This unit consists of a number of reed relays which connect the DEI/ICE UNDER TEST (D.U.T.) to the various power supplies and the measuring unit. It also contains the MULTIPLEXER (M.P.L.X.) to allow connection to the appropriate test decks, 6.3.3 Power Supplies (P.S.N.) (Unit Address 1 to 5 inclusive) The Power Supplies of which there may be up to five, contain a digital to analogue converter, a D.C. power amplifier with reed switching for voltage range (2), current range (6) and constant current/ constant voltage selection. These units are current limited in the constant voltage mode and can supply or sink current at any voltage (within their range, _+ 16 voits). Power supply five is permanently connected to the MEASUREMENT UNIT (M.U.) and acts as a forcing supply for that unit. 6.3.4 Measurement Unit (M.U.) (Unit Address 6) Tnis unit is permanently linked to P.S.5 and consists of an analogue signal conditioner and an analogue to digital converter. It produces 26 a sign magnitude eleven digit representation of its input, 6.3.5 Test Deck (T.D.) (Unit Address 7) Up to four of these units can be connected to one T.S, Each deck has facilities for indicating the test plan required (0 - 99) a start testing button, request noted light (red), a request recognised and waiting or testing, and a set of sixteen lights (bins) to indicate the result, 6.3.6 Software 2) The main features of the software are that it is open-ended and can be extended with minimum modification. Provision is made for up to four different programs being in core memory at one time and all four stations can work the same program if desired. All stations may data log. If required, the software also provides for programs to be swapped between disc and core during normal testing, as well as allowing large data-log records to be dumped into a second computer for processing. 2 Software development carried out by R.N. Walker of Technical Computing & Graphics Pty Ltd under Department of Supply Contract ME AS FIG. 6.2 COMPLETE TEST SET BLOCK DIAGRAM 23 • CHAPTER 7 DETAILS OF OPERATION 7.1 To start testing a particular device a test plan must be written and compiled (see Chapter 9 on Test Plan). This is loaded onto the disc of the computer with a disc update program. (See Chapter 8.9). This program also loads the options selected at load time by a question answer interchange with the operator. Figure 7.1 shows a flow chart of the system operation. 7.2 The operator sets up, on the test deck, the number corresponding to the test plan required and presses the start button. This sets a flip-flop TSTFLG'n' (n = 1 to 4) and lights up a red light on the test station, to indicate a request for service has been made. At the same time the interrupt signal buss of the computer is pulled to zero. The operating system then saves the current status of any program running and determines which station caused the interrupt. This is done without changing the multiplex switches or the status of any power supplies of the test set. The system then returns to the current program and continues until it has completed testing the current device, 7.3 When the present test plan is completed for that device the system checks to see if any other station is requiring service. If so it starts to service the next station in the order 1,2,3,4,1,2 etc. This station can be in one of three modes previous to this request. 7.3.1, Previous plan was number 0. This is a special situation that means no plan is in core for this station and a summary sheet has been printed, two possibilities exist. 7.3.1.1 The new plan-is 0. The flags are cleared and the system checks for another station requiring service. If there are none the system returns to background processing. 29 7*3.1,2 The new plan is not 0 then it is loaded and execution commenced*(see 7,5.) 7.3.2 Previous plan was same as the new plan and not 0. In this case the program starts testing the device(see 7,4.) 7.3.3 Previous plan was different to new plan and previous plan is not 0. 7.3.3.1 If the new plan is 0, then a summary sheet is printed and core occupied by the plan released. The system then clears the flags and goes back to see if any other stations require service. 7,3.3.2 If the new plan is not 0 then the system performs the actions as 7.3.3.1 but instead of going to the next station, it loads from the disc the new plan (see 7.5) and begins execution of it. 7.4 While a device is being tested the system locks out back ground programs. The interrupt system is ON to handle device requests and station requests for service. These requests are logged to later servicing and the current plan resumed. 7.5 When a station requires a new program the following action takes place. 7.5.1 If the same program is in core, used by another station, copy the option region from that station into the present station and begin testing. 7.5.2 Look up the disc directory and see if a program has been saved under that number. If not give an error message and return to system control. 7.5.3 The program is on the disc. Check to see if it can fit in the available core, if not type error message otherwise load into core, load option block into the communication region for the cur rent test station and begin execution. If the present program required data-logging, check that the punch is turned' on, if not tell operator, and punch out a header with test plan number and test station number# (See Chapter 8.) During execution of the program the options are checked at each LOG instruction and these are processed. As the power supplies, cross-point etc. are altered, a record is maintained in the communication region of their current status. At the completion of the test plan the bins are checked and the first zero bin is taken as the result. This number can be re-mapped, as set up in the options, to a different number. The testing in progress flag is cleared and the syst'em checks for further service requests. m i FIG. 7.1 TEST SYSTEM OPERATION FLOW CHART 31 32 CHAPTER 8 SOFTWARE The software for the system was written by Mr R.N. Walker of Technical Computing and Graphics under a contract to the Department of Supply. This was done in close and constant consultation with the author. The requirements and goals were set by the author in consultation with Mr R.N. Walker, Dr G.A. Rigby and other designers in the AWA Microelectronics facility. 8.1 The whole system ooerates in a Foreground/Background mode based on a monitor program by Mr John Alderman. 1) This allows the test system to have priority use of the processor and peripherals. The background programs are any program working in 4K of core and includes the test program loader TUPT, the editor EDIT and compiler TSMC. 8.2 The compiled test plan consists of calls to system macro routines with parameters following the call. This allows the program to load across page boundaries and only requires the address locations to be flagged to provide page re- locatability. 8.3 The software overlays itself to provide maximum core for ’Test Plans' the core allocation and overlays are shown below. 8.4 It can be seen from the figure 8.1 that there are 13 (decimal) pages for Test Plans. There is also, for each 'Test Station', a communications region to store the current test set status for datalogging purposes, and an accumulator region to store the number of devices failing specified tests (up to 32). D Foreground/Background/8 now by J.C. Alderman Jr. Georgia Institute of Technology Atlanta, Georgia Decas Program 8-230. 33 8.5 The overlays are so arranged that they do not contain counters or flags which have to be retained, therefore overlaying only involves a 'read' operation and not a swap 'write-read' operation. 8.6 Background programs occupy the 2nd field of core, and, in general, do not require modification. All 'field change' instructions are ignored- and 'halt' instructions cause a return to monitor. 8.7 The 'Test Plan' format is described more fully in Chapter 9 (Programming Test Plans) and appandirx A (Extracts of from 'Test Plan Writing for Automatic Test Set' by R.N. Walker). 8.8 A listing of the Software is company confidential and is supplied under separate cover. 8.9 The program to load test plans onto the disc is run under 'background' and is called 'TUPT'. An example of the dialogue is shown in figures 8,2 and 8.3. The question type out halts as soon as a character is entered. Only legal characters for the particular question are accepted and echoed. Illegal characters are ignored eg, an answer other than ' Y' or ' IM' for the question UPDATE? is ignored and anything other than an 'R' or an 'S' followed by a number is ignored for INPUT? 34 0- 177 GENERAL POIMTFR AMD CONSTANT REGION 200“ 377 FOR EG RO UN D/RACK G ROIJM D 40P~ 577 MOM I TOR 600“ 777 1000-1177 MONITOR COMMUNICATION REGION FOR 1000-1366 TEST STATIONS 1 > 2* 3 * 4. 1 400-1577 1600“ 177 7 2000“2177 T E S1' S E 7 M 0 NI T 0 R AN D PART OF 2200-2377 COPE ALLOCATOR ! 240P-2577 MESSAGE ROUTINES CORE ALLOCATOR TEST SYSTEM 2600-2777 DISK SEARCH SAM BLOCK SEARCH MACROS 3000-3177 LOADER FROM DISC ! AND 3200-3377 FOREGROUND/ BACKGROUND DATALOGGING 3400-3577 AND SYSTEM MESSAGE ROUTINES 3600-3777 ROUTI NFS 4000-4177 DISK BUFFER 4200- TEST PLANS (13 DECIMAL PAGES) DYNAMICALLY ALLOCATED AND LOADED INTO THIS REGION 7377 7 400-7 57 7 ACCUMULATORS FOR STATIONS 1*2*3 &4 7600-7777 FOREGROUND DISK I/O- 6 MONITOR HEAD FIG. 8.1 SYSTEM SOFTWARE CORE ALLOCATION. TABLE •HIE! TF'Sl PLAN NO.? 7_ UPPATF ?Y INPUT S1 P AT A-LOGGING? OVFR-RTPF _N CHANGF HTN STNGLF STFPPN SUMMAPY SHFFT1-IP. TFST PLAN NO.? fc FIG. 8.2 DISC UPDATE DIALOGUE (QUESTIONS IN FULL) . TUPT TFST PLAN NO. ? _7. INPUT Pt__ PA TA -LOGO TNG? Y_ ALT, TESTS? _N LT S T T F STS. FT NT SH VT TH A . 1,3-K,IP. FVFPY PFVTCF? N_ TVT PY N Tw PFVTCF? PASSFP PFVTCFS? JN FAILFP PFVTCFS? _Y OVEF-PTPF AUTO PFTTFCT? N_ CH ANGF PT M PPT 0RI TIFS? k STNGLF STEPPING? j± SUNNA PY SH FF T IF S T S. F T N TSH U TH A . 1-13. TFST PLAN NO.? fc FIG. 8.3 DISC UPDATE DIALOGUE (QUESTIONS INTERRUPTED BY ANSWER) 35 CHAPTER 9 PROGRAMMING TEST PLANS The designer writing a test plan for Automatic Test Set has at his disposal three power supplies, a measuring unit and a means of interconnecting these. Around these basic devices he has a number of software aids and techniques. SETUP STATEMENTS 9.1 To provide ease of modification and changing the pin connections, (eg, the same device, on prober and in a package has different pins) all instructions to connect pins, reference a pin library# These libraries are at the end of the program after the executable statements. 9.2 The instructions to set the cross-point matrix are two in number. 9.2.1 Set Cross-point (SXP) sets the first four lines in (Ground, Measurement Unit, Power Supply No 1#, Power Supply No 2). This instruction turns all power supplies off (zero amplitude) before changing the cross-point matrix. This is to ensure that the device is not unduly stressed due to the fixed order of changing the cross-point. 9.2.2 The Second instruction changes one line only and does not switch off the power supplies. It also has an index parameter to enable moping through a number of pin connections. The forms are: GND MSL1B, XL MUT PIN22, 1 where GND, MUT, PSU N, SPL N refer to Ground, Measurement Unit, Power Supply (1 to 4) and Spare Line (1, 2). MSL1B, PIN22 refers to specific pin libraries, and XL, 1 are the entry numbers used. 36 9.3 As in paragraph 9.1 the power supply conditions are in libraries. These specify the mode and a number of values of the amplitude parameter. The values can be accessed by an index such as a 'DO LOOP' index, or a constant (1, 2 etc). 9.4 The instructions to set a power supply is; SPS 51, SL2,4 or SPS S2, SL3,XK where S1, S2 are supplies 1 & 2 respectively SL2, SL3 supply libraries 4 indicates the 4th value in library SL2 XK is the 1XK' value in library SL3. The supply as yet is not 'turned on', ie, the amplitude is set to zero until a Power On (PWR S1 JON) instruction is issued. If the supply was previously on it remains on. 9.5 The Measurement Unit is tied to the Power Supply No 5, therefore the instruction to set it up, references a supply library to set the mode and amplitude of this supply or forcing function. The current overload is also the range for the measurement unit when the forcing function is supplying a voltage, and the voltage range is always \l 10 (0 to _+ 20 volts) when the forcing function is supplying current. These ranges are overridden by the range parameter of the set measurement unit instruction eg. smu C100U, SL3,4 SMU V, SL4,1 where C100U, V set the range / to +_ 100 uA and 0 to _+ 2 volts respectively and SL3 is a voltage setting and SL9 a current setting for the forcing function. The power supplies can be 'turned ON or OFF' by a PWR command, either separately or all together, eg. PWR S1J0FF /'Supply 1 off PWR S2J0N / Supply 2 on PWR ALL.’ON / All on 37 9.7 For some circuits a long settling time is required, this can be implimented by a delay instruction eg. DLY 10 ie. wait in a loop for 10 x 100 micro seconds. 9.8 When conditions are right a Read RMU command converts the current value of the measurement unit into a binary number- and stores it for future reference. A separate command RDF, subtracts the previous RMU value, before storing the converted value. SOFTWARE STATEMENTS 9.9 A limit test can now be applied and branches taken to different parts of the plan, depending on whether the reading was below lower limit, within limits, above upper limit. eg. LIYIT -100, AA1, AA2, AA3,+100 for reading -100 go to AA1 between -100 and +100 go to AA2 + 100 go to AA3 9.10 A direct transfer to another section is GOTO AB3 9.11 A reject is sent by RJT B13 where B13 is one of four reject bins (B13,B14,B15,B16) 9.12 A LOG command checks to see if any of the options are requested such as override, automatic reject etc. The actions taken for each option are set out below. 9.12.1 Data-log - If answer is yes. Is this test number to be logged? If answer is yes. Log it, if not check other options. 9.12.2 Single step. If answer is yes. Halt and on continue assume reject override is set, 9.12.3 Reject override. If set go to next executable statement. If not go to end of plan and end test. 38 9.13 A DO command provides looping facilities and the value of the index can be used to loop through a number of supply values and/or pin connections. There are four DO indexes XK, XL, Xl1,XN. Ihese are checked when data logging and if they are not zero their value is punched out. The DO statement must always end on a continue statement CNT. eg. DO DOL 1 XK,1,5 SPU S1,SL1,XK mUT mSLIB,XK D0L1, CNT 9.14 A computed go to statement provides branching dependant on the value of an index. eg. CGT XL; RL AA1; RLAA2; RL AA3 if the value of XL is 2 then branch to AA2 (NB. The 'RL' signifies a tag or address) 9.15 An IF command allows comparison of Indexes with each other or numbers up to 173 eg. IF XK,4,AA1,AA2,AA3 thus if XK is 3 go to AA1 4 go to AA2 5 go to AA3 9.16 If, as a result of a test, the device cannot be in certain categories the Clear Bin n(CLB B1) instruction inhibits that/ those particular bin/s eg. CLB B1.'B2.'B12 9.17 A TEST n sets the current test number for accumulation and data-logging purposes. 9.18 An END indicates the end of the plan and turns off all power supplies indicates the bin the device has been put into and then goes back to the syst-em. 9.19 The compiler used is the Digital Equipment Corporation r (YIACRO —8T with pre-defined macros and symbols. cr to cc LU > t—I X ao< X • t— H J U a. • x •d- i—•i (Jo N Q tn cn cn cn cc h- Q- X LD (N t-* _l-Hj |cn—■ eC X X LDt—l o *sf _J IX , CC X CO l-H X UJ LJ cc LD UJ UJ X X 3 CJ tn 1- 3 i i X 3 x cn i— FIG. 10.1 TEST STATION NO.1. PHOTOGRAPH 40 CHAPTER 10 TEST STATION 10.1 This unit forms the interface between the test system and the device under test, it also forms the major interface between the operator end the test system. 10.2 The interface between the device under test and the system connects the analogue signals from the multiplexer to the device under test. This means 72 leads have to be brought into a reliable socket which gives firm platform for the device under test. 10.3 There are a number of options open to the designer on this unit. Some of these are considered below. a) Universal socket with plug in sockets for specific package types, with access to individual leads as for extra components and checking out test plan. 10.4.1. b) Universal socket with a plug-in adaptor for each device type. 10.4.2. c) Separate sockets for each package type wired in parallel. 10.4.3. 10.4 Let us consider each in turn. 10.4.1 This method is flexible and economic. There are 1 ) available universal sockets for up to 16 leads# This could cover nearly all package types envisaged for the few with 24 pins we could wire in parallel an extra socket. A row of miniature sockets could allow access for measurement and extra components. The disadvantages are the ease of forgetting essential components in a production environment. The lack of shielding of extra components. The difficulty of inserting components in series with leads for checking etc. The advantages are ease of trying extra capacitors or shunt resistors. Only eight to sixteen pin 2) sockets are needed for most work. Special jigs for small runs or prototypes not needed. 1) Barnes catalogue 2-69 page 43 RD86X88 2) 8, 10, 12 pin T05 & 14, 16 pin DIL 41 10.4.2. This system is extremely flexible for large volume production environment. It can contain all required extra components and if necessary extra processing of input or output signals, without limiting the test system as a general tool. The disadvantages are the relatively high initial cost and lead time required. It would be a little more difficult to modify than the system 10.4.1. The advantages, chiefly in the production environment are, one unit completely sets up the device under test. The signals can be pre-conditioned readily. 10.4.3. This system is the least attractive. It has all the disadvantages of 10.4,1 and only offers the. advantage that all the sockets are hard wired, therefore, removing a possible source of contact noise. This is more than compensated by the increased number of exposed contacts and the possibility of a device, left in a socket not being used, upsetting conditions on the device under test. 10.4.4 It was decided by the author, in consultation with others to use the first method 10.4.1 in a form which will facilitate going to 10.4.2. This was because of the ease of setting up prototype and small runs with little lead time. It has now been converted to the plug-in adapter mode with a unit as in 10.4.1 as a first adaptor. 10.5 Fig 10.1 shows the layout of the Test Deck. The interface to the operator has to be as simple as possible. ihe requirements are (i) a means of starting the test sequence (ii) a means of indicating the test plan required (iii) an indication of the completion (iv) a result of the test. 10.5.1 Items (i) and (ii) and (iii) are also needed for automatic device sequensing units eg. automatic prober or automatic loader. The start testing can be initiated by a button which sets a flip-flop as a flag. It is desirable to have some indication that the button has been pressed. There can be three conditions which should be shown. (a) The button has been set, but the system has not yet accepted the request, (b) the test sequence is in progress, (c) the station is idle, ie. awaiting the operator or machine to set up new device and initiate another test. In this system two lights are used (a) a red one to indicate request not honoured, (b) a green one to indicate test in progress. The absence of either normally means idle state and should be accompanied by a binning light (see under). A two decade thumbwheel switch allows one of 99 test plans to be called, with 0 for special purposes. This switch is sampled when the start test button is sensed. A set of four flip-flops will indicate up to 16 results. These can drive lamps and/or inker units to indicate categories and pass failure results. To improve operator recognition of test complete, it was decided to blank the bin lights while the 'service request' light (red) or 'test in progress' (green) lamp is on. This is essential for short testing sequences when the same result on consecutive devices is indicated. (see figure 10.^) 43 TESTING BIT PRTOUT BUSS DRI VER THUMB - WHEEL SWITCH IOP1 6311 DEC - ODER I OPE 631£---- BIN TEST LIGHTS DECK N SKIP BUSS FIG. 10.2 TEST DECK LOGIC DIAGRAM 10.6 Figure 10.3 shows the logic diagram of the test deck and control. 10.6.1 The signal (14113, XPB30N1) is the test deck enable signal from the multiplexer (see Chapter 11). This is buffered and enables the 10P1, I0P2 and I0P4 pulses to access the registers and switches. The presence of the enable signal, gates the two decade BCD switches onto bits 4 - 11 of the DATOUT BUSS. Bits 2 and 3 indicate the status of the service request and testing in progress flags respectively, 10.6.2 On receipt of a I0P1 pulse bits 8 - 11 on the DATAIN 3USS are clocked into the test result register (M206, XPE35), bit 7 allows the testing in progress flag to be set or cleared. The previous state of the 'testing in progress' flag is clocked into the 'service request' flag. 10.6.3 I0P2 pulse is gated onto the skip buss if the service request flag is high. A service request flag high is buffer directly onto the interrupt buss (M 624 XPF25, 44 10.6.4 I0P4 pulse is used in the multiplex section to switch the analogue signals to the selected test station. This means the 'request for service' can be honoured without disturbing the analogue signals, thus minimizing the number of changeovers. 10.6.5 The least significant three bits of the test result register are decoded into one of eight by two SN7445N's and G1 and G2 enable the appropriate decoder as indicated by the fourth bit provided neither the 'request for service' or 'testing in progress' flags are up. 10.6.6 To prevent multiple interrupt caused by the interrupt test sequence being finished before the button is released an electronic momentary switch is used. In the rest position the switch discharges the capacitor and depressing the start button connects this to the 'high' set line of the 'service request' flag. This pulls the line low but allows it to rise again by charging the capacitor through the 3.9K resistor to the 5 volt rail. Thus the flag can only be set again by releasing the switch and pressing again. The 'start button' can be a start test relay from an automatic loader or prober; and the 'testing in progress' and service request signals the testing not complete signals. 10.7 Software Examples To read test plan No: 10.7.1 TAD (704 / Test Station 3) TSLR / Load address reg. TSRR / Read test station flags and thumb wheel switches 10*. 7.2 To check'flag TAD (702 / Test Station 2 TSLR TSF1 / Skip if flag set JIYIP NOFLAG / Flag not set JMP FLAG / Flag 'set 10.7.3 To clear service request flag and set testing in progress TAD (701 / Test Station 1 TSLR TAD (200 / Set Bit 7 TSF 2 / Load result register 10.7.4 To select bin TAD (710 / Test Station 4 TSLR TAD BINN0 / Bin No to be displayed TSF 2 4G O CrC \~~ b § o cj> $ ' z'JVV rJV t.\Y vs!V ^ o& j llllL o to l_l_l <0 ! a______%______s_$sj l______x <7> u_il g\ H o 00 $ a 2 CD **f oJ • -J 'X4, ‘ ' J,._' ■ X / • —"N^ ■ ' '1 W« JS3J JO 13NJJ JHOVJ V<0Ya ^ I Vo ^ ♦!j tSc [*9 s st ^ f* 3 * I > looln IS :j I Is LJ L_£ . _?Lj & 8 o UJ /j ♦— oo U-J rI wo> e ! i I p 0 l____ Slj —|h c4 in V I if p L _____ 71 _ ._ s.ss “ gf'"” _ 5.. _ _ 3_ _s _ £_ _2 _sj_ 5 _ 4_ a J a. SI , 13 ,r' t oi <.t\l Li' x ol £ ' l/> \>\ & s ts; ts 2 TLi X. Ol. L*J J - j i_ •4' iiJ or (v) ^ ir> nc ki C_> I OJ & go, /. j I a- ll !3 Is * 12 l« •=* ii FIG. 10.3 TEST DECK AND CONTROL LOGIC DIAGRAM 47 CHAPTER 11 MULTIPLEXER 11.1 This unit decodes the test deck address and sets the relays which control the analogue signals to the correct test station. (See Fig 12.1 and Fig 11.1). 11.2 The 'Test Deck' signal enable the bits 8 - 11 of the 'ADDRES BUSS' to select the deck to be serviced, all four decks can be address at once for clearing functions or rapid check if it was a test deck causing an interrupt. 11.3 Bits 8 - 11 of 'ADORES BUSS' are also buffered and drive the D inputs to the registers of the multiplexer matrix. This pattern is clocked in by a I0P4 pulse being enable by the 'Test Deck' select line, TD. This pulse is heavily loaded since it clocks all 96 registers at once. It is therefore, split to three drivers. 11.4 The coil of each relay is connected, via a lamp on the rear panel, to the 24 volts rail (see XP) in this case the four relays for a single line are connected to one lamp, because only one station is connected at a time. The exception to this is line 1, which has four lamps on the front panel to indicate which station is connected to the cross-point matrix. 11.5 Software Examples To set multiplex TAD (701 / Test Station 1 TSRR / Load address register TSF 4 / Set multiplexer 48 £ 2 * £ * V>1 § T i i i i ! I JL i i i ' it i ' i L. i ! I - t r \ fill Ll n~rr I ; l ! I T“ r~ t f ill! I T u , I i i I I I 1 i i I ' 1 1 l i JL± J. J7 ! • - i r i i rf- rtr' ~'"r * 1 1 i i I I I I ! o =? ; ? ! S f an 04 u • S, sail mm :> 3 _jC CO o i/i _ _— ~~ *7 C\l CM csfl u- U. s? U_ deck O- 5|!S X Q 0 0 o m £ cJ TEST L* n cn CNJffTl Q Q O O Q | L*' Znl S*i ^ ^ b 6 o q s: «ia _li11' r~ i «"] l 4. _ S T ongel 4 FIG, 11-1 TEST STATION MULTIPLEXER LOGIC DIAGRAM :__l LINES 1-24 SPARE 2 SPARE 1 P.S. 4 P.S. 3 P.S. 2 P.S. 1 m.UNIT GRND “ TEST STATION IN CONTROL FIG. 12.1 CORSS-POI NT MATRIX AND MULTIPLEXER FRONT PANEL FIG. 12.2 UNDERSIDE OF CROSS-POINT MATRIX AND MULTIPLEXER 50 CHAPTER 12 CROSS-POINT MATRIX 12.1 The cross-point matrix was designed to be easily maintained and use as few different units as possible. Figure 12.1 shows the front panel. Figure 12.2 shows underside. 12.2 The heart of the unit is the analogue switch at each cross- point. A number of alternatives were open (a) reed relays (b) bipolar transistors (c) field effect transistors. These must be considered against the requirements for the unit. 12.2.1 Each cross-point must (i) carry at least 100 mA and preferably 500 mA, (ii) sustain at least _h_ 40 volts and preferably _+ 100 to _+ 200 volts, (iii) have some form of memory to store its state, (iv) not introduce voltage offsets, and (v) not drop too much voltage at maximum current, preferably <20.5 volts at 500 mA. This is set by the power dissipated and the allowable voltage drop in the power supply system. (See Chapter 13 Power Supplies). 12.2.1.1 A reed relay can meet all the above requirements when combined with a semiconductor latch. If we consider a miniature reed FlGRR-2 (Hamlin) it has an on impedance of 10 milliohms, a voltage rating of 250 volts in the off state with an off impedance ^>10 megohms. The main disadvantages are, slow switch time *v//1 mS plus contact bounce .^0.5 mS (this can be eliminated by mercury whetted relays with a sacrifice in off impedance), higher failure rate than other devices. 12.2.1.2 The bipolar transistor has a problem of voltage offset which can be minimised, an induced current onto the analogue circuit, the same circuit could at one stage supply 100 mA and at another be trying 51 to sense 1nA ie, a range of 10 . Thus any current measuring sensor would have to be after the switch, this is impractical. Another problem is the voltage rating _+ 40 volts 11 ^ can be realized but special circuits must be used to allow the base to be within a few volts of the emitter. The major problem is switching the base, this requires two current sources, for each series element, with an effective supply greater than the max and less than min carrying voltage. 12.2.1.3 field effect transistors offer the best hope in the future, but as yet are not readily available with an impedance <1 ohm (the best seen by the author at the time was guaranteed ;T10 ohms). These will also require dual voltage sources as in the case of the transistor, but the current requirement is negligable and there is no current (except switching transients) induced into the analogue circuit. 12.3 The relay circuit used is shown in figure 12.3 and module circuit figure 12.7 and photograph of the module figure 12.8. £4- VOLTS DATA 12V 4-0M CLOCK FIG. 12.3 REED RELAY CIRCUIT 12.3.1 The philosophy adopted through the system when using reed relays was to always operate the coil in series with a lamp. 1 his has a number of advantages. (i) The lamp shows the state of the relay. 52 (ii) The lamp has a low cold resistance and will thus provide a high switch-on current giving maximum switching speed, but normal or lower holding current. (iii) This also gives a reduced current surge in the lamp. The lamp used is a 12 volt 40 mA T4 miniature telephone lamp, this matches the 12 volt 40 mA rating of a three reed relay cull (150 AT, OSMQ nT 12). When single and double reed units are used a 470 ohm and 680 ohm resistor respectively across the coil restores the balance of voltage. A diode clamps the positive swing of the coil on switch-off to limit ringing yet not slow the drop-out rate too severely. The lamps are on the front panel and show the status of the Cross-point matrix. (See figure 12.1). 12,3.2 The relay units were made up in cards of 4 relays each of 3 reeds. (See figure 12.6? and 12.7). This meant the same card can be used on the cross- point (6 cards per input line) and the multiplexer (1 card per pin line). The state of the relay is stored in the quad latch (SN 7475N) which drives Q1 to Q4 through a current limiting resistors R1 to R4. D1 to D4 and ZD1 (39 volt zener diode 1W) form the voltage spike suppression circuit. A ground plane on the circuit reduced induced current from the coils and adjacent lines in the analogue signals. 12-4 The control circuitry for the cross-point matrix is shown simplified in figure 12.4 and fully in figure 12.6 — V« X - POINT SIMPLIFIED CROSS-POINT LOGIC DIAGRAM 53 12*4.1 The cross-point matrix consists of 8 rows of 6 cards (M003) as described above. They are addressed in groups of 12 points (ie. 3 cards) thus half of one line can be set at a time. These groups can be address randomly or sequentially. 12.4.2 Referring to figure 12.5 DATA e CLOCK i. CLOCK £ FIG. 12.5 CURRENT DISTRIBUTION IN CLOCK AND DATA LINES The DATAIN BUSS is wired to the 16 groups of 12 points. The loading on these lines is as follows, in the high state each input draws c 40 uA (ie. < 640 uA total), in the low state with clock, low, the maximum current is still 4.40 uA (data line can drift up until clockline takes all the current, the only current in the data input being the transverse current from emitter to emitter). The clockline on the other hand must drive 12 clocks and in the SN 7445N this is (3.2 mA) 2 unit loads in the low state, therefore, the clock driver must drive 24 unit loads (or 38.4 mA). 12.4.3 The cross-point select line enables the I0P1, I0P2. and I0P4 pulses to form the XPIQP1, XPI0P2 and XPI0P4 pulses. 54 12.4.4 XPIDP1 pulse is used to clear the 4-bit counter (M204XP B29) this sets the count to octal 00. XPI0P2 pulse enables bits 11 - 8 of the ADDRES BUSS to set the state of the 4-bit counter (M204). The counter is a synchronous 4-bit count with J - K master-slave flip-flops, thus the output charges when the clock returns to low. 12.4.5 The bits 10-8 outputs of the counter are decoded into one of eight by the decoders M161,XPB26 and XPB27, these are enabled by bit 11 of the counter XPI0P4. Thus the bits 10-8 select the line to be clocked and bit 11 which half to be clocked. The selected clock is buffered by M624 driver to the appropriate clock inputs of the cross-point matrix. Since the output of the counter does not change until the clock goes low again the pulse which clocks the data into the cross-point matrix can also increment the counter to the next count. This means that any half line can be addressed and loaded by XPIGP7, (I0P1 - I0P2 - I0P4), the address register and 'ADDRES BUSS' holding the half line number and the 'DATAIN BUSS' the pins to be connected. 12.5 Software Examples Load a single line with pins stored intwo words starting at PL1 CMA TAD PL1 DCA- 10 TAD N /LINE TO BE LOADED RAL / 2 TSR3 /LOAD ADDRES REGISTER TAD I 10 TSF7 TAD I 10 TSE 4 EXIT PL1 P1.' P1 2 /Pins 1 & 12 P13JP15 /Pins 13 & 15 55 To load the whole cross-point with pins stored in 16 words, starting at PL2 cm TAD PL2 DCA 10 TSR3 TAD(-17 DCA CNTR TSF3 XPLUP TAD I ’10 TSF 4 ISZ CNTR JFIP XPLUP EXIT PL2, P1JP2 P23.' P24 5G H~B b b 8 B CONTROL MATRIX POINT X. I------e sa____| FIG 12.6 CROSS-POINT MATRIX CONTROL LOGIC DIAGRAM F2 E2 D2 K? JZ H2 N2 MZ IZ i iiii i FIG 12.7 REED — WV RELAY CARD I ______CIRCUIT ~6\ o DIAGRAM 1 57 53 FIG. 12.8 REED RELAY CARD. PHOTOGRAPH CONSTANT VOLT AGE current ^*s,b L.S.B. J ™RANGE \ I / +VE OVERLOAD O O 300000 o'o o o © OSCILLATION *Si O 0009 P.S. OFF , ; . I;; • •. « ;; |,*W -VC OVERLOAD - © oooooooooooo © «* @©©@© FIG. 13.1 POWER SUPPLY FRONT PANEL. PHOTOGRAPH 60 CHAPTER 13 POWER SUPPLIES A regulated power supply generally consists of a raw supply, a series (and/or shunt) element, a reference voltage and a means of comparing a proportion of the output voltage or current with the reference voltage. For a manual voltage' power supply varying the proportion of the output is a simple and convenient means of settling the output voltage. In a computer environment a digital signal must be used to control the output voltage. With the availability of accurate D/A converters (eg. _+ 0.04/ over a _+ 25°C range) or a fixed proportion of the output can be compared to a variable reference voltage. A simple series element is not satisfactory for the purpose because the supply may have to sink or supply current to maintain the correct output. A variation on the previous system is to use a high power low gain buffer amplifier using complementary or totem-pole output stage. Output current sensing presented similar problems of switching as the cross-point matrix (see Chapter 12) and the same arguments apply for the use of reed relays. 13.1 The complete power supply consists of a D/A converter 0 to 10V, a level shifter and buffer amplifier _+ 16 volts _+ 100 mA, a 12-bit register to store the digital value of the voltage or current and a 6-bit mode register to store (current overload range, voltage or current mode, and on off state). See figure 13.JT. 13.2 BOARD 1 (12-Bit Buffer and Gate) 13.2.1 •. This is a board designed by the author and contains a 12-bit latch plus a 12-bit gate on the output each cell as shown below. (Figure 13.2) (See figure 13/? for full schematic). DRTR BIT N r~ C LORD ENRBLE FIG. 13.2 BUFFER CELL LOGIC DIAGRAM 13.2.2 This configuration allows the data (2's complement of the mantissa) to be stored in the register and applied at a later time to the D-A converter thus providing a fast acting, logic switch for the power supply. It also allows the supplies to be set up in any order and then switched on in the required sequence. Figure 1 3-<4> shows photographs of each side. The latches are quad latches (SN 7475), the gates quad two input Nand gates (SIM 7400) and the inverter gates are dual power Nand buffers (SN 7440) The circuit board used plated through holes, bright tin rolled coated copper on a fibre-glass board with gold plated fingers. 1) D Boards made by Morris Prod, to artwork prepared by A.W.A. to the author's layout drawings. 62 13.3 BOARD 2 (6 Type D flip-flops) M 206 13.3.1 This is a standard commercial module manufactured by Digital Equipment Corp. of America. It contains 6 type D master-slave flip-flops with grouped reset lines separate clock, data, set, output and output lines. This unit stores the range and mode information' as set out below. (figure 13.3). CLOCK £ 6 P ,S . ON (OFF ) 7 . CONSTANT VOLTAGE (CURRENT) DflTPIN 8 . VOLTAGE RANGE £0(£)V BUSS 9 . 1 1 0 0 0 0 \ 10. CURRENT 0 0 1 10 0 RANGES 1 1. 10 10 10 CLOCK 1. ►-» 0 QQ3Q Q 3 D S C O 3 ID CD D ID FIG.. 13.3 MODE REGISTER ALLOCATION 13.4 BOARD 3 (D-A Converter 12-bit) A 613 13.4.1 This is also a commercial module and provides a 0 to 10 volt analogue output from a 12 digit input. It can be set for BCD or binary configuration (we use binary) and requires a - 10 volt reference voltage. It has in binary mode an accuracy of _+ 0.015^ of full scale at 25°C with a temperature coefficient of (10-50°C) _+ 0.001/6/°C plus drift due to reference voltage. 13.5 BOARD 4 Power Controller (AWM 005) 13.5.1 The board contains a DC power amplifier which can operate in any of'the four voltage current quadrants in either constant current or constant voltage modes, eg. it can supply + 17 volts and + or ~ 100 mA or - 17 volts at + or - 100 mA 63 V i 0y SIMPLIFIED POWER SUPPLY LOGIC DIAGRAM 13*5.2 Amplifier 1 is shown in detail in Figure 13.7 and is the main power amplifier. (ICI and Q3 to Q8). Amplifiers 2 (IC2) and 4 (IC4) are voltage follower buffer amplifiers giving an input impedance of approximately 3 meg-ohms (IC2, IC4). Amplifier 3 (IC3) is a differential amplifier whose output voltage is (-10 x R x I). 13.5.3 The analogue output drives a two core shielded cable giving guard, sense and drive funct.ions. Thus the capacitance of the output leads to shield is only driven through a maximum of 1 volt. A voltage of 0 to 10 volt from the D-A converter is applied through to pin AF2 to R3, this, together with a current from the - 10\l reference supply through pin AE2 to RV1 and R2 as well as from the feedback network form the closed loop system. To maintain the impedance matching during voltage range changing, the feedback resistor was designed as a T attenuator with an approximate impedance of 4 K ohm. When the relay contact RLC1 is in the normal state the attenuator has a gain of 0.1 and in the operated state a gain ef' 1.0 this gives an effective range change without upsetting the DC impedance matching around the operational amplifier. The voltage for the feedback 64 is either from the current sense line via a voltage follower or from the current sense resistor via a differential amplifier IC2. (Figures 13.5 and 13.6). CONSTANT CURRENT MODE CONFIGURATION CONSTANT VOLTAGE MODE CONFIGURATION 13.5.4 In the constant voltage mode the current sensing circuit is used to detect current overload and to effect current limiting (constant current). This is achieved by connecting two back-to-back zener diodes from the current amplifier to the summing junction of the main feedback loop. This inserts or extracts current so as to relieve the overload no matter what direction it is in, or what value voltage (within the voltage range of the supply). 65 13.5-5 Current, overload value, or range is set by a group of five reed relays. The three data inputs feed a one of eight decoder with output capabilities of 40 volts 80 mA (Sl\l 7475) this drives the relay coils in series with a 12 volt 40 mA lamp. The lamp gives front panel indication of status as well as giving a check on coil continuity. The lamp also gives a low cold resistance therefore, a large switch on surge to help speed up the reed switching. 13.5.6 Also on this board two overload detectors + ve overload, - ve overload and an oscillation detector. These drive a standard TTL gate to give "overload" and "Oscillation" signals. Two dual input 'Nand gates are available for outside connection. The overload and oscillation signals drive lights on the front panel. 13.5.7 In the constant current mode the voltage buffer is switched via RL.C2a .to pin ADI, and in the constant voltage mode the differential amplifier IC3 is switched to AD1, This means that at any time the value of the varying parameter is available at AD1. This is, therefore, the link to an Analogue to Digital converter to read the current or voltage supplied. (See Measurement Unit, Chapter 14). 66 sSsSS2-?5*45?S* «A j t I I I I S I » I f I I w jQ c\j Si « s? :*a: fj* 3?! § § Cro^S £ SSH * ^ FIG. 13,7 POWER CONTROLLER CIRCUIT DIAGRAM 67 KIMH inSag ’ FIG. 13.8 POWER CONTROLLER. PHOTOGRAPH 68 FIG. 13.8A POWER CONTROLLER COMPONENT LAYOUT 69 in 2o z O 0 I :> < 1 FIG. 13-9 12-BIT STORE AND GATE CARD LOGIC DIAGRAM 70 AWA-M-004 12 BIT STORE ft GATE FIG. 13.10 12-GIT BUFFER AND GATE. PHOTOGRAPH 71 CO r»S -< TTrrrrTT FIG. 13.11 POWER SUPPLY COMPLETE LOGIC DIAGRAM 7 3 A SAME AS FOR POWER SUPPLY CURRENT VOLTAGE RANGE RANGE FIG. 14.1 MEASURING UNIT FRONT PANEL. PHOTOGRAPH 73 CHAPTER 14 MEASUREMENT UNIT 14.0 The measurement unit is linked with the power supply No 5 ie. the forcing function. Since the output on pin AD1 of the power controller (see Chapter 12-5) is already scaled and current converted to voltage, the only requirement on the measurement unit is to convert the analogue signal to a digital form on request. 14.1 There are at least two ways of achieving this, one is to use a D/A converter and compare the generated voltage to the voltage being measured. The other is to convert the . voltage to a digital signal and comparing with limits with software. 14.1.1 The first method is acceptable if the main requirement is to check that the voltage is above or below a particular limit, ie. G0/N0-G0 testing. The difficulty is to obtain a reading of the actual parameter. Using successive comparisons, this could take 100 mS. 14.1.2 The second method is a little more expensive on hardware but much faster for obtaining a reading (">/ 20 uS) and about equal speed for limit testing. This method was chosen. 1 ) 14.2 The A/D converter readily available was a 10-bit unit. To give maximum resolution a sign magnitude pormat was used. 14.2.1 Figure 14.3 shows a circuit diagram of an absolute amplitude converter with switchable gain (0.5 or 5). Figure 14.2a shows the active section for a positive input. The output of IC1 is the inverse of the D DEC module A811 74 limit and because of the resistor ratios, gives a nett input current of -V/R +V/2R = -1//2R, this is balanced by an output of \l (or 10 V = 2 Volt range) through 2R (0.2R). 14.2.2 Referring to Figure 14.3 for a negative input the output of IC1 (pin 6) is positive, therefore,' D2 and D3 are forward biased and D1 back biased. Pin.2 of IC1 is a virtual earth and, therefore, the circuit reduces to figure 14.2b. V = V. 2R out in 2R Relay RL1 introduces a 10:1 attenuation without changing impedance, therefore, V . = 10 V. out in £R eR(0.£R) V OUT V IN - V IN FIG.1H-.CR POSITIVE" INPUT £R eR(0.£R) V OUT V IN FIG.iH-.BB NEGATIVE INPUT FIG. 14.2 ABSOLUTE MAGNITUDE CONVERTER MODES 75 14.3 When the measuring unit is addressed and a TSF4 (6314) instruction given a conversion flag flip-flop on AWFl 00 is reset and a start conversion pulse supplied to the A811 A - D converter. This module (D.E.C. A811) does a successive approximate conversion to 10-bits. At completion of conversion (10 us) a DONE pulse is generated and the conversion flag is set. This flag is checked by a TSF2 (6312) pulse. The sign bit plus the 10-bits of A - D converter plus the flag bit are gated onto the DATOUT buss by a 01101 inverter and a FI 624 buss driver. (Figure/4.3) 14.4 Software Example TAD (600 / FIE AS. UNIT TSLR TSF 4 /START CONVERSION TSF 2 /FINISHED JFIP .-1 /NO CLA /YES TSRR /READ VALUE FIG. SIGN CU *- 00 14.3 Q ►H a I M q a; b h- > O D Z I h* W c J h* Ul 01 co d w W U. 01 O Z O O > Z 1 Q M 01 i UJ CL O ? 01 UJ b lil QC 01 > UJ Q1 MEASURING (J) tt. 0. J J >- h* Q m M tH m U> a. SC 00 a? w D n o a. CvJ UNIT >0 co 0J LOGIC M o J- (L 'O CO :*• ^ DIAGRAM UJ (CH CO EDO? • J- Z h UJ J UJ o . 77 CvJ s^4 n £ D ur> 23 v- ZT £ •>4 U—W-| FIG. 14,4 ABSOLUTE MAGNITUDE CONVERTER CIRCUIT DIAGRAM FIG. 14.5 ABSOLUTE MAGNITUDE CONVERTER PHOTOGRAPH r~ i------10? I ro — ____ J -----3 I______l FIG. 14.6 CONVERSION DONE FLAG AND MISCELL.ANIOUS GATE CARD ficj /£■ O 80 CHAPTER 15 CONTROLLER 15.1 The controller method chosen was a small computer. The computer was a PDP 8/I with a negative l/O buss# This computer was selected because at the time it had the best range of peripherals, software back-up and logic modules. The negative buss was decided upon because most peripherals at the time used this mode. The final decision was out nf our hands as the D.O.S. purchased the unit and are lending it to us# 15.2 The next decision to be made was whether to use separate I/O slots (or addresses) for each sub-unit of the test set or to do this addressing in the test-set itself. The first method would require at least eight and possibly 16 slots# It would offer no advantages because we would still have to issue two I/O commands in most cases:- The first to set up range and the other to set up value of voltage/current in power supplies. The second method gave maximum flexibility and only used two computer I/O slots. Ihis left plenty of room for other peripherals such as data links, other test sets etc# 15.3 The negative buss of the computer gives a 0/-0.3 volt for 'O' logic and -3.2/-S volt '1' logic. To interface with standard DTL, TTL circuits this must be converted to 0/0.4 Volts 'O' and 2.4/3.6 volts for '1' logic. The inversion unit is as described in DEC module Application Note, entitled "Interfacing ' IV Series Logic to the PDP-8 computer". Figure 15.2 shows the logic diagram for this section. 1)2) The output signals used as follows ’ (see figure 15.2) 1) Bit 'O' is most significant bit '11* least significant. 2) Digital Equipment Small Computer Handbook 1970 BAC0 Buffered Accumulator - these lines give the -BAC11 contents of the accumulator for use by I/O devices. IDP1 When an I/O instruction is executed with bit '11' set a pulse 700 n3 wide, starting 900 nS after the instruction is initialled. I0P2 With bit '10' set a pulse 700 nS wide, starting 900 nS after the start of I0P1 if it were issued. IGP4 With 'bit' 9 set a pulse 700 nS wide, starting 900 nS after the start of I0P2 if it were issued. BTS3 A 250 nS pulse starting 150 nS after any instruction is initiated. BTS1 A 250 nS pulse starting when the memory is accessed for the next instruction. BPwrClr A pulse which is asserted when the processor is powered up or the START key is depressed; used to initialize peripherals. BMB 0 Buffered contents of the memory buffer. During -BMB11 1/0 this is the instruction causing the 1/0 there BMB3 fore bits 3-8 are 3-8 are used to enable the -BMB8 particular device. Bits 9-11 can be used for device subdivision, they are not necessary to obtain I0P1, I0P2 or IGP4. Inputs Note all inputs are inverted and must be driven by open collectors to provide 'OR' action. AC^ - This is the input buss which on a 1/0 instruction ACTT will be jam transferred into the accumulator forming an inclusive OR with the contents before the instruction. AC buss .AC ?AC SKIP When this line is asserted (pulled <0.4 volts) the next instruction is skipped and the one after executed. 82 InT When this line is asserted and the computer interrupt is on, an effective JMS 0000 is executed to indicate a device requires an interrupt. CL. AC When this line is asserted the accumulator is cleared at the beginning of any I/O instruction. 15.4 The Test--set Interface (See Fiqure 15,3) This section recognizes the address for the test set, stores the contents of the accumulator and decodes sections of this as an address for the particular section being serviced. 15.4.1 The |Y) 735 module decodes the BM8 3-8 by forming BMB (3,4,5,6,7,8) this corresponds to I/O device 30' (Octal). This enables the I□P1,2 and 4 pulses to module and system. 15.4.2 A 6301 (octal) instruction enables I0P1 which is gated onto the SKIP buss if any of the flags of the test system is set. 15.4.3 A 6303 instruction (TSLR) loads the contents of the BAC buss into a 12-bit register, on the same module. This is the 'ADDRESS REGISTER'. 15.4.4 A 6304 instruction (TSRR) strobes the contents of the 'DATOUT BUSS' via a series of gates on the module onto the computer input buss and thus into the accumulator. (This is done at event time 4). 15.4.5 A 14103 (INB10) module decodes BMB 3-8 by forming 3MB (octal) (TSFx) this enables the contents of the accumulator and I0P1, I0P2, I0P3 to be gated via a buss driver (I4624 IN812) onto the 'DATAIN' Buss. 83 15.4.6 Bits 0 - 2 of the address register are decoded to enable the second decoder if ADDRES (0,1.2) is true. This second decoder selects the unit being addressed by raising the appropriate line. 0 - Cross-point Matrix (Chapter 12) 1 - Power Supply 1 (Chapter 13) 2 - Power Supply 2 (Chapter 13) 3 - Power Supply 3 (Chapter 13) 4 - Power Supply 4 (Chapter 13) 5 - Power Supply 5 (Chapters 13 and 14) 6 - Measuring Unit (Chapter 14) 7 - Test Stations (Chapter 10) (See figure 15.4) 15.4.7 The contents of the 1 DATAIN' BUSS, 'DATAOUT' BUSS and 'ADDRESS' register are displayed by a series of lamps on the front panel. (See figure 15, V), 15.4.8 This panel contains the indicator lights for 'DATAIN', 'DATAOUT' buss and 'ADDRES' register. 15.4.9 A means of simulating the computer I/O instructions was considered essential to enable test set checking and adjustment. This was done by using a four decade thumbwheel switch to set the equivalent to the accumulator a switch to address with 630x or 631x and three push-buttons to simulate the I0P1, I0P2 and I0P4 pulses. A switch sets the test-set on line or manual. 1C-' 15.4.9.1 Referring to figure pS in the OFFLINE position removes -15 V- power to the BAC, BMB, AC, IN?, 5KP AND CLRAC logic conversion modules, also the 5 V power to the I0P1, I0P2, I0P4, BT53, BTS1 and BPWR.CL. logic conversion modules. This has the effect of isolating them from the computer busses. This switch also enables the Manual I/O system. - 15 volts through R1 and D1 creates a - 0.7 volt level so that when diodes in series with selection lines are at 'O' logic the line is pulled to 0 volts not 0.7 volts. 84 10P1, I0P2 and I0P3 push buttons drive cross- coupled inverters to eliminate switch bounce. 15.4.9.2 Diodes D3 - D9 select the device address, diodes D10 - D12 activate the IOP lines (these are not pulsed to facilitate tracing of levels) and 4 thumbwheel switches via diodes D13 - D24 activate the accumulator lines. ■-S«- l-g« r»-h «/KJ “ * i18 ID — LP.J I i L 'IT ------12| i I 1 Lin "V" “ "IS - T]3l _ ^-■*- ■* - J FIG. 'a 1 » i - r + -4 L * I l l i i i — L? Tl — 15.1 x s • 5-4- I +- J ■♦■ i I i i I 1 S l I ------E COMPUTER J 1 T I I/O £ M S 1 z SIMULATOR S |2 5 03 LU CD i z vi> .2 a CD oi 00 J z *2 £l 2 a> \ Mil cOi oj £ r< flQ £ *J LOGIC ID * < o L-J V r A z 5 £ — l I DIAGRAM O l O 65 35 (t rs- 13 is |M I-* )%s> 1 V0 h- IfO hsr, h* S 11 H Id «&- 2 s S a *i * C. 1 3 *1 a *a *F Si X K a 2 2 X H- 3 =: 5 s J —\ 2 r, ¥ 2 S’ H a n rS) 3 2 a 1 •a "3 2 a 2 1 1 & IBl J 7 l ) i/ N K :*517 > 7 \ 1 ‘1 r*M C 5? 2M s| S s 17ji.) i L*-® 3 £ 1 S' a 2 £ s; a a _ !* & a 3 X 3 z s ■5 *j - tu X S '2 a a *! iw * o 3 X 3 J Ki s . -I r a UJ ¥ a 1 a a a ■> 1 ^i«i s 2 ’S 2 z Si S 2 _J a i-- — 13 |2 lot l 2 x '2 fS? J i?L _S a __a j j sjj 3 .'Si 2 fji > 5 £ ___ I S £ r "5 - ------1------f--T — t» j Is,' js j COMPUTER I/O LEVEL CONVERTER LOGIC DIAGRAM fig. 15*2 tlMIl _____ I (Wi I tt j el lunJIini) I—»—I »!OTt t L______J Mu >‘ TEST SET INTFRFACF TEST SET INTERFACE AND ADDRESS REGISTER LOGIC DIAGRAM FIG. 15,3 86 SOS -1AI 0S0- W ei9- v PANELS MOUNTING ^3TIOyiNOO « qf UB-no«lNco 'HB VIEW «3ll0blN03 ^3 'tjS'.TO'tilNCO ys REAR «3T\OMiNOO \13 I^jL____ FIG. 15.4 LAYOUT OF MODULES IN INTERFACE AND POWER SUPPLIES 89 CONCLUSION A system has been designed and built which meets the requirements set by the task it was to perform. The system has been operating on package testing for sixteen months and wafer probing for fourteen months. Experience has shown that the system works well and has greatly eased the problem of wafer and package testing. As a result of being able to test wafers more thoroughly, a reduction in package rejects and therefore, in cost, has been achieved. Acknowledgments This project was jointly sponsored by A.W.A and the Department of Supply, The author gratefully acknowledges the support from both sources. In addition, the extensive contributions of John Dixon in the construction of this equipment, and in preparing the drawings are acknowledged. Also the helpful discussions with Dr G. Rigby of A.W.A. Microelectronics and my supervisor Mr F. Lewin of the University of New South Wales is acknowledged. BIBLIOGRAPHY "I.C. Test Equipment" G.C. Padwick Microelectronics Jan, 1968 "Hardware-software tradeoff in testing" J.E. Stuehler IEEE Spectrum Dec, 1968 "Economic Considerations in I.C. Testing" Gary Strong Solid State Technology March 1969 "Important Considerations in Selecting a Manual I.C. Tester" M. Eerland Solid State Technology March 1969 "Automatic I.C. Dynamic Testers" T, Drehar, D. Johnson Solid State Technology March 1969 "Probers in Automatic I.C. Testers" Mord Wiesler Solid State Technology March 1969 "Testing Linear Integrated Circuits" M.A. MacDonel.1 Solid State Technology March 1969 "Computer, software, P.C. cards match up to cut costs in an automatic test system" D. Mactaggart Electronics 6 July 1970 Pamphlets Fairchild TAC Test Equipment Corporation T eradyne