Ep 0752685 A1

Europaisches Patentamt (19) European Patent Office Office europeeneen des brevets EP 0 752 685 A1 (12) EUROPEAN PATENT APPLICATION (43) Date of publication: (51) Intel e G06T 15/10 08.01.1997 Bulletin 1997/02 (21) Application number: 96304978.8 (22) Date of filing: 05.07.1996 (84) Designated Contracting States: • Kamen, Yakov DE FR GB IT NL Cupertino. California 95014 (US) (30) Priority: 06.07.1995 US 498733 (74) Representative: Harris, Ian Richard c/o D. Young & Co., (71) Applicant: SUN MICROSYSTEMS, INC. 21 New Fetter Lane Mountain View, CA 94043 (US) London EC4A 1 DA (GB) (72) Inventors: • Goldberg, Richard M. Los Gatos, California 95030 (US) (54) Method and apparatus for efficient rendering of three-dimensional scenes (57) A method and apparatus for rendering an object or scene from a preselected viewpoint onto a display. The object is represented by a texture map stored in a memory of a processor-based system, and the view- 100 point is represented by geometry data stored in the memory. The viewpoint on the object may be represent- Intelligent Memory ed in the geometry data a polygon (or more than one Controller polygon). The processor determines span data by edge- MEMORY CONTROLLER walking the polygon, and transfers the span data to the memory controller. Beginning with a first such span, the processor then transfers the span data (one span at a time) to the memory controller. After each such transfer, the memory controller takes over execution of the rendering procedure, beginning with mapping the current span onto a span of voxels (volume elements) in texture map space. The memory controller then retrieves the colors and textures for that span, and renders the span accordingly (i.e. either displays it or writes it to an ap- propriate memory). Control then returns to the processor, which transfers the data for the next span, and the Mass Storage Display controller again takes over the remainder of the Geometry memory Data rendering procedure for that The transfer of con- span. Texture trol back and forth is repeated until all the of the 182 Map spans / first such polygon are rendered, and until all such poly- 184 gons have been so processed, thus greatly increasing the efficiency and throughput of graphics data in the rendering pipeline. The procedure is made more efficient Figure 1 00 by the use of a dedicated portion of memory for the CO graphics data, under the exclusive control of the mem- CM ory controller. IO Is- o a. LU Printed by Jouve, 75001 PARIS (FR) EP 0 752 685 A1 Description The present invention relates to the visualization and display of three-dimensional scenes or objects on a computer system, and in particular to a new method and apparatus for accelerating the display of three-dimensional scenes. 5 "Visualization" broadly refers to all of the steps taken by a graphics display system from accessing the 3D graphics data (of a scene or object) to rendering the data as a scene on a display device. There are three basic types of 3D data visualization carried out by computer systems today: (1 ) geometry (polygon) rendering (such as wire frame rendering); (2) volume rendering; and (3) 3D texture mapping, which will typically include some features of geometry rendering. The present invention is directed specifically towards more rapid texture mapping 10 than is available with conventional systems. For an extended treatment on methods of graphics visualization, see Foley, van Dam, et al., Computer Graphics - Principles and Practice (2d Ed. 1990 Addison Wesley), incorporated herein by reference. In conventional systems, a graphics application executing on a processor will generate three-dimensional data representing an object or scene for display on a computer monitor or other display or output device. 3D geometry data is are typically processed in the processor under the control of the graphics application. If the system includes a graphics accelerator, the processed data are then sent to the graphics accelerator for rendering on the monitor. 3D texture mapping is an intermediate visualization combining data from geometry rendering and volumetric data from volume rendering. Volumetric data at its simplest is simply a set of 3D pixels (discrete color values), normally referred to as "voxels". Conventional 3D texture mapping can also be combined with arbitrary cutting or clipping to 20 reveal hidden structures within the voxel data. Texture mapping in three dimensions is typically quite a time-consuming process. If the main processor of a computer or other processor-based system is used to carry out the rendering procedures, this can considerably degrade the performance of the system, which typically uses the processor for many other functions and processes. Dedicated graphics controllers and accelerators have been developed which can speed up the rendering procedures, but they 25 are generally quite expensive, so that fully equipping a system with dedicated graphics modules can be prohibitive. Some systems in use today utilize a dedicated pixel bus (a special memory bus just for the pixel data) with an extra memory controller in order to speed up the rendering/display procedure, but this increases the cost and complexity of the system. Thus, in conventional systems a choice must be made to stress either the low cost or the high performance of the 30 architecture. A system is needed that answers both of these challenges - speed and expense. Ideally, a system would be provided that provides the high performance of dedicated graphics modules with the lower cost of general-purpose processors. Aspects of the invention are set out in the accompanying independent claims. Preferred and further features are 35 set out in the dependent Claims. An embodiment of the invention provides for rendering an object or scene from viewpoints selected by a user or a program. The system utilizes an architecture with a processor, a memory, a display device and a dedicated graphics memory controller which is configured to take exclusive control over a number of processes conventionally handled by the processor. The system is provided, in memory, with standard geometry (model coordinate) data and texture 40 map data, and in the rendering method of the invention, the processor executes procedures to bind the model coordinate data to the texture map data, and to transform the model coordinates to device coordinates, i.e. coordinates corre- sponding to regions on the display device. The processor also generates conventional spans, i.e. vectors representing regions of the texture map that will eventually be displayed as scan lines on the display device. The processor then transfers the span information, one span at a time, to the memory controller. After each such 45 transfer, the memory controller takes over control of the rendering procedure and maps, the current span onto the voxels (volume elements) of the texture map space. Each span is in turn rendered with its assigned colors, textures, etc. to the display, or alternatively to a display memory or other memory, for later display. Execution control is now handed back to the processor, which transmits the data for the next span to the memory controller, and then transfers control to the memory controller for texture mapping and rendering. The procedure is so repeated until all the spans for a given polygon (representing the viewpoint onto the object) have been rendered. If there are other polygons, they are then processed in the same manner. The transfer of control back and forth between the processor and the memory controller greatly increases the speed with which objects can be rendered, because the respective functions that the processor and memory controller execute are particularly efficient for those respective devices, and the memory controller's execution of the texture 55 mapping and rendering procedures, which are especially computation-intensive, allows the processor to carry out other functions uninhibited by the multiple interrupts and general degradation of performance that would otherwise occur. The process is made yet more efficient by the establishment of a portion of main (or cache) memory exclusively for the control of the memory controller, so that block transfers of large amounts of graphics data to and from this 2 EP 0 752 685 A1 portion do not interfere with memory accesses to the other portions of memory by the processor. Embodiments of the invention are described hereinafter, by way of example only, with reference to the accompanying drawings, in which: 5 Figure 1 is a block diagram of an apparatus incorporating the present invention. Figure 2 is a diagram illustrating a slice-plane view on a 3D object in model coordinate space. Figure 3 is a diagram illustrating the object and view plane of Figure 2 in 3D texture map space. Figure 4 is a flow chart of a method of the invention. Figure 5 is a diagram illustrating the interpolation procedure of the invention for generating spans. 10 Figure 1 illustrates a computer system 100 of the invention, including a processor 110 coupled via a memory controller 120 including an Intelligent Memory Controller (IMC) 130 to a bus 140. The processor 110 may be a conventional microprocessor as currently used in workstations or personal computers, and the memory controller 120 is standard but for the inclusion of the IMC, whose functions are discussed in detail below. is Also coupled to the bus 140 is a main memory (such as DRAM) 150 or cache memory (e.g. SRAM), which is partitioned, preferably but not necessarily by the operating system, into contiguous memory CMEM 160 and system memory SYM 170. The INIC 130 is preferably dedicated hardware for controlling a portion the CMEM, and may for instance Sun Microsystems, Inc.'s SPARCstation 10SX memory controller chip discussed in detail in a document en- titled "SPARCstation 10sX Graphics Technology - A White Paper (Sun Microsystems, Inc.

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