The LINPACK Benchmark on the Fujitsu AP 1000∗

Total Page:16

File Type:pdf, Size:1020Kb

Load more

The LINPACK Benchmark on the Fujitsu AP 1000∗ Richard P. Brent† Computer Sciences Laboratory Australian National University Canberra, Australia Abstract 1.1 The Fujitsu AP 1000 We describe an implementation of the LINPACK The Fujitsu AP 1000 (also known as the “CAP 2”) Benchmark on the Fujitsu AP 1000. Design consider- is a MIMD machine with up to 1024 independent 25 1 ations include communication primitives, data distri- Mhz SPARC processors which are called cells. Each bution, use of blocking to reduce memory references, cell has 16 MByte of dynamic RAM and 128 KByte and effective use of the cache. Some details of our cache. In some respects the AP 1000 is similar to the blocking strategy appear to be new. The results show CM 5, but the AP 1000 does not have vector units, that the LINPACK Benchmark can be implemented ef- so the floating-point speed of a cell is constrained ficiently on the AP 1000, and it is possible to attain by the performance of its Weitek floating-point unit (5.56 Mflop/cell for overlapped multiply and add in about 80 percent of the theoretical peak performance 64-bit arithmetic). The topology of the AP 1000 is a for large problems. torus, with hardware support for wormhole routing [5]. There are three communication networks – the B-net, 1 Introduction for communication with the host; the S-net, for syn- chronization; and the T-net, for communication be- This paper describes an implementation of the LIN- tween cells. The T-net is the most significant for us. PACK Benchmark [6] on the Fujitsu AP 1000. Pre- It provides a theoretical bandwidth of 25 MByte/sec liminary results were reported in [2]. between cells. In practice, due to overheads such as The LINPACK Benchmark involves the solution copying buffers, about 6 MByte/sec is achievable by of a nonsingular system of n linear equations in n user programs. For details of the AP 1000 architecture unknowns, using Gaussian elimination with partial and software environment, see [3, 4]. pivoting and double-precision (64-bit) floating-point arithmetic. We are interested in large systems since 1.2 Notation there is no point in using a machine such at the AP 1000 to solve single small systems. Apart from the optional use of assembler for some The manner in which matrices are stored is very linear algebra kernels, our programs are written in important on a distributed-memory machine such as the C language. For this reason, we use C index- the AP 1000. In Section 2 we discuss several matrix ing conventions, i.e. rows and columns are indexed storage conventions, including the one adopted for the from 0. Because we often need to take row/column benchmark programs. indices modulo some number related to the machine Section 3 is concerned with the algorithm used for configuration, indexing from 0 is actually more con- parallel LU factorization. Various other aspects of the venient than indexing from 1. In C a matrix with design of the benchmark programs are mentioned in m ≤ MMAX rows and n ≤ NMAX columns may be de- Section 4. For example, we discuss the use of blocking clared as a[MMAX][NMAX], where MMAX and NMAX are con- to improve efficiency, effective use of the cache, and stants known at compile-time. The matrix elements communication primitives. are a[i][j], 0 ≤ i < m, 0 ≤ j < n. Rows are stored in In Section 5 we present results obtained on AP 1000 contiguous locations, i.e. a[i][j] is adjacent to a[i][j+1]. machines with up to 512 cells. Some conclusions are (Fortran conventions are to store columns in contigu- given in Section 6. ous locations, and to start indexing from 1 rather than from 0.) ∗Appeared in Proc. Frontiers ’92 (McLean, VA, October 1992), IEEE Press, 1992, 128–135. c 1992, IEEE. 1SPARCTM is a trademark of Sun Microsystems, Inc. †E-mail address: [email protected] rpb130 typeset using LATEX When referring to the AP 1000 configuration as addition of a multiple of the pivot row. The col- ncelx by ncely, we mean that the AP 1000 is con- umn which defines the multipliers also has to be figured as a torus with ncelx cells in the horizon- broadcast. tal (X) direction (corresponding to index j above) and ncely cells in the vertical (Y) direction (cor- Row/column send/receive. For example, if piv- responding to index i). Here “torus” implies that oting is implemented by explicitly interchanging the cell connections wrap around, i.e. cell (x, y) (for rows, then at each pivoting step two rows may 0 ≤ x < ncelx, 0 <= y < ncely) is connected to cell have to be interchanged. (x ± 1 mod ncelx, y ± 1 mod ncely). Wrap-around is Row/column scan. Here we want to apply an not important for the LINPACK Benchmark – our al- associative operator θ to data in one (or more) gorithm would work almost as well on a machine with rows or columns. For example, when selecting a rectangular grid without wrap-around. the pivot row it is necessary to find the index of The total number of cells is P = ncelx · ncely. The the element of maximum absolute value in (part aspect ratio is the ratio ncely : ncelx. If the aspect of) a column. This may be computed with a scan ratio is 1 or 2 we sometimes use s = ncelx. In this if we define an associative operator θ as follows: case ncely = s or 2s and P = s2 or 2s2. (a, i), if |a| ≥ |b|; (a, i) θ (b, j) = 1.3 Restrictions (b, j), otherwise. Our first implementation was restricted to a square Other useful associative operators are addition (of AP 1000 array, i.e. one with aspect ratio 1. Later this scalars or vectors) and concatenation (of vectors). was extended in an ad hoc manner to aspect ratio 2. This was sufficient for benchmark purposes since all It is desirable for data to be distributed in a “nat- AP 1000 machines have 2k cells for some integer k, ural” manner, so that the operations of row/column and can be configured with aspect ratio 1 (if k is even) broadcast/send/receive/scan can be implemented effi- or 2 (if k is odd). For simplicity, the description in ciently [1]. Sections 3 and 4 assumes aspect ratio 1. A simple mapping of data to cells is the column- A minor restriction is that n is a multiple of ncely. wrapped representation. Here column i of a matrix This is not a serious constraint, since it is easy to add is stored in the memory associated with cell i mod P , up to ncely −1 rows and columns (zero except for unit assuming that the P cells are numbered 0, 1,...,P −1. diagonal entries) to get a slightly larger system with Although simple, and widely used in parallel im- essentially the same solution. plementations of Gaussian elimination [13, 14, 18, 19], the column-wrapped representation has some disad- vantages – lack of symmetry, poor load balancing, and 2 Matrix storage conventions poor communication bandwidth for column broad- cast – see [1]. Similar comments apply to the anal- On the AP 1000 each cell has a local memory which ogous row-wrapped representation. is accessible to other cells only via explicit message Another conceptually simple mapping is the blocked passing. It is customary to partition data such as ma- representation. Here A is partioned into at most P trices and vectors across the local memories of several blocks of contiguous elements, and at most one block cells. This is essential for problems which are too large is stored in each cell. However, as described in [1], to fit in the memory of one cell, and in any case it the blocked representation is inconvenient for matrix is usually desirable for load-balancing reasons. Since operations if several matrices are stored with different vectors are a special case of matrices, we consider the block dimensions, and it suffers from a load-balancing partitioning of a matrix A. problem. Before considering how to map data onto the Harder to visualize, but often better than the AP 1000, it is worth considering what forms of data row/column-wrapped or blocked representations, is movement are common in Gaussian elimination with the scattered representation [8], sometimes called dot partial pivoting. Most other linear algebra algorithms mode [17] or cut-and-pile. Assume as above that the have similar data movement requirements. To perform cells form an s by s grid. Then the matrix element ai,j Gaussian elimination we need – is stored in cell (j mod s, i mod s) with local indices (bi/sc, bj/sc). The matrices stored locally on each cell Row/column broadcast. For example, the pivot have the same shape (e.g. triangular, ...) as the global row has to be sent to processors responsible for matrix A, so the computational load on each cell is ap- other rows, so that they can be modified by the proximately the same. 2 The blocked and scattered representations do not In the following we shall only consider the transfor- require a configuration with aspect ratio 1, although mation of A to U, as the transformation of A¯ to U¯ is matrix multiplication and transposition are easier to similar. implement if the aspect ratio is 1 than in the general If A has n rows, the following steps have to be re- case [20]. In the general case, the scattered represen- peated n−1 times, where the k-th iteration completes tation of A on an ncelx by ncely configuration stores computation of the k-th row of U – matrix element ai,j on cell (j mod ncelx, i mod ncely).
Recommended publications
  • Microprocessor

    Microprocessor

    MICROPROCESSOR www.MPRonline.com THE REPORTINSIDER’S GUIDE TO MICROPROCESSOR HARDWARE EEMBC’S MULTIBENCH ARRIVES CPU Benchmarks: Not Just For ‘Benchmarketing’ Any More By Tom R. Halfhill {7/28/08-01} Imagine a world without measurements or statistical comparisons. Baseball fans wouldn’t fail to notice that a .300 hitter is better than a .100 hitter. But would they welcome a trade that sends the .300 hitter to Cleveland for three .100 hitters? System designers and software developers face similar quandaries when making trade-offs EEMBC’s role has evolved over the years, and Multi- with multicore processors. Even if a dual-core processor Bench is another step. Originally, EEMBC was conceived as an appears to be better than a single-core processor, how much independent entity that would create benchmark suites and better is it? Twice as good? Would a quad-core processor be certify the scores for accuracy, allowing vendors and customers four times better? Are more cores worth the additional cost, to make valid comparisons among embedded microproces- design complexity, power consumption, and programming sors. (See MPR 5/1/00-02, “EEMBC Releases First Bench- difficulty? marks.”) EEMBC still serves that role. But, as it turns out, most The Embedded Microprocessor Benchmark Consor- EEMBC members don’t openly publish their scores. Instead, tium (EEMBC) wants to help answer those questions. they disclose scores to prospective customers under an NDA or EEMBC’s MultiBench 1.0 is a new benchmark suite for use the benchmarks for internal testing and analysis. measuring the throughput of multiprocessor systems, Partly for this reason, MPR rarely cites EEMBC scores including those built with multicore processors.
  • Load Testing, Benchmarking, and Application Performance Management for the Web

    Load Testing, Benchmarking, and Application Performance Management for the Web

    Published in the 2002 Computer Measurement Group (CMG) Conference, Reno, NV, Dec. 2002. LOAD TESTING, BENCHMARKING, AND APPLICATION PERFORMANCE MANAGEMENT FOR THE WEB Daniel A. Menascé Department of Computer Science and E-center of E-Business George Mason University Fairfax, VA 22030-4444 [email protected] Web-based applications are becoming mission-critical for many organizations and their performance has to be closely watched. This paper discusses three important activities in this context: load testing, benchmarking, and application performance management. Best practices for each of these activities are identified. The paper also explains how basic performance results can be used to increase the efficiency of load testing procedures. infrastructure depends on the traffic it expects to see 1. Introduction at its site. One needs to spend enough but no more than is required in the IT infrastructure. Besides, Web-based applications are becoming mission- resources need to be spent where they will generate critical to most private and governmental the most benefit. For example, one should not organizations. The ever-increasing number of upgrade the Web servers if most of the delay is in computers connected to the Internet and the fast the database server. So, in order to maximize the growing number of Web-enabled wireless devices ROI, one needs to know when and how to upgrade create incentives for companies to invest in Web- the IT infrastructure. In other words, not spending at based infrastructures and the associated personnel the right time and spending at the wrong place will to maintain them. By establishing a Web presence, a reduce the cost-benefit of the investment.
  • Microbenchmarks in Big Data

    Microbenchmarks in Big Data

    M Microbenchmark Overview Microbenchmarks constitute the first line of per- Nicolas Poggi formance testing. Through them, we can ensure Databricks Inc., Amsterdam, NL, BarcelonaTech the proper and timely functioning of the different (UPC), Barcelona, Spain individual components that make up our system. The term micro, of course, depends on the prob- lem size. In BigData we broaden the concept Synonyms to cover the testing of large-scale distributed systems and computing frameworks. This chap- Component benchmark; Functional benchmark; ter presents the historical background, evolution, Test central ideas, and current key applications of the field concerning BigData. Definition Historical Background A microbenchmark is either a program or routine to measure and test the performance of a single Origins and CPU-Oriented Benchmarks component or task. Microbenchmarks are used to Microbenchmarks are closer to both hardware measure simple and well-defined quantities such and software testing than to competitive bench- as elapsed time, rate of operations, bandwidth, marking, opposed to application-level – macro or latency. Typically, microbenchmarks were as- – benchmarking. For this reason, we can trace sociated with the testing of individual software microbenchmarking influence to the hardware subroutines or lower-level hardware components testing discipline as can be found in Sumne such as the CPU and for a short period of time. (1974). Furthermore, we can also find influence However, in the BigData scope, the term mi- in the origins of software testing methodology crobenchmarking is broadened to include the during the 1970s, including works such cluster – group of networked computers – acting as Chow (1978). One of the first examples of as a single system, as well as the testing of a microbenchmark clearly distinguishable from frameworks, algorithms, logical and distributed software testing is the Whetstone benchmark components, for a longer period and larger data developed during the late 1960s and published sizes.
  • Overview of the SPEC Benchmarks

    Overview of the SPEC Benchmarks

    9 Overview of the SPEC Benchmarks Kaivalya M. Dixit IBM Corporation “The reputation of current benchmarketing claims regarding system performance is on par with the promises made by politicians during elections.” Standard Performance Evaluation Corporation (SPEC) was founded in October, 1988, by Apollo, Hewlett-Packard,MIPS Computer Systems and SUN Microsystems in cooperation with E. E. Times. SPEC is a nonprofit consortium of 22 major computer vendors whose common goals are “to provide the industry with a realistic yardstick to measure the performance of advanced computer systems” and to educate consumers about the performance of vendors’ products. SPEC creates, maintains, distributes, and endorses a standardized set of application-oriented programs to be used as benchmarks. 489 490 CHAPTER 9 Overview of the SPEC Benchmarks 9.1 Historical Perspective Traditional benchmarks have failed to characterize the system performance of modern computer systems. Some of those benchmarks measure component-level performance, and some of the measurements are routinely published as system performance. Historically, vendors have characterized the performances of their systems in a variety of confusing metrics. In part, the confusion is due to a lack of credible performance information, agreement, and leadership among competing vendors. Many vendors characterize system performance in millions of instructions per second (MIPS) and millions of floating-point operations per second (MFLOPS). All instructions, however, are not equal. Since CISC machine instructions usually accomplish a lot more than those of RISC machines, comparing the instructions of a CISC machine and a RISC machine is similar to comparing Latin and Greek. 9.1.1 Simple CPU Benchmarks Truth in benchmarking is an oxymoron because vendors use benchmarks for marketing purposes.
  • Hypervisors Vs. Lightweight Virtualization: a Performance Comparison

    Hypervisors Vs. Lightweight Virtualization: a Performance Comparison

    2015 IEEE International Conference on Cloud Engineering Hypervisors vs. Lightweight Virtualization: a Performance Comparison Roberto Morabito, Jimmy Kjällman, and Miika Komu Ericsson Research, NomadicLab Jorvas, Finland [email protected], [email protected], [email protected] Abstract — Virtualization of operating systems provides a container and alternative solutions. The idea is to quantify the common way to run different services in the cloud. Recently, the level of overhead introduced by these platforms and the lightweight virtualization technologies claim to offer superior existing gap compared to a non-virtualized environment. performance. In this paper, we present a detailed performance The remainder of this paper is structured as follows: in comparison of traditional hypervisor based virtualization and Section II, literature review and a brief description of all the new lightweight solutions. In our measurements, we use several technologies and platforms evaluated is provided. The benchmarks tools in order to understand the strengths, methodology used to realize our performance comparison is weaknesses, and anomalies introduced by these different platforms in terms of processing, storage, memory and network. introduced in Section III. The benchmark results are presented Our results show that containers achieve generally better in Section IV. Finally, some concluding remarks and future performance when compared with traditional virtual machines work are provided in Section V. and other recent solutions. Albeit containers offer clearly more dense deployment of virtual machines, the performance II. BACKGROUND AND RELATED WORK difference with other technologies is in many cases relatively small. In this section, we provide an overview of the different technologies included in the performance comparison.
  • Power Measurement Tutorial for the Green500 List

    Power Measurement Tutorial for the Green500 List

    Power Measurement Tutorial for the Green500 List R. Ge, X. Feng, H. Pyla, K. Cameron, W. Feng June 27, 2007 Contents 1 The Metric for Energy-Efficiency Evaluation 1 2 How to Obtain P¯(Rmax)? 2 2.1 The Definition of P¯(Rmax)...................................... 2 2.2 Deriving P¯(Rmax) from Unit Power . 2 2.3 Measuring Unit Power . 3 3 The Measurement Procedure 3 3.1 Equipment Check List . 4 3.2 Software Installation . 4 3.3 Hardware Connection . 4 3.4 Power Measurement Procedure . 5 4 Appendix 6 4.1 Frequently Asked Questions . 6 4.2 Resources . 6 1 The Metric for Energy-Efficiency Evaluation This tutorial serves as a practical guide for measuring the computer system power that is required as part of a Green500 submission. It describes the basic procedures to be followed in order to measure the power consumption of a supercomputer. A supercomputer that appears on The TOP500 List can easily consume megawatts of electric power. This power consumption may lead to operating costs that exceed acquisition costs as well as intolerable system failure rates. In recent years, we have witnessed an increasingly stronger movement towards energy-efficient computing systems in academia, government, and industry. Thus, the purpose of the Green500 List is to provide a ranking of the most energy-efficient supercomputers in the world and serve as a complementary view to the TOP500 List. However, as pointed out in [1, 2], identifying a single objective metric for energy efficiency in supercom- puters is a difficult task. Based on [1, 2] and given the already existing use of the “performance per watt” metric, the Green500 List uses “performance per watt” (PPW) as its metric to rank the energy efficiency of supercomputers.
  • Opportunities and Open Problems for Static and Dynamic Program Analysis Mark Harman∗, Peter O’Hearn∗ ∗Facebook London and University College London, UK

    Opportunities and Open Problems for Static and Dynamic Program Analysis Mark Harman∗, Peter O’Hearn∗ ∗Facebook London and University College London, UK

    1 From Start-ups to Scale-ups: Opportunities and Open Problems for Static and Dynamic Program Analysis Mark Harman∗, Peter O’Hearn∗ ∗Facebook London and University College London, UK Abstract—This paper1 describes some of the challenges and research questions that target the most productive intersection opportunities when deploying static and dynamic analysis at we have yet witnessed: that between exciting, intellectually scale, drawing on the authors’ experience with the Infer and challenging science, and real-world deployment impact. Sapienz Technologies at Facebook, each of which started life as a research-led start-up that was subsequently deployed at scale, Many industrialists have perhaps tended to regard it unlikely impacting billions of people worldwide. that much academic work will prove relevant to their most The paper identifies open problems that have yet to receive pressing industrial concerns. On the other hand, it is not significant attention from the scientific community, yet which uncommon for academic and scientific researchers to believe have potential for profound real world impact, formulating these that most of the problems faced by industrialists are either as research questions that, we believe, are ripe for exploration and that would make excellent topics for research projects. boring, tedious or scientifically uninteresting. This sociological phenomenon has led to a great deal of miscommunication between the academic and industrial sectors. I. INTRODUCTION We hope that we can make a small contribution by focusing on the intersection of challenging and interesting scientific How do we transition research on static and dynamic problems with pressing industrial deployment needs. Our aim analysis techniques from the testing and verification research is to move the debate beyond relatively unhelpful observations communities to industrial practice? Many have asked this we have typically encountered in, for example, conference question, and others related to it.
  • Evaluation of AMD EPYC

    Evaluation of AMD EPYC

    Evaluation of AMD EPYC Chris Hollowell <[email protected]> HEPiX Fall 2018, PIC Spain What is EPYC? EPYC is a new line of x86_64 server CPUs from AMD based on their Zen microarchitecture Same microarchitecture used in their Ryzen desktop processors Released June 2017 First new high performance series of server CPUs offered by AMD since 2012 Last were Piledriver-based Opterons Steamroller Opteron products cancelled AMD had focused on low power server CPUs instead x86_64 Jaguar APUs ARM-based Opteron A CPUs Many vendors are now offering EPYC-based servers, including Dell, HP and Supermicro 2 How Does EPYC Differ From Skylake-SP? Intel’s Skylake-SP Xeon x86_64 server CPU line also released in 2017 Both Skylake-SP and EPYC CPU dies manufactured using 14 nm process Skylake-SP introduced AVX512 vector instruction support in Xeon AVX512 not available in EPYC HS06 official GCC compilation options exclude autovectorization Stock SL6/7 GCC doesn’t support AVX512 Support added in GCC 4.9+ Not heavily used (yet) in HEP/NP offline computing Both have models supporting 2666 MHz DDR4 memory Skylake-SP 6 memory channels per processor 3 TB (2-socket system, extended memory models) EPYC 8 memory channels per processor 4 TB (2-socket system) 3 How Does EPYC Differ From Skylake (Cont)? Some Skylake-SP processors include built in Omnipath networking, or FPGA coprocessors Not available in EPYC Both Skylake-SP and EPYC have SMT (HT) support 2 logical cores per physical core (absent in some Xeon Bronze models) Maximum core count (per socket) Skylake-SP – 28 physical / 56 logical (Xeon Platinum 8180M) EPYC – 32 physical / 64 logical (EPYC 7601) Maximum socket count Skylake-SP – 8 (Xeon Platinum) EPYC – 2 Processor Inteconnect Skylake-SP – UltraPath Interconnect (UPI) EYPC – Infinity Fabric (IF) PCIe lanes (2-socket system) Skylake-SP – 96 EPYC – 128 (some used by SoC functionality) Same number available in single socket configuration 4 EPYC: MCM/SoC Design EPYC utilizes an SoC design Many functions normally found in motherboard chipset on the CPU SATA controllers USB controllers etc.
  • The High Performance Linpack (HPL) Benchmark Evaluation on UTP High Performance Computing Cluster by Wong Chun Shiang 16138 Diss

    The High Performance Linpack (HPL) Benchmark Evaluation on UTP High Performance Computing Cluster by Wong Chun Shiang 16138 Diss

    The High Performance Linpack (HPL) Benchmark Evaluation on UTP High Performance Computing Cluster By Wong Chun Shiang 16138 Dissertation submitted in partial fulfilment of the requirements for the Bachelor of Technology (Hons) (Information and Communications Technology) MAY 2015 Universiti Teknologi PETRONAS Bandar Seri Iskandar 31750 Tronoh Perak Darul Ridzuan CERTIFICATION OF APPROVAL The High Performance Linpack (HPL) Benchmark Evaluation on UTP High Performance Computing Cluster by Wong Chun Shiang 16138 A project dissertation submitted to the Information & Communication Technology Programme Universiti Teknologi PETRONAS In partial fulfillment of the requirement for the BACHELOR OF TECHNOLOGY (Hons) (INFORMATION & COMMUNICATION TECHNOLOGY) Approved by, ____________________________ (DR. IZZATDIN ABDUL AZIZ) UNIVERSITI TEKNOLOGI PETRONAS TRONOH, PERAK MAY 2015 ii CERTIFICATION OF ORIGINALITY This is to certify that I am responsible for the work submitted in this project, that the original work is my own except as specified in the references and acknowledgements, and that the original work contained herein have not been undertaken or done by unspecified sources or persons. ________________ WONG CHUN SHIANG iii ABSTRACT UTP High Performance Computing Cluster (HPCC) is a collection of computing nodes using commercially available hardware interconnected within a network to communicate among the nodes. This campus wide cluster is used by researchers from internal UTP and external parties to compute intensive applications. However, the HPCC has never been benchmarked before. It is imperative to carry out a performance study to measure the true computing ability of this cluster. This project aims to test the performance of a campus wide computing cluster using a selected benchmarking tool, the High Performance Linkpack (HPL).
  • A Study on the Evaluation of HPC Microservices in Containerized Environment

    A Study on the Evaluation of HPC Microservices in Containerized Environment

    ReceivED XXXXXXXX; ReVISED XXXXXXXX; Accepted XXXXXXXX DOI: xxx/XXXX ARTICLE TYPE A Study ON THE Evaluation OF HPC Microservices IN Containerized EnVIRONMENT DeVKI Nandan Jha*1 | SaurABH Garg2 | Prem PrAKASH JaYARAMAN3 | Rajkumar Buyya4 | Zheng Li5 | GrAHAM Morgan1 | Rajiv Ranjan1 1School Of Computing, Newcastle UnivERSITY, UK Summary 2UnivERSITY OF Tasmania, Australia, 3Swinburne UnivERSITY OF TECHNOLOGY, AustrALIA Containers ARE GAINING POPULARITY OVER VIRTUAL MACHINES (VMs) AS THEY PROVIDE THE ADVANTAGES 4 The UnivERSITY OF Melbourne, AustrALIA OF VIRTUALIZATION WITH THE PERFORMANCE OF NEAR bare-metal. The UNIFORMITY OF SUPPORT PROVIDED 5UnivERSITY IN Concepción, Chile BY DockER CONTAINERS ACROSS DIFFERENT CLOUD PROVIDERS MAKES THEM A POPULAR CHOICE FOR DEVel- Correspondence opers. EvOLUTION OF MICROSERVICE ARCHITECTURE ALLOWS COMPLEX APPLICATIONS TO BE STRUCTURED INTO *DeVKI Nandan Jha Email: [email protected] INDEPENDENT MODULAR COMPONENTS MAKING THEM EASIER TO manage. High PERFORMANCE COMPUTING (HPC) APPLICATIONS ARE ONE SUCH APPLICATION TO BE DEPLOYED AS microservices, PLACING SIGNIfiCANT RESOURCE REQUIREMENTS ON THE CONTAINER FRamework. HoweVER, THERE IS A POSSIBILTY OF INTERFERENCE BETWEEN DIFFERENT MICROSERVICES HOSTED WITHIN THE SAME CONTAINER (intra-container) AND DIFFERENT CONTAINERS (inter-container) ON THE SAME PHYSICAL host. In THIS PAPER WE DESCRIBE AN Exten- SIVE EXPERIMENTAL INVESTIGATION TO DETERMINE THE PERFORMANCE EVALUATION OF DockER CONTAINERS EXECUTING HETEROGENEOUS HPC microservices. WE ARE PARTICULARLY CONCERNED WITH HOW INTRa- CONTAINER AND inter-container INTERFERENCE INflUENCES THE performance. MoreoVER, WE INVESTIGATE THE PERFORMANCE VARIATIONS IN DockER CONTAINERS WHEN CONTROL GROUPS (cgroups) ARE USED FOR RESOURCE limitation. FOR EASE OF PRESENTATION AND REPRODUCIBILITY, WE USE Cloud Evaluation Exper- IMENT Methodology (CEEM) TO CONDUCT OUR COMPREHENSIVE SET OF Experiments.
  • Fair Benchmarking for Cloud Computing Systems

    Fair Benchmarking for Cloud Computing Systems

    Fair Benchmarking for Cloud Computing Systems Authors: Lee Gillam Bin Li John O’Loughlin Anuz Pranap Singh Tomar March 2012 Contents 1 Introduction .............................................................................................................................................................. 3 2 Background .............................................................................................................................................................. 4 3 Previous work ........................................................................................................................................................... 5 3.1 Literature ........................................................................................................................................................... 5 3.2 Related Resources ............................................................................................................................................. 6 4 Preparation ............................................................................................................................................................... 9 4.1 Cloud Providers................................................................................................................................................. 9 4.2 Cloud APIs ...................................................................................................................................................... 10 4.3 Benchmark selection ......................................................................................................................................
  • An Effective Dynamic Analysis for Detecting Generalized Deadlocks

    An Effective Dynamic Analysis for Detecting Generalized Deadlocks

    An Effective Dynamic Analysis for Detecting Generalized Deadlocks Pallavi Joshi Mayur Naik Koushik Sen EECS, UC Berkeley, CA, USA Intel Labs Berkeley, CA, USA EECS, UC Berkeley, CA, USA [email protected] [email protected] [email protected] David Gay Intel Labs Berkeley, CA, USA [email protected] ABSTRACT for a synchronization event that will never happen. Dead- We present an effective dynamic analysis for finding a broad locks are a common problem in real-world multi-threaded class of deadlocks, including the well-studied lock-only dead- programs. For instance, 6,500/198,000 (∼ 3%) of the bug locks as well as the less-studied, but no less widespread or reports in the bug database at http://bugs.sun.com for insidious, deadlocks involving condition variables. Our anal- Sun's Java products involve the keyword \deadlock" [11]. ysis consists of two stages. In the first stage, our analysis Moreover, deadlocks often occur non-deterministically, un- observes a multi-threaded program execution and generates der very specific thread schedules, making them harder to a simple multi-threaded program, called a trace program, detect and reproduce using conventional testing approaches. that only records operations observed during the execution Finally, extending existing multi-threaded programs or fix- that are deemed relevant to finding deadlocks. Such op- ing other concurrency bugs like races often involves intro- erations include lock acquire and release, wait and notify, ducing new synchronization, which, in turn, can introduce thread start and join, and change of values of user-identified new deadlocks. Therefore, deadlock detection tools are im- synchronization predicates associated with condition vari- portant for developing and testing multi-threaded programs.