Standard Gotchas Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know! Stuart Sutherland Don Mills Sutherland HDL, Inc. Microchip Portland, Oregon Chandler, Arizona
[email protected] [email protected] Don Mills, Microchip Stu Sutherland Presentation Overview Sutherland training engineers HD to be SystemVerilog Wizards L What is a “gotcha”? Why do standards have gotchas? What’s covered in this paper Several example gotchas, and how to avoid them! Summary 2of 20 Don Mills, Microchip Stu Sutherland What Is A Gotcha? Sutherland training engineers HD to be SystemVerilog Wizards L In programming, a “gotcha” is a legal language construct that does not do what the designer expects A Classic C programming Gotcha... Gotcha! if (day = 15) IfIf middlemiddle ofof thethe month,month, thenthen paypay employees…employees… /* process payroll */ GOTCHA!GOTCHA!This This codecode willwill assignassign thethe valuevalue ofof 1515 toto day,day, andand thenthen ifif dayday isis notnot zero,zero, paypay thethe employeesemployees In hardware design and verification, most gotchas will simulate, but give undesired results Gotchas can be difficult to find and debug A gotcha can be disastrous if not found before tape-out! Engineers need to know how to recognize and avoid gotchas in hardware modeling! 3of 20 Don Mills, Microchip Why Do Stu Sutherland Sutherland Standards Have Gotchas? training engineers HD to be SystemVerilog Wizards L Standards developers are idiots Users of standards are idiots Languages