Standard Gotchas Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know!

Stuart Sutherland Don Mills Sutherland HDL, Inc. Microchip Portland, Oregon Chandler, Arizona [email protected] [email protected] Don Mills, Microchip Stu Sutherland Presentation Overview Sutherland training engineers HD to be SystemVerilog Wizards L

‰ What is a “gotcha”?

‰ Why do standards have gotchas?

‰ What’s covered in this paper

‰ Several example gotchas, and how to avoid them!

‰ Summary

2of 20 Don Mills, Microchip Stu Sutherland What Is A Gotcha? Sutherland training engineers HD to be SystemVerilog Wizards L

ƒ In programming, a “gotcha” is a legal language construct that does not do what the designer expects A Classic C programming Gotcha...

Gotcha! if (day = 15) IfIf middlemiddle ofof thethe month,month, thenthen paypay employees…employees… /* process payroll */ GOTCHA!GOTCHA!This This codecode willwill assignassign thethe valuevalue ofof 1515 toto day,day, andand thenthen ifif dayday isis notnot zero,zero, paypay thethe employeesemployees ƒ In hardware design and verification, most gotchas will simulate, but give undesired results ƒ Gotchas can be difficult to find and debug ƒ A gotcha can be disastrous if not found before tape-out! Engineers need to know how to recognize and avoid gotchas in hardware modeling! 3of 20 Don Mills, Microchip Why Do Stu Sutherland Sutherland Standards Have Gotchas? training engineers HD to be SystemVerilog Wizards L

ƒ Standards developers are idiots ƒ Users of standards are idiots ƒ Languages can be used the right way, or the wrong way

if (day = 15) Gotcha! AA dumbdumb wayway toto useuse “assignment“assignment /* process payroll */ withinwithin anan expression”expression”

while (data = fscanf(…)) AA cleverclever wayway toto useuse “assignment“assignment /* read in data until it is 0 */ withinwithin anan expression”expression”

ƒ Hardware models are not just simulated, they are synthesized, analyzed, emulated, prototyped, formally proved, … ƒ Each type of tool needs different information from the language ƒ Verilog and SystemVerilog allow designers to prove what will — and what will not — work correctly It needs to be legal syntax to model bad hardware ƒ 4of 20 Don Mills, Microchip Stu Sutherland Is This a Verilog Gotcha? Sutherland training engineers HD to be SystemVerilog Wizards L

ƒ Is the classic C gotcha also a gotcha in Verilog?

always @(state) Legal or Illegal? if (state = LOAD) Illegal! Verilog does not allow ... assignment statements inside of expressions

ƒ What about in SystemVerilog? ƒ SystemVerilog extends Verilog with more C and C++ features

always @(state) Legal or Illegal? if (state = LOAD) If you don’t know the answer, then ... you really need to read this paper! (We will answer this question at the end of our presentation...)

5of 20 Don Mills, Microchip Stu Sutherland What’s In This Paper… Sutherland training engineers HD to be SystemVerilog Wizards L

ƒ Detailed descriptions of 57 gotchas…and how to avoid them!

• Case sensitivity • Literal size mismatch in assignments • Operations in sensitivity lists • Implicit net declarations • Z extension backward compatibility • Sequential blocks with begin...end • Escaped identifiers in hierarchy paths • Filling vectors • Sequential blocks with partial reset • Verification of dynamic data • Passing real types through ports • Blocking assigns in sequential blocks • Variables declared in unnamed blocks • Port connection rules • Evaluation of true/false on 4-state values • Hierarchical references to package items • Back-driven input ports • Not operator versus invert operator • Variables not dumped to VCD files • Self- & context-determined operations • Nested if...else blocks • Shared variables in modules • Operation size and sign extension • Casez/casex masks in case expressions • Shared variables in interfaces, packages • Signed math operations • Incomplete or redundant decisions • Shared variables in tasks and functions • Bit and part select operations • Out-of-bounds in enumerated types • Importing enum types from packages • Increment and decrement operations • Statements that hide design problems • Importing from multiple packages • Pre-increment versus post-increment • Simulation versus synthesis mismatches • Resetting 2-state models • Multiple read/writes in one statement • Multiple levels of same virtual method • Locked state machines • Operator evaluation short circuiting • Event trigger race conditions • Hidden design problems • Assignments in expressions • Using semaphores for synchronization • Out-of-bounds indication lost • Procedural block activation • Using mailboxes for synchronization • Signed versus unsigned literal integers • Combinational logic sensitivity lists • Coverage reporting • Default base of literal integers • Arrays in sensitivity lists • $unit declarations • Size mismatch in literal integers • Vectors in sensitivity lists • Compiling $unit 6of 20 Don Mills, Microchip A Classic Verilog Gotcha: Stu Sutherland Sutherland Implicit Net Declarations training engineers HD to be SystemVerilog Wizards L

ƒ An undeclared signal used in a netlist infers an implicit net ƒ Implicit nets can save typing hundreds of lines of code in a large, gate-level design ƒ But… ƒ An undeclared vector connection infers a 1-bit wire, not a vector; ƒ A typographical error in a netlist becomes a functional bug

xor u1 (n0, a, b); ƒƒ NetsNets n0n0 “en-zero”“en-zero” andand nOnO “en-oh”“en-oh” areare Gotcha! inferred,inferred, butbut areare notnot connectedconnected togethertogether and u2 (n1, nO, c); ƒ Nets n1 “en-one” and nl “en-ell” are ram u3 (addr, data, nl); inferred, but are not connected together ƒ Nets addr and data are inferred as 1-bit wires, but should probably be vectors ƒ To avoid this Gotcha… ƒ Verilog’s default_nettype none turns off implicit net types ƒ SystemVerilog .name and .* port connections will not infer nets 7of 20 Don Mills, Microchip Gotcha: Default Base of Stu Sutherland Sutherland Literal Numbers is Decimal training engineers HD to be SystemVerilog Wizards L

ƒ Optionally, literal numbers can be defined with a base ’hC // unsized hex value 2’b01 // sized binary value

ƒ But…the default base is decimal Why don’t states 2 and 3 reg [1:0] state; ever execute?

always @(state) case (state) 00: // do State 0 stuff 01: // do State 1 stuff 10: // do State 2 stuff Gotcha! 11: // do State 3 stuff endcase

Hint:Hint: ThereThere areare 1010 typestypes ofof peoplepeople inin thethe world…world… ƒ To avoid this Gotcha… thosethose thatthat knowknow binary,binary, andand thosethose thatthat don’t!don’t! ƒ Use unique case to detect the error

ƒ Use based numbers to fix the problem (e.g 2’b10) 8of 20 Don Mills, Microchip Gotcha: Literal Numbers Are Stu Sutherland Sutherland Zero-extended to Their Size training engineers HD to be SystemVerilog Wizards L

ƒ Literal number syntax is: ’ ƒ (optional) is the number of bits (default size is 32 bits) ƒ (optional) is the letter s or S (default is unsigned) ƒ is b, o, d, h for binary, octal, decimal or hex (not case sensitive) ’hC // unsized hex value 2’b01 // sized binary value ƒ If the size does not match the number of bits in the value: ƒ If the left-most bit of value is 0 or 1, the value is left-extended with 0 ƒ If the left-most bit of value is Z, the value is left-extended with Z ƒ If the left-most bit of value is X, the value is left-extended with X ƒ But…a signed value is not sign-extended! 8’hA unsigned value extends to 00001010 8’shA8’shA isis notnot sign-extendedsign-extended 8’shA signed value extends to 00001010 becausebecause thethe signsign bitbit isis thethe MSBMSB ofof thethe size,size, notnot thethe ƒ To avoid this Gotcha… Gotcha! MSBMSB ofof thethe value!value! ƒ Engineers need to learn Verilog’s sign extension rules! 9of 20 Don Mills, Microchip Gotcha: Importing Enumerated Stu Sutherland Sutherland Types from Packages training engineers HD to be SystemVerilog Wizards L

ƒ Packages declarations can be “imported” into modules ƒ But…importing an enumerated type does not import the enumerated labels package chip_types; typedef enum {RESET, WAITE, LOAD, READY} states_t; endpackage module chip (...); import chip_types::states_t; states_t state, next_state; always @(posedge clk, negedge rstN) if (!resetN) state <= RESET; RESETRESET hashas notnot beenbeen ... Gotcha! importedimported intointo chipchip ƒ To avoid this Gotcha… ƒ Either use a wildcard import to import the full package, or explicitly import each enumerated label import chip_types::*; 10 of 20 Don Mills, Microchip Gotcha: Locked State Machines Stu Sutherland Sutherland with Enumerated Types training engineers HD to be SystemVerilog Wizards L

ƒ Enumerated types are useful for modeling FSM state names ƒ But…enumerated variables start simulation with uninitialized values (the starting value of the base data type of the enum) module chip (...); StateState andand nStatenState bothboth beginbegin withwith WAITEWAITE typedef enum {WAITE, LOAD, READY} states_t; ƒƒ TheThe defaultdefault basebase datadata typetype isis intint states_t State, nState; ƒƒ TheThe uninitializeduninitialized valuvaluee ofof anan intint isis 00 ƒƒ TheThe defaultdefault valuevalue ofof WAITEWAITE isis 00 always_ff @(posedge clk, negedge rstN) if (!rstN) State <= WAITE; ResetReset setssetsStateState toto WAITEWAITE else State <= nState; ƒ Since State is already WAITE, there is no change to State always @(State) ƒ The always @(State) does not trigger Gotcha! ƒ nState does not get updated (remains WAITE) case (State) WAITE: nState = LOAD; AA posedgeposedge clockclock setssets StateState toto nStatenState,, whichwhich isisWAITEWAITE ... ƒ Since State is already WAITE, there is no change to State ƒ The always @(State) does not trigger ƒ To avoid this Gotcha… ƒ nState does not get updated (remains WAITE) ƒ Use always_comb instead of always @(State) or always @*

ƒ and/or declare the enumerated type with a 4-state base type 11 of 20 Don Mills, Microchip Gotcha: Out-of-Bounds in Stu Sutherland Sutherland Enumerated Types training engineers HD to be SystemVerilog Wizards L

ƒ Enumerated types define a legal set of values for a variable ƒ It is illegal to assign an enumerated variable a value not in its list ƒ But…power-up and/or casting can cause out-of-bounds values module chip (...); typedef enum logic [2:0] {WAITE=3’b001, LOAD=3’b010, READY=3’b100} states_t; states_t State, nState; always_comb begin Gotcha! if (enable) nState = states_t’(State + 1); // move to next label in list? ...

ƒƒ IfIf StateState isis WAITEWAITE,, addingadding 11 resultsresults inin nStatenState havinghaving 3’b0103’b010(the (the valuevalue ofof LOADLOAD)) ƒ If State is LOAD, adding 1 results in nState having 3’b011 (not in the enumerated list!) ƒ If State is WAITE, adding 1 results in nState having 3’b101 (not in the enumerated list!) ƒ At start of simulation, State and nState have 3’bxxx (not in the enumerated list!) ƒ To avoid this Gotcha… ƒ Out-of-bounds at power-up is useful—it indicates reset problems ƒ Out-of-bounds assignments can be prevented using enumerated

methods nState = State.next; // move to next label in list 12 of 20 Don Mills, Microchip Gotcha: Hierarchical Stu Sutherland Sutherland References to Package Items training engineers HD to be SystemVerilog Wizards L

ƒ Verification can peek inside a design scope using hierarchy paths ƒ Hierarchy paths reference objects where there are declared ƒ But…package items are not declared within the design scope package chip_types; typedef enum {RESET, WAITE, LOAD, READY} states_t; endpackage module chip (...); module test (...); import chip_types::*; chip dut (...); always @(posedge clk, negedge rstN) ... Gotcha! if (!resetN) state <= RESET; master_reset = 1; ... ##1 assert (dut.state == dut.RESET);

ModuleModule chipchip cancan useuse RESETRESET,, butbut RESETRESET isis notnot defineddefined inin chipchip ƒ To avoid this Gotcha… ƒ The package must also be imported into test bench, OR… ƒ Package items can be referenced with a “scope resolution operator” ##1 assert (dut.state == chip_types::RESET); 13 of 20 Don Mills, Microchip Gotcha: Operation Stu Sutherland Sutherland training engineers H Size and Sign Extension DL Answer:to be SystemVerilog -2 ! Wizards ƒ There are two types of operators in Verilog and SystemVerilog ƒ Self-determined operators do not modify their operand(s) logic [1:0] a; Logical-ANDLogical-AND isis self-determinedself-determined(the (the operationoperation onon aa logic [3:0] b; doesdoes notnot dependdepend onon thethe sizesize oror signednesssignedness of of enaena oror bb;; ena = a && b; thethe operationoperation onon bb doesdoes notnot dependdepend onon enaena oror aa)) ƒ Context-determined operators modify all operands to have the same size, using zero-extension or sign-extension ƒ But,… the context for size and sign are different!

logic signed [3:0] a; ADDADD isis context-determinedcontext-determined(the (the operationoperation dependsdepends onon logic signed [4:0] c; thethe sizesize ofof aa,, cc andand 1’b11’b1)) andand signednesssignedness of of aa andand 1’b11’b1)) a = -1; c = a + 1’b1; Gotcha! What is -1 + 1? Answer A: -1 + 1’b1 = -16 ! Answer B: -1 + 1’sb1 = -2 ! ƒ To avoid this Gotcha… Answer C: -1 + 2’sb01 = 0 ! ƒ You have got to know if an operator is self-determined or context-

determined — See the table in this paper! 14 of 20 Don Mills, Microchip Explanation of Operation Size Stu Sutherland Sutherland and Sign Extension Example training engineers HD to be SystemVerilog Wizards L

ƒ Context-determined operators modify all operands to have the same size, using zero-extension or sign-extension ƒ But,… the context for size and sign are different! ƒ The context for size is both the right and left-hand side of an assignment ƒ The context for signedness is just the right-hand side of an assignment

logic signed [3:0] a = -1; logic signed [4:0] c;

Why is “c=a+1’b1” = -16? ƒƒSizeSize contextcontext isis5-bits 5-bits(largest (largest expressionexpression sizesize isis cc)) ƒƒSignSign contextcontext isisunsigned unsigned( (1’b11’b1 isis anan unsignedunsigned expression)expression) aa isis 11111111 ((-1-1)which)which extendsextends toto0011111111 (( 1515)) 1’b11’b1 isis 11 (( 11)which)which extendsextends toto0000000011 (( 11)) cc= =10000 10000 ((-16-16))

Why is “c=a+1’sb1” = -2? ƒƒSizeSize contextcontext isis5-bits 5-bits(largest (largest expressionexpression sizesize isis cc)) ƒƒSignSign contextcontext isissigned signed( (aa andand 1’sb11’sb1 areare signedsigned expressions)expressions) aa isis 11111111 ((-1-1)which)which extendsextends toto1111111111 ((-1-1)) 1’b11’b1 isis 11 (( 11)which)which extendsextends toto1111111111 ((-1-1)) c = 11110 (-2) c = 11110 (-2) 15 of 20 Don Mills, Microchip Stu Sutherland Gotcha: Signed Arithmetic Sutherland training engineers HD to be SystemVerilog Wizards L

ƒ Math operations are context-determined ƒ Signed arithmetic is done if all operands are signed ƒ But,… If any operand in the context is unsigned, then unsigned arithmetic is done UnsiUnsignedgned adderadder,, eveneven thoughthough aa,, bb andand sumsum areare signedsigned logic signed [3:0] a, b; ƒ Size context is largest vector on left and right sides logic ci; ƒ a, b and ci are extended to 5 bits before being added logic signed [4:0] sum; ƒ Sign context is only the operands on right side sum = a + b + ci; ƒ Gotcha! ci is unsigned, so the context is unsigned ƒ a and b are converted to unsigned and zero extended

logic signed [3:0] a, b; SignedSigned adderadderthat that subtractssubtracts carrycarry inin logic signed ci; ƒ a, b and ci are signed, so the context is signed logic signed [4:0] sum; ƒ if ci is 1, sign extending to 5 bits gives 11111 (binary) sum = a + b + ci; ƒ As a signed value, 11111 (binary) is -1! Gotcha! ƒ To avoid this Gotcha… ƒ Engineers must know Verilog’s context-operation rules! sum = a + b + signed’({1’b0,ci}); 16 of 20 Don Mills, Microchip Gotcha: Stu Sutherland Sutherland Operations in Sensitivity Lists training engineers HD to be SystemVerilog Wizards L

ƒ Verilog sensitivity lists can contain operations ƒ But,… the list is only sensitive to changes in the operation result

IfIf aa isis 11,, andand bb changeschanges always @(a or b) ““or”or” isis aa separator,separator, notnot anan operation;operation; fromfrom 00to to 11,, thethe blockblock sum = a + b; SensitiveSensitive toto changeschanges onon aa oror bb willwill triggertrigger

Gotcha! “||” is the logical-OR operator; If a is 1, and b changes always @(a || b) “||” is the logical-OR operator; If a is 1, and b changes Sensitive to changes on the result of from 0 to 1, the block sum = a + b; Sensitive to changes on the result of from 0 to 1, the block thethe testtest “is“is aa true,true, OROR isis bb true”true” willwill notnot triggertrigger

ƒ To avoid this Gotcha… ƒ For combinational logic, use always @* or always_comb to infer a correct combinational logic ƒ For sequential logic, using a comma instead of “or” to separate items in the sensitivity list 17 of 20 Don Mills, Microchip Gotcha: Stu Sutherland Sutherland Assignments in Expressions training engineers HD to be SystemVerilog Wizards L

ƒ Is the classic C gotcha also a gotcha in SystemVerilog?

always @(state) if (state = LOAD) Legal or Illegal? ... ƒ SystemVerilog allows assignments in expressions… ƒ But,… the syntax is different than C — the assign statement must be enclosed in parentheses TheThe differentdifferent syntaxsyntax helpshelps preventprevent thethe always @(state) gotchagotcha ofof usingusing ==where where ====is is intended,intended, but…but… if ( (state = LOAD) ) ... The different syntax is confusing to C/C++ Gotcha! programmers when an assignment is intended

ƒ To avoid this Gotcha… ƒ “It is what it is” — Engineers need to learn the unique SystemVerilog syntax 18 of 20 Don Mills, Microchip Stu Sutherland Summary Sutherland training engineers HD to be SystemVerilog Wizards L

ƒ Programming languages have gotchas ƒ A legal construct used in a way that gives unexpected results ƒ Gotchas occur because useful language features can be abused ƒ Some gotchas are because Verilog and SystemVerilog allow engineers to prove what won’t work in hardware ƒ A gotcha in a hardware model can be disastrous ƒ Difficult to find and debug ƒ If not found before tape-out, can be very costly ƒ This paper describes 57 Verilog and SystemVerilog gotchas ƒ Detailed explanations of each gotcha ƒ Guidelines on how to avoid each gotcha ƒ Lots of code examples

19 of 20 Don Mills, Microchip Stu Sutherland Questions & Answers… Sutherland training engineers HD to be SystemVerilog Wizards L

Do you have a favorite gotcha that is not in the paper?

Please send it to Stu or Don! And then stay tuned for a “Standard Gotchas, Part 2” paper at some future SNUG...

[email protected] [email protected]

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