Suppressing Voltage Spikes of MOSFET in H-Bridge Inverter Circuit

Article Suppressing Voltage Spikes of MOSFET in H-Bridge Inverter Circuit

Ezzidin Hassan Aboadla 1,2,* , Sheroz Khan 3,*, Kushsairy Abdul Kadir 1,* , Zulkhairi Md Yusof 1, Mohamed Hadi Habaebi 4, Shabana Habib 5, Muhammad Islam 3 , Mohammad Kamrul Hasan 6 and Eklas Hossain 7

1 Electrical Technology Section, British Malaysian Institute, University Kuala Lumpur, Batu 53100, Malaysia; [email protected] 2 Electrical and Electronics Department, Higher Institute of Science and Technology, Al-Zahra 47760, Libya 3 Department of Electrical and Renewable Energy Engineering, College of Engineering and Information Technology, Unaizah Colleges, Al-Qassim 51911, Saudi Arabia; [email protected] 4 Electrical and Computer Engineering Department, International Islamic University Malaysia, Jalan Gombak 53100, Malaysia; [email protected] 5 Department of Information Technology, College of Computer, Qassim University, Buraydah 51452, Saudi Arabia; [email protected] 6 Center for Cyber Security, Universiti Kebangsaan Malaysia, Bangi 43600, Malaysia; [email protected] 7 Oregon Renewable Energy Center (OREC), Department of Electrical Engineering & Renewable Energy, Oregon Institute of Technology, Klamath Falls, OR 97601, USA; [email protected] * Correspondence: [email protected] or [email protected] (E.H.A.); [email protected] (S.K.); [email protected] (K.A.K.)

Abstract: Power electronics devices are made from semiconductor switches such as thyristors, MOS- FETs, and diodes, along with passive elements of inductors, capacitors, and resistors, and integrated circuits. They are heavily used in power processing for applications in computing, communication, Citation: Aboadla, E.H.; Khan, S.; medical electronics, appliance control, and as converters in high power DC and AC transmission Abdul Kadir, K.; Md Yusof, Z.; in what is now called harmonized AC/DC networks. A converter’s operation is described as a Habaebi, M.H.; Habib, S.; Islam, M.; periodic sequencing of different modes of operation corresponding to different topologies interfaced Hasan, M.K.; Hossain, E. Suppressing to filters made of passive elements. The performance of converters has improved considerably using Voltage Spikes of MOSFET in high switching frequency, which leads to a significant improvement in a power converter’s perfor- H-Bridge Inverter Circuit. Electronics 2021, 10, 390. https://doi.org/ mance. However, the high dv/dt through a fast-switching transient of the MOSFET is associated 10.3390/electronics10040390 with parasitic components generating oscillations and voltage spikes having adverse effects on the operation of complementary switches, thereby affecting the safe operation of the power devices. Academic Editor: Francisco Gordillo In this paper, the MOSFET gate-driver circuit performance is improved to suppress the H-Bridge Received: 6 January 2021 inverter’s voltage spikes. The proposed technique is a simple improvement to the gate driver based Accepted: 1 February 2021 on the IR2112 driver (IC) by adding a capacitor to attenuate the effect of parasitic components and Published: 5 February 2021 the freewheeling current, suppressing the negative voltage spikes. This paper’s main contribution is to improve the gate driver circuit’s capability for suppressing the voltage spikes in the H-Bridge Publisher’s Note: MDPI stays neutral inverter. The improved gate driver circuit is validated experimentally and is compared with the with regard to jurisdictional claims in conventional gate driver. The experimental results show that the proposed technique can effectively published maps and institutional affil- suppress the MOSFET’s voltage spikes and oscillations. iations.

Keywords: H-Bridge inverter; voltage spikes; power switches; gate driving circuit

Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland. 1. Introduction This article is an open access article Producing high-quality output waveforms from Multilevel Inverter (MLI) has been distributed under the terms and conditions of the Creative Commons challenging for researchers working in the area. The high-quality output results from Attribution (CC BY) license (https:// reduced switching losses in the power semiconductors and for improving output wave- creativecommons.org/licenses/by/ form [1–4]. With the rapid development of the power transistor industry, fast switching 4.0/).

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frequency speed has greatly increased. Although higher switching frequency guaran- tees quality output, it increases switching losses. However, by applying high switching speed, the parasitic parameters such as parasitic capacitance and inductance with the PCB traces become crucial factors that mainly affect the power transistors’ performance. Therefore, it is important to analyze these parasitic components’ effect and calculate the loss of the MOSFET accurately. One has to engage in a tradeoff between the two situations when it comes to implementing power converters. On the other hand, H-Bridge inverters have suffered from voltage spikes in their output signals. These spikes have undesirable effects such as phonetic noise and harmonic heating losses, semiconductors switching power losses, and mechanical vibrations [5,6]. On the other hand, the parasitic inductance can boost the voltage overshoot, leading to total harmonic distortion. It is important to eliminate the parasitic resonance to improve the H-Bridge converter’s performance and mitigate the effect of the total harmonic distortion [7]. A root locus technique has been used with an RC snubber circuit design in Reference [8] for a double pulse circuit of the SiC MOSFET by ignoring the parasitic inductance source. Simultaneous switching of these devices can generate a high voltage spike and high dv/dt at the inverters’ output terminal. This high voltage spike may easily damage the power switches. In practical operation of H-Bridge converter during ON/OFF transient of one MOSFET under fast switching conditions will produce voltage spikes on its complementary MOSFET [9–14]. Several techniques have been used to suppress the effect of voltage spikes [15,16]. Reference [17] proposed controlled gate resistance to mitigate the voltage spikes. However, it needs to use feedback control, which leads to a relative time delay. A level shift circuit is proposed in Reference [18] to produce a negative gate voltage to suppress the positive gate spikes; however, this negative gate voltage considers a risk to damage the MOSFET. In [19–23], Snubber circuits have been utilized with semiconductor devices to absorb the high dv/dt energy and reduce harmonic spikes. The voltage spikes will increase due to the reverse load current by increasing the load current [24]. Developing a gate driver of SiC MOSFET will eliminate the gate-source voltage spike. A series of capacitors have been connected to the gate of a MOSFET transistor by an auxiliary transistor to absorb the negative voltage spike when the complementary power transistor is turned off [25]. In [26], a new active driver circuit is proposed for the MOSFET transistor to absorb the effect of turn-off spikes and oscillation. Another technique is proposed to reduce positive voltage spikes by using an auxiliary transistor for controlling JFET. However, this technique cannot mitigate negative voltage spikes [27]. The soft gate technique and active driver-controlled circuit are presented in Reference [28]. A novel technique for the driver gate controller to suppress the negative voltage spikes is introduced in Reference [29]. In the turn off state and due to the voltage rising across the MOSFET, charging current stream via its parasitic capacitance leads to inducing positive voltage spikes at the gate. If the voltage of these spikes overrun gate threshold voltage, the high side of the MOSFET could be falsely triggering. The gate impedance monitoring method has been used to decrease the gate voltage spikes in order to provide a low impedance path by added external gate-source capacitance [30,31] This paper presents a new design to suppress the voltage spikes by improving the MOSFET gate driver circuit in the H-Bridge circuit based on the integrated circuit IR2112. The performance of the proposed technique has been evaluated experimentally.

2. H-Bridge Inverter The H-Bridge inverter is the most common inverter used to convert DC to AC, as shown in Figure1. Two power switches in a complementary manner are used in each leg of the H-Bridge circuit, which can be controlled (ON/OFF) using modulation signals such as Sinusoidal Pulse Width Modulation (SPWM) or Selective Harmonic Elim- ination (SHE) technique [32,33]. Each H-Bridge topology unit can generate three-level output voltages, +Vdc, 0, and −Vdc. ElectronicsElectronics 20212021, 10, 10, x, 390FOR PEER REVIEW 3 of 16 3 of 17 Electronics 2021, 10, x FOR PEER REVIEW 3 of 17

Figure 1. MOSFET based H-bridge dc-ac inverter. FigureFigure 1.1. MOSFETMOSFET based based H-Bridge H-bridge dc-ac dc-ac inverter. inverter. 3. Proposed Technique 3. Proposed Technique 3. ProposedIn power Technique switching applications, switching losses at most are dependent on switch- In power switching applications, switching losses at most are dependent on switching ing speed.In power Thus, switching the switching applications, characteristic switching is the lossesmost important at most are in thedependent high-power on switch- speed.switching Thus, application. the switching In addition, characteristic a voltage is the mostspike important is a very insignificant the high-power issue that switching affects ingapplication. speed. Thus, In addition, the switching a voltage spikecharacteristic is a very signiﬁcant is the most issue important that affects in the the perfor- high-power the performance of the power inverter adversely, and it is presented and addressed in this switchingmance of the application. power inverter In addition, adversely, a andvoltage it is presentedspike is a andvery addressed significant in thisissue paper that affects paper using the proposed approach to design and improved high-performance gate drive using the proposed approach to design and improved high-performance gate drive circuits thecircuits performance based on ofthe the gate power driver inverter IR2112 adversely,for high-efficiency and it is and presented high-power, and addressedswitching in this based on the gate driver IR2112 for high-efﬁciency and high-power, switching applications paperapplications using usingthe proposed a power MOSFETapproach and to IGBT.design and improved high-performance gate drive circuitsusing a powerbased MOSFETon the gate and IGBT.driver IR2112 for high-efficiency and high-power, switching applicationsOperating PrinciplePrinciple using a power MOSFET and IGBT. Figure2 2shows shows the the circuit circuit diagram diagram of the of half-bridgethe half-bridge circuit circuit with driver with IR2112,driver IR2112, which Operatingdriveswhich thedrives Principle power the power transistors. transistors. This integrated This integrated circuit circuit has a high-performancehas a high-performance and high and voltagehigh Figurevoltage driver 2driver forshows power for thepower switches circuit switches with diagram with two independenttwo of independentthe half-bridge channels channels forcircuit high for withhigh side andsidedriver lowand IR2112, low side output. By adding an external bootstrap capacitor (CBOOT) and bootstrap diode whichside output. drives Bythe adding power an transistors. external bootstrap This integrated capacitor circuit (CBOOT has) and a bootstraphigh-performance diode and (DBOOT), the driver provides a high switching speed [34]. The High Side Floating Voltage high(DBOOT voltage), the driver driver provides for power a high switches switching with speed two [ 34independent]. The High Sidechannels Floating for Voltage high side and (VS)(VS) ofof thethe IR2112IR2112 driverdriver isis already connectedconnected toto thethe outputoutput viavia thethe upperupper transistortransistor sourcesource low side output. By adding an external bootstrap capacitor (CBOOT) and bootstrap diode (Q1).(Q1). When When the the low low side side channel channel (LO) (LO) is isturn turneded ON, ON, the the lower lower MOSFET MOSFET (Q2) (Q2) will willbe ON, be (DBOOT), the driver provides a high switching speed [34]. The High Side Floating Voltage ON,and the and high the side high (HO) side turned (HO) turned OFF, the OFF, upper the MOSFET upper MOSFET (Q1) will (Q1) be OFF. will beIn this OFF. case, In this the (VS) of the IR2112 driver is already connected to the output via the upper transistor source case,VS pin the will VS get pin connected will get connected to the grou tond the via ground a lower via transistor a lower transistor (Q2). The (Q2). CBOOT The capacitor CBOOT (Q1). When the low side channel (LO) is turned ON, the lower MOSFET (Q2) will be ON, capacitorstarts charging starts chargingup via the up D viaBOOT the from DBOOT thefrom VCC the source, VCC source, as shown as shown in Figure in Figure 3. [35].3.[ The35]. andThehighest highestthe voltagehigh voltage side charges (HO) charges from turned from CBOOT OFF, C areBOOT dependenttheare upper dependent on MOSFET the onvoltage the (Q1) voltage value will of valuebe the OFF. VCC of theIn source. this VCC case, the VSsource.The pin equivalent Thewill equivalentget schematic connected schematic of theto the MOSFET of grou the MOSFETnd parasitic via a parasitic lowercomponents transistor components in a half-bridge (Q2). in aThe half-bridge circuitCBOOT capacitoris startscircuitshown charging isin shown Figure in 4.up Figure via 4the. DBOOT from the VCC source, as shown in Figure 3. [35]. The highest voltage charges from CBOOT are dependent on the voltage value of the VCC source. The equivalent schematic of the MOSFET parasitic components in a half-bridge circuit is shown in Figure 4.

Figure 2.2. Conventional half-bridge inverters withwith thethe IR2112IR2112 driverdriver circuit.circuit.

Figure 2. Conventional half-bridge inverters with the IR2112 driver circuit.

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IR2112

LOAD LOAD

FigureFigure 3. 3.3. Bootstrap Bootstrap power powerpower supply-circuit supply-circuit supply-circuit for afor half-bridge for a half-bridge a half-bridge inverter. inverter. inverter.

Figure 4. Equivalent circuit of the MOSFET based half-bridge dc-ac inverter with the parasitic components.Figure 4. Equivalent circuit of the MOSFET based half-bridge dc-ac inverter with the parasitic Figure 4. Equivalent circuit of the MOSFET based half-bridge dc-ac inverter with the parasitic components. components.This circuit's biggest issue is the negative voltage spike existent at the switching de- vice Thissource circuit’s during biggest the OFF issue state is the that negative causes voltageload current spike existentflow suddenly at the switching in the low-side freewheelingdeviceThis source circuit'sduring diode. biggest the This OFF negative issue state that is spike the causes negative can load defe currentct voltage the ﬂow gate spike suddenly driver’s existent inoutput the low-side at because the switching it di- de- freewheeling diode. This negative spike can defect the gate driver’s output because it vicerectly source affects during the source the OFFVS pin state of the that driver causes or PWMload currentcontrol ICflow and suddenly might pull in some the low-sideof directly affects the source VS pin of the driver or PWM control IC and might pull some of freewheelingthethe internal circuitry circuitry diode. signiﬁcantly significantlyThis negative below below spike ground, grou can asnd, showndefe as shownct in the Figure ingate Figure5. Thedriver’s other5. The problemoutput other problem because it di- rectlycausedcaused affects byby the the negativethe negative source voltage voltag VS transient pine transient of isthe developing driver is developing or an PWM over-voltage an control over-voltage condition IC and acrosscondition might the pull across some of thethebootstrap internal bootstrap capacitor. circuitry capacitor. Given significantly Given the fast-rising the belowfast-rising drain-source grou drain-sourcend, voltage, as shown the voltage, parasitic in Figure the capacitances parasitic5. The other capaci- problem causedtances ofby a theMOSFET negative cause voltag a negativee transient voltage is spike developing during switching an over-voltage transitions condition and may across theresult bootstrap in spurious capacitor. turn-on Given if it exceeds the fast-rising the threshold drain-source voltage. When voltage, the upperthe parasitic MOSFET capaci- turns ON, the current flow between the drain and source leads to induce the parasitic tances of a MOSFET cause a negative voltage spike during switching transitions and may capacitor Cdg in the lower MOSFET, and it will motivate the gate-source capacitor Cgs to result in spurious turn-on if it exceeds the threshold voltage. When the upper MOSFET charge up. Therefore, it will push up the lower MOSFET's gate voltage and generate a turns ON, the current flow between the drain and source leads to induce the parasitic capacitor Cdg in the lower MOSFET, and it will motivate the gate-source capacitor Cgs to charge up. Therefore, it will push up the lower MOSFET's gate voltage and generate a

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Electronics 2021, 10, x FOR PEER REVIEW 5 of 17 of a MOSFET cause a negative voltage spike during switching transitions and may result in spurious turn-on if it exceeds the threshold voltage. When the upper MOSFET turns ON, the current ﬂow between the drain and source leads to induce the parasitic capacitor Cdg in the lower MOSFET, and it will motivate the gate-source capacitor Cgs to charge Electronics 2021, 10, x FOR PEERpositive REVIEW pseudo pulse. On the other side, when the lower MOSFET is5 ofturned 17 ON, and the up. Therefore, it will push up the lower MOSFET’s gate voltage and generate a positive upperpseudo switch pulse. On is the turned other side, OFF, when a negative the lower MOSFETpseudo is voltage turned ON, will and generate the upper between the lower MOSFETswitch is turned gate OFF, and a negativesource, pseudo as shown voltage in will Figure generate 6 [36]. between the lower MOSFET gatepositive and source, pseudo as shownpulse. inOn Figure the other6[36 ].side, when the lower MOSFET is turned ON, and the upper switch is turned OFF, a negative pseudo voltage will generate between the lower MOSFET gate and source, as shown in Figure 6 [36].

Figure 5. VS signal and negative spike at turn off condition. Figure 5. VS signal and negative spike at turn off condition. Figure 5. VS signal and negative spike at turn off condition.

Upper MOSFET

ON Upper MOSFET

Lower MOSFET

OFF

Lower MOSFET

OFF (a)

Figure 6. Cont.

(a)

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UpperUpper MOSFET MOSFET

OFFOFF

LowerLower MOSFET MOSFET

ONON

(b) (b) FigureFigure 6. (a 6.) Turned (a) Turned ON ON state state of thethe of upperupperthe upper MOSFET.MOSFET. MOSFET. ((bb)) Turned Turned(b) Turned OFFOFF OFF statestate state ofof thethe of upper upperthe upper MOSFET. MOSFET. MOSFET.

WhenWhen the thepower power source source Vcc Vcc of the of the driver driver is referenced is referenced to the to the ground, ground, the the maximummaximum maximum voltagevoltage that that can can build build on theon the CBoot CBoot capacitor capacitor is the is the sum sum of Vcc of Vcc and and the the amplitudeamplitude amplitude of the of the negativenegative voltage voltage at VS at pin.VS pin. Figure Figure 77 illustrates illustrates 7 illustrates thethe waveformsthewaveforms waveforms ofof thethe of high-sidethehigh-side high-side MOSFETMOSFET MOSFET duringduring thethe OFFtheOFF OFF state.state. state. TheThe negativeThe negative negative voltage voltage voltage spike’s spike's sp amplitudeike's amplitude amplitude is proportionalis proportional is proportional to theto the parasiticto thepara- para- siticinductancessitic inductances inductances and theand turn-offand the theturn-off speed,turn-off speed, di/dt. speed, di/dt. Sum di/dt. Sum of CgsSum of andCgs of Cgs Cgd,and and Cgd, called Cgd, called Miller called Miller capacitance. Miller capaci- capaci- Thetance.tance. biggest The The biggest problem biggest problem is problem when is the when is VS when goesthe theVS below goesVS goesground below below ground signiﬁcantly, ground significantly, significantly, and therefore, and and therefore, the therefore, gate thedrive thegate suffers gate drive drive damage. suffers suffers damage. damage.

FigureFigure 7. Voltage 7. Voltage spike spike during during turned turned OFF OFF state state ofof thethe of upperupperthe upper MOSFET.MOSFET. MOSFET.

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4. Proposed Proposed Design to Suppress Voltage Spikes The proposed design is usedused toto reducereduce dv/dtdv/dt at the power switches’switches' transition and suppress the voltage spikes from the output voltagevoltage signal. The gate driver circuit is based on the integrated circuit IR2112.IR2112. The driver connects to thethe H-BridgeH-Bridge inverter’sinverter's power transistor viavia threethree terminals:terminals: Ho_ Ho_ gate gate signal signal of of the the upper upper transistor, transistor, Lo_ Lo_ gate gate signal signal of the of thelower lower transistor, transistor, and and VS feedbackVS feedback signal signal between between the sourcethe source of the of topthe top transistor transistor and and the thedrain drain of the of the lower lower transistor. transistor. When the upper MOSFET is turned OFF and the lower MOSFET is turned ON, the VS pin connection will be connected to the gr groundound via a lower transistor. Therefore, most of the load current (freewheel current) will ﬂowflow suddenlysuddenly throughthrough thethe lowerlower MOSFET’sMOSFET's internal diode. diode. Hence, Hence, a a negative negative voltage voltage spike spike will will appear appear at VS-pin, as shown in Figure 88.. This negative spike will develop across the CBOOT CBOOT capacitor, capacitor, reaching maximum ampli- ampli- tude as the sum of VCC source and the negative spike’sspike's amplitude. At the same time, part of the load load current current will will flow ﬂow through through the parasitic parasitic gate-source capacitance Cgs of the lower transistor Q2, which leads to charge the capacitorcapacitor Cgs. In this case, the gate voltage will push up and generate another harmful gate-sourcegate-source spurious voltage pulse.pulse. The voltage spikes issue has occurred during the transienttransient process of the complementary switches of the H-Bridge inverter. The voltage spikes’spikes' value depends on the source voltage and ON time of the duty cycle.

CBOOT

N. spike

Figure 8. Load current direction and negative spike at the turn off condition.

To give the mathematical modeling of the voltage spikes and oscillation oscillation conditions, conditions, the turn off process of the MOSFET has beenbeen analyzed dependingdepending onon FigureFigure9 9.. AnAn idealideal MOSFET transistortransistor consists consists of of a gate-draina gate-drain capacitance capacitance (Cgd), (Cgd), drain-source drain-source capacitance capacitance (Cds), (Cds),gate-source gate-source capacitance capacitance (Cgs), (Cgs), and internal and inte diodernal diode with with the parasitic the parasitic inductance inductance (LD ,(LD,LS). LS)However,. However, Rg is Rg the isgate the gate driver driver resistance. resistance During. During turn-off turn-off condition condition of the of MOSFET,the MOSFET, Cgs Cgscapacitance capacitance starts starts discharge discharge via Rg via resistance, Rg resist leadingance, leading to decreased to decreased gate-source gate-source voltage volt- Vgs. age Vgs.

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Cdg

Rg Cds G Cgs

S FigureFigure 9. 9.Equivalent Equivalent circuit circuit of the of MOSFET the MOSFET transistor. transistor.

Therefore, the pseudo-gate-source voltage of the MOSFET can be based on Reference [25]: Therefore, the pseudo-gate-source voltage of the MOSFET can be based on Reference dVC [25]: i = C gs (1) Cgs gs dt = (1) dVCdg iC = Cdg (2) dg dt = + = (2) Vs VCgs VCdg (3)

where: Cgs, Cdg, Cds MOSFET parasitic capaciyance; VC is the maximum charge value of =gs + (3) the Cgs capacitor, and VCdg is the maximum charge value of the Cds capacitor. where: ,, ; is the maximum charge value V V = s (4) of the capacitor, and Cgs (max is the) maximum charge value of the capacitor. 1 + Cgs/Cdg

While the drain current id starts falling, the load() current= moves out to the freewheeling (4) / diode (FWD), as illustrated in Equations (5) and (6). Additional to the voltage spikes, the drain currentWhile idthe composes drain current oscillation id duestarts to thefalling, parasitic the components load current of themoves MOSFET out into the freewheel- theing power diode loop (FWD), at turn-off as illustrated operation [26 in]. Equations (5) and (6). Additional to the voltage spikes, the drain current id composesid oscillation= gm Vgs − Vdueth to the parasitic components(5) of the MOSFET in the power loop at turn-off operation [26]. did dVgs = gm (6) dt =dt − (5) where: id is the drain current; gm is the transconductance. These issues of voltage spikes will affect the MOSFET= through their gate signals. (6) The spikes’ entrance into the circuit may lead to the failure of the switches and damage towhere: the IC driver. is the Besides, drain these current; spikes will is show the uptransconductance. on the output voltage waveform of the inverter.These Theyissues may of createvoltage more spikes problems will toaffect the loadthe MOSFET in the form through of electromagnet their gate signals. The interferencespikes' entrance and harmonic-related into the circuit heating may effects. lead to the failure of the switches and damage to the To tackle the issue of a negative voltage spike, a new capacitor CA is added to the driverIC driver. IR2112 Besides, between VS-pinthese andspikes the groundwill show to absorb up on these the spikes output effectively, voltage asshown waveform of the in- inverter. Figure They 10. This may capacitor’s create more main problems objective is to suppressthe load thein negativethe form voltage of electromagnet spike, interfer- ence and harmonic-related heating effects. To tackle the issue of a negative voltage spike, a new capacitor CA is added to the driver IR2112 between VS-pin and the ground to absorb these spikes effectively, as shown in Figure 10. This capacitor's main objective is to suppress the negative voltage spike, which appears at VS pin of IR2112, to improve the output voltage signal's quality and reduce voltage spikes.

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which appears at VS pin of IR2112, to improve the output voltage signal’s quality and reduce voltage spikes.

FigureFigure 10.10. ProposedProposed designdesign toto removeremove thethe voltagevoltage spikes.spikes. Figure 10. Proposed design to remove the voltage spikes. ThisThis capacitorcapacitor CACA providesprovides aa lowlow impedanceimpedance looploop toto thethe reversereverse loadload currentcurrent duringduring thetheThis transienttransient capacitor conditioncondition CA provides ofof thethe uppera low impedance transistor, leadingleadingloop to the toto suppressingsuppressing reverse load thethe current voltagevoltage during spikes.spikes. theAtAt transient OFFOFF statestate condition (when(when Q1 Q1of istheis OFF),OFF), upper VSVS transistor pinpin isis connectedconnected, leading to toto thethe suppressing groundground viavia the Q2.Q2. voltage However,However, spikes. atat thethe At ONOFFON state statestate (Q1 (Q1(when is is ON), ON)Q1 is the, theOFF), voltage voltage VS ofpin o VS fis VS equalsconne equalscted the the DCto theDC source’s ground source's voltage, via voltag Q2. and However,e, theand voltage-time the atvoltage the - ONoftime state this of point(Q1 this is depends pointON), the depends onvoltage the duty on of theVS cycle dutyequals of PWM.cycle the DC of The PWM.source's equivalent The voltage, equivalent circuit and of the the circuit voltageproposed of the timeschemeproposed of this at point thescheme turn depends at off the state turnon isthe off shown duty state incycl isFigure showne of PWM. 11 in. Therefore,Figure The equivalent11. Therefore, the new circuit capacitor the newof the CA capacitor pro- value posedcanCA scheme bevalue calculated can at bethe calculated dependingturn off state dep on isending the shown DC on voltage in the Figure DC source voltage 11. Therefore, and source ton of andthe the newton duty of capacitor cycle.the duty CA cycle. value can be calculated depending on the DC voltage source and ton of the duty cycle.

VS id D VS id D LD LD

CA CA Cds Cds

LS LS

S S FigureFigure 11.11. TheThe equivalentequivalent circuitcircuit ofof thethe proposedproposed capacitorcapacitor withwith thethe MOSFETMOSFET parasiticparasitic parameters.parameters. Figure 11. The equivalent circuit of the proposed capacitor with the MOSFET parasitic parameters. AccordingAccording toto Kirchhoff’sKirchhoff’s voltagevoltage lawlaw (KVL)(KVL) gives:gives: According to Kirchhoff’s voltage law (KVL) gives: 푉 + 푉 + 푉 = 푉 (7) VLD 퐿퐷+ VLS퐿푆+ VCds퐶푑푠= VS푆 (7) 푑𝑖+ +푑𝑖 1= (7) 퐿퐷 + 퐿푆 + Z ∫ 푖푑푡 = 푉푆 (8) di 푑푡 di 푑푡 1 퐶푑푠 LD ++LS ++ idt = = V S (8)(8) dt dt 푑𝑖Cds1 (퐿퐷 + 퐿푆) + ∫ 푖푑푡 = 푉푆 (9) di 푑푡 1 퐶푑푠Z ( + ) + = (9) (LD + LS) + idt = VS (9) Applying a Laplace transform anddt solvingCds the differential equation, Applying a Laplace transform and solving the 1differential equation, 푆(퐿퐷 + 퐿푆)퐼(푆) + 퐼(푆) = 푉푆(푆) (10) 푆퐶푑푠 ( + )() + () = () (10)

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[( + ) +1]()=() (11) Electronics 2021, 10, 390 = 10 of(12) 16

= , = (13) where:Applying a Laplace transform and solving the differential equation, t1 and t2 is the ON time at the period time of PWM; LD MOSFET Internal Drain Induct- 1 ance; S(LD + LS)I(S) + I(S) = VS(S) (10) SCds LS is the Internal Source Inductance; CA is the external capacitor; VS is the voltage at VS pin. 2 S [(LD + LS)Cds + 1]I(S) = VS(S) (11) Z ,1= (14) VS = ∗idt (12) CA where: fs is the switching frequency. 1 Z t2 C = idt, t = t (13) A V on 5. Experimental Verification S t1 where:The proposed gate driver circuit was implemented and tested for the H-Bridge in- tverter,1 and t 2whereis the ONthe inductive time at the load period was time utilized of PWM; to verifyLD MOSFET the proposed Internal design's Drain effectiveness Inductance; LSforis the the suppression Internal Source of the Inductance; voltage spikeCA is and the externaloscillation, capacitor; as shown VS isin the Figure voltage 12. atIn VSthe pin. experimental prototype, MOSFET IRF640 and IC driver IR2112 were used. An Arduino Uno α board was used to generate PWM. Thet experime= 1 ntal parameters of the design circuit(14) are 1,2 f ∗ listed in Table 1. s 360 where: fs is the switching frequency. Table 1. The experimental parameters. 5. Experimental Veriﬁcation Parameter Value The proposed gate driver circuit was implemented and tested for the H-Bridge inverter, where the inductive loadDC was voltage utilized to verify the proposed design’s effectiveness12 V for the suppression of the voltageSwitching spike frequency and oscillation, as shown in Figure 50 12Hz. In& the10 kHz experimental prototype, MOSFET IRF640Load inductance and IC driver IR2112 were used. An Arduino 100 µH Uno board was used to generate PWM.Load The Resistance experimental parameters of the design 100 circuit Ω are listed in Table1. Gate resistor R 10 Ω

FigureFigure 12.12.The The hardwarehardware setupsetup ofof aa proposedproposed H-Bridge H-Bridge inverter inverter circuit. circuit.

6. Experimental Results Table 1. The experimental parameters. A 50 Hz and 10 kHz switching frequency was used to operate the inverter circuit to address the effectParameter of negative voltage spikes and the oscillation Value of the H-bridge inverter of renewable energyDC voltage application. 12 V Switching frequency 50 Hz & 10 kHz 6.1. 50 Hz SwitchingLoad inductance Results 100 µH Load Resistance 100 Ω Gate resistor R 10 Ω

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6. Experimental Results A 50 Hz and 10 kHz switching frequency was used to operate the inverter circuit to address the effect of negative voltage spikes and the oscillation of the H-Bridge inverter of Electronics 2021, 10, x FOR PEER REVIEWrenewable energy application. 11 of 17

Electronics 2021, 10, x FOR PEER REVIEW 11 of 17 6.1. 50 Hz Switching Results

FigureFigure 1313 showsshows thethe negativenegative spikespike atat VSVS pinpin inin aa conventionalconventional gate drive circuit be- before usingfore Figureusing theproposed the 13 proposedshows design. the design. negative It canIt can spike be be seen seen at VS that that pin thethe in voltage a conventional of of the the negative negative gate drive spike spike circuit at V-Spike at V-Spike be- isforeis 2.5 2.5 using V.V. the proposed design. It can be seen that the voltage of the negative spike at V-Spike is 2.5 V.

Figure 13. The voltage spike at VS pin for a conventional gate driver circuit, switching frequency Figure 13. The voltage spike at VS pin for a conventional gate driver circuit, switching frequency Figurefs = 50 13.Hz. The voltage spike at VS pin for a conventional gate driver circuit, switching frequency fsfs = 50 50 Hz. Hz. The gate-source voltage and the drain-source voltage signals for a conventional gate driveThe circuit gate-source gate-source and the voltageproposed voltage and and driver the the drain-source circuit drain-source are shown voltage voltage in signals Figures signals for 14 fora and conventional a conventional15. Comparing gategate drivethe results circuit of and and Figures the the proposed proposed14 and 15, driver driverafter circuitimproving circuit are are shown the shown driver in inFigures circuit, Figures 14 the and14 oscillation and 15. 15Comparing. Comparing and the thethevoltage results spike of of Figures Figuresamplitude 14 14 and andhave 15, 15 been after, after mitigated improving improving from the the 10.40 driver driver V circuit,to circuit,1.50 V.the theoscillation oscillation and andthe the voltagevoltage spike amplitude amplitude have have been been mitigated mitigated from from 10.40 10.40 V to V 1.50 to 1.50 V. V.

Figure 14. Gate-source and drain-source voltage of the conventional drive circuit for switching Figurefrequency 14. 14. Gate-source fsGate-source = 50 Hz. and and drain-source drain-source voltage voltage of the of conventional the conventional drive circuit drive for circuit switching for switching frequencyfrequency fs fs = = 50 50 Hz. Hz.

ElectronicsElectronicsElectronics2021 20212021, ,10, 1010,, 390, xx FORFOR PEERPEER REVIEWREVIEW 121212 of ofof 16 1717

FigureFigureFigure 15. 15.15. Gate-source Gate-sourceGate-source and andand drain-source drain-sourcedrain-source voltage voltagevoltage signal signalsignal after afterafter improved improvedimproved the thethe drive drivedrive circuit circuitcircuit or oror switching switch-switch- frequencyinging frequencyfrequency fs = 50fsfs = Hz.= 5050 Hz.Hz.

6.2.6.2.6.2. 101010 KHzKHzKHz SwitchingSwitchingSwitching Frequency FrequencyFrequency ByByBy using using 1010 10 kHzkHz kHz asas as aa switchingswitching a switching frequencyfrequency frequency forfor thethe for H-bridgeH-bridge the H-Bridge DCDC toto ACAC DC inverter,inverter, to AC Figure inverter,Figure 1616 Figureshowsshows 16 thethe shows signalsignal the atat VS signalVS pinpin at duringduring VS pin OFFOFF during statestate OFF forfor conventionalconventional state for conventional gategate drive.drive. gate drive.

FigureFigureFigure 16. 16.16. The The voltagevoltage spikespike at at VS VS pin pin for for conventional conventional gategate driverdriver driver circuitcircuit circuit atat at switchingswitching switching frequencyfrequency frequency fsfs == 1010 kHz.kHz. fs = 10 kHz.

FigureFigureFigure 16 1616 shows showsshows that thatthat the thethe negative negativenegative voltage voltagevoltage spike spikespike at atat switching switchingswitching frequency frequencyfrequency 10 1010 kHz kHzkHz is isis less lessless thanthanthan when whenwhen the thethe switching switchingswitching frequency frequencyfrequency is isis 50 5050 HzHz withwith 2.222.22 VV and and 2.50 2.502.50 V, V,V, respectively.respectively. The The gate-gate- sourcesourcesource voltage voltagevoltage Vgs VgsVgs and andand drain-source drain-sourcedrain-source voltage voltagevoltage Vds VdsVds waveform waveformwaveform are areare shown shownshown in ininFigure FigureFigure 17 1717 under underunder switchingswitchingswitching frequency frequencyfrequency fs fsfs = == 101010 kHz.kHz.kHz. TheTheThe voltagevoltagevoltage spikespikespike isisis raised raisedraised to toto 13 1313 V VV with withwith high highhigh oscillation oscillationoscillation forforfor the thethe drain-source drain-sourcedrain-source voltage. voltage.voltage. By ByBy increasing increasingincreasing the thethe switching switchingswitching frequency, frequency,frequency, the voltagethethe voltagevoltage spikes spikesspikes and theandand overshoot thethe overshootovershoot oscillation oscillationoscillation are increased areare increasedincreased on drain-source onon drain-sourcedrain-source voltage Uds.voltagvoltag However,ee Uds.Uds. However,However, the negative thethe voltagenegativenegative spike voltagevoltage at VS spikespike pin atisat decreasedVSVS pinpin isis decreadecrea whensed thesed when switchingwhen thethe switchingswitching frequency frequencyfrequency increases. increases.increases.

Electronics 2021, 10, 390 13 of 16 Electronics 2021, 10, x FOR PEER REVIEW 13 of 17 Electronics 2021, 10, x FOR PEER REVIEW 13 of 17

FigureFigure 17. 17. Gate-source Gate-source and and drain-source drain-source drain-source voltage voltage voltage of of ofth the thee conventional conventional conventional drive drive drive circuit circuit circuit for for forswitching switching switching frequency fs = 10 kHz frequency fsfs == 10 kHz

TheThe experimentalexperimental prototypeprototype inin FigureFigure 10 10 has hahass been beenbeen utilized utilizedutilized to toto verify verifyverify the thethe proposed proposedproposed scheme’sscheme'sscheme's effect effecteffect for for the the the output output output voltage voltage voltage waveform waveform waveform of of the ofthe theH-Bridge H-Bridge H-Bridge inverter. inverter. inverter. Figure Figure Figure 18 18 illus- illus- 18 illustratestratestrates the the output theoutput output voltage voltage voltage waveform waveform waveform with with with the the conventional theconventional conventional gate gate gate driver driver driver circuit circuit circuit before before before im- im- improvingprovingproving the the the driver. driver. driver. The The The output output output vo voltageltage voltage signal signal signal is is affected affected is affected by by the the by positive thepositive positive and and negative andnegative negative volt- volt- voltageageage spikes, spikes, spikes, which which which lead lead lead to to more more to more issues issues issues for for power forpower power transistors transistors transistors and and and the the theload load load system. system. system.

10V/div10V/div

VoltageVoltage spikes spikes

Figure 18. Experimental result of using a conventional driver circuit for H-Bridge inverter. Figure 18. Experimental result of using a conventionalconventional driverdriver circuitcircuit forfor H-BridgeH-Bridge inverter.inverter.

OnOn thethe other otherother hand, hand,hand, the thethe proposed proposedproposed scheme’s scheme’sscheme’s performance performanceperformance for forfor mitigating mitigatingmitigating the thethe voltage voltagevoltage spikesspikes of of thethe the outputoutput output voltagevoltage voltage waveformwaveform waveform ofof of thethe the H-BridgeH-bridge H-bridge isis is presentedpresented presented inin in FigureFigure Figure 1919. 19.. InIn In thethe the proposedproposed design, design, bothboth both thethe the positivepositive positive andand and negativenegati negativeve voltagevoltage voltage spikesspikes spikes havehave have beenbeen been removedremoved removed fromfrom from thethe outputoutput output voltagevoltage voltage signalsignal signal toto to aa a considerablyconsiderably considerably goodgood good level.level. level.

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10V/div

Figure 19.19. The experimentalexperimental results results of of the the proposed proposed design design for for the the H-Bridge H-Bridge output output voltage voltage waveform. waveform. 7. Comparison of MOSFET Gate Driver Techniques for Suppressing Voltage Spikes 7. ComparisonA comparison of MOSFET with different Gate methodsDriver Techniques is presented for in Suppressing References [13 Voltage–17] to showSpikes the proposedA comparison scheme’s with advantage. different These methods techniques is presented can improve in References the performance [13–17] to show on some the sides.proposed However, scheme's they advantage. all have some These disadvantages techniques can in otherimprove aspects. the performance Table2 illustrates on some the comparisonsides. However, between they differentall have some techniques disadvan for thetages capability in other ofaspects. suppressing Table 2 voltage illustrates spikes. the Thiscomparison paper’s between proposed different method techniques has superior for characteristics the capability compared of suppressing to other voltage gate driversspikes. inThis terms paper's of the proposed voltage method spikes suppression has superior capability characteristics and the compared simplicity to inother design. gate drivers in terms of the voltage spikes suppression capability and the simplicity in design. Table 2. Comparison between different gate driver techniques. Table 2. Comparison between different gate driver techniques. Suppressing of Suppressing of Reference Proposed Technique Positive VoltageSuppressing Spike Negative of Suppressing Voltage Spike of A newReference gate drive based on adjustmentProposed ofTechnique Positive Voltage Negative Voltage [9] No Yes magnetic bead’s Spike Spike [18] RCD level-shifter for bridge-legA new configuration gate drive based on ad- Yes No [9] No Yes A passive triggered transistorjustment with aof series magnetic bead’s [25] Yes Yes capacitor to suppress the negativeRCD level-shifter voltage spikes for bridge-leg [18] Yes No Active Gate Driver for MOSFET toconfiguration Suppress [26] No Yes Turn-Off Spike and OscillationA passive triggered The proposed Improvement of gate drivertransistor circuit for with MOSFET a series capacitor Yes Yes [25] Yes Yes to suppress the negative voltage 8. Conclusions spikes Active Gate Driver for MOSFET A gate driver circuit for the H-Bridge inverter based on the integrated circuit IR2112 was proposed[26] to suppressto Suppress the Turn-Off voltage spikes. Spike and The proposedNo gate driver circuit’sYes performance and efficiency have beenOscillation validated and tested experimentally by leading IRF640 MOSFET on the H-BridgeImprovement DC-AC of invertergate driver at a cir- switching frequency of 50 Hz and 10 kHz. The proposed Yes Yes The design has been efficientcuit for in reducingMOSFET pins’ impact on the inverter circuit’s output; however, unavoidable parasitic components impacted its ability to demonstrate its effec- tiveness8. Conclusions in eliminating the voltage spikes. The findings of this research can be applied in renewableA gate electronics. driver circuit Moreover, for the H-Bridge such results inverter are suitablebased on for the running integrated the circuit solar source-IR2112 operatedwas proposed induction to suppress motors usedthe voltage in electric spikes. vehicles. The proposed gate driver circuit's performance and efficiency have been validated and tested experimentally by leading IRF640 MOSFET on the H-bridge DC-AC inverter at a switching frequency of 50 Hz and 10 kHz. The design has been efficient in reducing pins' impact on the inverter circuit's output;

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Author Contributions: Conceptualization, E.H.A. and S.K.; methodology, E.H.A. and S.K.; software, E.H.A., S.K., S.H., and M.I.; validation, E.H.A., S.K., K.A.K., and Z.M.Y.; formal analysis, E.H.A., K.A.K., Z.M.Y., S.K., S.H. and M.I.; investigation, E.H.A., S.K., and M.H.H.; writing—original draft preparation, E.H.A., S.K., and M.K.H.; writing—review and editing, E.H.A., S.K., M.I., S.H., M.K.H. and E.H.; supervision, S.K., K.A.K., Z.M.Y. and M.H.H.; funding acquisition, S.K., S.H., and M.I. All authors have read and agreed to the published version of the manuscript. Funding: This research publication has got no external or institutional funding. It is funded by Muhammad Islam, Shabana Habib, and Sheroz Khan. Acknowledgments: The authors have used the laboratories of the University Kuala Lumpur Malaysia, International Islamic University Malaysia, and Onaizah College of Engineering and Information Technology Saudi Arabia–this laboratories’ support is gratefully acknowledged. Conﬂicts of Interest: The authors declare no conﬂict of interest.

References 1. Kouro, S.; Malinowski, M.; Gopakumar, K.; Pou, J.; Franquelo, L.G.; Wu, B.; Rodriguez, J.; Perez, M.A.; Leon, J.I. Recent Advances and Industrial Applications of Multilevel Converters. IEEE Trans. Ind. Electron. 2010, 57, 2553–2580. [CrossRef] 2. Gautam, S.P.; Kumar, L.; Gupta, S. Single-phase multilevel inverter topologies with self-voltage balancing capabilities. IET Power Electron. 2018, 11, 844–855. [CrossRef] 3. Aboadla, E.H.E.; Khan, S.; Habaebi, M.H.; Gunawan, T.; Hamidah, B.A.; Tohtayong, M. Modulation Optimization Effect on Total Harmonic Distortion of Single Phase H-Bridge Inverter Based Selective Harmonics Elimination Technique. In Proceedings of the 2016 International Conference on Computer and Communication Engineering (ICCCE), Kuala Lumpur, Malaysia, 26–27 July 2016; pp. 200–203. 4. Roshankumar, P.; Rajeevan, P.P.; Mathew, K.; Gopakumar, K.; Leon, J.I.; Franquelo, L.G. A five-level inverter topology with single-DC supply by cascading a flying capacitor inverter and an H-Bridge. IEEE Trans. Power Electron. 2012, 27, 3505–3512. [CrossRef] 5. Qi, C.; Tu, P.; Wang, P.; Zagrodnik, M.A. Random nearest level modulation strategy of multilevel cascaded H-Bridge inverters. IET Power Electron. 2016, 9, 2706–2713. [CrossRef] 6. Bae, C.H.; Ryu, J.H.; Lee, K.W. Suppression of Harmonic Spikes in Switching Converter Output Using Dithered Sigma–Delta Modulation. IEEE Trans. Ind. Appl. 2002, 38, 159–166. 7. Chen, Z.; Yao, Y.; Boroyevich, D.; Ngo, K.; Mattavelli, P. Exploration of a switching loop snubber for parasitic ringing suppression. In Proceedings of the 2014 IEEE Energy Conversion Congress and Exposition, Pittsburgh, PA, USA, 14–18 September 2014; pp. 1605–1612. 8. Yatsugi, K.; Nomura, K.; Hattori, Y. Analytical Technique for Designing an RC Snubber Circuit for Ringing Suppression in a Phase-Leg Configuration. IEEE Trans. Power Electron. 2018, 33, 4736–4745. [CrossRef] 9. Tian, Y.; Yang, X.; Xie, R.; Huang, L.; Liu, T.; Wang, J.; Hao, X. A Passive Component Based Gate Drive Scheme for Negative Gate Voltage Spike Mitigation in a SiC-Based Dual-Active Bridge. In Proceedings of the 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, USA, 23–27 September 2018; pp. 1841–1845. 10. Ahmed, M.M.; Hasan, M.K.; Yusoff, N.S.F. Dynamic Load Modeling and Parameter Estimation of 132/275 KV Using PMU- Based Wide Area Measurement System. In International Conference on Innovative Computing and Communications; Springer: Berlin/Heidelberg, Germany, 2020; pp. 1151–1164. 11. Hasan, M.K.; Ahmed, M.M.; Musa, S.S. Measurement and Modeling of DTCR Software Parameters Based on Intranet Wide Area Measurement System for Smart Grid Applications. In International Conference on Innovative Computing and Communications; Springer: Berlin/Heidelberg, Germany, 2020; pp. 1139–1150. 12. Akhtaruzzaman, M.; Hasan, M.K.; Kabir, S.R.; Abdullah, S.N.H.S.; Sadeq, M.J.; Hossain, E. HSIC Bottleneck Based Distributed Deep Learning Model for Load Forecasting in Smart Grid With a Comprehensive Survey. IEEE Access 2020, 8, 222977–223008. [CrossRef] 13. Habib, A.A.; Motakabber, S.; Ibrahimy, M.; Hasan, M. Active voltage balancing circuit using single switched-capacitor and series LC resonant energy carrier. Electron. Lett. 2020, 56, 1036–1039. [CrossRef] 14. Habib, A.K.M.A.; Hasan, M.K.; Motakabber, S.; Mahmud, M.; Islam, S. A Review: Energy Storage System and Balancing Circuits for Electric Vehicle Application. IET Power Electron. 2020, 14, 1–16. [CrossRef] 15. Kim, S.H.; Lee, K.B. Elimination of harmonic spikes using second-order Space Dithered Sigma-Delta Modulation. In Proceedings of the 2009 13th European Conference on Power Electronics and Applications, Barcelona, Spain, 8–10 September 2009; pp. 1–10. 16. Vinod, B.R.; Shiny, G.; Baiju, M.R. Space vector direct torque control for five-level open-end winding induction motor drive to suppress harmonic spikes. In Proceedings of the 2017 IEEE Region 10 Symposium (TENSYMP), Cochin, India, 14–16 July 2017; pp. 1–5. Electronics 2021, 10, 390 16 of 16

17. Ishikawa, K.; Ogawa, K.; Yukutake, S.; Kameshiro, N.; Kono, Y. Traction Inverter that applies compact 3.3kV/1200A SiC hybrid module. In Proceedings of the 2014 International Power Electronics Conference, Shanghai, China, 5–8 November 2014; pp. 2140–2144. 18. Wang, J.; Chung, H.S.H. A novel RCD level shifter for elimination of spurious turn-on in the bridge-leg configuration. IEEE Trans. Power Electron. 2015, 30, 976–984. [CrossRef] 19. He, X.; Chen, A.; Wu, H.; Deng, Y.; Zhao, R. Simple passive lossless snubber for high-power multilevel inverters. IEEE Trans. Ind. Electron. 2006, 53, 727–735. 20. Yamamoto, M.; Shinji, S.; Mutsuo, N. A Novel Voltage Clamped Snubber Circuit Topology Suitable for a Multilevel Inverter with Lowered Power Loss Performance. Electr. Eng. Jpn. 2005, 150, 995–1003. [CrossRef] 21. Fu, J.; Li, C.; Zhu, C. Influence of RCD snubber circuit on the commutation process of high-power three-level inverter with 4.5 kV IEGTs. In Proceedings of the 2016 19th International Conference on Electrical Machines and Systems (ICEMS), Chiba, Japan, 13–16 November 2016; pp. 1–6. 22. Pronin, M.V.; Vorontsov, A.G.; Grigoryan, A.S.; Mamutov, A.R.; Dikun, I.A. Modeling of IGBT-converters by interconnected subsystems with considering of snubber circuit and switching transistor time. In Proceedings of the 2018 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow, Russia, 29 January–1 February 2018; pp. 748–753. 23. Lee, Y.; Kim, J.; Cho, E. Design of Bus-Side RCD Snubber Circuit for Three-Phase High-Power Inverters. Can. J. Electr. Comput. Eng. 2018, 41, 55–61. 24. Kim, J.H.; Park, D.H.; Kim, J.B.; Kwon, B.H. An active gate drive circuit for high power inverter system to reduce turn-off spike voltage of IGBT. In Proceedings of the 2007 7th International Conference on Power Electronics, Daegu, Korea, 22–26 October 2007; pp. 127–131. 25. Gao, F.; Zhou, Q.; Wang, P.; Zhang, C. A gate driver of SiC MOSFET for suppressing the negative voltage spikes in a bridge circuit. IEEE Trans. Power Electron. 2017, 33, 2339–2353. [CrossRef] 26. Jiang, Y.; Feng, C.; Yang, Z.; Zhao, X.; Li, H. A new active gate driver for MOSFET to suppress turn-off spike and oscillation. Chin. J. Electr. Eng. 2018, 4, 43–49. 27. Zushi, Y.; Sato, S.; Matsui, K.; Murakami, Y.; Tanimoto, S. A novel gate assist circuit for quick and stable driving of SiC-JFETs in a 3-phase inverter. In Proceedings of the 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, USA, 5–9 February 2012; pp. 1734–1739. 28. Yamaguchi, K.; Katsura, K.; Yamada, T.; Sato, Y. Comprehensive study on gate driver for SiC-MOSFETs with gate boost. IEEJ J. Ind. Appl. 2018, 7, 218–228. [CrossRef] 29. Yin, S.; Tseng, K.J.; Tong, C.F.; Simanjorang, R.; Gajanayake, C.J.; Gupta, A.K. A novel gate assisted circuit to reduce switching loss and eliminate shoot-through in SiC half bridge configuration. In Proceedings of the 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, USA, 20–24 March 2016; pp. 3058–3064. 30. Zaman, H.; Wu, X.; Zheng, X.; Khan, S.; Ali, H. Suppression of switching crosstalk and voltage oscillations in a SiC MOSFET based half-bridge converter. Energies 2018, 11, 3111. [CrossRef] 31. Li, H.; Liao, X.; Hu, Y.; Huang, Z.; Wang, K. Analysis of voltage variation in silicon carbide MOSFETs during turn-on and turn-off. Energies 2017, 10, 1456. [CrossRef] 32. Aboadla, E.H.; Khan, S.; Habaebi, M.H.; Gunawan, T.S.; Hamida, B.A.; Yaacob, M.B.; Aboadla, A. A novel optimization harmonic elimination technique for cascaded multilevel inverter. Bull. Electr. Eng. Inform. 2019, 8, 405–413. [CrossRef] 33. Wang, L.; Wu, Q.H.; Tang, W. Novel cascaded switched-diode multilevel inverter for renewable energy integration. IEEE Trans. Energy Convers. 2017, 32, 1574–1582. [CrossRef] 34. HV Floating MOS-Gate Driver ICs. Available online: https://www.infineon.com/dgdl/Infineon-HV_Floating_MOS_Gate_ Drivers-ApplicationNotes-v01_00-EN.pdf?fileId=5546d4626c1f3dc3016c47de609d140a (accessed on 6 January 2021). 35. Semiconductor, F. Design and Application Guide of Bootstrap Circuit for High-Voltage Gate-Drive IC. Available online: https://www.eeweb.com/wp-content/uploads/articles-app-notes-files-design-and-application-guide-of-bootstrap-circuit- for-high-voltage-gate-drive-ic.pdf (accessed on 6 January 2021). 36. Yu, S.; Zhu, J.; Lu, Y.; Li, D.; Wang, Y.; Xiang, Z.; Zhang, Y.; Zhang, L.; Sun, W. A self-adaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC. Analog Integr. Circuits Signal Process. 2020, 105, 13–20. [CrossRef]