DOCSLIB.ORG

Tutorial on MPI: the Message-Passing Interface

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Tutorial on MPI: the Message-Passing Interface Tutorial on MPI: The Message-Passing Interface Willi am Gropp NA TIO L NA LA B O E R N A N T O O G R R Y A • • U N O I G V E A R C S I I T C H Y O F Mathematics and Computer Science Division Argonne National Lab oratory Argonne, IL 60439 [email protected] 1 Course Outline Background on Parallel Computing Getting Started MPI Basics Intermediate MPI To ols for writing libraries Final comments Thanks to Rusty Lusk for some of the material in this tutorial. This tutorial maybe used in conjunction with the book \Using MPI" which contains detailed descriptions of the use of the MPI routines. Material that b eings with this symb ol is `advanced' and may b e skipp ed on a rst reading. 2 Background Parallel Computing Communicating with other pro cesses Co op erative op erations One-sided op erations The MPI pro cess 3 Parallel Computing Separate workers or pro cesses Interact by exchanging information 4 Typ es of parallel computing All use di erent data for each worker Data-parallel Same op erations on di erent data. Also called SIMD SPMD Same program, di erent data MIMD Di erent programs, di erent data SPMD and MIMD are essentially the same b ecause any MIMD can be made SPMD SIMD is also equivalent, but in a less practical sense. MPI is primaril y for SPMD/MIMD. HPF is an example of a SIMD interface. 5 Communicating with other pro cesses Data must be exchanged with other workers Co op erative | all parties agree to transfer data One sided | one worker p erforms transfer of data 6 Co op erative op erations Message-passing is an approach that makes the exchange of data co op erative. Data must b oth be explicitl y sent and received. An advantage is that any change in the receiver's memory is made with the receiver's participation. Process 0 Process 1 SEND( data ) RECV( data ) 7 One-sided op erations One-sided op erations between parallel pro cesses include remote memory reads and writes. An advantage is that data can be accessed without waiting for another pro cess Process 0 Process 1 PUT( data ) (Memory) Process 0 Process 1 (Memory) GET( data ) 8 Class Example Take a pad of pap er. Algorithm: Initialize with the numb er of neighb ors you have Compute average of your neighb or's values and subtract from your value. Make that your new value. Rep eat until done Questions 1. Howdoyou get values from your neighb ors? 2. Which step or iteration do they corresp ond to? Do you know? Do you care? 3. Howdoyou decide when you are done? 9 Hardware mo dels The previous example illustrates the hardware mo dels by how data is exchanged among workers. Distributed memory e.g., Paragon, IBM SPx, workstation network Shared memory e.g., SGI Power Challenge, Cray T3D Either may be used with SIMD or MIMD software mo dels. All memory is distributed. 10 What is MPI? A message-passing library sp eci cation { message-passing mo del { not a compiler sp eci cation { not a sp eci c pro duct Forparallel computers, clusters, and heterogeneous networks Full-featured Designed to p ermit unleash? the development of parallel software libraries Designed to provide access to advanced parallel hardware for { end users { library writers { to ol develop ers 11 Motivation for a New Design Message Passing now mature as programming paradigm { well understo o d { ecient match to hardware { many applications Vendor systems not p ortable Portable systems are mostly research projects { incomplete { lack vendor supp ort { not at most ecient level 12 Motivation cont. Few systems o er the full range of desired features. mo dularity for libraries access to p eak p erformance portability heterogeneity subgroups top ologies p erformance measurement to ols 13 The MPI Pro cess Began at Williamsburg Workshop in April, 1992 Organized at Sup ercomputing '92 Novemb er Followed HPF format and pro cess Met every six weeks fortwodays Extensive, op en email discussions Drafts, readings, votes Pre- nal draft distributed at Sup ercomputing '93 Two-month public comment p erio d Final version of draft in May, 1994 Widely availablenow on the Web, ftp sites, netlib http://www.mcs.anl.gov/mpi/index.html Public implementations available Vendor implementations coming so on 14 Who Designed MPI? Broad participation Vendors { IBM, Intel, TMC, Meiko, Cray, Convex, Ncub e Library writers { PVM, p4, Zip co de, TCGMSG, Chameleon, Express, Linda Application sp ecialists and consultants Companies Lab oratories Universities ARCO ANL UC Santa Barbara Convex GMD Syracuse U Cray Res LANL Michigan State U IBM LLNL Oregon Grad Inst Intel NOAA U of New Mexico KAI NSF Miss. State U. Meiko ORNL U of Southampton NAG PNL U of Colorado nCUBE Sandia Yale U ParaSoft SDSC UofTennessee Shell SRC UofMaryland TMC Western Mich U U of Edinburgh Cornell U. Rice U. U of San Francisco 15 Features of MPI General { Communicators combine context and group for message security { Thread safety Point-to-p oint communication { Structured bu ers and derived datatyp es, heterogeneity { Mo des: normal blo cking and non-blo cking, synchronous, ready to allow access to fast proto cols, bu ered Collective { Both built-in and user-de ned collective op erations { Large numb er of data movement routines { Subgroups de ned directly orby top ology 16 Features of MPI cont. Application-oriented pro cess top ologies { Built-in supp ort for grids and graphs uses groups Pro ling { Ho oks allow users to intercept MPI calls to install their own to ols Environmental { inquiry { error control 17 Features not in MPI Non-message-passing concepts not included: { pro cess management { remote memory transfers { active messages { threads { virtual shared memory MPI do es not address these issues, but has tried to remain compatible with these ideas e.g. thread safety as a goal, intercommunicators 18 Is MPI Large or Small? MPI is large 125 functions { MPI's extensive functionality requires many functions { Numb er of functions not necessarily a measure of complexity MPI is small 6 functions { Many parallel programs can b e written with just 6 basic functions. MPI is just right { One can access exibility when it is required. { One need not master all parts of MPI to use it. 19 Where to use MPI? You need a portable parallel program You are writing a parallel library You have irregular or dynamic data relationships that do not t a data parallel mo del Where not to use MPI: You can use HPF or a parallel Fortran 90 You don't need parallelism at all You can use librari es which may be written in MPI 20 Why learn MPI? Portable Expressive Good way to learn ab out subtle issues in parallel computing 21 Getting started Writing MPI programs Compiling and linking Running MPI programs More information { Using MPI by William Gropp, Ewing Lusk, and Anthony Skjellum, { The LAM companion to \Using MPI..." by Zdzislaw Meglicki { Designing and Building Parallel Programs by Ian Foster. { ATutorial/User's Guide for MPI byPeter Pacheco ftp://math.usfca.edu/pub/MPI/mpi.guide.ps { The MPI standard and other information is available at http://www.mcs.anl.gov/mpi. Also the source for several implementations. 22 Writing MPI programs include "mpi.h" include <stdio.h> int main argc, argv int argc; char **argv; { MPI_Init &argc, &argv ; printf "Hello world\n" ; MPI_Finalize; return 0; } 23 Commentary include "mpi.h" provides basic MPI de nitions and typ es MPI_Init starts MPI MPI_Finalize exits MPI Note that all non-MPI routines are lo cal; thus the printf run on each pro cess 24 Compiling and linking For simple programs, sp ecial compiler commands can be used. For large projects, it is b est to use a standard Make le. The MPICH implementation provides the commands mpicc and mpif77 as well as `Makefile' examples in `/usr/local/mpi/examples/Makefile.in' 25 Sp ecial compilation commands The commands mpicc -o first first.c mpif77 -o firstf firstf.f may b e used to build simple programs when using MPICH. These provide sp ecial options that exploit the pro ling features of MPI -mpilog Generate log les of MPI calls -mpitrace Trace execution of MPI calls -mpianim Real-time animation of MPI not available on all systems There are sp eci c to the MPICH implementation; other implementations mayprovide similar commands e.g., mpcc and mpxlf on IBM SP2. 26 Using Make les The le `Makefile.in' is a template Make le. The program script `mpireconfig' translates this to a Make le for a particular system. This allows you to use the same Make le for a network of workstations and a massively parallel computer, even when they use di erent compilers, librari es, and linker options. mpireconfig Makefile Note that you must have `mpireconfig' in your PATH. 27 Sample Make le.in User configur ab le options ARCH = @ARCH@ COMM = @COMM@ INSTALL_D IR = @INSTAL L_ DI R@ CC = @CC@ F77 = @F77@ CLINKER = @CLINKE R@ FLINKER = @FLINKE R@ OPTFLAGS = @OPTFLA GS @ LIB_PATH = -L$INS TA LL _D IR / li b/ $ AR CH /$ C OM M FLIB_PATH = @FLIB_PAT H_ LE AD ER @$ I NS TA LL _D IR / li b/ $ ARC H /$ C OM M LIB_LIST = @LIB_LI ST @ INCLUDE_D IR = @INCLUD E_ PA TH @ -I$INST AL L_D IR / in cl ud e End User configur ab le options 28 Sample Make le.in con't CFLAGS = @CFLAGS @ $OPTFLA GS $INCLUD E_D IR -DMPI_$ AR CH FFLAGS = @FFLAGS@ $INCLU DE _D IR $OPTFLAG S LIBS = $LIB_PA TH $LIB_LI ST FLIBS = $FLIB_ PA TH $LIB_LI ST EXECS = hello default: hello all: $EXECS hello: hello.o $INSTAL L_ DI R /i nc lu de /m pi.
Load more

Recommended publications
  • 2.5 Classification of Parallel Computers
    52 // Architectures 2.5 Classification of Parallel Computers 2.5 Classification of Parallel Computers 2.5.1 Granularity In parallel computing, granularity means the amount of computation in relation to communication or synchronisation Periods of computation are typically separated from periods of communication by synchronization events. • fine level (same operations with different data) ◦ vector processors ◦ instruction level parallelism ◦ fine-grain parallelism: – Relatively small amounts of computational work are done between communication events – Low computation to communication ratio – Facilitates load balancing 53 // Architectures 2.5 Classification of Parallel Computers – Implies high communication overhead and less opportunity for per- formance enhancement – If granularity is too fine it is possible that the overhead required for communications and synchronization between tasks takes longer than the computation. • operation level (different operations simultaneously) • problem level (independent subtasks) ◦ coarse-grain parallelism: – Relatively large amounts of computational work are done between communication/synchronization events – High computation to communication ratio – Implies more opportunity for performance increase – Harder to load balance efficiently 54 // Architectures 2.5 Classification of Parallel Computers 2.5.2 Hardware: Pipelining (was used in supercomputers, e.g. Cray-1) In N elements in pipeline and for 8 element L clock cycles =) for calculation it would take L + N cycles; without pipeline L ∗ N cycles Example of good code for pipelineing: §doi =1 ,k ¤ z ( i ) =x ( i ) +y ( i ) end do ¦ 55 // Architectures 2.5 Classification of Parallel Computers Vector processors, fast vector operations (operations on arrays). Previous example good also for vector processor (vector addition) , but, e.g. recursion – hard to optimise for vector processors Example: IntelMMX – simple vector processor.
    [Show full text]
  • CS650 Computer Architecture Lecture 10 Introduction to Multiprocessors
    NJIT Computer Science Dept CS650 Computer Architecture CS650 Computer Architecture Lecture 10 Introduction to Multiprocessors and PC Clustering Andrew Sohn Computer Science Department New Jersey Institute of Technology Lecture 10: Intro to Multiprocessors/Clustering 1/15 12/7/2003 A. Sohn NJIT Computer Science Dept CS650 Computer Architecture Key Issues Run PhotoShop on 1 PC or N PCs Programmability • How to program a bunch of PCs viewed as a single logical machine. Performance Scalability - Speedup • Run PhotoShop on 1 PC (forget the specs of this PC) • Run PhotoShop on N PCs • Will it run faster on N PCs? Speedup = ? Lecture 10: Intro to Multiprocessors/Clustering 2/15 12/7/2003 A. Sohn NJIT Computer Science Dept CS650 Computer Architecture Types of Multiprocessors Key: Data and Instruction Single Instruction Single Data (SISD) • Intel processors, AMD processors Single Instruction Multiple Data (SIMD) • Array processor • Pentium MMX feature Multiple Instruction Single Data (MISD) • Systolic array • Special purpose machines Multiple Instruction Multiple Data (MIMD) • Typical multiprocessors (Sun, SGI, Cray,...) Single Program Multiple Data (SPMD) • Programming model Lecture 10: Intro to Multiprocessors/Clustering 3/15 12/7/2003 A. Sohn NJIT Computer Science Dept CS650 Computer Architecture Shared-Memory Multiprocessor Processor Prcessor Prcessor Interconnection network Main Memory Storage I/O Lecture 10: Intro to Multiprocessors/Clustering 4/15 12/7/2003 A. Sohn NJIT Computer Science Dept CS650 Computer Architecture Distributed-Memory Multiprocessor Processor Processor Processor IO/S MM IO/S MM IO/S MM Interconnection network IO/S MM IO/S MM IO/S MM Processor Processor Processor Lecture 10: Intro to Multiprocessors/Clustering 5/15 12/7/2003 A.
    [Show full text]
  • What Is SPMD? Messages
    1 2 Outline Motivation for MPI Overview of PVM and MPI The pro cess that pro duced MPI What is di erent ab out MPI? { the \usual" send/receive Jack Dongarra { the MPI send/receive { simple collective op erations Computer Science Department New in MPI: Not in MPI UniversityofTennessee Some simple complete examples, in Fortran and C and Communication mo des, more on collective op erations Implementation status Mathematical Sciences Section Oak Ridge National Lab oratory MPICH - a free, p ortable implementation MPI resources on the Net MPI-2 http://www.netlib.org/utk/p eople/JackDongarra.html 3 4 Messages What is SPMD? 2 Messages are packets of data moving b etween sub-programs. 2 Single Program, Multiple Data 2 The message passing system has to b e told the 2 Same program runs everywhere. following information: 2 Restriction on the general message-passing mo del. { Sending pro cessor 2 Some vendors only supp ort SPMD parallel programs. { Source lo cation { Data typ e 2 General message-passing mo del can b e emulated. { Data length { Receiving pro cessors { Destination lo cation { Destination size 5 6 Access Point-to-Point Communication 2 A sub-program needs to b e connected to a message passing 2 Simplest form of message passing. system. 2 One pro cess sends a message to another 2 A message passing system is similar to: 2 Di erenttyp es of p oint-to p oint communication { Mail b ox { Phone line { fax machine { etc. 7 8 Synchronous Sends Asynchronous Sends Provide information about the completion of the Only know when the message has left.
    [Show full text]
  • Exploiting Automatic Vectorization to Employ SPMD on SIMD Registers
    Exploiting automatic vectorization to employ SPMD on SIMD registers Stefan Sprenger Steffen Zeuch Ulf Leser Department of Computer Science Intelligent Analytics for Massive Data Department of Computer Science Humboldt-Universitat¨ zu Berlin German Research Center for Artificial Intelligence Humboldt-Universitat¨ zu Berlin Berlin, Germany Berlin, Germany Berlin, Germany [email protected] [email protected] [email protected] Abstract—Over the last years, vectorized instructions have multi-threading with SIMD instructions1. For these reasons, been successfully applied to accelerate database algorithms. How- vectorization is essential for the performance of database ever, these instructions are typically only available as intrinsics systems on modern CPU architectures. and specialized for a particular hardware architecture or CPU model. As a result, today’s database systems require a manual tai- Although modern compilers, like GCC [2], provide auto loring of database algorithms to the underlying CPU architecture vectorization [1], typically the generated code is not as to fully utilize all vectorization capabilities. In practice, this leads efficient as manually-written intrinsics code. Due to the strict to hard-to-maintain code, which cannot be deployed on arbitrary dependencies of SIMD instructions on the underlying hardware, hardware platforms. In this paper, we utilize ispc as a novel automatically transforming general scalar code into high- compiler that employs the Single Program Multiple Data (SPMD) execution model, which is usually found on GPUs, on the SIMD performing SIMD programs remains a (yet) unsolved challenge. lanes of modern CPUs. ispc enables database developers to exploit To this end, all techniques for auto vectorization have focused vectorization without requiring low-level details or hardware- on enhancing conventional C/C++ programs with SIMD instruc- specific knowledge.
    [Show full text]
  • Polynomial-Time Algorithms for Enforcing Sequential Consistency in SPMD Programs with Arrays
    Polynomial-time Algorithms for Enforcing Sequential Consistency in SPMD Programs with Arrays ¡ Wei-Yu Chen , Arvind Krishnamurthy , and Katherine Yelick ¢ Computer Science Division, University of California, Berkeley £ wychen, yelick ¤ @cs.berkeley.edu ¥ Department of Computer Science, Yale University [email protected] Abstract. The simplest semantics for parallel shared memory programs is se- quential consistency in which memory operations appear to take place in the or- der specified by the program. But many compiler optimizations and hardware fea- tures explicitly reorder memory operations or make use of overlapping memory operations which may violate this constraint. To ensure sequential consistency while allowing for these optimizations, traditional data dependence analysis is augmented with a parallel analysis called cycle detection. In this paper, we present new algorithms to enforce sequential consistency for the special case of the Single Program Multiple Data (SPMD) model of parallelism. First, we present an algo- rithm for the basic cycle detection problem, which lowers the running time from ¥ ¦¨§ © ¦¨§ © to . Next, we present three polynomial-time methods that more ac- curately support programs with array accesses. These results are a step toward making sequentially consistent shared memory programming a practical model across a wide range of languages and hardware platforms. 1 Introduction In a uniprocessor environment, compiler and hardware transformations must adhere to a simple data dependency constraint: the orders of all pairs of conflicting accesses (accesses to the same memory location, with at least one a write) must be preserved. The execution model for parallel programs is considerably more complicated, since each thread executes its own portion of the program asynchronously, and there is no predetermined ordering among accesses issued by different threads to shared memory locations.
    [Show full text]
  • Data Management and Control-Flow Aspects of an SIMD/SPMD Parallel Language/Compiler
    222 lltt TRANSA('TI0NS ON PARALLEL AND DISTRIBUTED SYSTEMS. VOL. 4. NO. 2. FEBRUARY lYY3 Data Management and Control-Flow Aspects of an SIMD/SPMD Parallel Language/Compiler Mark A. Nichols, Member, IEEE, Howard Jay Siegel, Fellow, IEEE, and Henry G. Dietz, Member, IEEE Abstract-Features of an explicitly parallel programming lan- map more closely to different modes of parallelism [ 191, [23]. guage targeted for reconfigurable parallel processing systems, For instance, most parallel systems designed to exploit data where the machine's -1-processing elements (PE's) are capable of parallelism operate solely in the SlMD mode of parallelism. operating in both the SIMD and SPMD modes of parallelism, are described. The SPMD (Single Program-Multiple Data) mode of Because many data-parallel applications require a significant parallelism is a subset of the MIMD mode where all processors ex- number of data-dependent conditionals, SIMD mode is un- ecute the same program. By providing all aspects of the language necessarily restrictive. These types of applications are usually with an SIMD mode version and an SPMD mode version that are better served when using the SPMD mode of parallelism. syntactically and semantically equivalent, the language facilitates Several parallel machines have been built that are capable of experimentation with and exploitation of hybrid SlMDiSPMD machines. Language constructs (and their implementations) for operating in both the SIMD and SPMD modes of parallelism. data management, data-dependent control-flow, and PE-address Both PASM [9], [17], [51], [52] and TRAC [30], [46] are dependent control-flow are presented. These constructs are based hybrid SIMDiMIMD machines, and OPSILA [2], [3],[16] is on experience gained from programming a parallel machine a hybrid SIMDiSPMD machine.
    [Show full text]
  • Regent: a High-Productivity Programming Language for Implicit Parallelism with Logical Regions
    REGENT: A HIGH-PRODUCTIVITY PROGRAMMING LANGUAGE FOR IMPLICIT PARALLELISM WITH LOGICAL REGIONS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF COMPUTER SCIENCE AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Elliott Slaughter August 2017 © 2017 by Elliott David Slaughter. All Rights Reserved. Re-distributed by Stanford University under license with the author. This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/ This dissertation is online at: http://purl.stanford.edu/mw768zz0480 ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Alex Aiken, Primary Adviser I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Philip Levis I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy. Oyekunle Olukotun Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost for Graduate Education This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives. iii Abstract Modern supercomputers are dominated by distributed-memory machines. State of the art high-performance scientific applications targeting these machines are typically written in low-level, explicitly parallel programming models that enable maximal performance but expose the user to programming hazards such as data races and deadlocks.
    [Show full text]
  • Message Passing Interface Part - I
    Message Passing Interface Part - I Dheeraj Bhardwaj Department of Computer Science & Engineering Indian Institute of Technology, Delhi – 110016 India http://www.cse.iitd.ac.in/~dheerajb Message Passing Interface Dheeraj Bhardwaj <[email protected]> 1 Message Passing Interface Outlines ? Basics of MPI ? How to compile and execute MPI programs? ? MPI library calls used in Example program ? MPI point-to-point communication ? MPI advanced point-to-point communication ? MPI Collective Communication and Computations ? MPI Datatypes ? MPI Communication Modes ? MPI special features Message Passing Interface Dheeraj Bhardwaj <[email protected]> 2 What is MPI? ? A message-passing library specification • Message-passing model • Not a compiler specification • Not a specific product ? Used for parallel computers, clusters, and heterogeneous networks as a message passing library. ? Designed to permit the development of parallel software libraries Message Passing Interface Dheeraj Bhardwaj <[email protected]> 3 Information about MPI Where to use MPI ? ? You need a portable parallel program ? You are writing a parallel Library ? You have irregular data relationships that do not fit a data parallel model Why learn MPI? ? Portable & Expressive ? Good way to learn about subtle issues in parallel computing ? Universal acceptance Message Passing Interface Dheeraj Bhardwaj <[email protected]> 4 Information about MPI MPI Resources ? The MPI Standard : http://www.mcs.anl.gov/mpi ? Using MPI by William Gropp, Ewing Lusk and Anthony Skjellum
    [Show full text]
  • 2.1 Flynn's Taxonomy of Parallel Architectures-Twoslidesxpage
    Flynn’s Taxonomy of Parallel Architectures Stefano Markidis, Erwin Laure, Niclas Jansson, Sergio Rivas-Gomez and Steven Wei Der Chien 1 Sequential Architecture • The von Neumann architecture was conceived in the mid-1940s • Arithmetic logic unit (ALU) is the heart of the computer, performing the actual computation. • Registers can be read and written to at the speed of the surrounding logic. A bank of several registers allow for simultaneous reads and writes • The processor accesses the main memory of the computer system to store and use the values of the program variables making up the state of the calculation. • The operation of the processor is managed by the controller, which creates a sequence of signals to the hardware. • Originally this was done as a series of phases: fetch instructions, execute operation, and write back to register (or memory). • This would be repeated for each succeeding operation of the instruction stream. 2 3/20/17 Flynn's Taxonomy • In the 1966, Michael Flynn proposed a Flynns taxonomy (1966) taxonomy that simplified categorization of distinct classes of parallel architecture and n {Single, Multiple} {Instructions, Data} control methods based on the relationships of data and instruction (control) • Comprising four characters, it divides the SISD SIMD world of computing structures into four Single Instruction, Single Data Single Instruction, Multiple Data classes in a 2D space. • One dimension concerns the data stream, D, • whether there is one such stream, S, or multiple MISD MIMD data streams, M. Multiple Instruction, Single Data Multiple Instruction, Multiple Data • The other dimension relates to the control or instruction stream, I • whether there is one instruction stream, S, or 3 multiple instructions streams, M.
    [Show full text]
  • Introduction to Parallel Programming with MPI Lecture #1
    Introduction to Parallel Programming with MPI Lecture #1: Introduction Andrea Mignone1 1Dipartimento di Fisica- Turin University, Torino (TO), Italy Course Requisites § In order to follow these lecture notes and the course material you will need to have some acquaintance with • Linux shell • C / C++ or Fortran compiler • Basic knowledge of numerical methods § Further Reading & Links: • The latest reference of the MPI standard: https://www.mpi-forum.org/docs/ Huge - but indispensible to understand what lies beyond the surface of the API • Online tutorials: • https://mpitutorial.com (by Wes Kendall) • https://www.codingame.com/playgrounds/349/introduction-to-mpi/introduction- to-distributed-computing • http://adl.stanford.edu/cme342/Lecture_Notes.html The Need for Parallel Computing § Memory- and CPU-intensive computations can be carried out using parallelism. § Parallel programming methods on parallel computers provides access to increased memory and CPU resources not available on serial computers. This allows large problems to be solved with greater speed or not even feasible when compared to the typical execution time on a single processor. § Serial application (codes) can be turned into parallel ones by fulfilling some requirements which are typically hardware-dependent. § Parallel programming paradigms rely on the usage of message passing libraries. These libraries manage transfer of data between instances of a parallel program unit on multiple processors in a parallel computing architecture. Parallel Programming Models § Serial applications will not run automatically on parallel architectures (no such thing as automatic parallelism !). § Any parallel programming model must specify how parallelism is achieved through a set of program abstractions for fitting parallel activities from the application to the underlying parallel hardware.
    [Show full text]
  • Introduction to Matlab Parallel Computing Toolbox
    INTRODUCTION TO MATLAB PARALLEL COMPUTING TOOLBOX Keith Ma ---------------------------------------- [email protected] Research Computing Services ----------- [email protected] Boston University ---------------------------------------------------- MATLAB Parallel Computing Toolbox 2 Overview • Goals: 1. Basic understanding of parallel computing concepts 2. Familiarity with MATLAB parallel computing tools • Outline: • Parallelism, defined • Parallel “speedup” and its limits • Types of MATLAB parallelism • multi-threaded/implicit, distributed, explicit) • Tools: parpool, SPMD, parfor, gpuArray, etc MATLAB Parallel Computing Toolbox 3 Parallel Computing Definition: The use of two or more processors in combination to solve a single problem. • Serial performance improvements have slowed, while parallel hardware has become ubiquitous • Parallel programs are typically harder to write and debug than serial programs. Select features of Intel CPUs over time, Sutter, H. (2005). The free lunch is over. Dr. Dobb’s Journal, 1–9. MATLAB Parallel Computing Toolbox 4 Parallel speedup, and its limits (1) • “Speedup” is a measure of performance improvement 푡푖푚푒 speedup = 표푙푑 푡푖푚푒푛푒푤 • For a parallel program, we can with an arbitrary number of cores, n. • Parallel speedup is a function of the number of cores 푡푖푚푒 speedup(p) = 표푙푑 푡푖푚푒푛푒푤(푝) MATLAB Parallel Computing Toolbox 5 Parallel speedup, its limits (2) • Amdahl’s law: Ideal speedup for a problem of fixed size • Let: p = number of processors/cores α = fraction of the program that is strictly serial T = execution
    [Show full text]
  • Computer Architecture: SIMD and Gpus (Part III) (And Briefly VLIW, DAE, Systolic Arrays)
    Computer Architecture: SIMD and GPUs (Part III) (and briefly VLIW, DAE, Systolic Arrays) Prof. Onur Mutlu Carnegie Mellon University A Note on This Lecture n These slides are partly from 18-447 Spring 2013, Computer Architecture, Lecture 20: GPUs, VLIW, DAE, Systolic Arrays n Video of the part related to only SIMD and GPUs: q http://www.youtube.com/watch? v=vr5hbSkb1Eg&list=PL5PHm2jkkXmidJOd59REog9jDnPDTG6IJ &index=20 2 Last Lecture n SIMD Processing n GPU Fundamentals 3 Today n Wrap up GPUs n VLIW n If time permits q Decoupled Access Execute q Systolic Arrays q Static Scheduling 4 Approaches to (Instruction-Level) Concurrency n Pipelined execution n Out-of-order execution n Dataflow (at the ISA level) n SIMD Processing n VLIW n Systolic Arrays n Decoupled Access Execute 5 Graphics Processing Units SIMD not Exposed to Programmer (SIMT) Review: High-Level View of a GPU 7 Review: Concept of “Thread Warps” and SIMT n Warp: A set of threads that execute the same instruction (on different data elements) à SIMT (Nvidia-speak) n All threads run the same kernel n Warp: The threads that run lengthwise in a woven fabric … Thread Warp 3 Thread Warp 8 Thread Warp Common PC Scalar Scalar Scalar Scalar Thread Warp 7 ThreadThread Thread Thread W X Y Z SIMD Pipeline 8 Review: Loop Iterations as Threads for (i=0; i < N; i++) C[i] = A[i] + B[i]; Scalar Sequential Code Vectorized Code load load load Iter. 1 load load load add Time add add store store store load Iter. Iter. Iter. 2 load 1 2 Vector Instruction add store Slide credit: Krste Asanovic 9 Review:
    [Show full text]