DOCSLIB.ORG

VIA C7, Eden (V4 Bus), CN900 Product Brief Available N Windows CE MPEG-2 SDK for CLE266/CN400 V1.0 Beta N Windows XP Embedded with Service Pack 2

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
VIA C7, Eden (V4 Bus), CN900 Product Brief Available N Windows CE MPEG-2 SDK for CLE266/CN400 V1.0 Beta N Windows XP Embedded with Service Pack 2 VIA Embedded Platform Roadmap January 20th 2005 Update and Proprietary VIA Confidential 17-1 Latest Updates n Added VIA C7 processors n Updated Power/Schedule Page n VIA C7, Eden (V4 bus), CN900 Product Brief available n Windows CE MPEG-2 SDK for CLE266/CN400 V1.0 Beta n Windows XP Embedded with Service Pack 2 n All VIA Embedded Products Available in Lead-free Package. Certification documents available upon request • VIA's lead-free manufacturing processes comply with: - RoHS Restriction of Hazardous Substances - WEEE Waste Electrical and Electronic Equipment and Proprietary VIA Confidential 17-2 Embedded Product Positioning High Performance 9High speed, high bandwidth, yet low power consumption and heat dissipation 9Excellent Digital Media Application Performance Mainstream 9Balanced solution for feature and value 9Excellent productivity application performance Fanless 9Low heat and low power consumption 9Smallest footprint x86 platform 9High integration and scalability and Proprietary VIA Confidential 17-3 VIA C3/C7 Power & Schedules TDPmax 25W 2.0 GHz 1.4 GHz 1.4 GHz 1.4 GHz 1.81.4 GHz GHz 1.41.8 GHzGHz 20W 1.3 GHz 1.3 GHz 1.3 GHz 1.7 GHz 1.71.3 GHz 1.71.3 GHz 1.2 GHz 1.2 GHz 1.2 GHz 1.2 GHz 1.4 GHz 15W 1.6 GHz 1.6 GHz 1.6 GHz 1.1 GHz 1.1 GHz 1.1 GHz 1.1 GHz 1.1 GHz 1.0 GHz 1.0 GHz 1.51.0 GHz 1.51.0 GHzGHz 1.51.0 GHzGHz 1.0 GHz 1.0 GHz 1.0 GHz 1.0 GHz 1.0 GHz Low Power 10W C3 800 MHz 800 MHz 800 MHz 800 MHz 800 MHz 5W 4Q ‘‘04 1Q ‘‘05 2Q ‘‘05 3Q ‘‘05 4Q ‘‘05 V4 interface based on “Esther” core Available in both current and V4 interface n C3 800MHz not included n C7 power consumption are preliminary estimations and Proprietary VIA Confidential 17-4 VIA Eden Power & Schedules TDPmax 10W 1.0 GHz 1.0 GHz 1.0 GHz 1.0 GHz 1.0 GHz 1.2 GHz 1.2 GHz 1.2/1.5 GHz 733/800 MHz 733/800 MHz 733/800 MHz 733/800 MHz 733/800 MHz 600 MHz 600 MHz 600 MHz 600 MHz 600 MHz 1.0 GHz / 800 MHz / 667 MHz 5W 533 MHz 533 MHz 533 MHz 533600 MHzMHz 533 MHz 533 MHz 533 MHz 533/1.0 GHz 400 MHz 400 MHz 400 MHz 400 MHz 400 MHz 300 MHz 300 MHz 400300 MHzMHz 400300 MHzMHz 300400 MHz 4Q ‘‘04 1Q ‘‘05 2Q ‘‘05 3Q ‘‘05 4Q ‘‘05 V4 interface based on “Esther” core n Power Consumption for Eden processors with V4 bus are preliminary estimations n Eden Processor power numbers are the absolute maximum power consumption and Proprietary VIA Confidential 17-5 V4 Platform n New “V4” bus interface at 400/533MHz, future plans up to 800MHz n 32-bit addressing, 64-bit data n Less pin count, lower power consumption n 50% better write bandwidth n Linear ordering modes for better read-latency n Based on “Esther” core with IBM 90nm SOI process technology n Proprietary flip-chip BGA Package n C7 up to 2.0GHz, Eden up to 1.5GHz n L1/L2 cache = 128/128KB (128/64KB for C3) n SSE3/SSE2 / MMX (SSE/MMX for C3) n JTAG port enabled n Built-in hardware RNG, AES Encryption, RSA, SHA-1 (RNG and AES only for C3) n “NX” bit for virus protection and Proprietary VIA Confidential 17-6 VIA Processor Core Roadmap Esther (C5J) V4 bus 400/533MHz Isaiah (CN) Future Plan for 800MHz FSB 64-bit L1/L2 = 128/128KB 90nm Process 90nm SOI SSE3/SSE2 / MMX Out of order exe. More Security Features Super scalar JTAG Support “NX” bit for virus protection Late June Production Nehemiah (C5P) Ruth (C5Q) L1/L2 = 128/64KB V4 bus 400/533MHz 0.13u SSE / MMX SSE/MMX, APIC support Full speed FPU RNG&ACE unit APIC support “NX” bit for virus protection Samuel 2 (C5B) RNG&ACE unit Late June Production 133FSB 0.15u L1/L2 = 128/64KB MMX/3DNOW! 1.5GHz- 2.0GHz Product 1.0GHz- 1.0GHz- 800MHz Lines 1.4GHz 1.4GHz Supported 300- 733MHz- 400MHz- 600MHz 1.0GHz 1.5GHz 2002 2003 2004 2005 2005+ (Production Date) VIA Confidential and Proprietary 17-7 Product Differentiation – C3/C7 C3 Processor C7 Processor Regular Low Power V4 V4 Speed 1.0 - 1.4GHz 800MHz / 1.0GHz 800MHz - 1.4GHz 1.5 - 2.0GHz Offerings TDP max 13 - 21W * 9 / 11W 9 - 21W 12 - 25W Max ** Package CPGA & EBGA EBGA Flip chip BGA Flip chip BGA 800MHz:1.65V Vcore 1.25V TBD TBD 1.0GHz+: 1.4/1.45V L1/L2 128 / 64KBy te 128 / 64KBy te 128 / 64KBy te 128 / 128KBy te Case CPGA: 70C 85C 100C 100C Temperature EBGA: 85C Dimension CPGA:50x503x6.13 35x35x1.57 TBD TBD (mm) EBGA:35x35x1.57 Power Saving PowerSav er 1.0 PowerSav er 1.0 TBD TBD Technology (Frequency Change) (Frequency Change) * C3 EBGA parts TDP max not 100% tested and guaranteed. Eden TDPmax are absolute maximum power numbers ** C7 TDP max not 100% tested and guaranteed and Proprietary VIA Confidential 17-8 Product Differentiation – Eden Ed e n Ed e n - N Regular V4 V4 Ultra Low Voltage Regular Speed 300MHz - 1.0GHz 400MHz - 1.2GHz 1.0GHz / 1.5GHz 533/800/1.0GHz Offerings 3.5W @ 1.0GHz TDP max 3 - 7 W 2.5 - 7 W 3 / 5 / 7 W 7W @ 1.5GHz Package EBGA Flip chip BGA Flip chip BGA nanoBGA 1.05 V Vcore TBD TBD 1.05 V 1.2 V (533&667MHz) L1/L2 128 / 64KBy te 128 / 128KBy te 128 / 128KBy te 128 / 64KBy te Case 85C 100C 100C 85C Temperature 100C By Request Dimension 35x35x1.57 TBD TBD 15x15x1.85 (mm) Power Saving Power Sav er 1.0 PowerSav er 3.0 TBD TBD Technology (Frequency Change) f or 1.0GHz part and Proprietary VIA Confidential 17-9 VIA Embedded Chipset Solutions Northbridge for C3/Eden Northbridge for All-In-One for V4 bus V4 Bus CN400/CN333CN400/CN333 CN900 CX700M ••FFSBSB @10 @1000/133/133/200/200MHzMHz((CCNN400400 o onnlyly)) CN900 CX700M • DDR266/333/400(CN400 only) • DDR266/333/400(CN400 only) • V4 FSB 400/533 MHz • V4 FSB 400/533 MHz • Int. UniChromeTMTMPro GFX • V4 FSB 400/533 MHz • V4 FSB 400/533 MHz • Int. UniChrome Pro GFX • DDR 333/400, DDR2 400/533 • DDR333, DDR2 400/533 ••DiDisplsplaayy Re Ressoolution:lution: • DDR 333/400, DDR2 400/533 • DDR333, DDR2 400/533 • Int. UniChromeTMTMPro graphics • Int.128-bit UniChromeTMTMPro 2D/3D graphics 19201920 x x 144 14400 @75 @75 H Hzz • Int. UniChrome Pro graphics • Int.128-bit UniChrome Pro 2D/3D graphics TM • Int. MPEG-2 decoder •MPEG2/MPEG4 Decoder ••Int.Int. UniChro UniChroCN400/CN333mmeeTMProProGGraphraphicicss • InCN400/CN333t. MPEG-2 decoder •MPEG2/MPEG4 Decoder • 2D/3D/Video H/W Rotation ••AAGGPP 3 3.0.0 8X 8X In Intteerrffaceace ••WWMMV9V9 Decod Decodeerr • 2D/3D/Video H/W Rotation • DuoView™,CRT,DVO ports • DuoView™,CRT,DVO ports ((CCN400N400 on only)ly) • DuoView™,CRT,DVO ports • DuoView™,CRT,DVO ports • AGP 4X/8X port(CN400 only) ••88XX V-Link V-Link ••IntegIntegrratedated HDTV HDTV en encodcodeerr • AGP 4X/8X port(CN400 only) • Sample: Q1’05 • Integrated LVDS/DVI transmitter ••FFuullll MPEG2 MPEG2/MPEG4/MPEG4 deco decoddeerr((CCN400N400 o onnly)ly) • Sample: Q1’05 • Integrated LVDS/DVI transmitter • Int. video processor ••PProducroduction:tion: Q2 Q2’05’05 ••IntInetensnsivivee P Poowerwer M Manageanagememenntt • Int. video processor • 6 USB 2.0 ports ••UUltraltra V-Li V-Linknk • 6 USB 2.0 ports •TDP@ 2.5W ••HDHD A Auudidioo,L,LPPC,ACC,ACPIPI 2. 2.00 •TDP@ 2.5W • Sample: May ’05, ’Production: July ‘05 •• PProducroductiontion N Nooww • Sample: May ’05, ’Production: July ‘05 CX700CX700 ••VV44 FSB FSB 400/ 400/533533 MH MHzz VT8237R VT8251 ••DDDDRR333,333, D DDDRR22 400/533 400/533 ••32/64b32/64b D DRRAAMM D Daatata W Wididtthh • 2 ports SATA • ECC support • Ultra V-Link • 2x1 Lane PCI-Express • ECC support • Int.128-bit UniChromeTMTMPro 2D/3D graphics • Total 6 HDD support • Ultra V-Link • High Definition AudioTM • Int.128-bit UniChrome Pro 2D/3D graphics • Up to 2 MPEG2 HD streams, PiP support • RAID 0, 1, 0+1 support • Total 8 HDD support 192k/32bit 8CH • Up to 2 MPEG2 HD streams, PiP support •`8 ports USB 2.0 • SATA Advanced Host ••DDuuoViewoView™,™CRT,DV,CRT,DVOO ppoortsrts • AC97 96K/20-bit 6 channel • VIA MAC with MII Interface Controller Interface (AHCI) ••InInttegegratrateded LVD LVDS/S/DDVIVI trans transmmitteitterr • 10/100 BT w/ Ext. PHY • RAID 0, 1, 0+1 HSP V.92 ••IntInetensnsivivee P Powowerer M Manageanagememenntt • 6 ch. AC’97 audio, Int. • JBOD support •ACPI 2.0 ••66 US USBB 2. 2.00 p poortsrts • IO/APIC •VIA 10/100MAC • Production:Q2’05 ••HDHD A Auudidioo,L,LPPC,ACC,ACPIPI 2. 2.00 ••SSamamplple:e: M Maayy ’0 ’05,5, ’Pro ’Prodduucctitioonn: :July July ‘0 ‘055 and Proprietary VIA Confidential 17-10 CoreFusion™ Roadmap The VIA “CoreFusionTM” technology provides highest level of integration and miniaturization. Leveraging proven technologies and infrastructure, developers can introduce small form factor designs with the fastest time-to-market LukeLuke All-in-One “John” ••533MHz,533MHz, 8800MHz00MHz && 1.1.00 GHzGHz DDR 2, WMV9, 32 bit CPU+ NorthBridge: ••DDRDDR 333/4333/40000 memory option ,HD • Int. UniChromeTMTMPro Graphics DDR, USB2.0, SATA, • Int. UniChrome Pro Graphics Audio, etc ••MPEG2/4MPEG2/4 AGP Port, etc ••ExternalExternal AGPAGP PortPort ••Sample:Sample: MMaarchrch ‘05‘05 ••ProductionProduction:: AprilApril ‘05‘05 CPU+ NorthBridge: MarkMark ISA Extension, Special ••533MHz533MHz Resolutions Support ••PC13PC1333 Current ••TTwwiissterter--TT DriverDriver ReaReaddyy ••CompanioCompanionn :: 686B686B CPU+NorthBridge ••Sample:Sample: MMaarchrch ‘05‘05 + SouthBridge ••ProductionProduction:: AprilApril ’05’05 Platform Q1 ‘05 Q2 ‘05 Q3 ‘05 Q4 ‘05 VIA Confidential and Proprietary 17-11 VIA Processor Security Roadmap Faster, More Secure, Direct Access, and Built-in! Complete Set of security primitives in the processor: Hardware provides increased security & performance.
Load more

Recommended publications
  • Operating Guide
    Operating Guide EPIA EN-Series Mini-ITX Mainboard January 18, 2012 Version 1.21 EPIA EN-Series Operating Guide Table of Contents Table of Contents ...................................................................................................................................................................................... i VIA EPIA EN-Series Overview.............................................................................................................................................................. 1 VIA EPIA EN-Series Layout .................................................................................................................................................................. 2 VIA EPIA EN-Series Specifications ...................................................................................................................................................... 3 VIA EPIA EN Processor SKUs .............................................................................................................................................................. 4 VIA CN700 Chipset Overview ............................................................................................................................................................... 5 VIA EPIA EN-Series I/O Back Panel Layout ...................................................................................................................................... 6 VIA EPIA EN-Series Layout Diagram & Mounting Holes ..............................................................................................................
    [Show full text]
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • Intel® Architecture and Tools
    Klaus-Dieter Oertel Intel-SSG-Developer Products Division FZ Jülich, 22-05-2017 The “Free Lunch” is over, really Processor clock rate growth halted around 2005 Source: © 2014, James Reinders, Intel, used with permission Software must be parallelized to realize all the potential performance 4 Optimization Notice Copyright © 2014, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Changing Hardware Impacts Software More cores More Threads Wider vectors Intel® Intel® Xeon® Intel® Xeon® Intel® Xeon® Intel® Xeon® Intel® Future Intel® Xeon Intel® Xeon Phi™ Future Intel® Xeon® Processor Processor Processor Processor Xeon® Intel® Xeon® Phi™ x100 x200 Processor Xeon Phi™ Processor 5100 series 5500 series 5600 series E5-2600 v2 Processor Processor1 Coprocessor & Coprocessor (KNH) 64-bit series E5-2600 (KNC) (KNL) v3 series v4 series Up to Core(s) 1 2 4 6 12 18-22 TBD 61 72 TBD Up to Threads 2 2 8 12 24 36-44 TBD 244 288 TBD SIMD Width 128 128 128 128 256 256 512 512 512 TBD Intel® Intel® Intel® Intel® Intel® Intel® Intel® Intel® Vector ISA IMCI 512 TBD SSE3 SSE3 SSE4- 4.1 SSE 4.2 AVX AVX2 AVX-512 AVX-512 Optimization Notice Product specification for launched and shipped products available on ark.intel.com. 1. Not launched or in planning. Copyright © 2016, Intel Corporation. All rights reserved. 9 *Other names and brands may be claimed as the property of others. Changing Hardware Impacts Software More cores More Threads Wider vectors Intel® Intel® Xeon® Intel® Xeon® Intel® Xeon® Intel® Xeon® Intel® Future Intel® Xeon Intel® Xeon Phi™ Future Intel® Xeon® Processor Processor Processor Processor Xeon® Intel® Xeon® Phi™ x100 x200 Processor Xeon Phi™ Processor 5100 series 5500 series 5600 series E5-2600 v2 Processor Processor1 Coprocessor & Coprocessor (KNH) 64-bit series E5-2600 (KNC) (KNL) v3 series v4 series Up to Core(s) 1 2 4 6 12 18-22 TBD 61 72 TBD Up to Threads 2 High2 performance8 12 24software36-44 mustTBD be 244both: 288 TBD SIMD Width 128 .
    [Show full text]
  • Communication Theory II
    Microprocessor (COM 9323) Lecture 2: Review on Intel Family Ahmed Elnakib, PhD Assistant Professor, Mansoura University, Egypt Feb 17th, 2016 1 Text Book/References Textbook: 1. The Intel Microprocessors, Architecture, Programming and Interfacing, 8th edition, Barry B. Brey, Prentice Hall, 2009 2. Assembly Language for x86 processors, 6th edition, K. R. Irvine, Prentice Hall, 2011 References: 1. Computer Architecture: A Quantitative Approach, 5th edition, J. Hennessy, D. Patterson, Elsevier, 2012. 2. The 80x86 Family, Design, Programming and Interfacing, 3rd edition, Prentice Hall, 2002 3. The 80x86 IBM PC and Compatible Computers, Assembly Language, Design, and Interfacing, 4th edition, M.A. Mazidi and J.G. Mazidi, Prentice Hall, 2003 2 Lecture Objectives 1. Provide an overview of the various 80X86 and Pentium family members 2. Define the contents of the memory system in the personal computer 3. Convert between binary, decimal, and hexadecimal numbers 4. Differentiate and represent numeric and alphabetic information as integers, floating-point, BCD, and ASCII data 5. Understand basic computer terminology (bit, byte, data, real memory system, protected mode memory system, Windows, DOS, I/O) 3 Brief History of the Computers o1946 The first generation of Computer ENIAC (Electrical and Numerical Integrator and Calculator) was started to be used based on the vacuum tube technology, University of Pennsylvania o1970s entire CPU was put in a single chip. (1971 the first microprocessor of Intel 4004 (4-bit data bus and 2300 transistors and 45 instructions) 4 Brief History of the Computers (cont’d) oLate 1970s Intel 8080/85 appeared with 8-bit data bus and 16-bit address bus and used from traffic light controllers to homemade computers (8085: 246 instruction set, RISC*) o1981 First PC was introduced by IBM with Intel 8088 (CISC**: over 20,000 instructions) microprocessor oMotorola emerged with 6800.
    [Show full text]
  • Intel® Software Guard Extensions (Intel® SGX)
    Intel® Software Guard Extensions (Intel® SGX) Developer Guide Intel(R) Software Guard Extensions Developer Guide Legal Information No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied war- ranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel rep- resentative to obtain the latest forecast, schedule, specifications and roadmaps. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, Xeon, and Xeon Phi are trademarks of Intel Corporation in the U.S. and/or other countries. Optimization Notice Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations.
    [Show full text]
  • AMD Ryzen 5 1600 Specifications
    AMD Ryzen 5 1600 specifications General information Type CPU / Microprocessor Market segment Desktop Family AMD Ryzen 5 Model number 1600 CPU part numbers YD1600BBM6IAE is an OEM/tray microprocessor YD1600BBAEBOX is a boxed microprocessor with fan and heatsink Frequency 3200 MHz Turbo frequency 3600 MHz Package 1331-pin lidded micro-PGA package Socket Socket AM4 Introduction date March 15, 2017 (announcement) April 11, 2017 (launch) Price at introduction $219 Architecture / Microarchitecture Microarchitecture Zen Processor core Summit Ridge Core stepping B1 Manufacturing process 0.014 micron FinFET process 4.8 billion transistors Data width 64 bit The number of CPU cores 6 The number of threads 12 Floating Point Unit Integrated Level 1 cache size 6 x 64 KB 4-way set associative instruction caches 6 x 32 KB 8-way set associative data caches Level 2 cache size 6 x 512 KB inclusive 8-way set associative unified caches Level 3 cache size 2 x 8 MB exclusive 16-way set associative shared caches Multiprocessing Uniprocessor Features MMX instructions Extensions to MMX SSE / Streaming SIMD Extensions SSE2 / Streaming SIMD Extensions 2 SSE3 / Streaming SIMD Extensions 3 SSSE3 / Supplemental Streaming SIMD Extensions 3 SSE4 / SSE4.1 + SSE4.2 / Streaming SIMD Extensions 4 SSE4a AES / Advanced Encryption Standard instructions AVX / Advanced Vector Extensions AVX2 / Advanced Vector Extensions 2.0 BMI / BMI1 + BMI2 / Bit Manipulation instructions SHA / Secure Hash Algorithm extensions F16C / 16-bit Floating-Point conversion instructions
    [Show full text]
  • Evolution Des X86befehlssatzes Und Seiner Erweiterungen
    Technische Universität Dresden Evolution des x86-Befehlssatzes und seiner Erweiterungen Peter Ebert Dresden, 15.07.2009 Einführung · Überblick & Historie · Konkurrierende Befehlssatzarchitekture n · Befehlsarten · Registerstruktur · x87 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 2/24 Übersicht & Historie · IBM 1981: erster PC · x86-Architektur verwendet einen CISC-Befehlssatz · alle Prozessoren seit dem Pentium Pro sind aber hybride CISC/RISC-Prozessoren 1978 1. Gen.: 8086 1982 2. Gen.: 80286 1985 3. Gen.: 80386 IA-32 1989 4. Gen.: 80486 1993 5. Gen.: Pentium MMX 1995 6. Gen.: P2, P3 3DNow!, SSE 1999 7. Gen.: Athlon (XP), P4 SSE2 2003 8. Gen.: Opteron x86-64 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 3/24 Konkurrierende Befehlssatzarchitekturen · ARM (Acorn Risc Machine) RISC-Architektur 1983 vom englischen Computerhersteller Acorn. Einsatz vor allem im eingebetteten Bereich z.B.: Mobiltelefonen, PDAs, Routern, iPod, iPhone, Internet Tablets von Nokia und den neueren PDAs von ASUS, Konsolen wie der Nintendo DS, der GP2X und die Pandora. · PowerPC (Performance optimization with enhanced RISC Performance Chip) 1991 durch ein Konsortium aus Apple, IBM und Motorola. z.B.: Nintendo GameCube und Wii, Xbox 360 von Microsoft, Playstation 3 von Sony und in vielen eingebetteten Systemen. Auch benutzen PKW und Produkte in der Luft- und Raumfahrt · SPARC (Scalable Processor ARChitecture) Von Sun Microsystems entwickelt ab 1985 und vermarktete ab 1987, offene Architektur, 1995 64-Bit-Erweiterung (UltraSparc) 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 4/24 Befehlsarten · Transferbefehlen werden Daten innerhalb des Systems bewegt. Die Daten werden dabei nur kopiert, d. h. bleiben an ihrem Quellort unverändert.
    [Show full text]
  • X86 Intrinsics Cheat Sheet Jan Finis [email protected]
    x86 Intrinsics Cheat Sheet Jan Finis [email protected] Bit Operations Conversions Boolean Logic Bit Shifting & Rotation Packed Conversions Convert all elements in a packed SSE register Reinterpet Casts Rounding Arithmetic Logic Shift Convert Float See also: Conversion to int Rotate Left/ Pack With S/D/I32 performs rounding implicitly Bool XOR Bool AND Bool NOT AND Bool OR Right Sign Extend Zero Extend 128bit Cast Shift Right Left/Right ≤64 16bit ↔ 32bit Saturation Conversion 128 SSE SSE SSE SSE Round up SSE2 xor SSE2 and SSE2 andnot SSE2 or SSE2 sra[i] SSE2 sl/rl[i] x86 _[l]rot[w]l/r CVT16 cvtX_Y SSE4.1 cvtX_Y SSE4.1 cvtX_Y SSE2 castX_Y si128,ps[SSE],pd si128,ps[SSE],pd si128,ps[SSE],pd si128,ps[SSE],pd epi16-64 epi16-64 (u16-64) ph ↔ ps SSE2 pack[u]s epi8-32 epu8-32 → epi8-32 SSE2 cvt[t]X_Y si128,ps/d (ceiling) mi xor_si128(mi a,mi b) mi and_si128(mi a,mi b) mi andnot_si128(mi a,mi b) mi or_si128(mi a,mi b) NOTE: Shifts elements right NOTE: Shifts elements left/ NOTE: Rotates bits in a left/ NOTE: Converts between 4x epi16,epi32 NOTE: Sign extends each NOTE: Zero extends each epi32,ps/d NOTE: Reinterpret casts !a & b while shifting in sign bits. right while shifting in zeros. right by a number of bits 16 bit floats and 4x 32 bit element from X to Y. Y must element from X to Y. Y must from X to Y. No operation is SSE4.1 ceil NOTE: Packs ints from two NOTE: Converts packed generated.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • PC-Doctor Service Center 12 Data Sheet
    PC-Doctor Service Center TM Data Sheet PC-Doctor Service Center is the diagnostic toolkit used by repair organizations, IT professionals, system builders and others to troubleshoot and isolate hardware issues, and to verify system integrity on servers, desktops, notebooks and mobile devices. The Service Center Kit includes diagnostics for Windows, DOS, Android, and Bootable Diagnostics that includes support for PCs and Intel-based Macs. Each kit contains a bootable USB key, CD and DVD test media, loopback adapters for serial, parallel, audio, and RJ45 ports, and a professional carrying case. In addition, the Service Center Premier Kit includes a power supply tester and PCI and miniPCI POST cards with remote display. What’s New? • Drive Erase – Certified NIST compliant! • Organize by customer, system or other desired parameters o Sanitization improvements for NVMe and ATA drives • Store test results from multiple test environments in one place as organized by your choice of sessions o Cloud storage for reports • Android version 8.x Oreo and 9.x Pie support My Links • Support for NVDIMM testing Create shortcuts to the most used utilities, test scripts, • DirectX 12 testing or websites: The first five links are added to the main • Storage testing improvements application screen for easy access. o Improved SAS drive coverage o Improved Intel Optane support System Snapshots o Expanded NVMe testing Snapshots provide a one-click solution to save a • Improved processor support detailed system inventory on PCs and Macs: o AMD Ryzen Mobile CPUs • All hardware devices o Skylake-W Xeon processors • (Windows) OS, virus protection, web browser, o AVX2 for AMD CPUs Windows startup programs and device drivers • Windows Server 2016 support Compare two system snapshots to visually display all • Updated Video Interactive testing hardware and driver changes—great for auditing and building customer confidence.
    [Show full text]
  • Intel® Architecture Instruction Set Extensions and Future Features Programming Reference
    Intel® Architecture Instruction Set Extensions and Future Features Programming Reference 319433-030 OCTOBER 2017 Intel technologies features and benefits depend on system configuration and may require enabled hardware, software, or service activation. Learn more at intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifica- tions. Current characterized errata are available on request. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Intel does not guarantee the availability of these interfaces in any future product. Contact your Intel representative to obtain the latest Intel product specifications and roadmaps. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1- 800-548-4725, or by visiting http://www.intel.com/design/literature.htm. Intel, the Intel logo, Intel Atom, Intel Core, Intel SpeedStep, MMX, Pentium, VTune, and Xeon are trademarks of Intel Corporation in the U.S.
    [Show full text]
  • SBC82700 Series All-In-One Half-Size CPU Card with Dualview Display and SATA User's Manual
    SBC82700 Series All-In-One Half-Size CPU Card With DualView Display and SATA User’s Manual Disclaimers This manual has been carefully checked and believed to contain accurate information. AXIOMTEK Co., Ltd. assumes no responsibility for any infringements of patents or any third party’s rights, and any liability arising from such use. AXIOMTEK does not warrant or assume any legal liability or responsibility for the accuracy, completeness or usefulness of any information in this document. AXIOMTEK does not make any commitment to update the information in this manual. AXIOMTEK reserves the right to change or revise this document and/or product at any time without notice. No part of this document may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without the prior written permission of AXIOMTEK Co., Ltd. Caution If you replace wrong batteries, it causes the danger of explosion. It is recommended by the manufacturer that you follow the manufacturer’s instructions to only replace the same or equivalent type of battery, and dispose of used ones. ©Copyright 2007 AXIOMTEK Co., Ltd. All Rights Reserved September 2007, Version A1 Printed in Taiwan ii ESD Precautions Computer boards have integrated circuits sensitive to static electricity. To prevent chipsets from electrostatic discharge damage, please take care of the following jobs with precautions: Do not remove boards or integrated circuits from their anti-static packaging until you are ready to install them. Before holding the board or integrated circuit, touch an unpainted portion of the system unit chassis for a few seconds.
    [Show full text]