INTRODUCTION This service manual provides a variety of service compatible computer. It can write as much as 700 information. Mbytes of digital data into CD-R/RW disc, and can It contains the mechanical structure of the CD- read as much as 650 Mbytes of digital data stored R/RW Drive and the electronic circuits in in a CD-ROM, CD-R and CD-RW disc. schematic form. This CD-R/RW Drive was This CD-R/RW Drive can easily meet the manufactured and assembled under our strict upcoming MPC level 3 specification, and its quality control standards and meets or exceeds Enhanced Intelligent Device Electronics (E-IDE) industry specifications and standards. and ATAPI interface allows Plug and play This CD-R/RW drive is an internal drive unit integration in the majority of today’s PCs without designed for use with IBM PC, HP Vectra, or the need of an additional interface card. FEATURES
1. General 1) Enhanced IDE interface. 2) Internal 5.25 inch, halfheight CD-R/RW Drive. 3) 2 Mbytes buffer memory. 4) Audio CD like tray loading of a disc without using a caddy. 5) Power loading and power ejecting of a disc. The disc can also be ejected manually. 6) Supports Power saving mode and Sleep mode. 7) Vertical and Horizontal operation. 8) Super Link Function. 2. Supported disc formats 1) Reads and writes data in each CD-ROM, CD-ROMXA, CD-I FMV, Video CD, and CD-EXTRA 2) Reads data in Photo CD (Single and Multi session). 3) Reads and writes standard CD-DA. 4) Reads and writes CD-R discs conforming to “Orange Book Part 2”. 5) Reads and writes CD-RW discs conforming to “Orange Book Parts 3”. 3. Supported write method 1) Disc at once (DAO), Session at once (SAO), Track at once (TAO), Variable packet, Fixed packet, and Multi-session. 4. Performance 1) Random 110 ms average access time. 2) CD-R Record speed : 4X, 8X, 12X, 16X. 3) CD-RW Record speed : 2X, 4X, 10X. 4) CD-ROM : Max 6,000 KB/s(Max 40x) Sustained Transfer rate. 5) Supports real time error correction and real time layered error correction at each speed. 6) Supports CD-R write operation at each double speed, quadruple speed, eighth speed. 7) Supports CD-RW write operation at double speed and quadruple speed. 8) PIO Mode 4, Multi DMA Mode 2 . 9) Multimedia MPC-3 Spec compliant. 10) Support CD-TEXT read/write. 5. Audio 1) Output 16 bit digital data over ATA interface. 2) 8 Times Digital Filter for CD Audio 3) Software Volume Control 4) Equipped with audio line output and headphone jack for audio CD playback. 5) Front panel Volume Control for Headphone Output.
3 LOCATION OF CUSTOMER CONTROLS
Front Panel
Emergency Eject Hole
Disc Tray WRITE READ
Stop/Eject Button
Play/Skip Button
Volume Control Drive Activity Indicators
Headphone Jack
1. Disc tray 5. Volume control This is the tray for the disc. Place the disc on the This is used to adjust the output volume of the ejected disc tray, then lightly push the tray (or headphone jack. It can’t be used to adjust the push the eject button) and the CD will be loaded. output volume for the audio output connectors on NOTE: Don’t pull out or push in the disc tray the rear panel. forcibly. This might cause damage to the loading NOTE : Turn the volume down before turning on section of the drive. the power. Sudden loud noises can damage your hearing. 2. Stop/Eject button This button is pressed to open the CD tray. 6. Headphone jack This button works only when power is supplied to This jack is for connecting headphones or mini- the drive. speakers. If an Audio CD is playing, pressing this button will 7. Drive activity indicators stop it, and pressing it again will open the tray. Two colored LEDs are used to indicate the 3. Play/Skip button operation of CD-R/RW Drive. When an Audio CD is in the disc drawer, pressing (1) Read this button will start playing Audio CDs from the The orange color is displayed when the spindle first track. If an Audio CD is playing, pressing this motor begins the Spin up operation: accessing button will skip to the next track. data, reading data, playing Audio, and up loading tray. 4. Emergency Eject Hole (2) Write Insert a paper clip here to eject the Disc tray The green color is flashed during disc writing manually or when there is no power. sessions.
6 Rear Panel
Analog Audio Output Connector IDE Interface Connector
Jumper Connector Power Connector
Digital Audio Output Connector
1. Power Connector 3. Jumper Connector Connects to the power supply (5-and 12-V DC) of This jumper determines whether the drive is the host computer. configured as a master or slave. Changing the NOTE : Be careful to connect with the proper master-slave configuration takes effect after polarity. Connecting the wrong way may damage power-on reset. the system (and is not guaranteed). Usually this 4. Analog Audio Output Connector connector can only be attached one-way. Provides output to a sound card (analog signal). 2. IDE Interface Connector Generally you need this to play a regular audio Connect to the IDE (Integrated Device CD. Electronics) Interface using a 40-pin flat IDE 5. Digital Audio Output Connector cable. Provides output to a sound card (digital signal). NOTE : Do not connect or disconnect the cable when the power is on, as this could cause a short circuit and damage the system. Always turn the power OFF when connecting or disconnecting the cable.
7 GLOSSARY
ATIP Absolute Time in Pre-groove. With an additional modulation of the “Wobble”, the “Groove” contains a time code information. Wobble The pre-groove in the Disc is not a perfect spiral but is wobbled. With : – A typical amplitude of 30 nm – A spatial peried of 54~64 µm CW Continuous Wave. The laser light output is at a constant level. DOW Direct Over-Write. The action in which new information is recored over previously recorded information in CD-RW disc. Overwrite The action in which new information is recorded over previously recorded information. (Pre-)Groove The guidance track in which clocking and time code information is stored by means of an FM modulated wobble. Land Land is characterized in the following way: When radial signals are concerned,land is defined as the area between the grooves. When HF signal are concerned,land is defined as the area between the marks(pits) in tangential direction. Hybrid Disc A Multisession disc of which the first Session is mastered. On a hybrid disc, recorded and mastered information may co-exist. Mastered Information,stored as pits on the disc during the manufacturing process of the disc. Information (when making the master) OPC Optimum Power Control. Procedure is determined optimum recording power according to CD- R/RW Media in recording start step. ROPC Running OPC. The purpose is to continuously adjust the writing power to the optimum power that is required. When the optimum power may change because of changed conditions of disc and change in operating temperature. Jitter The 16 value of the time variation between leading and trailing edges of a specific (I3 … I11) pit or land as measured by Time Interval Analysis. Deviation The difference between a fixed value of Pit length and Land length. TOC Table Of Contents : in the Lead-in Area the subcode Q-channel contains information about the Tracks on the disc. Packet A method of writing data on a CD in small increments. Writing Two kinds of packets can be written : Fixed-length and Variable-length. Write The shape of the HF write signal used to modulate the power of the laser. Strategy The Write Strategy must be used for recordings necessary for disc measurements. Information Wobble, ATIP, Disc Identification, Write Power, Speed Range OPC Parameters, etc are Area recorded in the Information area of CD-RW Disc Finalization The action in which (partially) unrecorded or logically erased tracks are finished and the Lead-in and/or Lead-out areas are recorded or overwritten with the appropriate TOC subcode. Logical Erase A method to remove information from a disc area by overwriting it with an EFM signal containing mode 0 subcode A logically erased area is equivalent to an unrecorded Physical Erase The action in which previously recorded information is erased by overwriting with a CW laser output. After a Physical Erase action, the erased area on the CD-RW disc is in the unrecorded state again. Session An area on the disc consisting of a Lead-in area, a Program area, a lead-out area. Multi session A session that contains or can contain more than one session composed Lead-in and Lead-out
10 The differences of CD-R/CD-RW discs and General CD-ROM 1. Recording Layer Recordable CD has a wobbled pre-groove on the surface of disc for laser beam to follow track.
Track pitch(p) CD-ROMRead-only (READ-ONLY Disc DISC) a=30nm A
Iw O 1.6um Radial Direction a
3~11T
0.4~0.5 um Radial Error Signal Land Groove
CD-R and CD-RW Disc a
Average center (Pit)Groove
Land Actual center
The Groove wobble
2. Disc Specification
CD-ROM CD-R CD-RW Standard Yellow Book Orange Book II Orange Book III Record Not available Write once Re-writable
I 11/Itop > 0.6 > 0.6 0.55 > M11> 0.70 (HF Modulation) Write Laser Power(mW) 10-30 mW 6-25 mW Read Laser Power(mW) < 0.5 mW < 0.7 mW < 1.0 mW Jitter < 35 nsec < 35 nsec < 35 nsec
Reflectivity (Rtop) 70 % 65 % 15 % ~ 25 %
18 3. Disc Materials 1) CD-ROM disc • It is composed of Silver _ colored aluminum plate and Reflective layer. • Groove (Pit) of aluminum plate make a track. • Laser wavelength : 780 nm, Laser Power (Read): 0.5mW • Signal is detected by the difference of reflective beam intensity between “pit” and “Land” on the disc.
Label Printing Protective Layer
Reflective Layer
Substrate (Polycarbonate)
Pit Laser Beam 2) CD-R disc • It is so-called WORM (Write Once Read Many) CD. • It is composed of polycarbonate layer, Organic dye layer, Reflective layer, and Protective layer.Gold/Silver Reflective layer is used to enhance the reflectivity • According to the kinds of Organic dye layer, it is divided by Green CD, Gold CD, Blue CD. • Laser Wavelength : 780 nm, Laser Power (read) : 0.7 mW • Recording Power : 4x(10~15mW), 8x(14~20mW), 12x(15~30mW, 16x(25~35mW) • When some part of dye layer is exposed to laser heat, it’s color changs black.Therefore, writing and reading is enabled by the difference of reflectivity between changed part and unchanged part. • Polycarbonate layer has Pre_Groove which make a Track.
Pigment Reflective Layer Color Phtalocyanine Gold/Silver Yellow/White Cyanine Gold/Silver Dark Green/Bright Green Azo Gold/Silver Dark Blue
Label Printing Protective Layer Reflective Layer Organic Dye Layer
Substrate (Polycarbonate)
Laser Beam Groove
19 3) CD-RW Disc
Label Printing Protective Layer Dielectric Layer(TL) Reflective Layer Dielectric Layer(UL)
Substrate (Polycarbonate)
Laser Beam Groove
• It is composed of polycarbonate layer, alloy(silver, arsenic) layer, aluminum reflectivity layer, protective layer. • An crystalized alloy layer is transformed into noncrystalized by the laser heat. Therefore, writing and reading is enabled by the difference of reflectivity. • It is possible to overwrite about 1000 times. • Laser Wavelength : 780 nm, Laser Power (Read) : 1.0mW • Recording Power : Erase (4~18mW), Write (6~35mW) • When disc rewriting, new data is overwritten previously recorded data. • Polycarbonate layer has a Pre-Groove which make a track.
4. Reading process of Optical Disc
Lens H D θ
Beam Spot Focusing Numerical aperture: NA=nsinθ, Lens n: Refractive index Focus depth : H = λ/NA laser spot diameter : D = λ/NA2 Laser Spot at Constant Read Intensity Previously Recorded Marks
Groove Land Mirror
Reflected Light Signal I11 IG IL I0
I3 Itop Laser Spot Position (Time)
20 5. Writing Process of CD-R Disc
Incident (Write) Laser Power (Read) (Read)
Laser Spot a b c d e f g Position (Time)
a
Laser b Spot Below "ORP"– Mark Too Short Reflected At Optimum Record Power ("ORP") c Light Signal Above "ORP" – Mark Too Long d
e
f
Recorded g Mark Time
Reflected Light Signal
Laser Spot a b c d e f g Position (Time)
6. Writing process of CD-RW Disc
Write Power Crystal phase Amorphous Melting/ quenching Erase Power
Heating/ Read Power gradual cooling Erased state Recorded state (higher reflectivity) (lower reflectivity) Groove
Crystal Amorphous
21 7. Organization of the PCA, PMA and Lead-in Area 1) Layout of CD-ROM disc
Disc Center Diameter 120 mm
Diameter 46 mm
Diameter 15 mm
Center hole Clamping and Label Area Information Area
Read Only Disc
Lead-in Area Program Area Lead-out Area
2) Layout of CD-R/RW disc Disc Center Diameter 120 mm
Diameter 45 mm
Diameter 15 mm
Center hole Clamping and Label Area Information Area
Unrecorded Disc PCA PMA Lead-in Area Program Area Lead-out Area
Test Area : for performing OPC procedures. Count Area : to find the usable area immediately in T.A Test Area Count Area Tsl : start time of the Lead-in Area, as encoded in ATIP in out PMA : Program Memory Area
Tsl-00:35:65 Tsl-00:15:05 Tsl-00:13:25 Tsl 99:59:74 00:00:00
22 8. Function of PCA and PMA area 1) PCA (Power Calibration Area)
• PCA area is used to determine the correct Laser Power for a disc. – Method 1 : PCA area is divided by a track. – Method 2 : The previous Calibration value is referred. – Method 3 : ROPC is used to determine Laser Power value automatically in data writing. • CD-R Disc can write maximum 99 Tracks but CD-RW Disc can write unlimited tracks because it has a rewritable function. 2) PMA (Program Memory Area)
• It has a track information (track No, track Start/End time) of every track before writing completed. – PMA area has the last written point and the next writable point of a disc. – In case of CD to CD copy, some writer may not write PMA area. * When Disc is Finalized, PMA information is transferred to the Lead_In area so that general Driver can read it.
* Because PCA and PMA area exist before Lead-In area, General CD Player or CD-ROM Drive can’t read these areas.
9. OPC and ROPC 1) OPC (Optimum Power Control) • This is the first step of writing process, because CD writer has its own laser power value and media have different writing characteristics, – This is determined by the Writing characteristic, speed, temperature, and humidity. – Laser wavelength is determined by the environmental temperature (775~795nm) and Optical Laser Power is determined by the test and retry. • Asymmetry and optimum writing Power – EFM signal Asymmetry is determined by the writing power. Therefore, Optical Power which has the same value to the preset power value can be estimated by measuring HF signal Asymmetry on the PCA area. • Measurement of Asymmetry * Parameter setting (Beta) : Using AC coupled HF signal before equalization Beta = (A1+A2)/(A1-A2)
A1
0 HF Signal
A2 P = Po P >> Po Time P << Po Time Time
23 2) ROPC (Running Optimum Power Control) • Variable primary factor of Optimum Power – Change of Power sensitivity on the Disc. (limited to 0.05 *Po) – Wavelength shift of the laser diode due to the operating temperature change. – Change of the Spot aberration due to the Disc skew, Substrate thickness, Defocus. – Change of Disc or Optics conditions due to the long term OPC Incident recording pulse ==> It is necessary to adjust continuously to obtain the Optimum Power. Sampled timing B • Principle of Running OPC – To meet the factors mentioned above, a horizontal _ direction movement of a curve is uesd. – Beta = f(B-level) = constant on the Recorded Disc – Procedure of ROPC a. Reference B-level is determined during OPC Procedure. b. During Recording, B-level value is controlled to have a close Reflected recording pulse Reference B-level value. c. Normalization of B-level is used to eliminate the effect of reflectivity fluctuation. ==> The reflected B-level value is normalized by the disc reflectivity itself.
Sample Disc Reflectivity Sampled at timing B (Read power) Level B 11T normalized to recording power
Level B with Pwo
Sample B-level (Write Power) Pwo decided by OPC Recording Power
10. Writing Process of DISC
CD-R/RW Media Program Area
Write Strategy PMA Area Determination ROPC
PCA Test Area Lead-In Area OPC
PCA Count Area Lead-out Area
* Recording Capacity of CD-R/RW (74Minute Recording media) • (2048 Byte/Sector) X (75 Sector/Second) X (60 Second/Minute) X 74 Minute = 681,984,000 Bytes = 682 Mbytes
• But the actual recording capacity is about 650 Mbytes. (according to the ISO 9660 standard, approximately 30 Mbytes are used to make directory structure and volume names.) 24 INTERNAL STRUCTURE OF THE PICK-UP 1. KRS-302B Circuit Diagram
2 Axis Actuator 1 FCS - 2 TRK - 3 TRK + 4 FCS + 5 GND 6 PDGND 7 F 8 B C1 1 12 9 A Vcc GND 2 11 10 H H G 3 D 10 11 PDVCC A IC1 4 9 12 PDVC B PDIC C 5 8 13 G F E 6 7 14 D Vc RF C2 15 C 16 E
IC2 FPDIC 17 RF SUM 1 10 18 FPDVCC 2 9 GND GND 19 FPDVC 3 8 GND GND 20 FPDGND 4 7 Vc Vcc 5 6 21 FPDO OUT Bin R1 L1 22 VCC C3 C4 R3 R2 23 VCC VR1 24 VRDC C5 C6 25 VWDC2 26 VWDC1 L2 27 GND 1 24 28 GND VOUT PDIN 2 23 OSCEN VREF VCC LD 29 3 22 GND VCC 11 30 WE2 4 IC3 21 IINR IOUT 5 LD 20 31 WE1 IIN2 IOUT A C 6 Driver 19 32 ENBL R4 IIN3 GND 7 18 RFREQ GND 8 17 R5 GND RAMP 9 16 GND ENABLE 10 15 WEN3 OSCEN 11 14 C7 WEN2 VCC 12 13 GND GND
C10 C9 C8 R6 R7 R8
25 2. Signal detection of the P/U
Infrared Iaser
Pick-Up module Focusing
Photo Diode Tracking
1) Focus Error Signal ==> (A+C)-(B+D) This signal is generated in RF IC (IC401 : MT1506) and controls the pick-up’s up and down to focus on Disc.
2) Tracking Error Signal (DPP Method) ==> {(A+D)-(B+C)}- k x {(F+H)-(E+G)} This signal is generated in RF IC (IC401 : MT1506) and controls the pick-up’s left and right shift to find to track on Disc.
3) RF Signal ==> (A+B+C+D) This signal is converted to DATA signal in DSP IC (IC301 : MT1505).
Track Center
Tp/2 Sub1 F,E
Main D,C A,B
Sub2 H,G
Tp
k[(F+H) - (E+G)] Offset (A+D) - (B+C)
TE (A+D) - (B+C) - k[(F+H) - (E+G)]
26 DESCRIPTION OF CIRCUIT 1. ALPC (Automatic Laser Power Control) Circuit 1-1. ALPC Loop Circuit 34 33 32 26 21 24 VWDC20 VRDCO VWDC10 M2 M2 M2 VRDC VRDCO VWDC2 VWDC1 VWDC20 VWDC10 FPDOX FPDOX M2 Gain Gain Gain
VRDCDAG
VRDC1DAG VWDC2DAG FVREF) ’ VRDCX VWDC1X VWDC2X FPDOG
FPDOG VRDCDA 256 Steps 256 Steps 256 Steps VWDC2DA VWDC1DA (Level Shift to 2 0V-VWDC1B 0V-VWDC2B 0V-VWDC1B M2 WLDONDLY M2 M2 VRDCB VWDC2B VWDC1B "H" "H" "L" "L" "L" "H" 20 VRDCBSEL CKT
(AUX-6) Digital D FPDO VRDC WREF1X VWDC1 RREFX VWDC2 WLDON WREF2X RREF IC401 MT1506 VRDC VWDC1 VRDCN 29 28 27 26 25 24 23 22 21 VWDC2 WREF2 VWDC2N WREF1 PN401 (P/U) VWDC1N M2 M2 M2 RREF WREF2 VRDC VWDC2 VWDC1 WREF1 RREFON WREF2ON VWDC1B WREF1ON RREFX WREF1X WREF2X "H" : short "L" : open "H" : short "L" : open "H" : short "L" : open
WDA2SEL RDAON WDAC1X WDA2ON WDA1ON RDACX "L" "H" "H" "H" "H" "L" "L" "L"
WDAC1G WDAC2X WLDON RLDON RDAC x1/x2 "H" : short "L" : open "H" : short "L" : open "H" : short "L" : open WLDON 8
WAPC2ON x1/x2
RWMODE RDACRG to 0.5V to GND "L" "H" WDAC2G to GND Level Shift Level Shift Level Shift WDAC1 8 8
10 VRDCG VRDCG VRDCG WDAC2 x2, x4, x8, x10
RDAC
VBDAC VRDCG VWDC2G V WDC1G 10
W1DAC RDAOUT
WAPC2ON S/H S/H WDA1OUT S/H WAPC2ON WDA2OUT W2DAC
RWMODE "H" "L" M1 FPDO FVREF M1 FPDO 73 72 19 20 54 53 21 FPDO FVREF RLDON WLDON RFPDSH WFPDSH
29 28
27 WLDON
IC403 RLDON 26 0 4.7K 10K MT1501 2Vref IC201 RFPDSH WFPDSH
27 1-2. ALPC(Automatic Laser Power Control) Circuit Operation
ALPC (Automatic Laser Power Control) function in CD-R/RW analog front-end is for constant power level control purpose. Based on the accurate power sensor(FMD) in PU, APC feedback loop maintains constant power level against laser diode’s temperature variation.
There are three power control loops in CD-R/RW analog front-end, which are used with different combination for different applicatioins. Generally, the first APC loop is used for read power control. The 2nd & 3rd APC loop is used for write (or erase) power control for CD-R/RW disc.
The first APC loop amplifies (up to 10x) the FMD signal (FPDO) to enhance the accuracy of read power control. VRDCG is used to adjust the gain of FMD signal. The built -in 8-bit RDAC is used to set the read power level.
The 2nd & 3rd APC loop is used for high power control. Both WDAC1 and WDAC2 are 10-bats DAC, which are used to set the wanted power level. The 3rd APC loop can alos be used as a voltage divider, which take input from 2nd APC loop (VWDC1B).
Besides, three 8-bit potentiometers (VRDCDA, VWDC1DA, and VWDC2DA) and amplifiers (VRDCDAG, VWDC1DAG, VWDC2DAG) are used to speed up the transient response of VRDCO, VWDC1O, VWDC2O.
On the other hand, the input signal FPDO after amplification (x2 or x4) will send the MPXOUT2 for monitoring.
28 2. RF Amplifier Circuit Block Diagram RFI RFIS FEI CEI TEI SBAD ATFG IC201 IC301 MT1501 MT1505 41 122 121 120 118 123 124 FE CE/MPP TE SBAD ATFG EQRF ATFM 10 11 12 14 88 60 50 x1 MPPG Adj Gain Adj Gain
K*E+F+G+H) Data Slicer K2*[MPPO-SPPO] HPF VREF Adj Gain SPPO GAIN ADD Offset adj. Fix Fix Gain Gain
K1*(A+C)-(B+D) Fix Gain AGC3 Adj Gain MPPO LPF
LPF LPF
(40kHZ) /320KHz) Filter EQRF LPF (40K/80K/160K LPF (40kHZ) IC401 MT1506 x1/x3 AGC1/2 (A+C)-(B+D) 150KHz BPF 150KHz 150KHz 150KHz VGA ADD LPF LPF LPF LPF (22.05KHz) HPF
adj LPF SPPO TEOS MPPO Offset ADD x1/x2 Offset adj Offset adj Offset adj
2 3 4 5 95 96 97 98 E,F,G,H A,B,C,D 7 9 8 16 13 10 15 14 Pick up KRS-302B
29 3. Focus/Tracking/Sled Servo Circuit 3-1. Focus, Tracking & Sled Servo Process
Focus, Tracking Servo
IC401 MT1506 Pick- up
E F FE Focus Error C B A,B,C,D Detector A,B,C,D,E,F,G,H D A
G H Track Error TE A,B,C,D Detector E,F,G,H
Tracking Focusing Actuator F- F+ T+ T- IC301 A/D Servo Control MT1505 TE FE
Focus x5 FEO
Tracking x5 27 115 DAC PARALLEL DIGITAL TEO COMPENSATOR 28 114 IC501 M63024FP
SLED COMPENSATOR
108 107
Sled Control IC501 M63024FP
Stepping Control SL1+ STEP1 1
SL1- Logic M SL2- STEP2 SL2+ 2
30 3-2. Focus Servo The aim of Focus Servo is to maintain the distance between object lens of P/U and disc surface, so that the detected RF signals (A, B, C, D) can be maximized. Focus Servo is based on focus error (FE) signal which is generated from focus error detection block in MT1506(IC401) using Astigmatism Method. Focus gain and path can be changed at the MT1506 according to the disc, and the resulting output (FE) is input to Servo IC (IC301, MT1505). FE signal after first amplification in MT1505 is A/D converted and input to Digital Equalizer Block, most important part at the Focus Servo. At the Digital Equalizer, adjustments for Focus Bias and Loop Gain are performed. After D/A converted, Focus servo signal is output through FOO port (MT1505, Pin115) and drive Focus Actuator through the Focus Drive IC (IC501, M63024FP). 3-3. Tracking Servo The aim of Tracking Servo is to make laser beam trace the data track on disc. Tracking Error (TE) signal is generated from tracking error detection block in MT1506 (IC401) using DPP (Differential Push-Pull) Method. DPP method uses not only main beam (A, B, C, D) but side beams (E,F and G, H) for correcting DC offset generated in Push-Pull method. The remaining procedures of TE signal processing in MT1505 is similar to Focus Servo. After D/A converted, Tracking servo signal is output through TRO port (MT1505, Pin114) and drive Tracking Actuator through the Tracking Drive IC (IC501, M63024FP). 3-4. Sled Servo The working distance of tracking actuator is too short to cover whole disc radius. Sled Servo make PU move by little and little so that the laser beam keep tracing the data track on disc continuously when tracking actuator reaches the working limit. Another function of Sled Servo is to seek a target point on disc, following user commands. Sled control signal, STEP 1, 2 is generated in MT1505. STEP 1, 2 are output to sled motor via IC501 (M63024FP).
31 4. Spindle Servo Circuit 4-1. Spindle Servo Process
Pick- up IC401 MT1506 E EQRF F RF 8 88 C B DA SRF IC301 G ATFG 124 MT1505 H Wobble Signal 60 Generator
Spindle Motor Data PLL
M 106 Spindle Control
Hall Sensor PWM
6 CD EFM CLV CAV x40
110 RDMO
41 73
Divider
FG 120 24 8 Wobble Spindle MATRIX CLV Control IC510 BA6664FM Current comp. WDMO PWM CTL amp. 26 74
IC501 M63024F IC201 MT1501
4-2. Spindle Servo Spindle servo is as followings; 1) Wobble CLV x2, x4, x8, x10, x12, x16 : Blank area in CD-R, CD-RW. 2) CD 15x CAV: Eccentric CD-R/RW. 3) CD 20x CAV: Video CD, CD-DA in CD-ROM/R 4) CD 32x CAV: Recorded area in CD-RW. 5) CD 40x CAV: CD-ROM. Recorded area in CD-R. – Spindle Servo is controlled by IC201 (MT1501), IC301(MT1505) and servo signal is output via WDMO (IC201 pin74).
32 BLOCK DIAGRAM FUNCTIONAL BLOCK DIAGRAM 5V 12V S T H O Line Out 2MB IC202 SDRAM L,R 3.3V Reset I/F Cable Data Mute Audio Circuit
I/F IC201 34.57MHz MT1501E DECODER ENCODER Write Strategy Write Write S/H Singnal Write ATIP Demodulator ATIP 2KB IC203 AT93C86 EEPROM Servo S/H, Servo Address/Data Wobble FG/EFM Wobble Write S/H Signal Data L,R Audio RFAC, RFDC, FEI, TEI DAC IC401 ALPC DSP Wobble IC301 RF Amp Servo Audio MT1506E MT1505E IC302 256KB 39SF020A Flash ROM Laser Power Ref. Address/Data Writing Strategy PD VWDC VRDC SLED DC Motor SLO FEO TEO Optical Pick-up KRS-302B FCS TRK IC501 M63024FP DMO control Try 5Ch Servo DRIVE 5Ch Servo Spindle Motor
74 MAJOR IC INTERNAL BLOCK DIAGRAM AND PIN DESCRIPTION IC401 (MT1506) : CD-R/RW Analog Signal Processor Block Diagram XRST SDATA XLAT DVDD1 DVDD2 DVSS2 SCLK DVSS1 AVDD1 AVSS1 XDEFM SUBGND AVDD2 AVDD3 AVSS2 AVSS3 AVDD5 VREF AVDD4 AVSS5 AVSS4 SLPFP DEFM SLPFN MPX2BHC MPX2PHC
DIG. P/H EQRF Data REG. MPX2 & Slicer MPXOUT2 AVSS AUX1 VREF TESTM2 DRCMO DRCSO RRFXLP AUX2 VWDC2O VRDCO ROPCO VWDC1 VWDC2 VWDC1O VRDC B/H AUX1 MCLK MPX2B AUX2 EQRF MPX2B OSTCC VCON EQRF RRF MPX2 MPX2 RFAGCC MCLK 10-Bit RRFX EQBIAS ADC DEFECT WLDON GAINUP INB INC INA IND MPX1 HAVC FELP TELP RFRP SPPO MPPO DRCLP
RRF FE MPXOUT1 RECD1 FPDOX TE RRFX SBAD ATFM FPDO ROPCO RECDIN TESTM1
RRF CE/MPP SBADLP RECD1_DG1 AGCON
RRFXLP RRFX VCON INTAGCON RRF AGC1C MPX1 MPX1 AGC2C INB INC INA IND HAVC AGC3C
ADCTG GAINUP ATIP DEFECT ATFM H11T
TZC INTAGCON ASH BSH FSH CSH HSH GSH ESH DSH ATFG
WRF RFZC1 ADO ROPC WBLCLK ROPCC BCO ROPCO ADBCO
MCLK INB INC INA IND HAVC WBLSH WLDON SERVSH ADO RLDON BCO FPDOX GAINUP S/H ADBCO WFPDSH INB RECD1-DG1 MCLK & APC RFPDSH INA FEO
MATRIX TZC VRDCO ING MPPO RFZC1 DEFECT
GAINUP VWDC1O INF SPPO SERVO HAVC SBADO VWDC2O FE TE INE INC IND INH TEIN RFZC SBAD XTOR FPDO RREF SHPC SHBC TRON VRDC FVREF XTAND DRCSO WREF2 WREF1 VRDCN DRCMO VWDC2 VWDC1 CE/MPP SBADLP DEFECT DRCSO2 DRCMO2 VWDC2N VWDC1N RFZC1VC
33 • Pin Assignment
Pin Numbers Symbol Type Description RF Signals & S/H Control Pulses 2 INA Analog Input Input of Main Beam Signal (A) 3 INB Analog Input Input of Main Beam Signal (B) 4 INC Analog Input Input of Main Beam Signal (C) 5 IND Analog Input Input of Main Beam Signal (D) 95 INE Analog Input Input of Side Beam Signal (E) 96 INF Analog Input Input of Side Beam Signal (F) 97 ING Analog Input Input of Side Beam Signal (G) 98 INH Analog Input Input of Side Beam Signal (H) 99 HAVC Analog Input Reference Voltage of Main and Side Beams (2.0V) 56 GAINUP Digital Input (TTL) Gain Control Switch for CD-RW Read Mode 68 SERVSH Digital Input (TTL) S/H Control Pulse of Main and Side Beam Signals 70 WBLSH Digital Input (TTL) S/H Control Pulse of Wobble Signal Focus/Tracking Error & Servo Control Signals 6 DRCMO Analog Output Output of (A+B+C+D) Summing Signal 8 DRCSO Analog Output Output of (E+F+G+H) Summing Signal 7 DRCMO2 Analog Input Re-Input of (A+B+C+D) Summing Signal 9 DRCSO2 Analog Input Re-Input of (E+F+G+H) Summing Signal 10 FE Analog Output Output of Focusing Error Signal 12 TE Analog Output Output of Tracking Error Signal 11 CE/MPP Analog Output Output of Center Error or Main Push-Pull Signal 14 SBAD Analog Output Output of SBAD Signal 13 TEIN Analog Input Input of Out-of-Track Detection Circuit 61 XTOR Digital Output (TTL) Output of Out-of-Track Detection Signal (OR) 62 XTAND Digital Output (TTL) Output of Out-of-Track Detection Signal (AND) 15 SBADLP Analog Input Input of SBAD Signal after LPF for DEFECT Detection 77 DEFECT Digital Output (TTL) Output of DEFECT Signal 16 SHPC Analog Output External Capacitor Connection for Peak Hold of RFRP Signal 17 RFZC1VC Analog Output Reference Voltage for RFRP Peak/Bottom Hold 18 SHBC Analog Output External Capacitor Connection for Bottom Hold of RFRP Signal 78 TRON Digital Input (TTL) Input of Seeking ON Control Signal 64 RFZC Digital Output (TTL) Output of RF Zero Crossing Binary Signal EQRF (RF Equalizer Filter and Data Slicer) & RRF Circuit 82 EQBIAS Analog Output External Bias Connection for Circuits in EQRF Block 83 OSTCC Analog Output External Capacitor Connection for Offset Cancellation Circuit of Equalizer Output 84 RFAGCC Analog Output External Capacitor Connection for RF AGC in EQRF Block 88 EQRF Analog Output Output of RF EFM Signal after Equalizer Filter 51 DEFM Digital Output (TTL) Binary Output of EFM Signal after Slicing 52 XDEFM Digital Output (TTL) Binary Output of EFM Inversion Signal after Slicing 80 SLPFP Analog Input Input (+) of Auto Slicing Level 81 SLPFN Analog Input Input (-) of Auto Slicing Level 90 RRF Analog Output Output of Read RF Signal 35 RRFXLP Analog Output Low Pass Output of RRF Signal before Level Shift 86 RECDIN Analog Input Input of RF Signal for Recorded Area Detection
34 Pin Numbers Symbol Type Description 63 RECD1 Digital Output (TTL) Output of Recorded Area Detection Signal ROPC (Running OPC) Related Signals 92 WRF Analog Output Output of Write RF Signal 94 ROPCO Analog Output Output of Amplified B-Level of Write RF Signal 93 ROPCC Analog Input Vin(-) of Amplifier for Sampled B-Level of WRF Signal 55 H11T Digital Input (TTL) S/H Control Pulse of WRF Signal 59 ADCTG Digital Input (TTL) Digital Control Signal for S/H of WRF Signal APC (Auto Power Control for Laser) 20 FPDO Analog Input Input of Laser Monitor Voltage 19 FVREF Analog Input Reference Voltage of APC Loops (2.0V) 73 RLDON Digital Input (TTL) Laser Diode Control for Read Mode 72 WLDON Digital Input (TTL) Laser Diode Control for Write Mode 54 RFPDSH Digital Input (TTL) S/H Control Pulse for Read APC Mode 53 WFPDSH Digital Input (TTL) S/H Control Pulse for Write APC Mode 27 RREF Analog I/O (1). Input of Power Setting Voltage for Read APC ; (2). Output of Read APC Reference Voltage Generated by Built-in DAC 29 VRDCN Analog Input Vin(-) of Midcourse Amplifier for Read APC Loop 28 VRDC Analog Output Midcourse Output of Laser Diode Controlling in Read Mode 34 VRDCO Analog Output Output Voltage of Laser Diode Controlling in Read APC 24 WREF1 Analog I/O (1). Input of Power Setting Voltage for Write APC 1; (2). Output of Write APC 1 Reference Voltage Generated by Built-in DAC 26 VWDC1N Analog Input Vin(-) of Midcourse Amplifier for Read APC 1 25 VWDC1 Analog Output Midcourse Output of Laser Diode Controlling in Write APC 1 33 VWDC1O Analog Output Output Voltage of Laser Diode Controlling in Write APC 1 21 WREF2 Analog I/O (1). Input of Power Setting Voltage for Write APC 2; (2). Output of Write APC 2 Reference Voltage Generated by Built-in DAC 23 VWDC2N Analog Input Vin(-) of Midcourse Amplifier for Write APC 2 22 VWDC2 Analog Output Midcourse Output of Laser Diode Controlling in Write APC 2 32 VWDC2O Analog Output Output Voltage of Laser Diode Controlling in Write APC 2 ATIP (Absolute Time In Pre-groove) 57 AGCON Digital Input (TTL) External ATIP AGC1/2 Enable Pin ( H :AGC ON; L :AGC Reset) 49 AGC1C Analog Output External Capacitor Connection for AGC1 in ATIP Block 48 AGC2C Analog Output External Capacitor Connection for AGC2 in ATIP Block 47 AGC3C Analog Output External Capacitor Connection for AGC3 in ATIP Block 50 ATFM Analog Output Output of Analog Wobble Signal 60 ATFG Digital Output (TTL) Digital Output of Wobble Signal after Slicing 58 WBLCLK Digital Input (TTL) External Clock Input for Wobble BPF (SCF) MPXOUT (Multiplexer Circuit for Various Signals) and Testing Interface 38 AUX1 Analog Input Auxiliary Input 1 for Signal Monitoring 37 AUX2 Analog Input Auxiliary Input 2 for Signal Monitoring 39 MPXOUT1 Analog Output Multiplexer Output 1 for Signal Monitoring 40 MPXOUT2 Analog Output Multiplexer Output 2 for Signal Monitoring 41 MPX2PHC Analog Output External Capacitor Connection for Peak Hold of MPXOUT2 Signal 42 MPX2BHC Analog Output External Capacitor Connection for Bottom Hold of MPXOUT2 Signal Serial Interface & Other Digital Control Signals 76 XTAT Digital Input (TTL) Latch Input for Register Setting
35 Pin Numbers Symbol Type Description 74 SCLK Digital Input (TTL) Clock Input for Register Setting 75 SDATA Digital I/O (TTL) Data Input/Output for Register Setting 79 XRST Digital Input (TTL) Digital Input for Register Resetting 66 MCLK Digital Input (TTL) Digital Input of Main Clock Reference Voltage and Power Supplies 44 VREF Analog Input Input of Reference Voltage (2.0V) 46 SUBGND Analog Ground Ground Pin for Substrate Bias of Internal Digital Circuitry 100 AVDD1 Analog Power Power Pin for Internal Analog Circuitry (5V) 1 AVSS1 Analog Ground Ground Pin for Internal Analog Circuitry 30 AVDD2 Analog Power Power Pin for Internal Analog Circuitry(5V) 31 AVSS2 Analog Ground Ground Pin for Internal Analog Circuitry 43 AVDD3 Analog Power Power Pin for Internal Analog Circuitry (5V) 45 AVSS3 Analog Ground Ground Pin for Internal Analog Circuitry 87 AVDD4 Analog Power Power Pin for Internal Analog Circuitry (5V) 85 AVSS4 Analog Ground Ground Pin for Internal Analog Circuitry 89 AVDD5 Analog Power Power Pin for Internal Analog Circuitry (5V) 91 AVSS5 Analog Ground Ground Pin for Internal Analog Circuitry 69 DVDD1 Digital Power Power Pin for Internal Digital Circuitry (5V) 71 DVSS1 Digital Ground Ground Pin for Internal Digital Circuitry 65 DVDD2 Digital Power Power Pin for Digital I/O Pads Buffer Circuitry (5V) 67 DVSS2 Digital Ground Ground Pin for Digital I/O Pads Buffer Circuitry
36 IC201(MT1501) : CD-R/RW Encoder/Decoder/Write Strategy Chip Block Diagram RA[11:0] RD[15:0] CASH#/RWEH# CLK CKE ROE# RAS# CAS# RWE# DQML BA0 BA1 UA8~UA10 UA14 UA15 UPSEN#/IO3 UALE/UA7 UAD[7:0] URST UINT0# UINT1# UWR# URD# FLASH_WE#/IO4 FLASH_OE#/IO5
16 8 12
uP Interface Logic & Buffer Memory Controller ADGO Flash Controller High Speed Audio ABCK ALRCK Playback ASDATA Logic ACLK
SBSO Subcode WFCK FIFO/ SUB EXCK Parallelizer
DSP_CS# RSPC LRCK DSP Decoding & SDATA Interface Encoding BCK Logic Logic C2PO
WSR_ENBL WSR_WXR Write CIRC Encoder & WSR_ODON strategy EFM Modulation & WSR_CSCEN Interface Subcode generator WSR_CMOD Logic WSR_CFREQ
AGCON Wobble DEVSEL FMCK/IO2 Signal DASP# FMDT/IO1 Interface FM Demodulator & ATIP Sync Protection & CS3FX# ATFG Logic Bi-Phase data CRC check & CS1FX# HA[2:0] RelDemodulator VersiTarget MSF Search 3 FG PDIAG# GAINUP Host IOCS16# MIRR/RFZC Interface INTRQ DMACK# XCLK Wobble Logic XDATA IORDY Spindle CLV XLAT ASP DIOR# Control XRST Control DIOW# DMARQ RLDON Interface HD[15:0] 16 SERVSH/WG Logic HRST# WBLSH RFPDSH/EFMDATA AK_DECEFM WFPDSH/EFMCLK WLDON From uP IPLL To EFM DECEFM Time to Digital (System IPLLVDD Jitter Metter H11T Converter clock IPLLVSS
TRON_IN synthesizer) HRFZC XTOR SERVO Lasor Power OPC & ROPC 9 MISC FLAG_[8:0]/UA[6:0] Control Computation XTAND/IO0 Status Interface TEST_MODE RECD1 Logic Unit Detection Logic PRST# RC/IO6 Circuit MCLK SLHOLD Reference Voltage EFMPLL DAC Generator & X'tal Clock (efmclk Control WDMO Control ADC Control Logic Generator synthesizer) Logic Logic
4 3 REFT XTALI XTALO WDMO VREFO BGVSS BGVDD DLLVSS DLLVDD V2REFO DACVSS DACVDD RDMO_IN ADCVSS1 ADCVSS2 ADCVDD1 ADCVDD2 EFMVCOIN ADC_IN[2:0] EFMPLLVSS EFMPLLVDD EFMLPFGND DAC_OUT[3:0]
37 PIN DESCRIPTION
Pin Numbers Symbol Type Description DSP interface 2 C2PO TTL Input, SMT, C2 error pointer. Active high when errors occur after CIRC C2 50K pull-up correction. 3 SBSO TTL Input, SMT, Subcode serial data input. Supplies the serial Subcode data from 50K pull-up DSP. The Subcode is stored in the order of P–W. 4 WFCK TTL Input, SMT, Subcode frame clock input. The active-high signal is used to 50K pull-up indicator the Subcode frame header. 5 SUB TTL Input, SMT, Subcode sync input. The active-high signal indicates the position 50K pull-up of a Subcode SYNC pattern. 6 EXCK TTL Input, SMT, External clock. This input signal is a clock from the DSP for 50K pull-up reading the serial Subcode data. 8 FG TTL Input, SMT, Motor Hall sensor input. 50K pull-up 12 TRON_IN TTL Input, SMT, On track indicator. The active-high input signal is a indicator used 50K pull-up to point the tracking servo is on track. 13 HRFZC TTL Output, RF ripper zero crossing signal output. Slew rate 205 DSP_CS# TTL Output DSP chip select. 206 LRCK TTL Input, SMT, L/R channel indicator. A logical low indicates L channel 16-bit data 50K pul -up and high. indicates R channel 16-bit data. 207 SDATA TTL Input, SMT, Serial data input. The serial input is used for receiving the digital 50K pull-up data after CIRC correction of DSP. 208 BCK TTL Input, SMT, Bit clock input. The signal clocks the serial data on the SDATA 50K pull-up input. Proper synchronization between LRCK and BCK is necessary. Audio Output Interface 9 ABCK TTL Output Audio bit clock output. The signal clocks the serial data on the ASDATA output. Data on the ASDATA signal shall be latched by an audio DAC at the rising edge of ABCK. 10 ALRCK TTL Output Audio L/R channel indicator. The signal is the audio left and right channel clock which indicates the data on ASDATA is from left or right channel. 11 ASDATA TTL Output Audio serial data output. The signal is the audio serial data output which supplies the serialized audio sample. 194 ACLK TTL I/O DSP main clock input or output. (33.8688M Hz) The ACLK function is determined by the “AGCON” status during power-on stage. And can be changed by the “ACLKOUT_SEL” bit of ATIP “MISCCTL” (0x70) command. 134 ADGO TTL I/O, SMT, Digital Audio Output. The signal is the Digital Audio Output which Slew rate, supplies the IEC-958 digital audio data. 50K pull-up Alternate function : CPU type selection input during power-on stage. A logical low input indicates an address/data bus separated type CPU (eg. H8) is used. A logical high input indicates an address/data bus multiplexed type CPU (eg. 8051, 8032) is implemented. Write Strategy Interface 14 WSR_ENBL CMOS Output Laser diode enable signal output
38 15 WSR_WXR CMOS Output, Laser diode write power control output. (Write/Read mode SW Slew rate signal) 16 WSR_ODON CMOS Output, Laser diode over drive control output. (Over drive control SW Slew rate signal) 18 WSR_OSCEN CMOS Output, High frequency modulation enable signal output. (Module control Slew rate SW signal) 19 WSR_CMOD CMOS Output, High frequency modulation mode selection signal output. Slew rate 20 WSR_CFREQ CMOS Output, Frequency selection signal output. Slew rate RF Interface 22 XLAT CMOS Output Latch signal output for RF register setting. 23 XDATA CMOS Output Data signal output for RF register setting. 24 XCLK CMOS Output Carrier clock signal output for RF register setting. 25 SLHOLD CMOS Output RF slice level hold control signal. 26 RLDON CMOS Output Read laser diode on control signal. 27 WLDON CMOS Output Write laser diode on control signal. 28 WFPDSH CMOS Output, Sample pulse control signal for RF write APC. /EFMCLK Slew rate Alternate function : Recording EFM clock output. 29 RFPDSH CMOS Output Sample pulse control signal for RF read APC. /EFMDATA Alternate function : Recording EFM data output. 31 WBLSH CMOS Output Sample pulse for wobble signal. 32 SERVSH CMOS Output Sample pulse for servo signal (main beam/ side beam) /WG Alternate function : Write gate enable signal. 33 DECEFM TTL Input, SMT1 Slicing EFM signal input. 35 MCLK CMOS Output RF main clock output. (34.5744M Hz) Slew rate 36 MIRR/RFZC TTL Input, SMT RF mirror signal input. 37 RC/IO6 TTL I/O, Slew rate, RF radial contrast signal input. 50K pull-down Alternate function : Programmable bi-directional I/O. 38 RECD1 TTL Input, SMT Recorded area detection signal input. Active high when the pick- up head is in recorded area. 39 XTAND/IO0 TTL I/O, SMT Off track detection signal input. Alternate function : Programmable bi-directional I/O. 40 XTOR TTL Input, SMT Tracking amplitude signal input. 41 ATFG TTL Input, SMT Digital wobble signal (22.05 ± 1 K Hz) input 42 FMDT/IO1 TTL I/O, SMT, FM digital data (Bi-phase data) input. Slew rate, 50K pull-up 44 FMCK/IO2 TTL I/O, Slew rate, FM demodulation PLL clock (Bi-phase clock) input. 50K pull-up 45 AGCON CMOS I/O Wobble AGC circuit enable control output. 50K pull-down Alternate function : ACLK function selection input during power-on stage. A logical low input indicates ACLK is a 33.8688M Hz clock input for the clock synchronization of high-speed audio playback. A logical high input indicates ACLK is as 33.8688M Hz clock output to provide main clock for DSP chip (MT1505). 46 GAINUP CMOS Output CD-RW media RF gain-up control output.
39 47 H11T TTL Output, EFM 11T indicator for ROPC sampling. Slew rate EFMPLL VCO Interface 48 EFMPLLVDD Analog VDD Power pin for EFMPLL VCO circuitry. 49 EFMVCOIN Analog input EFMPLL VCO input. 50 EFMPLLVSS Analog VSS Ground pin for EFMPLL VCO circuitry. 51 EFMLPFGND Analog input EFMPLL LPF ground input. DLL (Delay Lock Loop) Interface 52 DLLVSS Analog Ground Ground pin for DLL circuitry. 53 DLLVDD Analog Power(5V) Power pin for DLL circuitry. DAC Interface 54 DACVDD Analog Power(5V) Power pin for DAC circuitry. 55 ~ 58 DAC_OUT0 ~ Analog output DA converter output. (10-bit resolution) DAC_OUT3 59 DACVSS Analog Ground Ground pin for DAC circuitry. ADC Interface 61, 62, 63 ADC_IN0 ~ Analog Input AD converter inputs that want to perform analog to digital ADC_IN2 conversion. (8-bit resolution) 66 REFT Analog Output ADC reference ladder top. 64, 65 ADCVDD1, Analog Power(5V) Power pin for ADC circuitry. ADCVDD2 60, 67 ADCVSS1, Analog Ground Ground pin for ADC circuitry. ADCVSS2 Reference Voltage Interface 68 BGVSS Analog Ground Ground pin for reference voltage generation circuitry. 69 VREFO Analog output 2V reference voltage output. 70 V2REFO Analog output 4V reference voltage output. 71 BGVDD Analog Power(5V) Power pin for reference voltage generation circuitry. DMO Interface 73 RDMO_IN Analog input Reading path DMO input from DSP. 74 WMDO Analog output Spindle motor PWM control output. Miscellaneous Interface 76 PRST# CMOS Input, SMT Power on reset input, low active. 77 TEST_MODE TTL Input, Test mode enable pin, high active. A logical high sets MT1501 50K pull-down enter test mode. An internal pull-down resistor sets MT1501 in normal operation mode when this pin is floating. 80, 82 FLAG_8, TTL I/O, Internal flag monitor output. FLAG_7 Slew rate, 2nd function : GPIO function. 50K pull-up 3rd function : External ADC interface
40 83, 85, 86, FLAG_6/UA6 ~ TTL I/O, Internal flag monitor output. 88~91 FLAG_0/UA0 Slew rate, 2nd function : Address bus bit 6 ~ bit 0 input during address/ data 50K pull-up bus separated type CPU (eg. H8) application. (FLAG_0 ~ FLAG_6) 3rd function : Address bus bit 11 ~ bit 13, bit 16 and bit 17 output during IDE flash programming mode. (FLAG_0 ~ FLAG_4) 4th function : GPIO function. 5th function : External ADC interface. For detail information, please reference to the ”ATI P Regi st er Definition” manual. Crystal Interface 78 XTALI Input X`tal input. The working frequency is 34.5744 MHz. 79 XTALO Output X`tal output. IPLL VCO Interface 104 IPLLVSS Ground Ground pin for IPLL VCO circuitry. 105 IPLLVDD Analog power(5V) Power pin for IPLL VCO circuitry. Host Interface 92 HRST# TTL Input, SMT, Host reset input. The active-low input is referred to as hardware 50K pull-up reset and is used to reset this chip. 113, 110, 108, HD15 ~ HD0 TTL I/O, SMT, Host Data bus. This is the 8-bit or 16-bit bi-directional data bus to 106, 101, 99, Slew rate, PDR, the host. The lower 8 bits, HD0–HD7, are used for 8-bit data 96, 94, 93, PPU, PPD transfers. Normally data transfers are 16-bit wide. 95, 98, 100, Note : All pins except HD7 (no any pull) may be selectively 103, 107, 109, pull-up or pull-down with 20K resistant. 111 114 DMARQ TTL Output DMA request. This signal is used for DMA data transfers between host and device and it shall be asserted by the MT1501 when it is ready to transfer data to or from the host. The direction of data transfer is controlled by DIOR# and DIOW#. 115 DIOW# TTL Input, SMT, Device I/O write. Stop ultra DMA burst. 50K pull-up For Device I/O Write, this signal is the strobe signal asserted by the host to write device register or the data port. For Stop Ultra DMA, this signal shall be negated by the host before data is transferred in an Ultra DMA burst and is asserted by host during an Ultra DMA burst to signal the termination of Ultra DMA burst. 116 DIOR# TTL Input, SMT, Device I/O read. Ultra DMA ready. Ultra DMA data strobe. 50K pull-up For Device I/O Read, this signal is the strobe signal asserted by the host to read device registers or the data port. For Ultra DMA ready, this is asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in burst to the host. For Ultra DMA data strobe, this signal is the data out strobe signal from the host for an Ultra DMA data out burst
41 118 IORDY TTL Output, SMT, I/O Channel Ready. Ultra DMA ready. Ultra DMA data strobe. Slew rate, PDR For I/O channel Ready, this signal is negated to extend the host transfer cycle of any register read or write when the device is not able to complete the transfer. For Ultra DMA Ready, this signal is asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out bursts from the host. For Ultra DMA data strobe, this is the data in strobe signal from device for Ultra DMA data in burst to the host. 119 DMACK# TTL Input, SMT, DMA Acknowledge. This signal shall be used by the host in 50K pull-up response to DMARQ to acknowledge that it is ready for DMA transfers. 120 INTRQ TTL I/O, Device Interrupt. This signal is used to interrupt the host system. Slew rate INTRQ is driven only when this chip is addressed. When not driven, INTRQ is in a high impedance state. 121 IOCS16# TTL Output, Device 16-BIT I/O. In PIO transfer modes 0, 1, and 2, IOCS16# Open-Drain indicates to the host system that the 16-bit data port has been addressed and that the device is prepared to send or receive a 16-bit data word. 124 PDIAG# TTL I/O, Passed Diagnostics. This signal is asserted by Device 1 to 50K pull-up indicate to Device 0 that it has completed diagnostics. 126, 123, 125 HA2, HA0, HA1 TTL Input, SMT, Device Address. This is the 3-bit binary coded address provided 50K pull-up by the host to access an ATA register or data. 128 CS1FX# TTL Input, SMT, Device Chip Select 0 (for 1Fxh/17xh). This is the chip select signal 50K pull-up from the host to select the Command Block Registers. 129 CS3FX# TTL Input, SMT, Device Chip Select 1 (for 3Fxh/37xh). This is the chip select signal 50K pull-up from the host to select the Control Block Registers. 130 DASP# TTL I/O, Device Active / Device 1 Present. This is a time-multiplexed signal 50K pull-up that indicates that a device is active, or that Device 1 is present. 132 DEVSEL TTL Input, SMT, Device Select. Cleared to zero indicates the driver is master 50K pull-up device. Set to one indicates the driver is slave device. Buffer Memory Interface 141 BA1 3.3V CMOS SDRAM bank address 1 signal. For SDRAM application only. Output, When 4-bank SDRAM is used, this pin is used to select bank2 and Slew rate, PDR bank3 space and musts connect to “BA1” pin of SDRAM. When two 2-bank SDRAM are used, this pin is used as “Chip Select” signal output for second SDRAM and musts connect to “CS#” pin of second SDRAM. 142 BA0 3.3V TTL Output, SDRAM bank address 0 signal. For SDRAM application only. Slew rate, PDR 153 DQML 3.3V CMOS2 SDRAM low-byte data output mask control signal, high active. For Output, SDRAM application only. Slew rate, PDR3
42 154 RWE# 3.3V CMOS RAM Write Enable/RAM Write Enable Low. RAM write enable Output, signal, low active. When two write enable pins are used, it is the Slew rate, PDR Write Enable Low signal for writing the lower bytes of a two-WE_ 16-bit RAM. For SDRAM application, this pin is dedicated for “Write Enable” usage. 155 CAS# 3.3V CMOS Column Address Strobe Low / Column Address Strobe. When two Output, column address strobe pins are used, this pin is the Column Slew rate, PDR Address Strobe Low signal for accessing the lower bytes of a two-CAS# 16-bit RAM. When an 8-bit DRAM is used, this pin shall be connected to CAS# of the DRAM. For SDRAM application, this pin is “column address strobe” signal output connected to SDRAM. 156 RAS# 3.3V CMOS RAM Row Address Strobe. This active-low output is the Row Output, Address Strobe signal to the RAM. Slew rate, PDR For SDRAM application, this pin is “row address strobe” signal output connected to SDRAM. 157 ROE# 3.3V CMOS RAM Output Enable, low active. Output, For SDRAM application this pin is "Chip Select"signal output Slew rate, PDR connected to “CS#” pin of SDRAM. When two 2-bank SDRAM are used, this pin musts connect to “CS#” pin of first SDRAM. 168 CASH#/ 3.3V CMOS Column Address Strobe High / RAM Write Enable High. When a RWEH# Output, 16-bit DRAM is used, this active-low pin functions as Column Slew rate, PDR address Strobe High for accessing the upper bytes of a two-CAS# RAM, or. as Write Enable High for writing the upper bytes of a two-WE# RAM. For SDRAM application, this pin is changed to DQMH and is used to as SDRAM high-byte data mask control signal, high active. 169 CLK 3.3V CMOS SDRAM clock output. For SDRAM application only. Output, Slew rate, PDR 170 CKE 3.3V CMOS SDRAM clock enable signal output. For SDRAM application only. Output, Slew rate, PDR 158, 159, 160, RD15 ~ RD0 3.3V CMOS I/O, RAM Data bus. These pins are the bi-directional upper Buffer RAM 161, 162, 164, Slew rate, PDR, data bus to the external buffer memory. 165, 167, 143, PPU4, PPD5 144, 145, 146, 147, 148, 150, 151 171, 140, 172, RA11~ RA0 3.3V CMOS RAM address bus. 173, 174, 175, Output, 176, 177, 136, Slew rate, PDR 137, 138, 139 Microcontroller Interface 179 URD# TTL Input, SMT, Microcontroller read strobe signal, low active. 50K pull-up
43 180 UWR# TTL Input, SMT, Microcontroller write strobe signal, low active. 50K pull-up 182 UINT1# TTL Output, Interrupt 1 signal output, low active. Open-Drain 183 UINT0# TTL I/O, SMT, Interrupt 0 signal output, low active. Slew rate, Alternate function : ROM chip select input during 50K pull-up microcontroller flash programming mode. A logical low signal indicates to select flash ROM data for read cycle. And a logical high indicates to select non-flash ROM data for read cycle. 184 URST TTL Output Microcontroller reset signal output, high active. 185, 186, 188, UAD0 ~ UAD7 TTL I/O, Microcontroller address/data buses interface. Address and data 189, 190, 191, Slew rate, are multiplexed by microcontroller and used ALE pin to separate 192, 193 50K pull-up address and data bus. 195 UALE/UA7 TTL Input, SMT, Address latch enable input, high active. 50K pull-up Alternate function : Address bus bit 7 input during address/data bus separated type CPU (eg. H8) application. 197 UPSEN#/IO3 TTL I/O, SMT, External ROM output port enable signal input, low active. Slew rate, Alternate function : Programmable bi-directional IO3. For non- 50K pull-up flash ROM application, the pin can be programmed as GPIO function. 198, 200 UA15, UA14 TTL I/O, Address bus bit 15 and14 input. Slew rate, Alternate function : Address bus bit 15 and 14 output during 50K pull-up IDE flash programming mode. 199 FLASH_WE# TTL I/O, Flash memory write enable signal output, low active. /IO4 Slew rate, Alternate function : Programmable bi-directional IO4. For non- 50K pull-up flash ROM application, the pin can be programmed as GPIO function. 201, 202, 204 UA8, UA9, TTL I/O, Address bus bit 10, 9 and 8 input. UA10 Slew rate, Alternate function : Address bus bit 10, 9 and 8 output during 50K pull-up IDE flash programming mode. 203 FLASH_OE# TTL I/O, Flash memory output enable signal output, low active. /IO5 Slew rate, Alternate function : Programmable bi-directional IO5. For non- 50K pull-up flash ROM application, the pin can be programmed as GPIO function. Power Supply 7, 30, 43, DGND Ground Ground pin for general pad buffer circuitry. 84,187 1, 34, 87, 196 DVDD Power (5V) Power pin for general pad buffer circuitry. 21, 133, 181 DVDD3 Power (3.3V) Power pin for internal digital circuitry. 17, 81, 131, 178 DGND Ground Ground pin for internal digital circuitry. 152, 166 DVDD3 Power (3.3V) Power pin for RAM pad buffer circuitry. 149, 163 DGND Ground Ground pin for RAM pad buffer circuitry. 97, 112, DGND Ground Ground pin for Host pad buffer circuitry. 122,135 102, 117, 127 DVDD Power (5V) Power pin for Host pad buffer circuitry. 72 W_DVDD Power (5V) Power pin for internal fully digital circuitry. 75 W_DGND Ground Ground pin for internal fully digital circuitr
44 IC301 (MT1505) : DSP/Servo Controller/up chip Block Diagram ADCVDD SCO RFDTSLV ADCVSS RFI RFIS FEI CSI TEI TEZILP SBAD DEFECT PDMVDD FOO TRO PDMVSS PWM2VREF PWMVREF DMO ENDM FMO FMO2 FG PRST_ TRCLOSE TROPEN 111 119 118 117 116 115 114 113 112 110 128 127 126 125 124 123 122 121 120 109 108 107 106 105 104
RFRO 1 102 DVDD3 RFRPSLV 2 101 LIMIT_ PDM & HRFZC 3 RFRP 100 TRAYOUT_ PWM RFBIAS 4 Servo Data Circuit 99 TRAYIN_ ADC DAC VBDPLL 5 Slicer 98 DGND PLLVSS 6 Circuit 97 LDE LPIO 7 96 TEST LPIN 8 95 ICEMODE Mega LPFO 9 Interface 94 IO3 LPFN 10 Data PLL CLV& Zone- 93 IO2 Sync and IREF 11 CLV & True- 92 IO1 Protection GPIO PDO 12 CAV Control Control 91 IO0 PLLVDD 13 90 DSEFM/O5 DVDD5 14 89 UP1_7/MUTE TRON 15 EFM & Q-code 88 UP1_6/GSW Demodulation ASDATA 16 87 UP1_5/CB ALRCK 17 86 UP1_4/APCSW DGND 18 85 UP1_3 ABCK 19 84 UP1_2/AKXRST Audio CIRC Error EXCK 20 Subcode Processing 83 UP1_1 Correction SBSY 21 FIFO/ Unit 82 PLAY_ WFCK 22 Parallelizer 81 EJECT_ SBSO 23 80 UP3_5/UT0 C2PO 24 79 UP3_4/UT0 BCK 25 78 UP3_1/UTXD SDATA 26 77 UP3_0/URXD LRCK 27 76 DGND UP2_5/UA13 28 75 UXI/O4 UP2_4/UA12 29 Over-sampling 74 DVDD5 UP2_3/UA11 30 8032 Digital Filter 73 UA7/OI5 UP2_2/UA10 31 Micro processor 72 UA6/OI4 UP2_1/UA9 32 71 UA5/OI3 UP2_0/UA8 33 70 UA4/OI2 UP2_6/UA14 34 Varipitch 69 UA3/OI1 X’tal Clock Clock UP2_7/UA15 35 DAC & 68 IA2/OI1 Generator Generator LPF UP1_0/UA16 36 67 UA1/O9 UPSEN_ 37 66 UA0/O8 UALE 38 65 DACVDD 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 LO RO XTALI DGND DGND XTALO HRST_ VPVSS DVDD5 DVDD3 VPVDD VCOCIN DACVSS DACVREF UP0_7/UAD7 UP0_6/UAD6 UP0_5/UAD5 UP0_4/UAD4 UP0_3/UAD3 UP0_2/UAD2 UP0_1/UAD1 UP0_0/UAD0 UP3_7/URD_ UP3_6/UWR_ UP3_2/UNIT0_ UP3_3/UNIT1_
45 •Pin Description
Pin Numbers Symbol Type Description
Data PLL Interface 5 VBDPLL Analog Output Reference voltage. 6 PLLVSS Anlog Ground Ground pin for data PLL and related analog circuitry. 7 LPIO Analog Output The output of VCO integrator. 8 LPIN Analog Input The negative input terminal of VCO integrator. 9 LPFO Analog Output The output of loop filter amplifier. 10 LPFN Analog Input The negative input terminal of loop filter amplifier. 11 IREF Analog Input Current reference input. It generate reference current for data PLL. Connect an external 15K resistor to this pin and PLLVSS. 12 PDO Analog Output Phase comparator output. Output the phase difference of EFM and Pck. Sink or (source) a constant current to loop filter over this pin when phase difference occurs. Otherwise, this pin is high impedance. 13 PLLVDD Analog Power(5V) Power for data PLL and related analog circuitry. 14 DVDD5 Power (5V) Power pin for analog digital circuitry. 18 DGND Ground Ground pin for analog digital circuitry. Decoder Interface 15 TRON TTL output, 4mA Seeking On, active high 16 ASDATA TTL inputmer 0 input. High Audio serial data input, 17 ALRCK TTL input High Audio serial LR input. 19 ABCK TTL input High Audio serial bit clock input. 20 EXCK TTL I/O output ,4mA Subcode data clock. This clock is used for reading/writing subcode data out through SBSO pin.. Default is output. 21 SBSY TTL output, 4mA Subcode block sync signal. This pin is high when S0 and S1 is detected. 22 WFCK TTL output, 4mA Frame sync signal. 23 SBSO TTL output, 4mA Subcode P-W data serial output. The subcode data are stored in internal buffer and wait for EXCK clock to read. 24 C2PO TTL output, 4mA C2 error pointer. Active high after CIRC C2 corrected is serially output over this pin. 25 BCK CMOS output, 8mA Serial bit clock output. 26 SDATA CMOS output, 8mA Serial data output. 27 LRCK CMOS output, 8mA L/R channel output. A logical low indicates L channel 16-bit data and high indicates R channel 16-bit data. 90 DSEFM/O5 TTL output, 4mA After data slicer EFM data Turbo 8032 Interface 89 ~ 83 UP1_[7:1] TTL I/O, Slew rate Programmable bi-directional I/O. 50K pull_up, 4mA 80 UP3_5/UT1 TTL I/O, Slew rate Programmable bi-directional I/O. 50K pull_up, 4mA Alternate function : T1. Timer 1 input. 79 UP3_4/UT0 TTL I/O, Slew rate Programmable bi-directional I/O. 50K pull_up, 4mA Alternate function : T0. Timer 0 input
46 78 UP3_1 TTL I/O, Slew rate Programmable bi-directional I/O. / UTXD 50K pull_up, 4mA Alternate function : TXD. Serial transmit data. 77 UP3_0 TTL I/O, Slew rate Programmable bi-directional I/O. / URXD 50K pull_up, 4mA Alternate function : RXD. Serial receive data. 75 UXI/O4 TTL otuput, Slew Microprocessor clock for ICE mode or general output O4 for non-ice rate, 8mA mode 73~ 66 UA[7:0] TTL I/O, Slew rate Lower address bus output for external device. / O[15:8] programmable Alternate function : Programmable output. 57 UP3_7 TTL I/O, Slew rate Programmable bi-directional I/O. / URD_ SMT, 50K pull_up, Alternate function : RD_. Data write signal. 4mA 56 UP3_6 TTL I/O, Slew rate Programmable bi-directional I/O. / UWR_ SMT, 50K pull_up, Alternate function : WR_. Data write signal. 4mA 54 UP3_3 TTL I/O, Slew rate Programmable bi-directional I/O. / UINT1_ 50K pull_up, 4mA Alternate function : INT1_. External interrupt 0. 53 UP3_2 TTL I/O, Slew rate Programmable bi-directional I/O. / UINT0_ 50K pull_up, 4mA Alternate function : INT0_. External interrupt 0. 43 ~ 50 UP0_[7:0] TTL I/O, Slew rate, Programmable bi-directional I/O. programmable / UAD[7:0] Alternate function : AD[7:0]. Lower address/data bus output for external device. 38 UALE TTL I/O, 50K Address latch enable output, active high. pull_up, 4mA Alternate function : Programmable GPIO. 37 UPSEN_ TTL I/O, 50K Programmable store enable output, active low. PSEN_ enables the pull_up, 4mA external ROM output port. Alternate function : Programmable output. 36 UP1_0 TTL I/O, Slew rate Programmable bi-directional I/O. / UA16 50K pull_up, 4mA Alternate function : A16. Address bit 16 output. 35, 34, 28, 29 UP2_[7:0] TTL I/O, Slew rate Programmable bi-directional I/O. 30, 31, 32, 33 / UA[15:8] programmable Alternate function : A[15:8]. Upper address bus input/output. 39 DVDD5 Power(5V) Power pin for output pad circuitry. 42 DGND Ground Ground pin for output pad circuitry. 51 DGND Ground Ground pin for internal digital circuitry. 55 DVDD3 Power(3.3V) Power pin for internal digital circuitry. 74 DVDD5 Power(5V) Power pin for output pad circuitry. 76 DGND Ground Ground pin for output pad circuitry. 98 DGND Ground Ground pin for internal digital circuitry. 102 DVDD3 Power(3.3V) Power pin for internal digital circuitry. Xtal Interface 40 XTALI Input Xtal input. The working frequency is 33.8688 MHz. 41 XTALO Output Xtal output. Varipitch VCO Interface 58 VPVDD Analog power(5V) Power pin for varipitch VCO circuitry. 59 VCOCIN Analog Input Connect capacitor for compensator loop filter.
47 60 VPVSS Ground Ground pin for varipitch VCO circuitry. Internal Audio Interface 61 DACVSS Ground Ground pin for internal DAC circuitry. 62 RO Analog Output Right channel of audio. 63 DACVREF Analog Output Reference voltage for external audio filter circuit. 64 LO Analog Output Left channel of audio. 65 DACVDD Analog Power(5V) Power pin for internal DAC circuitry. Reset Interface 52 URST TTL Input, SMT reset input. The active high input is used to reset MT1505. 105 PRST_ TTL Input, SMT Power on reset input, active low. Extended GPIO Interface 94 ~91 IO3~ IO0 TTL I/O, Slew rate, Programmable GPIO. 50K pull up, 4mA Mega Interface 81 EJECT_ TTLpull up input Eject/stop key input, active low. 82 PLAY_ TTL pull up input Play/pause key input, active low. 95 ICEMODE TTL pull down input ICE mode, active high 96 TEST TTL pull down input Test mode, active high 97 LED TTL Output, 4mA LED control output. Controlled by µP. 99 TRAYIN_ TTL pull up input Tray_is_in input, A logical low indicates the tray is in. Feedback flag from tray connector. 100 TRAYOUT_ TTL pull up input Tray_is_out input. A logical low indicates the tray is out. Feedback flag from tray connector. 101 LIMIT_ TTL pull up input Sledge inner limit input, active low. 103 TROPEN PWM/TTL output Tray open output. Controlled by µP. 104 TRCLOSE PWM/TTL output Tray close output. Controlled by µP. Motor and Actuator Driver Interface 106 FG TTL Input, SMT Motor Hall sensor input. 50K pull-up 107 FMO2 Analog Output Feed motor 2 control. PWM output.. 108 FMO Analog Output Feed motor control. PWM output. 109 ENDM TTL Output, 4mA Enable/disable disk motor. A logical high enables disk motor. 110 DMO Analog Output Disk motor control output. PWM output. 111 PWMVREF Analog Input A reference voltage input for PWM circuitry. A typical value of 2.0 v. 112 PWM2VREF Analog Input A reference voltage input for PWM circuitry. A typical value of 4.0 v. 113 PDMVSS Ground Ground for PDM circuitry. 114 TRO Analog Output Tracking servo output. PDM output of tracking servo compensator. 115 FOO Analog Output Focus servo output. PDM output of focus servo compensator 116 PDMVDD Analog Power(5V) Power for PDM circuitry. Signal Amplifier Interface 117 DEFECT Analog input Hardware detect Defect from Disk 118 SBAD Analog Input Sub beam add input(E+F)
48 119 TEZILP Analog Input Tracking error zero crossing low pass input 120 TEI Analog Input Tracking error input. 121 CSI Analog Input Central servo input. 122 FEI Analog Input Focus error input. 123 RFIS Analog Input RF ripple input. 124 RFI Analog Input RF signal input. 125 ADCVSS Ground Ground pin for ADC circuitry. 126 RFDTSLV Analog Output RF data slicer level output. 127 SCO Analog Output Analog slicer current output. 128 ADCVDD Analog Power(5V) Power pin for ADC circuitry. 1 RFRO Analog Output RF ripple detect output 2 RFRPSLV Analog Output RF ripple slice level output. 3 HRFZC Analog Input High frequency RF ripple zero crossing. 4 RFBIAS Analog Input RF ripple bias adjustment input.
49 IC501 (M63024FP): Spindle Motor and 5ch Actuator Driver
Block Diagram VM1 RSP U V W RSL1 SL1+ SL1- VM2 RSL2 SL2+ SL2-
FG x3 ss s s FG Reverse Detect
FG HU+ HU- 120 Logic Logic HV+ MATRIX HV- HW+ HW- Hall Bias CTL Current CTL Current amp. comp. amp. comp. CTL Current amp. comp. TSD
Direction Direction BIAS MU1 SPIN comp. comp. Direction comp. Brake select MU2 REF Frequency OCS SL1IN generator VM1 SL2IN 5V power supply FOIN 5VCC Regulator TOIN Reg LOIN+
VM3
Tracking Focus LO-
x8 LO+ x5 x5 TO- FO- TO+ FO+ GND
50 • Pin Description
Terminal Symbol Terminal function Terminal Symbol Terminal function 1 SL1IN Slide control voltage input1 22 VM1 Motor Power Supply1 ( for Spindle) 2 SL2IN Slide control voltage input2 23 HB Bias for Hall Sensor 3 VM2 Motor Power Supply2(for Slide) 24 FG Frequency generator output 4 RSL2 Slide current sense2 25 REF Reference voltage input 5 SL2+ Slide non-inverted output2 26 SPIN Spindle control voltage input 6 SL2- Slide inverted output2 27 FOIN Focus control voltage input 7 GND GND 28 TOIN Tracking control voltage input 8 RSL1 Slide current sense1 29 GND GND 9 SL1+ Slide non-inverted output1 30 TO- Tracking inverted output 10 SL1- Slide inverted output1 31 TO+ Tracking non-inverted output 11 GND GND 32 5VCC 5V Power Supply (for FS, TS) 12 W Motor drive output W 33 GND GND 13 V Motor drive output V 34 FO+ Focus non-inverted output 14 U Motor drive output U 35 FO- Focus inverted output 15 RSP Spindle current sensie 36 LO+ Loading non-inverted output 16 HW- HW- sensor amp. Input 37 LO- Loading inverted ouput 17 HW+ HW+ sensor amp. input 38 MU2 mute / break select terminal2 18 HV- HV- sensor amp. input 39 VM3 Power Supply3 (for Loading) 19 HV+ HV+ sensor amp. input 40 LOIN+ Loading control input(+) 20 HU- HU- sensor amp. input 41 MU1 mute / break select terminal 1 21 HU+ HU+ sensor amp. input 42 OSC PWM carrier oscilation set
• Channel select function
Logic control Drive channel Brake select MU1 MU2 Loading Slide1 Slide2 Forcus Tracking Spindle (SPIN 51 DISASSEMBLY 1. CABINET and CIRCUIT BOARD 1-3. Cabinet and Main Circuit Board A. Remove the Cabinet in the direction of arrow (4). DISASSEMBLY (See Fig. 1-3) 1-1. Bottom Chassis B. Release 2 hooks (a) and remove the CD Tray A. Release 4 screws (A) and remove the Bottom Chassis drawing forward. in the direction of arrow (1). (See Fig.1-1) C. Remove the Main Circuit Board in the direction of arrow (5). D. At this time, be careful not to damage the 4 connectors, are positioned at bottom or right side, of the Main Circuit Board. Cabinet (1) Hooks (a) (4) (A) Bottom Chassis (5) (A) (A) (A) Main Fig. 1-1 Circuit Board 1-2. Front Bezel Assy A. Insert and press a rod in the Emergency Eject Fig. 1-3 Hole and then the CD Tray will open in the direction of arrow (2). B. Remove the Tray Door in the direction of arrow 2. MECHANISM ASSY DISASSEMBLY (3) by pushing the stoppers forward. C. Release 3 stoppers and remove the Front Bezel Assy. 2-1. Pick-up Unit A. Release screw (B). B. Separate the Pick-up Unit in the direction of arrow (6). Tray Door (B) (B) (3) Stoppers (6) Pick-up Unit (2) CD Tray Front Bezel Assy Emergency Eject Hole Mechanism Assy Fig. 1-2 Fig. 2-1 8 2-2. Pick-up A. Release 1 screw (C) and remove the Pick-up. Pick-up Unit (C) (C) Pick-up Fig. 2-2 9 035 004 005 013 5 EXPLODED VIEW 008 006 014 009 015 PBM00 (MAIN C.B.A) 4 012 016 PBF00 (FRONT C.B.A) A01 010 400 3 011 031 001 034 026 027 007025 030 430 2 030 419 A02 021 400 029 413 430 028 400 003 021 413 413 002 050 020 033 032 413 017 400 1 400 020 A B C D E F GH 11 12