Station Designer Software User Guide, 51

Total Page:16

File Type:pdf, Size:1020Kb

Station Designer Software User Guide, 51 Station Designer Software User Guide Doc. No.: 51-52-25-149 Revision: 12 Date: April 2021 Honeywell Process Solutions Notices and Trademarks Copyright 2021 by Honeywell Revision 12, April 2021 Warranty/Remedy Honeywell warrants goods of its manufacture as being free of defective materials and faulty workmanship. Contact your local sales office for warranty information. If warranted goods are returned to Honeywell during the period of coverage, Honeywell will repair or replace without charge those items it finds defective. The foregoing is Buyer's sole remedy and is in lieu of all other warranties, expressed or implied, including those of merchantability and fitness for a particular purpose. Specifications may change without notice. The information we supply is believed to be accurate and reliable as of this printing. However, we assume no responsibility for its use. While we provide application assistance personally, through our literature and the Honeywell web site, it is up to the customer to determine the suitability of the product in the application. Honeywell Process Solutions 1250 W Sam Houston Pkwy S Houston, TX 770424 ControlEdge HC900, 559 and 1042 are U.S. registered trademarks of Honeywell Other brand or product names are trademarks of their respective owners ii Station Designer User’s Guide Revision 12 April 2021 About This Document About This Document Abstract This manual describes the setup and operation of Station Designer Software for configuring 900 Control Stations for use with ControlEdge HC900 controllers. References The following list identifies all documents that may be sources of reference material discussed in this publication. Document Title Doc ID ControlEdge HC900 Control Station Installation 51-52-33-147 900 Control Station Specification 51-52-03-46 Legacy ControlEdge HC900 Controller Installation and User Guide 51-52-25-107 900 Control Station User Guide 51-52-25-148 Process Control Designer User Guide 51-52-25-110 Process Control Designer Function Block Reference Guide 51-52-25-109 ControlEdge HC900 Controller Communications User Guide 51-52-25-111 ControlEdge HC900 Controller Redundancy Overview & System Operation 51-52-25-133 Revision Information Document Name Revision Number Publication Date This manual … 51-52-25-149 Station Designer Software 1st release Revision 2 October 2009 Configuring Setpoint Programmer - updated Revision 3 March 2010 RS485 Serial Comms - updated Revision 4 October 2010 USB 3.0 support is only available on the 900CS10 Emulator function is not supported on Microsoft Revision 5 March 2013 64bit OS (for both 900CS10, 900CS15) Seattle updates Revision 6 September 2013 PDF Viewer added Revision 7 January 2014 Updated “HC900” to “ControlEdge HC900”, Revision 8 April 2018 Configuring SMS added Added “How to configure an FTP Server on a PC with Revision 9 March 2019 Widows 7” R700 Updates Revision 10 November 2019 R710 Updates Revision 11 September 2020 Split Rack Redundancy_R720 Revision 12 April 2021 Revision 12 Station Designer User’s Guide iii April 2021 About This Document Support & Contact Information For Europe, Asia Pacific, North and South America contact details, refer to the back page of this manual or the appropriate Honeywell Solution Support web site: Honeywell Organization WWW Address (URL) Corporate http://www.honeywell.com Honeywell Process Solutions http://www.hpsweb.honewell.com/ps HPS Technical tips http://hpsweb.honeywell.com/Cultures/en- US/Products/Instrumentation/hybrid/hc900/TechnicalT ips/documents.htm Telephone and Email Contacts Area Organization Phone Number United States and 1-800-343-0228 Customer Service Honeywell Inc. Canada 1-800-423-9883 Global Technical Support Email: (Sales) [email protected] Global Email Support Honeywell Process Solutions or (TAC) [email protected] Revision 12 Station Designer User’s Guide iv April 2021 Symbol Definitions The following table lists those symbols that may be used in this document to denote certain conditions. Symbol Definition This DANGER symbol indicates an imminently hazardous situation, which, if not avoided, will result in death or serious injury. This WARNING symbol indicates a potentially hazardous situation, which, if not avoided, could result in death or serious injury. This CAUTION symbol may be present on Control Product instrumentation and literature. If present on a product, the user must consult the appropriate part of the accompanying product literature for more information. This CAUTION symbol indicates a potentially hazardous situation, which, if not avoided, may result in property damage. WARNING PERSONAL INJURY: Risk of electrical shock. This symbol warns the user of a potential shock hazard where HAZARDOUS LIVE voltages greater than 30 Vrms, 42.4 Vpeak, or 60 Vdc may be accessible. Failure to comply with these instructions could result in death or serious injury. ATTENTION, Electrostatic Discharge (ESD) hazards. Observe precautions for handling electrostatic sensitive devices Protective Earth (PE) terminal. Provided for connection of the protective earth (green or green/yellow) supply system conductor. Functional earth terminal. Used for non-safety purposes such as noise immunity improvement. NOTE: This connection shall be bonded to protective earth at the source of supply in accordance with national local electrical code requirements. Earth Ground. Functional earth connection. NOTE: This connection shall be bonded to Protective earth at the source of supply in accordance with national and local electrical code requirements. Chassis Ground. Identifies a connection to the chassis or frame of the equipment shall be bonded to Protective Earth at the source of supply in accordance with national and local electrical code requirements. Revision 12 Station Designer User’s Guide v April 2021 Contents Contents Introduction/Overview ................................................................................. 1 How to use this manual .......................................................................................... 1 File Structure and Architecture .............................................................................. 1 Station Designer Layout Overview ......................................................................... 2 PC Communications .............................................................................................. 3 Getting Started ........................................................................................... 5 PC Requirements ................................................................................................... 5 ControlEdge HC900 Controller and 900 Control Station Setup ............................. 5 Using RS485 Serial Communications .................................................................. 13 Troubleshooting ................................................................................................... 16 Alternate Programming Method- Using TCP/IP To Program The Station ........... 17 Station Designer Basics ........................................................................... 25 Window Layout ..................................................................................................... 25 The Categories ..................................................................................................... 26 Getting Around ..................................................................................................... 28 Navigation Lists .................................................................................................... 29 Global Search ...................................................................................................... 30 Undo and Redo .................................................................................................... 30 Using Balloon Help ............................................................................................... 31 Working with Databases ...................................................................................... 31 Conversion of SDS database from 10 inch Display to 15 inch Display ............... 32 Downloading to a Device ..................................................................................... 40 Extracting Databases ........................................................................................... 41 Mounting the Flash memory ................................................................................ 41 Formatting the Flash memory .............................................................................. 42 Time and Date ...................................................................................................... 43 Remote Monitoring ............................................................................................... 43 Building Custom Displays ......................................................................... 45 Tag characters and conflicts ................................................................................ 45 Display Pages Navigation Pane ........................................................................... 46 Custom Displays 1 – 16 ....................................................................................... 46 Adding Custom Displays ...................................................................................... 47 Adding Signals to Displays .................................................................................. 48 Adding variables to displays ...............................................................................
Recommended publications
  • Podcast Ch23a
    Podcast Ch23a • Title: Bit Arrays • Description: Overview; bit operations in Java; BitArray class • Participants: Barry Kurtz (instructor); John Helfert and Tobie Williams (students) • Textbook: Data Structures for Java; William H. Ford and William R. Topp Bit Arrays • Applications such as compiler code generation and compression algorithms create data that includes specific sequences of bits. – Many applications, such as compilers, generate specific sequences of bits. Bit Arrays (continued) • Java binary bit handling operators |, &, and ^ act on pairs of bits and return the new value. The unary operator ~ inverts the bits of its operand. BitBit OperationsOperations x y ~x x | y x & y x ^ y 0 0 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 1 1 0 1 1 0 Bit Arrays (continued) Bit Arrays (continued) • Operator << shifts integer or char values to the left. Operators >> and >>> shift values to the right using signed or unsigned arithmetic, respectively. Assume x and y are 32-bit integers. x = 0...10110110 x << 2 = 0...1011011000 x = 101...11011100 x >> 3 = 111101...11011 x = 101...11011100 x >>> 3 = 000101...11011 Bit Arrays (continued) Before performing the bitwise operator |, &, or ^, Java performs binary numeric promotion on the operands. The type of the bitwise operator expression is the promoted type of the operands. The rules of promotion are as follows: • If either operand is of type long, the other is converted to long. • Otherwise, both operands are converted to type int. In the case of the unary operator ~, Java converts a byte, char, short to int before applying the operator, and the resulting value is an int.
    [Show full text]
  • Binary Index Trees a Cumulative Frequency Array Allows Us To
    Binary Index Trees A cumulative frequency array allows us to calculate the sum of the range of values in O(1), as long as there are no changes to the data once the queries start. But consider situations where we might change the value at an index in an array, then query for the sum of a range of values in the array, followed by some more changes and more queries. In this sort of situation, a cumulative frequency array would still give us O(1) query times, but it would take O(n) time to update after each change!!! (Basically, if we change one index in a cumulative frequency array, all other indexes above it would have to have this value added to it as well.) Here is a quick illustration: Current cumulative frequency array: Index 0 1 2 3 4 5 6 7 8 Value 2 4 4 4 6 8 11 13 17 Now, consider adding the value 2 to the data, recalling that index i stores the number of values less than or equal to i. The adjusted array is: Index 0 1 2 3 4 5 6 7 8 Value 2 4 5 5 7 9 12 14 18 We had to edit each index 2 or greater, which would take O(n) for a cumulative frequency array of size n. Thus, we want a new arrangement where both the query AND the update are relatively fast. The creative insight here is that perhaps if we store data in a different way, perhaps we can reduce the update time by quite a bit while incurring only a modest increase in query time.
    [Show full text]
  • B-Bit Sketch Trie: Scalable Similarity Search on Integer Sketches
    b-Bit Sketch Trie: Scalable Similarity Search on Integer Sketches Shunsuke Kanda Yasuo Tabei RIKEN Center for Advanced Intelligence Project RIKEN Center for Advanced Intelligence Project Tokyo, Japan Tokyo, Japan [email protected] [email protected] Abstract—Recently, randomly mapping vectorial data to algorithms intending to build sketches of non-negative inte- strings of discrete symbols (i.e., sketches) for fast and space- gers (i.e., b-bit sketches) have been proposed for efficiently efficient similarity searches has become popular. Such random approximating various similarity measures. Examples are b-bit mapping is called similarity-preserving hashing and approximates a similarity metric by using the Hamming distance. Although minwise hashing (minhash) [12]–[14] for Jaccard similarity, many efficient similarity searches have been proposed, most of 0-bit consistent weighted sampling (CWS) for min-max ker- them are designed for binary sketches. Similarity searches on nel [15], and 0-bit CWS for generalized min-max kernel [16]. integer sketches are in their infancy. In this paper, we present Thus, developing scalable similarity search methods for b-bit a novel space-efficient trie named b-bit sketch trie on integer sketches is a key issue in large-scale applications of similarity sketches for scalable similarity searches by leveraging the idea behind succinct data structures (i.e., space-efficient data structures search. while supporting various data operations in the compressed Similarity searches on binary sketches are classified
    [Show full text]
  • Compact Fenwick Trees for Dynamic Ranking and Selection
    Compact Fenwick trees for dynamic ranking and selection Stefano Marchini Sebastiano Vigna Dipartimento di Informatica, Universit`adegli Studi di Milano, Italy October 15, 2019 Abstract The Fenwick tree [3] is a classical implicit data structure that stores an array in such a way that modifying an element, accessing an element, computing a prefix sum and performing a predecessor search on prefix sums all take logarithmic time. We introduce a number of variants which improve the classical implementation of the tree: in particular, we can reduce its size when an upper bound on the array element is known, and we can perform much faster predecessor searches. Our aim is to use our variants to implement an efficient dynamic bit vector: our structure is able to perform updates, ranking and selection in logarithmic time, with a space overhead in the order of a few percents, outperforming existing data structures with the same purpose. Along the way, we highlight the pernicious interplay between the arithmetic behind the Fenwick tree and the structure of current CPU caches, suggesting simple solutions that improve performance significantly. 1 Introduction The problem of building static data structures which perform rank and select operations on vectors of n bits in constant time using additional o(n) bits has received a great deal of attention in the last two decades starting form Jacobson's seminal work on succinct data structures. [7] The rank operator takes a position in the bit vector and returns the number of preceding ones. The select operation returns the position of the k-th one in the vector, given k.
    [Show full text]
  • Efficient Data Structures for High Speed Packet Processing
    Efficient data structures for high speed packet processing Paolo Giaccone Notes for the class on \Computer aided simulations and performance evaluation " Politecnico di Torino November 2020 Outline 1 Applications 2 Theoretical background 3 Tables Direct access arrays Hash tables Multiple-choice hash tables Cuckoo hash 4 Set Membership Problem definition Application Fingerprinting Bit String Hashing Bloom filters Cuckoo filters 5 Longest prefix matching Patricia trie Giaccone (Politecnico di Torino) Hash, Cuckoo, Bloom and Patricia Nov. 2020 2 / 93 Applications Section 1 Applications Giaccone (Politecnico di Torino) Hash, Cuckoo, Bloom and Patricia Nov. 2020 3 / 93 Applications Big Data and probabilistic data structures 3 V's of Big Data Volume (amount of data) Velocity (speed at which data is arriving and is processed) Variety (types of data) Main efficiency metrics for data structures space time to write, to update, to read, to delete Probabilistic data structures based on different hashing techniques approximated answers, but reliable estimation of the error typically, low memory, constant query time, high scaling Giaccone (Politecnico di Torino) Hash, Cuckoo, Bloom and Patricia Nov. 2020 4 / 93 Applications Probabilistic data structures Membership answer approximate membership queries e.g., Bloom filter, counting Bloom filter, quotient filter, Cuckoo filter Cardinality estimate the number of unique elements in a dataset. e.g., linear counting, probabilistic counting, LogLog and HyperLogLog Frequency in streaming applications, find the frequency of some element, filter the most frequent elements in the stream, detect the trending elements, etc. e.g., majority algorithm, frequent algorithm, count sketch, count{min sketch Giaccone (Politecnico di Torino) Hash, Cuckoo, Bloom and Patricia Nov.
    [Show full text]
  • K-Mer Data Structures Rayan Chikhi CNRS, Univ
    k-mer data structures Rayan Chikhi CNRS, Univ. Lille, France CGSI - July 24, 2018 Baseline problem In-memory representation of a large set of short k-mers: e.g. ACTGAT GTATGC ATTAAA GAATTG ... (Indirect) applications ● Assembly ● Error-correction of reads ● Detection of similarity between sequences ● Detection of distances between datasets ● Alignment ● Pseudoalignment / quasi-mapping ● Detection of taxonomy ● Indexing large collections of sequencing datasets ● Quality control ● Detection of events (e.g. SNPs, indels, CNVs, alt. transcription) ● ... Goals of this lecture ● Broad sweep of state of the art, with applications ● Refresher of basic CS elements Au programme: ● Basic structures (Bloom Filters, CQF, Hashing, Perfect Hashing) ● k-mer data structures (SBT, BFT, dBG ds) ● Some reference-free applications k-mers Sequences of k consecutive letters, e.g. ACAG or TAGG for k=4 Problem statement: Framing the problem Representation of a set of k-mers: ACTGAT 6 11 Large set of k-mers : 10 - 10 elements GTATGC k in [11; 103] .. Problem statement: Operations to support Representation of a set of k-mers: - Construction (from a disk stream) ACTGAT - Membership (“is X in the set?”) GTATGC - Iteration (enumerate all elements in the set) - ... .. 106 - 1011 elements Extensions: k: 11 - 500 - Associate value(s) to k-mers (e.g. abundance) - - Navigate the de Bruijn graph Problem statement: Data structures Representation of a set of k-mers: ACTGAT “In computer science, a data structure is a GTATGC particular way of organizing and storing data in a
    [Show full text]
  • CMU SCS 15-721 (Spring 2020) :: OLTP Indexes (Trie Data Structures)
    ADVANCED DATABASE SYSTEMS OLTP Indexes (Trie Data Structures) @Andy_Pavlo // 15-721 // Spring 2020 Lecture #07 2 Latches B+Trees Judy Array ART Masstree 15-721 (Spring 2020) 3 LATCH IMPLEMENTATION GOALS Small memory footprint. Fast execution path when no contention. Deschedule thread when it has been waiting for too long to avoid burning cycles. Each latch should not have to implement their own queue to track waiting threads. Source: Filip Pizlo 15-721 (Spring 2020) 3 LATCH IMPLEMENTATION GOALS Small memory footprint. Fast execution path when no contention. Deschedule thread when it has been waiting for too long to avoid burning cycles. Each latch should not have to implement their own queue to track waiting threads. Source: Filip Pizlo 15-721 (Spring 2020) 4 LATCH IMPLEMENTATIONS Test-and-Set Spinlock Blocking OS Mutex Adaptive Spinlock Queue-based Spinlock Reader-Writer Locks 15-721 (Spring 2020) 5 LATCH IMPLEMENTATIONS Choice #1: Test-and-Set Spinlock (TaS) → Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly, not OS friendly. → Example: std::atomic<T> std::atomic_flag latch; ⋮ while (latch.test_and_set(…)) { // Yield? Abort? Retry? } 15-721 (Spring 2020) 5 LATCH IMPLEMENTATIONS Choice #1: Test-and-Set Spinlock (TaS) → Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly, not OS friendly. → Example: std::atomic<T> std::atomic_flag latch; ⋮ while (latch.test_and_set(…)) { // Yield? Abort? Retry? } 15-721 (Spring 2020) 6 LATCH IMPLEMENTATIONS Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex std::mutex m; ⋮ m.lock(); // Do something special... m.unlock(); 15-721 (Spring 2020) 6 LATCH IMPLEMENTATIONS Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex std::mutex m; pthread_mutex_t ⋮ m.lock(); futex // Do something special..
    [Show full text]
  • Space- and Time-Efficient String Dictionaries
    Tokushima University Ph.D. Thesis Space- and Time-Efficient String Dictionaries z間¹率hB間¹率noD文W列辞ø Author: Supervisor: Shunsuke Kanda Prof. Masao Fuketa A thesis submitted in fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Advanced Technology and Science Department of Information Science and Intelligent Systems March 2018 iii Abstract In modern computer science, the management of massive data is a fundamental problem because the amount of data is growing faster than we can easily handle them. Such data are often represented as strings such as documents, Web contents and genomics data; therefore, data structures and algorithms for space-efficient string processing have been developed by many researchers. In this thesis, we focus on a string dictionary that is an in-memory data structure for storing a set of strings. It has been traditionally used to manage vocabulary in natural language processing and information retrieval. The size of the dictionaries is not problematic because of Heaps’ Law. However, string dictionaries in recent applications, such as Web search engines, RDF stores, geographic information systems and bioinformatics, need to handle very large datasets. As the space usage of string dictionaries is a significant issue in those applications, it is necessary to develop space-efficient data structures. If limited to static applications, existing data structures have already achieved very high space efficiency by exploiting succinct data structures and text compression techniques. For example, state-of-the-art string dictionaries can be implemented in space up to 5% of the original dataset size. However, there remain trade-off problems among space efficiency, lookup-time performance and construction costs.
    [Show full text]
  • Reconfigurable Architecture for Minimal Perfect Sequencing Using the Convey Hybrid Core Computer Chad Michael Nelson Iowa State University
    Iowa State University Capstones, Theses and Graduate Theses and Dissertations Dissertations 2012 RAMPS: reconfigurable architecture for minimal perfect sequencing using the Convey hybrid core computer Chad Michael Nelson Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/etd Part of the Bioinformatics Commons, and the Computer Engineering Commons Recommended Citation Nelson, Chad Michael, "RAMPS: reconfigurable architecture for minimal perfect sequencing using the Convey hybrid core computer" (2012). Graduate Theses and Dissertations. 12846. https://lib.dr.iastate.edu/etd/12846 This Thesis is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. RAMPS: reconfigurable architecture for minimal perfect sequencing using the Convey hybrid core computer by Chad Michael Nelson A thesis submitted to the graduate faculty in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Major: Computer Engineering Program of Study Committee: Joseph Zambreno, Major Professor Phillip Jones Heike Hofmann Iowa State University Ames, Iowa 2012 Copyright ⃝c Chad Michael Nelson, 2012. All rights reserved. ii DEDICATION For Erin, family, and friends... thank you. Life would not be so sweet without you all. iii TABLE OF CONTENTS LIST OF TABLES . v LIST OF FIGURES . vi ACKNOWLEDGEMENTS . vii ABSTRACT . viii CHAPTER 1. OVERVIEW . 1 CHAPTER 2. REVIEW OF LITERATURE . 3 CHAPTER 3. PRELIMINARIES . 6 3.1 Background on DNA Sequencing .
    [Show full text]
  • The Guide to Xillybus Lite
    The guide to Xillybus Lite Xillybus Ltd. www.xillybus.com Version 2.1 1 Introduction3 1.1 General....................................3 1.2 Obtaining Xillybus Lite............................4 2 Usage5 2.1 Sample design................................5 2.2 Host application interface..........................6 2.3 Logic design interface............................7 2.3.1 Register related signals.......................7 2.3.2 Module hierarchy...........................8 2.3.3 32-bit aligned register access....................9 2.3.4 Unaligned register access...................... 12 2.4 Interrupts................................... 16 3 Xillybus Lite on non-Xillinux projects 17 3.1 Applying the IP core............................. 17 3.2 Modifying the device tree.......................... 21 3.3 Compiling the Linux driver.......................... 23 3.4 Installing the driver.............................. 24 Xillybus Ltd. www.xillybus.com 3.5 Loading and unloading the driver...................... 24 The guide to Xillybus Lite 2 Xillybus Ltd. www.xillybus.com 1 Introduction 1.1 General Xillybus Lite is a simple kit for easy access of registers in the logic fabric (PL) by a user space program running under Linux. It presents an illusion of a bare-metal environment to the software, and a trivial interface of address, data and read/write- enable signals to the logic design. Using this kit frees the development team from dealing with the AXI bus interface as well as Linux kernel programming, and allows a straightforward memory-like control of the peripheral without the operating system or the bus protocol coming in the way. The kit consists of an IP core and a Linux driver. These are included in the Xillinux distribution for the Zedboard (versions 1.1 and up), and are also available for download separately for inclusion in projects.
    [Show full text]
  • Hashing and Amortization
    Lecture 10 Hashing and Amortization Supplemental reading in CLRS: Chapter 11; Chapter 17 intro; Section 17.1 10.1 Arrays and Hashing Arrays are very useful. The items in an array are statically addressed, so that inserting, deleting, and looking up an element each take O(1) time. Thus, arrays are a terrific way to encode functions ©1,..., nª T, ! where T is some range of values and n is known ahead of time. For example, taking T {0,1}, we Æ find that an array A of n bits is a great way to store a subset of {1,..., n}: we set A[i] 1 if and only Æ if i is in the set (see Figure 10.1). Or, interpreting the bits as binary digits, we can use an n-bit array to store an integer between 0 and 2n 1. In this way, we will often identify the set {0,1}n with the set ¡ {0,...,2n 1}. ¡ What if we wanted to encode subsets of an arbitrary domain U, rather than just {1,..., n}? Or to put things differently, what if we wanted a keyed (or associative) array, where the keys could be arbitrary strings? While the workings of such data structures (such as dictionaries in Python) are abstracted away in many programming languages, there is usually an array-based solution working behind the scenes. Implementing associative arrays amounts to finding a way to turn a key into an array index. Thus, we are looking for a suitable function U {1,..., n}, called a hash function.
    [Show full text]
  • Memory-Efficient Search Trees for Database Management Systems
    Memory-Ecient Search Trees for Database Management Systems Huanchen Zhang CMU-CS-20-101 Febuary 2020 Computer Science Department School of Computer Science Carnegie Mellon University Pisburgh, PA 15213 esis Committee: David G. Andersen, Chair Michael Kaminsky Andrew Pavlo Kimberly Keeton, Hewle-Packard Labs Submied in partial fulllment of the requirements for the degree of Doctor of Philosophy. Copyright © 2020 Huanchen Zhang is research was sponsored by the National Science Foundation under grant number CNS-1314721, Intel ISTC-CC, Intel ISTC-VCC, and the VMware University Research Fund. e views and conclusions con- tained in this document are those of the author and should not be interpreted as representing the ocial policies, either expressed or implied, of any sponsoring institution, the U.S. government or any other entity. Keywords: search tree, memory-eciency, database management system, indexing, range ltering, succinct data structure, key compression To my son. iv Abstract e growing cost gap between DRAM and storage together with increas- ing database sizes means that database management systems (DBMSs) now operate with a lower memory to storage size ratio than before. On the other hand, modern DBMSs rely on in-memory search trees (e.g., indexes and l- ters) to achieve high throughput and low latency. ese search trees, how- ever, consume a large portion of the total memory available to the DBMS. is dissertation seeks to address the challenge of building compact yet fast in-memory search trees to allow more ecient use of memory in data pro- cessing systems. We rst present techniques to obtain maximum compres- sion on fast read-optimized search trees.
    [Show full text]