Lecture #07 @ ( OLTP Indexes SYSTEMS DATABASE ADVANCED Trie Andy_Pavlo Data Structures) // 15 // - 721 721 2020 Spring // 2
Latches B+Trees Judy Array ART Masstree
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LATCH IMPLEMENTATION GOALS
Small memory footprint.
Fast execution path when no contention. Deschedule thread when it has been waiting for too long to avoid burning cycles.
Each latch should not have to implement their own queue to track waiting threads.
Source: Filip Pizlo
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LATCH IMPLEMENTATION GOALS
Small memory footprint.
Fast execution path when no contention. Deschedule thread when it has been waiting for too long to avoid burning cycles.
Each latch should not have to implement their own queue to track waiting threads.
Source: Filip Pizlo
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LATCH IMPLEMENTATIONS
Test-and-Set Spinlock Blocking OS Mutex Adaptive Spinlock Queue-based Spinlock Reader-Writer Locks
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LATCH IMPLEMENTATIONS
Choice #1: Test-and-Set Spinlock (TaS) → Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly, not OS friendly. → Example: std::atomic
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LATCH IMPLEMENTATIONS
Choice #1: Test-and-Set Spinlock (TaS) → Very efficient (single instruction to lock/unlock) → Non-scalable, not cache friendly, not OS friendly. → Example: std::atomic
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LATCH IMPLEMENTATIONS
Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex std::mutex m; ⋮ m.lock(); // Do something special... m.unlock();
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LATCH IMPLEMENTATIONS
Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex std::mutex m; pthread_mutex_t ⋮ m.lock(); futex // Do something special... m.unlock();
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LATCH IMPLEMENTATIONS
Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex OS Latch std::mutex m; pthread_mutex_t Userspace Latch ⋮ m.lock(); futex // Do something special... m.unlock();
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LATCH IMPLEMENTATIONS
Choice #2: Blocking OS Mutex → Simple to use → Non-scalable (about 25ns per lock/unlock invocation) → Example: std::mutex OS Latch std::mutex m; pthread_mutex_t Userspace Latch ⋮ m.lock(); futex // Do something special... m.unlock();
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LATCH IMPLEMENTATIONS
Choice #3: Adaptive Spinlock → Thread spins on a userspace lock for a brief time. → If they cannot acquire the lock, they then get descheduled and stored in a global "parking lot". → Threads check to see whether other threads are "parked" before spinning and then park themselves. → Example: Apple's WTF::ParkingLot
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LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch next
CPU1 15-721 (Spring 2020) 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch next next
CPU1 15-721 (Spring 2020) 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch next next
CPU1 15-721 (Spring 2020) 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch next next
CPU1 15-721 (Spring 2020) 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch next next next
CPU1 15-721 (Spring 2020) CPU2 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch next next next
CPU1 15-721 (Spring 2020) CPU2 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch next next next
CPU1 15-721 (Spring 2020) CPU2 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch CPU3 Latch next next next next
CPU1 15-721 (Spring 2020) CPU2 CPU3 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch CPU3 Latch next next next next
CPU1 15-721 (Spring 2020) CPU2 CPU3 8
LATCH IMPLEMENTATIONS
Choice #4: Queue-based Spinlock (MCS) → More efficient than mutex, better cache locality → Non-trivial memory management → Example: std::atomic
Base Latch CPU1 Latch CPU2 Latch CPU3 Latch next next next next
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0 =0 =0 =0
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=1 =0 =0 =0
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=1 =0 =0 =0
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=12 =0 =0 =0
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=12 =0 =0 =0
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=12 =0 =0 =0=1
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=12 =0 =0 =0=1
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LATCH IMPLEMENTATIONS
Choice #5: Reader-Writer Locks → Allows for concurrent readers. → Must manage read/write queues to avoid starvation. → Can be implemented on top of spinlocks.
Latch
read write =0=12 =0 =0=1 =0=1
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B+TREE
A B+Tree is a self-balancing tree data structure that keeps data sorted and allows searches, sequential access, insertions, and deletions in O(log n). → Generalization of a binary search tree in that a node can have more than two children. → Optimized for systems that read and write large blocks of data.
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LATCH CRABBING /COUPLING
Acquire and release latches on B+Tree nodes when traversing the data structure.
A thread can release latch on a parent node if its child node considered safe. → Any node that won’t split or merge when updated. → Not full (on insertion) → More than half-full (on deletion)
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LATCH CRABBING
Search: Start at root and go down; repeatedly, → Acquire read (R) latch on child → Then unlock the parent node.
Insert/Delete: Start at root and go down, obtaining write (W) latches as needed. Once child is locked, check if it is safe: → If child is safe, release all locks on ancestors.
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EXAMPLE #1: SEARCH 23
20 A
10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #1: SEARCH 23 R 20 A
10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #1: SEARCH 23 We can release the latch on A as soon as we acquire the latch for C. 20 A
R 10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #1: SEARCH 23 We can release the latch on A as soon as we acquire the latch for C. 20 A
R 10 B 35 C
R 6 D 12 E 23 F 38 44 G
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EXAMPLE #1: SEARCH 23 We can release the latch on A as soon as we acquire the latch for C. 20 A
10 B 35 C
R 6 D 12 E 23 F 38 44 G
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EXAMPLE #2: DELETE 44 W 20 A
10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #2: DELETE 44 We may need to coalesce C, so we W can’t release the latch on A. 20 A
W 10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #2: DELETE 44 We may need to coalesce C, so we W can’t release the latch on A. 20 A G will not merge with F, so we can release latches on A and C. W 10 B 35 C
W 6 D 12 E 23 F 38 44 G
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EXAMPLE #2: DELETE 44 We may need to coalesce C, so we can’t release the latch on A. 20 A G will not merge with F, so we can release latches on A and C.
10 B 35 C
W 6 D 12 E 23 F 38 44 G
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EXAMPLE #3: INSERT 40 W 20 A
10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #3: INSERT 40 C has room if its child has to split, so W we can release the latch on A. 20 A
W 10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #3: INSERT 40 C has room if its child has to split, so we can release the latch on A. 20 A
W 10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #3: INSERT 40 C has room if its child has to split, so we can release the latch on A. 20 A G must split, so we can’t release the latch on C. W 10 B 35 C
W 6 D 12 E 23 F 38 44 G
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EXAMPLE #3: INSERT 40 C has room if its child has to split, so we can release the latch on A. 20 A G must split, so we can’t release the latch on C. W 10 B 35 44 C
W 6 D 12 E 23 F 38 4044 G 44 H
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EXAMPLE #3: INSERT 40 C has room if its child has to split, so we can release the latch on A. 20 A G must split, so we can’t release the latch on C.
10 B 35 44 C
6 D 12 E 23 F 38 4044 G 44 H
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BETTER LATCH CRABBING
The basic latch crabbing algorithm always takes a write latch on the root for any update. → This makes the index essentially single threaded.
A better approach is to optimistically assume that the target leaf node is safe. → Take R latches as you traverse the tree to reach it and verify. → If leaf is not safe, then do previous algorithm.
CONCURRENCY OF OPERATIONS ON B-TREES ACTA INFORMATICA 1977
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EXAMPLE #4: DELETE 44 R 20 A
10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #4: DELETE 44 We assume that C is safe, so we can release the latch on A. 20 A
R 10 B 35 C
6 D 12 E 23 F 38 44 G
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EXAMPLE #4: DELETE 44 We assume that C is safe, so we can release the latch on A. 20 A Acquire an exclusive latch on G.
10 B 35 C
W 6 D 12 E 23 F 38 44 G
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EXAMPLE #4: DELETE 44 We assume that C is safe, so we can release the latch on A. 20 A Acquire an exclusive latch on G.
10 B 35 C
W 6 D 12 E 23 F 38 44 G
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VERSIONED LATCH COUPLING
Optimistic crabbing scheme where writers are not blocked on readers. Every node now has a version number (counter). → Writers increment counter when they acquire latch. → Readers proceed if a node’s latch is available but then do not acquire it. → It then checks whether the latch’s counter has changed from when it checked the latch. Relies on epoch GC to ensure pointers are valid.
THE ART OF PRACTICAL SYNCHRONIZATION DAMON 2016
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VERSIONED LATCHES: SEARCH 44
v3 20 A
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 @A A: Read v3 v3 20 A
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A @B
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 @B
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 @B A: Recheck v3
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
v4 10 B v5 35 C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5 35 C @C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5 35 C B: Recheck v5 @C C: Examine Node v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5 35 C B: Recheck v5 @C C: Examine Node v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
v4 10 B v5 35 C @C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5 35 C @C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5v6 35 C @C v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5v6 35 C @C B: Recheck v5 v5 6 D v4 12 E v6 23 F v9 38 44 G
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VERSIONED LATCHES: SEARCH 44 A: Read v3 @A A: Examine Node v3 20 A B: Read v5 A: Recheck v3 @B B: Examine Node
C: Read v9 v4 10 B v5v6 35 C @C B: Recheck v5 v5 6 D v4 12 E v6 23 F v9 38 44 G
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OBSERVATION
The inner node keys in a B+tree cannot tell you whether a key exists in the index. You always must traverse to the leaf node.
This means that you could have (at least) one cache miss per level in the tree.
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TRIE INDEX Keys: HELLO, HAT, HAVE H Use a digital representation of keys to examine prefixes one-by-one A E instead of comparing entire key. → Also known as Digital Search Tree, T V L Prefix Tree.
¤ E L
¤ O
¤
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TRIE INDEX Keys: HELLO, HAT, HAVE H Use a digital representation of keys to examine prefixes one-by-one A E instead of comparing entire key. → Also known as Digital Search Tree, T V L Prefix Tree.
¤ E L
¤ O
¤
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TRIE INDEX PROPERTIES
Shape only depends on key space and lengths. → Does not depend on existing keys or insertion order. → Does not require rebalancing operations.
All operations have O(k) complexity where k is the length of the key. → The path to a leaf node represents the key of the leaf → Keys are stored implicitly and can be reconstructed from paths.
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TRIE KEY SPAN
The span of a trie level is the number of bits that each partial key / digit represents. → If the digit exists in the corpus, then store a pointer to the next level in the trie branch. Otherwise, store null.
This determines the fan-out of each node and the physical height of the tree. → n-way Trie = Fan-Out of n
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 0 ¤ 1 Ø Keys:
0 ¤ 1 Ø ←Repeat 10x 0 ¤ 1 ¤ K10→ 00000000 00001010 0 Ø 1 ¤ 0 Ø 1 ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 0 ¤ 1 Ø 0 ¤ 1 ¤ 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 ¤ 1 Ø 0 Ø 1 ¤ 0 Ø 1 ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 ¤ Ø Keys:
¤ Ø ←Repeat 10x ¤ ¤ K10→ 00000000 00001010 Ø ¤ Ø ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 ¤ Ø ¤ ¤ Ø ¤ ¤ Ø Ø ¤ ¤ Ø Ø ¤ Ø ¤
Tuple Node Pointer Pointer
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TRIE KEY SPAN 1-bit Span Trie K10,K25,K31 ¤ Ø Keys:
¤ Ø ←Repeat 10x ¤ ¤ K10→ 00000000 00001010 Ø ¤ Ø ¤ K25→ 00000000 00011001 K31→ 00000000 00011111 ¤ Ø ¤ ¤ Ø ¤ ¤ Ø Ø ¤ ¤ Ø Ø ¤ Ø ¤
Tuple Node Pointer Pointer
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RADIX TREE 1-bit Span Radix Tree ¤ Ø Omit all nodes with only a single child. ¤ Ø Repeat 10x → Also known as Patricia Tree. ¤ ¤ Ø ¤ Can produce false positives, so the ¤ ¤ DBMS always checks the original tuple to see whether a key matches.
Tuple Node Pointer Pointer
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TRIE VARIANTS
Judy Arrays (HP) ART Index (HyPer) Masstree (Silo)
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JUDY ARRAYS
Variant of a 256-way radix tree. First known radix tree that supports adaptive node representation. Three array types → Judy1: Bit array that maps integer keys to true/false. → JudyL: Map integer keys to integer values. → JudySL: Map variable-length keys to integer values.
Open-Source Implementation (LGPL). Patented by HP in 2000. Expires in 2022. → Not an issue according to authors. → http://judy.sourceforge.net/
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JUDY ARRAYS
Do not store meta-data about node in its header. → This could lead to additional cache misses.
Pack meta-data about a node in 128-bit "Judy Pointers" stored in its parent node. → Node Type → Population Count → Child Key Prefix / Value (if only one child below) → 64-bit Child Pointer
A COMPARISON OF ADAPTIVE RADIX TREES AND HASH TABLES ICDE 2015
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JUDY ARRAYS: NODE TYPES
Every node can store up to 256 digits. Not all nodes will be 100% full though.
Adapt node's organization based on its keys. → Linear Node: Sparse Populations → Bitmap Node: Typical Populations → Uncompressed Node: Dense Population
A COMPARISON OF ADAPTIVE RADIX TREES AND HASH TABLES ICDE 2015
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JUDY ARRAYS: LINEAR NODES Linear Node 0 1 5 0 1 5 Store sorted list of partial prefixes K0 K2 ... K8 ¤ ¤ ... ¤ up to two cache lines. → Original spec was one cache line
Store separate array of pointers to children ordered according to prefix sorted.
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JUDY ARRAYS: LINEAR NODES Linear Node 0 1 5 0 1 5 Store sorted list of partial prefixes K0 K2 ... K8 ¤ ¤ ... ¤ up to two cache lines. Sorted Digits → Original spec was one cache line Store separate array of pointers to children ordered according to prefix sorted.
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JUDY ARRAYS: LINEAR NODES Linear Node 0 1 5 0 1 5 Store sorted list of partial prefixes K0 K2 ... K8 ¤ ¤ ... ¤ up to two cache lines. Sorted Digits Child Pointers → Original spec was one cache line Store separate array of pointers to children ordered according to prefix sorted.
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JUDY ARRAYS: LINEAR NODES Linear Node 0 1 5 0 1 5 Store sorted list of partial prefixes K0 K2 ... K8 ¤ ¤ ... ¤ up to two cache lines. Sorted Digits Child Pointers → Original spec was one cache line
6 × 1-byte = 6 × 16-bytes = Store separate array of pointers to 6 bytes 96 bytes children ordered according to prefix sorted. 102 bytes 128 bytes (padded)
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JUDY ARRAYS: BITMAP NODES Bitmap Node 256-bit map to mark whether a 0-7 8-15 248-255 prefix is present in node. ... 01000110 ¤ 00000000 ¤ 00100100 ¤ Bitmap is divided into eight ... segments, each with a pointer to a ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sub-array with pointers to child nodes.
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JUDY ARRAYS: BITMAP NODES Bitmap Node Prefix Bitmaps 256-bit map to mark whether a 0-7 8-15 248-255 prefix is present in node. ... 01000110 ¤ 00000000 ¤ 00100100 ¤ Bitmap is divided into eight ... segments, each with a pointer to a ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sub-array with pointers to child nodes. Digit 0→00000000 4→00000100 1→00000001 5→00000101 2→00000010 6→00000110 Offset 3→00000011 7→00000111
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JUDY ARRAYS: BITMAP NODES Bitmap Node Prefix Bitmaps Sub-Array Pointers 256-bit map to mark whether a 0-7 8-15 248-255 prefix is present in node. ... 01000110 ¤ 00000000 ¤ 00100100 ¤ Bitmap is divided into eight ... segments, each with a pointer to a ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sub-array with pointers to child nodes.
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JUDY ARRAYS: BITMAP NODES Bitmap Node Prefix Bitmaps Sub-Array Pointers 256-bit map to mark whether a 0-7 8-15 248-255 prefix is present in node. ... 01000110 ¤ 00000000 ¤ 00100100 ¤ Bitmap is divided into eight ... segments, each with a pointer to a ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ sub-array with pointers to child Child Pointers nodes.
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ADAPATIVE RADIX TREE (ART)
Developed for TUM HyPer DBMS in 2013.
256-way radix tree that supports different node types based on its population. → Stores meta-data about each node in its header.
Concurrency support was added in 2015.
THE ADAPTIVE RADIX TREE: ARTFUL INDEXING FOR MAIN-MEMORY DATABASES ICDE 2013
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ART vs. JUDY
Difference #1: Node Types → Judy has three node types with different organizations. → ART has four nodes types that (mostly) vary in the maximum number of children.
Difference #2: Purpose → Judy is a general-purpose associative array. It "owns" the keys and values. → ART is a table index and does not need to cover the full keys. Values are pointers to tuples.
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ART: INNER NODE TYPES (1) Node4 0 1 2 3 0 1 2 3 Store only the 8-bit digits that exist K0 K2 K3 K8 ¤ ¤ ¤ ¤ at a given node in a sorted array. The offset in sorted digit array corresponds to offset in value Node16 array.
0 1 15 0 1 15 K0 K2 ... K8 ¤ ¤ ... ¤
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ART: INNER NODE TYPES (1) Node4 0 1 2 3 0 1 2 3 Store only the 8-bit digits that exist K0 K2 K3 K8 ¤ ¤ ¤ ¤ at a given node in a sorted array. Sorted Digits The offset in sorted digit array corresponds to offset in value Node16 array.
0 1 15 0 1 15 K0 K2 ... K8 ¤ ¤ ... ¤
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ART: INNER NODE TYPES (1) Node4 0 1 2 3 0 1 2 3 Store only the 8-bit digits that exist K0 K2 K3 K8 ¤ ¤ ¤ ¤ at a given node in a sorted array. Sorted Digits Child Pointers The offset in sorted digit array corresponds to offset in value Node16 array.
0 1 15 0 1 15 K0 K2 ... K8 ¤ ¤ ... ¤
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ART: INNER NODE TYPES (2) Node48 Instead of storing 1-byte digits, K0 K1 K2 K255 0 1 47 maintain an array of 1-byte offsets ¤ Ø ¤ ... ¤ ¤ ¤ ... ¤ to a child pointer array that is indexed on the digit bits.
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ART: INNER NODE TYPES (2) Node48 Pointer Array Offsets Instead of storing 1-byte digits, K0 K1 K2 K255 0 1 47 maintain an array of 1-byte offsets ¤ Ø ¤ ... ¤ ¤ ¤ ... ¤ to a child pointer array that is indexed on the digit bits.
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ART: INNER NODE TYPES (2) Node48 Pointer Array Offsets Instead of storing 1-byte digits, K0 K1 K2 K255 0 1 47 maintain an array of 1-byte offsets ¤ Ø ¤ ... ¤ ¤ ¤ ... ¤ to a child pointer array that is indexed on the digit bits.
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ART: INNER NODE TYPES (2) Node48 Pointer Array Offsets Instead of storing 1-byte digits, K0 K1 K2 K255 0 1 47 maintain an array of 1-byte offsets ¤ Ø ¤ ... ¤ ¤ ¤ ... ¤ to a child pointer array that is indexed on the digit bits. 256 × 1-byte = 48 × 8-bytes = 256 bytes 384 bytes
640 bytes
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ART: INNER NODE TYPES (3) Node256 Store an array of 256 pointers to K0 K1 K2 K3 K4 K5 K6 K255 ... child nodes. This covers all ¤ Ø ¤ ¤ Ø ¤ Ø ¤ possible values in 8-bit digits.
Same as the Judy Array's Uncompressed Node.
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ART: INNER NODE TYPES (3) Node256 Store an array of 256 pointers to K0 K1 K2 K3 K4 K5 K6 K255 ... child nodes. This covers all ¤ Ø ¤ ¤ Ø ¤ Ø ¤ possible values in 8-bit digits.
256 × 8-byte = Same as the Judy Array's 2048 bytes Uncompressed Node.
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ART: BINARY COMPARABLE KEYS
Not all attribute types can be decomposed into binary comparable digits for a radix tree. → Unsigned Integers: Byte order must be flipped for little endian machines. → Signed Integers: Flip two’s-complement so that negative numbers are smaller than positive. → Floats: Classify into group (neg vs. pos, normalized vs. denormalized), then store as unsigned integer. → Compound: Transform each attribute separately.
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ART: BINARY COMPARABLE KEYS 8-bit Span Radix Tree 0D 0A 0A Int Key: 168496141 0C 0B 0B 0C 0B 0F Hex Key: 0A 0B 0C 0D 0A 0D Little Big 0B 0C 1D ¤ Endian Endian
¤ 0B 0D ¤
¤ ¤
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ART: BINARY COMPARABLE KEYS 8-bit Span Radix Tree 0D 0A 0A Int Key: 168496141 0C 0B 0B 0C 0B 0F Hex Key: 0A 0B 0C 0D 0A 0D Little Big 0B 0C 1D ¤ Endian Endian Find: 658205 ¤ 0B 0D ¤ Hex: 0A 0B 1D
¤ ¤
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ART: BINARY COMPARABLE KEYS 8-bit Span Radix Tree 0D 0A 0A Int Key: 168496141 0C 0B 0B 0C 0B 0F Hex Key: 0A 0B 0C 0D 0A 0D Little Big 0B 0C 1D ¤ Endian Endian Find: 658205 ¤ 0B 0D ¤ Hex: 0A 0B 1D
¤ ¤
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MASSTREE Masstree
Bytes [0-7] Instead of using different layouts for each trie node based on its size, use an entire B+Tree. ¤ ¤ → Each B+tree represents 8-byte span. → Optimized for long keys. Bytes [8-15] Bytes [8-15] → Uses a latching protocol that is similar to versioned latches. ¤ ¤ ¤ ¤ ¤ ¤ ¤ ¤ Part of the Harvard Silo project.
CACHE CRAFTINESS FOR FAST MULTICORE KEY-VALUE STORAGE EUROSYS 2012
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IN-MEMORY INDEXES Processor: 1 socket, 10 cores w/ 2×HT Workload: 50m Random Integer Keys (64-bit) Open Bw-Tree Skip List B+Tree Masstree ART 60 51.5 50 44.9 42.9 40 29 30.5 30 25.1 22 17.9 18.9 20 15.5 13.3 9.94 8.09 10 5.43 3.68 3.43 Operations/sec Operations/sec (M) 2.51 2.78 1.51 2.43 0 Source: Ziqi Wang Insert-Only Read-Only Read/Update Scan/Insert
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IN-MEMORY INDEXES Processor: 1 socket, 10 cores w/ 2×HT Workload: 50m Keys Open Bw-Tree Skip List B+Tree Masstree ART 5 4.22
4 3.37 3 2.86 2.34 2.49 2.07 2.18 1.79 1.91 2 1.59 1.44 1.15 1.3
Memory Memory (GB) 0.722 1 0.42 0 Source: Ziqi Wang Mono Int Rand Int Emails
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PARTING THOUGHTS
Andy was wrong about the Bw-Tree and latch- free indexes.
Radix trees have interesting properties, but a well- written B+tree is still a solid design choice.
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NEXT CL ASS
System Catalogs Data Layout Storage Models
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