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Electronic Device Failure Analysis a Resource for Technical Information and Industry Developments 2015 Winners NOVEMBER 2016 | VOLUME 18 | ISSUE 4 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS 2015 WINNERS a b c d e f SUPERCONDUCTING SINGLE-PHOTON LVI AND LVP APPLICATIONS IN IN-LINE SCAN CHAIN FAILURE ANALYSIS DETECTOR ENABLES TIME-RESOLVED EMISSION TESTING OF LOW-VOLTAGE SCALED ICs EMERGING TECHNIQUES FOR 2-D/2.5-D/ 3-D TECHNOLOGY: FAILURE ANALYSIS 3-D PACKAGE FAILURE ANALYSIS: EOTPR, 3-D X-RAY, AND PLASMA FIB NOVEMBER 2016 | VOLUME 18 | ISSUE 4 edfas.org ELECTRONIC DEVICE FAILURE ANALYSIS A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS 2015 WINNERS PAGE 59 a b c d e f SUPERCONDUCTING SINGLE-PHOTON LVI AND LVP APPLICATIONS IN IN-LINE DETECTOR ENABLES TIME-RESOLVED 4 SCAN CHAIN FAILURE ANALYSIS 16 EMISSION TESTING OF LOW-VOLTAGE SCALED ICs EMERGING TECHNIQUES FOR 2-D/2.5-D/ 3-D TECHNOLOGY: FAILURE ANALYSIS 3-D PACKAGE FAILURE ANALYSIS: EOTPR, 24 CHALLENGES 30 3-D X-RAY, AND PLASMA FIB 1 NOVEMBER 2016 | VOLUME 18 | ISSUE 4 edfas.org ELECTRONIC DEVICE ANALYSIS DEVICE FAILURE ELECTRONIC FAILURE ANALYSIS A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS 4 LVI and LVP Applications in In-Line Scan Chain Failure Analysis Zhigang Song and Laura Safran This article discusses the combination of laser voltage imaging and laser voltage probing to improve the failure 4 16 analysis success rate for in-line scan chain logic macro diagnosis. 4 NO. 18 VOLUME | 16 Superconducting Single-Photon Detector Enables Time-Resolved Emission Testing of Low-Voltage Scaled ICs Andrea Bahgat Shehata, Franco Stellari, and Peilin Song Time-resolved optical probing techniques remain an indis- pensable tool for increasing fault localization speed and accuracy. Read about the use of a novel photon detector for low-voltage applications. 24 3-D Technology: Failure Analysis Challenges 24 30 Ingrid De Wolf Chip-level 3-D integration promises performance and func- tionality improvements in microelectronics systems, but ABOUT THE COVER what are the additional challenges for the failure analysis See page 59 for a description of the contest winners' collage community? on the cover. 30 Emerging Techniques for 2-D/2.5-D/3-D Package Failure Analysis: EOTPR, Author Guidelines Author guidelines and a sample article are available at edfas. 3-D X-Ray, and Plasma FIB org. Potential authors should consult the guidelines for useful Christian Schmidt, Jesse Alton, Martin Igarashi, Lisa Chan, information prior to manuscript preparation. and Edward Principe This article discusses emerging FA trends for package products using three techniques as the next-generation of For the digital edition, log in to edfas.org, FA methods to meet specific needs. Case studies highlight click on the "News/Magazines" tab, and the benefits of the techniques and discuss obstacles and select "EDFA Magazine." future improvements. DEPARTMENTS 62 GUEST COLUMNIST Christopher Henderson 43 SPECIAL! ISTFA 2016 SHOW LISTING 2 GUEST EDITORIAL P.A.W. van der Heide 64 ADVERTISERS’ INDEX 58 LITERATURE REVIEW Mike Bruce 44 BOD ELECTION RESULTS Jeremy Walraven 48 PRODUCT NEWS Larry Wagner 41 CALL FOR PAPERS 54 TRAINING CALENDAR Rose Ring 60 DIRECTORY OF FA PROVIDERS Rose Ring 56 UNIVERSITY HIGHLIGHT Mike Bruce edfas.org 2 ELECTRONIC DEVICE FAILURE ANALYSIS A RESOURCE FOR TECHNICAL INFORMATION AND INDUSTRY DEVELOPMENTS GUEST EDITORIAL NOVEMBER 2016 | VOLUME 18 | ISSUE 4 PURPOSE: To provide a technical condensation of VOLUME 18 NO. 4 NO. 18 VOLUME FAILURE ANALYSIS IN HIGH-VOLUME | information of interest to electronic device failure analysis technicians, engineers, and managers. MANUFACTURING Felix Beaudoin Editor/Globalfoundries; felix.beaudoin@ P.A.W. van der Heide, Globalfoundries globalfoundries.com [email protected] Scott D. Henry Publisher he ever-increasing financial stakes faced by semi- Mary Anne Fleming conductor high-volume manufacturing (HVM) on Manager, Technical Journals Kelly Sukol moving to the next node have propelled failure analysis (FA) to levels Production Supervisor T unimaginable even 20 years ago. The primary driving forces behind this can Liz Marquard be summed up as resulting from: Managing Editor ASSOCIATE EDITORS • Increased process complexity (new materials and structures) Michael R. Bruce • Increased number of mask steps per device node Consultant ELECTRONIC DEVICE FAILURE ANALYSIS FAILURE DEVICE ELECTRONIC David L. Burgess • Tighter process control Accelerated Analysis The increased process complexity derives from the fact that 20 years Lihong Cao ASE Group ago shrinkage simply entailed shrinkage. However, excessive leakage (short Jiann Min Chin channel effects, etc.) in logic devices brought an end to this Dennard scaling Advanced Micro Devices Singapore at approximately the 130 nm node (launched in 2001, at which time copper Edward I. Cole, Jr. Sandia National Labs interconnects and low-k dielectrics were already mainstream). Progressing James J. Demarest beyond 130 nm required the introduction of strain engineering, high-k metal IBM Christopher L. Henderson gate stacks, and movement to 3-D structures. Semitracks Inc. The increased number of mask steps arises from the increased process Jason M. Higgins TSMC (Wafertech) complexity discussed above, and the fact that ArF lithography (193 nm wave- Bobby Hooghan length) has been used throughout the 90 to 14 nm logic nodes, with the latter Weatherford Laboratories being well beyond the dry ArF lithography diffraction limit. Surpassing this Eckhard Langer Globalfoundries limit has required the introduction of new approaches, such as immersion Philippe H.G. Perdu lithography (193i), phase shift masks (PSM), optical proximity correction CNES France (OPC), litho-etch-litho-etch (LELE) techniques, self-aligned double pattern- Rose M. Ring Qorvo, Inc. ing (SADP), and so on. Moving to 7 nm without the use of extreme ultraviolet H.S. Silvus, Jr. (EUV) lithography will likely require the extension of LELE, that is, LELELELE, Southwest Research Institute implementation of self-aligned quadruple patterning (SAQP), and so on. E. Jan Vardaman TechSearch International, Inc. These processes have driven the number of mask steps from ~50 steps for Martin Versen the 28 nm node when using OPC, PSM, 193i, etc., to ~66 steps for 14 nm when University of Applied Sciences Rosenheim, Germany Lawrence C. Wagner using OPC, 193i, PSM, SADP, etc., to an expected ~80 steps for the 7 nm node LWSN Consulting Inc. if not using EUV. GRAPHIC DESIGN Tighter process control drives the need for additional metrology and more www.designbyj.com stringent control of contamination/particles. In this vein, airborne particle PRESS RELEASE SUBMISSIONS sizes have not changed over the last 20 years, which implies that their impact [email protected] Electronic Device Failure Analysis™ (ISSN 1537-0755) is pub- should increase in a quadratic fashion with each subsequent node. In addi- lished quarterly by ASM International ®, 9639 Kinsman Road, Materials Park, OH 44073; tel: 800.336.5152; website: edfas. tion, smaller particles are having a greater impact. org. Copyright© 2016 by ASM International. Receive Electronic Device Failure Analysis as part of your EDFAS member ship The scope of FA labs can encompass everything from the chemical analysis of $88 U.S. per year. Non-member subscrip tion rate is $135 of incoming chemicals, qualification/matching of process tools/recipes/envi- U.S. per year. Authorization to photocopy items for internal or per sonal use, ronment, to the evaluation of the root cause of electrical issues noted at the or the internal or personal use of speci ficclients, is granted by ASM International for libraries and other users registered with unfinished die through to the shipped package level. As with HVM, the FA labs the Copyright Clear ance Center (CCC) Transactional Reporting have had to derive new analytical solutions to the questions raised on moving Service, provided that the base fee of $19 per article is paid directly to CCC, 222 Rose wood Drive, Danvers, MA 01923, USA. (continued on page 45) Electronic Device Failure Analysis is indexed or ab stracted by Compendex, EBSCO, Gale, and ProQuest. edfas.org 3 ELECTRONIC DEVICE FAILURE ANALYSIS DEVICE FAILURE ELECTRONIC | VOLUME 18 NO. 4 NO. 18 VOLUME | edfas.org 4 EDFAAO (2016) 4:4-14 1537-0755/$19.00 ©ASM International® LVI AND LVP APPLICATIONS IN IN-LINE SCAN CHAIN VOLUME 18 NO. 4 NO. 18 VOLUME | FAILURE ANALYSIS Zhigang Song and Laura Safran, Globalfoundries [email protected] aser voltage imaging (LVI) has the unique capability “THE COMBINATION OF LVI AND LVP of mapping the periodic signal in a device under Ltest (DUT). It is very suitable for scan chain diagno- APPLICATION IN SCAN CHAIN DIAGNOSIS sis because data propagation through the scan chain is HAS IMPROVED THE IN-LINE SCAN CHAIN clocked with a periodic signal. Thus, LVI can easily iden- tify the broken point for a scan chain failure, whether its LOGIC FAILURE ANALYSIS SUCCESS RATE ELECTRONIC DEVICE FAILURE ANALYSIS FAILURE DEVICE ELECTRONIC defect is in the data path or in the clock path. Laser voltage TO THAT OF SRAM FAILURE ANALYSIS. ” probing (LVP) involves acquiring the waveform in a time domain from a particular point, such as the signal broken point identified by LVI, and a reference point. This can LVI’s unique capability to map the periodic signal[7-9] in further confirm the failure and help with understanding a DUT makes it a great diagnostic technique for scan the failure signature. This article discusses combining chain failure, whether the scan chain failure is due to a these two techniques in an in-line scan chain logic macro clock issue or an issue with the latch itself. In addition, diagnosis, which has greatly improved the failure analysis LVP probing[10-13] can further confirm the failure identi- success rate. fied by LVI. The combination of LVI and LVP application in scan chain diagnosis has improved the in-line scan chain INTRODUCTION logic failure analysis success rate to that of SRAM failure Historically, static random access memory (SRAM) analysis.
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