A Practical Introduction to Digital Power Supply Control Laszlo Balogh

ABSTRACT The quest for increased integration, more features, and added flexibility – all under constant cost pressure – continually motivates the exploration of new avenues in power management. An area gaining significant industry attention today is the application of digital technology to power supply control. This topic attempts to clarify some of the mysteries of digital control for the practicing analog power supply designer. The benefits, limitations, and performance of the digital control concept will be reviewed. Special attention will be focused on the similarities and differences between analog and digital implementations of basic control functions. Finally, several examples will highlight the contributions of digital control to switched-mode power supplies.

I. INTRODUCTION

Power management is one of the most digital delay techniques to adjust proper timing of interdisciplinary areas of modern electronics, gate drive signals, microcontrollers and state merging hard core analog circuit design with machines for battery charging and management, expertise from mechanical and RF engineering, and the list could go on. safety and EMI, knowledge of materials, If power conversion already incorporates semiconductors and magnetic components. such a large amount of digital circuitry, it is a Understandably, power supply design is regarded legitimate question to ask: what has changed? as a pure analog field. But from the very early What is this buzz about “digital power”? days, by the introduction of relays and later the first rectifiers, power management is slowly II. GOING DIGITAL incorporating more and more ideas from the Despite the tremendous amount of digital digital world. Ones and zeros are translated to circuitry used in power management integrated “on and off’s” but at the end a diode can be circuits, it remained mainly hidden from the viewed as a “digital component”. The users. Most externally accessible functions are introduction of switched mode power conversion implemented by fundamentally analog circuit required even more digital knowledge seeping blocks today. Thus PWM controllers and other into the repertoire of the practicing power supply power management integrated circuits have designers. The know-how of the first discrete successfully upheld their analog feel to them, implementations of the PWM logic using making analog measurements and accepting comparators, gates and latches have faded away analog controls. Their interfaces to the outside long time ago. Integrated pulse width modulator world are the various comparators and amplifiers ICs have turned those simple digital circuits to monitoring the operating conditions and history and have introduced even more digital providing a choice of protection options for the content to power management. designer of the power supply. This elemental Today’s highly integrated power management principle prevails in existing controllers as ICs are packed with digital gates. The digital demonstrated in Fig. 1. circuits allow the integration of some highly sophisticated features. Some examples are EEPROM based trimming after packaging to eliminate package stress related initial offsets,

6-1 Power Power IN Filter OUT IN Filter OUT Stage Stage

LOGIC ADC (PWM) VOLTAGE DIGITAL ADC VOLTAGE & PROCESSOR & CURRENT CURRENT ADC REGULATION REGULATION

ADC ADC CONTROLLER CONTROLLER SENSORY INPUTS SENSORY INPUTS & & COMMAND FUNCTIONS COMMAND FUNCTIONS Fig. 1. Top level analog PWM controller Fig. 2. Top level representation of a “digital” architecture. power supply. Another important aspect to notice in Fig. 1 is This fundamental change in the control the fact that the analog inputs are converted to philosophy is summarized in Fig. 2. When digital signals as soon as practical. The point comparing Fig. 1 and 2, it is important to where the conversion is taking place in today’s emphasize that the deployment of digital control controllers varies depending on the signal type. had no effect on the operating principle and the When an under voltage lock out function is design of the power stage. The specification of considered, the conversion is done by the the power supply still determines the choice of simplest of all analog-to-digital converters, an topology, the selection of power components and UVLO comparator. Its input is strictly analog, the required control functions. That leaves a fair while the output is already a digital signal, it is amount of design tasks still in the analog realm either high (“1”) or low (“0”), with no for the power supply expert. intermediate value. But this digital output is also buried inside the integrated circuit and it is very B. What is Changing? rarely accessible by the designer. Output voltage The striking difference between “analog” and and current regulation employs closed loop “digital” control is the quality and the amount of negative feedback, traditionally done by error information available for the controller to make amplifiers and the conversion to the digital decisions regarding the operation of the power “domain” is performed by a PWM comparator, stage. For example, the output of a comparator again well concealed inside the IC. carries limited information about the monitored parameter, i.e. only whether it is above or below A. What Really is “Digital Power”? a threshold. When the border between analog and “Digital power” is an inaccurate description digital is moved from the output of a comparator of a new direction in the controller design of the to the input by converting the actual information power supply to replace the analog circuits by to digital form, the controller suddenly knows the digital implementations. Accordingly, “digital concrete value of the parameter. Now, in addition power” really stands for digital control of the to comparing it to a threshold, changes in the power supply. Digital power supply control parameter’s value can be detected, stored and attempts to move the barrier between the analog later reported back to a supervisory system. If and digital sections of the power supply right to necessary, parameter values can be combined the pins of the control IC.

6-2 with other information in complex algorithms to Z-domain. The Z-domain transfer function of a perform even more sophisticated functions. sampled data system can be used to predict the Of course, this large amount of information small signal behavior of the converter. Additional can not be processed by traditional logic gates. new problems surface as well, like bandwidth Digital controllers take advantage of large scale limitations, resolution issues in time and voltage integration offered by state of the art measurements and limit cycle oscillation, just to semiconductor technology. Typically, a mention a few which will be discussed later. microcontroller (µC) or a digital signal processor One more key aspect of digital (DSP) is at the heart of a suitable digital implementations is to recognize that controller for power supply applications. microcontrollers and DSPs are powered by very Another important controller property which low voltages due to their semiconductor changes significantly is the flexibility to technologies. As a result they are not capable of implement various control algorithms. directly interfacing with the power components, Traditional, “analog” controllers may employ unlike their analog counterparts. Thus, they sophisticated decision trees driven by the digital require their own low voltage supply and a outputs of the various peripheral circuits. But the suitable high current gate driver with a reactions to the changes in the operating compatible input threshold and adequate output conditions are pre-programmed and rigidly voltage range. These requirements establish a executed by the internal logic. For instance, the clear partitioning between the analog and digital usual reaction to exceeding a current limit sections of the power supply. A closer look of the threshold is to shut down the converter and start fundamental architecture of a digitally controlled over, hard coded into the logic of analog converter is shown in Fig. 3. controllers. The power supply designer has no V option and in most cases it requires a significant IN amount of external circuitry to circumvent some of the built-in features of the controllers. By the BIAS introduction of a digital engine such as a µC or POWER STAGE DSP, the decision, how to react to certain LOW V BIAS conditions becomes user programmable. In the current limit example the designer might opt to ANALOG let the power supply operate in current limit for a DIGITAL number of switching cycles before resorting to shutdown. This would allow riding through short overload conditions during transient operation. In COM other cases where this behavior is not necessary uC or DSP or outright dangerous, the controller could be programmed to shut down immediately. Another area to address in digital control is to ensure stable operation of the power supply. The output voltage is still regulated by a closed Fig. 3. Analog – digital boundary in a power negative feedback loop, but it will be the result of supply. complex calculations performed by the µC or The low voltage bias shown in Fig. 3 must be DSP. While stability criterias for a power supply able to power the digital controller independently with analog control is well established and without operation of the power stage to allow understood by the designers, these control laws initialization during start-up and to preserve are not directly applicable to the digital intelligence during standby (disable) and short controllers. The digital implementations require circuit operation when traditional bootstrap bias new expertise, being familiar with and being able might not be available as a viable power source. to apply the stability requirements in the

6-3 Furthermore, the output of the digital strategies can be refined and adapted as required controller must be converted to a suitable signal by diverse applications. For example, once the to drive the power switches in the converter and output current of the converter is measured by the all voltages must be scaled to the input voltage digital controller this information can be used to range of the analog inputs, usually determined by program fold back, constant power, constant the reference voltage of the analog-to-digital current, delayed shutdown or any other mode of converter on-board the digital controller. over current protection. Moreover, any combination of these output characteristics can C. Advantages of Digital Control be implemented without ever changing any Flexibility is definitely the most noteworthy components in the power supply. benefit of digital controllers. It is especially The use of modern digital controllers also remarkable considering the consolidation of all adds communication as a potential feature to the necessary functions into one highly integrated, power supply. When this communication sophisticated controller. As mentioned before, by capability is utilized, the flexibility of the digital the introduction of a digital controller, the approach is greatly enhanced through the on-the- hardwired, hardly customizable control flow of fly programmability. The adjustability of the analog controllers is exchanged for an open converter’s output voltage is a great advantage as structure, where the designer has the ultimate demonstrated in processor applications using freedom to decide the right course of action to a VID code. In a communication enabled power given stimuli. This new opportunity can be rather supply, not just the output voltage, but current overwhelming for practicing power supply limit, operating frequency and other vital designers, because most of these decisions were operating parameters become programmable by a made for them by the semiconductor host system during operation. Beyond manufacturers of analog controllers. In addition, programming, communication permits remote this freedom comes with another new data logging of the operating conditions of the complication, the digital controller must be told power supply. By examining the data such as what to do. Software must be written to program efficiency, output ripple, temperature rise, certain the execution of all the functions assigned to the shifts in the measured parameters may be the µC or DSP. The software carries the knowledge leading indicators of pending failures. These and intellectual property which was previously trends can be used for failure prediction, down- realized in the controller hardware. time avoidance and intelligent fault management. There are three major areas in the design In a centrally managed power supply, start-up, where flexibility can provide significant benefits. shut-down and sequencing can also be supervised The first one is adjustability. Every parameter remotely by a higher level supervisory system. which is measured or programmed can also be All these options and the corresponding adjusted by the digital controller. These include computing power on-board can open the door for voltage and current thresholds, operating customization of future power supplies and entire frequency, thermal shut down, startup time, and power systems through software. This approach so on. promotes platform development and a faster The next level of flexibility is offered by the Time to Market window. Despite the potential user defined what-if decision making process standardization of the hardware, digital control inside the digital controller. This tool can be allows unique product differentiation through exploited for enhanced functionality like green software. The implementation methods of the mode or low power stand-by operation, load various power supply features remain well share or hot swap control, just to mention a few. protected due to the software code security The foundation of these features is the option to feature of modern microcontrollers and DSPs invoke different control algorithms as the which ensures that the program can not be read operating conditions of the power supply are by unauthorized users. changing. In addition, fault containment

6-4 In complex systems such as the academia and in the industry as well. Numerous telecommunication power infrastructure or high publications in major conferences discuss the end computing environments, digital control also theoretical and practical aspects of digital control offers reduced component count even with the implementations. Significant interest of the increased functionality. Fewer components mean subject had been expressed at APEC 2003 where lower manufacturing cost and higher reliability. the first Rap Session on digital power took place It is important to note though that all this with participation from end users, power supply flexibility and adjustability is restricted by the manufacturers and IC companies. The first capabilities of the power stage. For example, Market Report was published by iSupply on widely varying output voltages might require digital power in early 2003. different turn ratios in the transformer and filter A closer look at the reported results confirms inductors must be selected with the maximum that in power supplies, digital technology might output current in mind. Lowering the operating not yet be ready for prime time. Some of the frequency still increases output ripple although it problem stems from the ever present price might improve light load efficiency. All these pressure the industry is operating under. Like any effects of the adjustable parameters must be new technology, digital controllers cost more carefully considered otherwise the performance until reasonable sales volume is reached. of the power supply can be significantly Reaching a sufficient level of production is penalized. But it is possible to use the same delayed by the required time to learn and digital controller with several versions of the introduce new design disciplines and to address power stage, taking advantage of its ultimate manufacturing needs associated with digital flexibility. controllers. Also hindering the effort is the lack of appropriate analog support components to go D. Present Status of Digital Control in Power along with the microcontroller or DSP. Management On the theoretical front, the majority of The “digital revolution” is in its early phase present implementations “translate” S-domain in power supply applications. Its present state transfer functions to Z-domain. This approach resembles the motion control and UPS field just permits utilization of the well understood some 20 years ago. The first digital controllers linearized small signal model of the power operated at moderate switching frequency and supply. Once the poles and zeros are calculated to debuted in those applications in the early ‘80’s. ensure the stability of the system, the Z- The digital control acceptance rate was coefficients of the digital transfer function can be relatively slow, despite the fact that the found easily. The weakness of this method is that technology was readily available and capable of by starting from a linearized model, the benefits performing the job. Microcontrollers and DSPs of a higher performance non-linear control theory had sufficient computing power to handle speed can not be fully utilized. As a result, the control, sine wave generation and other similar performance of power supplies using either low speed control function. In addition they digital or analog controllers are very similar offered the possibility of communication between today. a host supervisor and the equipment. As the To set realistic expectations of today’s digital performance has improved and the price of the implementations in power supplies, Table 2 digital controllers has dropped during the years, attempts to highlight the pros and cons of the the technology became standard in most motor analog and digital approaches. control and large UPS systems. Digital control in power management is gaining considerable attention in recent years in

6-5 TABLE 1. COMPARISON OF ANALOG AND DIGITAL CONTROLLER PERFORMANCE (+ BETTER; - WORSE) Control Properties Analog Digital

Switching frequency (CPU limitations) + - Precision (tolerances, aging, temperature effects, drift, offset, etc.) - + Resolution (numerical problems, quantization, rounding, etc.) + - Bandwidth (sampling loop, ADC – DAC speed) + - Instantaneous over current protection + - Compatibility with power components + - Power requirements + - Communication, data management - + Understanding theory + - Advanced control algorithm (non-linear control, improved transient) - + Multiple loops - + Cost of controller + - Cost of a platform (flexibility, time to market) - + Component count (comparable functionality, integration) - + Reliability + ?

Achieving high switching frequency is accuracy, great resilience against temperature definitely easier using analog controllers. drift and aging effects. Digital controllers are a Obtaining high enough clock frequency to better fit to implement advanced control implement direct digital pulse width modulation algorithms and to manage multiple control loops with reasonable resolution is the fundamental if necessary. problem. Today’s digital controllers with suitable In the most important comparison – cost – clock speed for high switching frequency digital power supply control can be competitive. operation are not cost effective and consume a If all the functions provided by a digital significant amount of bias power. Another area implementation are necessary to meet where speed is critical is the performance of the specification, digital controllers will come out on digital controller’s analog-to-digital converter. top. In this case, component count and cost will The ADC’s conversion time and the number of be significantly lower than the cost of analog instructions needed to acknowledge the result control circuits and the required additional have an effect on the digital controller’s support ICs to accomplish comparable features. performance. Where sensing and reacting to When the only task is to regulate an output certain conditions should happen simultaneously voltage, digital controllers might have a hard – peak current limiting for example – analog time competing on price. In this instance, a circuits still has a significant advantage over pure bigger picture should be considered to evaluate digital implementations. Furthermore, the the real advantages of a digital implementation. If repetition rate of converting important parameters the design is expected to be re-used in several like output voltage, impacts the bandwidth of the power supplies, the flexibility and possibility of control algorithm. An additional important quick modifications in software is a very valuable characteristic of the analog-to-digital converter is attribute of the digital implementation although it its resolution which can introduce rounding or could be difficult to identify its cost benefit. quantization errors. These numerical issues are Finally, reliability is a key question. Analog inherent in digital control and represent a new controllers have a proven track record in power challenge for the power supply designer. On a supply applications. They work reliably in harsh, positive note, digital components can offer better noisy environment. Digital controllers have

6-6 proven to be very reliable as well, but not Since the R and C values can be set to any necessarily inside a power supply. It is unclear desired value, this oscillator can run at any whether microcontrollers and DSPs will operate frequency within its wide operating range. In an reliably under the same circumstances. analog implementation the controller’s clock frequency and the converter’s operating III. DIGITAL BASICS frequency (fSW) are the same. To fully understand the potential benefits of On the other hand, the clock frequency (fCLK) digital control, some basic operating principles of a microcontroller or a DSP is much higher and terminology must be clarified. The two than the actual operating frequency of the fundamental building blocks to understand are converter. The digital controller uses fCLK as the the time base and how the analog signals are time base for the central processor unit and its converted to digital form. These two circuits peripherals only. All other timing functions, interface with the surrounding analog world and including the switching period, must be generated are critical to the digital controller’s performance. using the internal resources of the digital controller. A. Generating the Time Base Fig. 5 demonstrates the principle of deriving One of the first steps in the design procedure the switching frequency. Once the clock is to establish the operating frequency of the frequency of the digital controller and the controller. It is usually defined by an on-board switching frequency of the converter are fixed, oscillator, often programmed by R-C timing the switching period can be established. The components. A frequently used implementation number of clock cycles in the switching period of a simple analog oscillator is shown in Fig. 4. can be calculated by dividing the switching period by the clock period. This number is stored V+ in the “period register”. Every clock signal increments the counter by one and eventually the counter value will be equal to the period. At that time the digital comparator produces an output V pulse which will reset the counter to zero. The PEAK R Q f SW frequency of the comparator output pulse is also S Q the desired operating frequency of the converter.

VVALLEY As fCLK increases with respect to fSW, more clock cycles become available within a switching period to perform the complex arithmetic calculations, data conversions and housekeeping functions. This indicates that the higher clock frequency has a desirable effect on the Fig. 4. Analog oscillator. performance of the digital controller. Another important reason to push the clock frequency higher becomes clear when the relationship between the number of clock cycles n in a switching period and the PWM resolution of

RESET the digital controller is investigated. An analog COUNTER f controller can command any pulse width as the SW decision is made using analog signals providing fCLK n COMPARE infinite resolution. In a digital controller the PWM pulse width is represented by an integer PERIOD number of clock cycles calculated by the REGISTER arithmetic unit, therefore the pulse width has a finite number of discrete values. Fig. 5. Simplified digital oscillator (fCLK >> fSW).

6-7 TABLE 2. EFFECTIVE NUMBER OF BITS, NUMBER OF CLOCK CYCLES PER PERIOD AND DUTY CYCLE RESOLUTION IN %, USING TYPICAL COMBINATIONS OF SWITCHING AND CLOCK FREQUENCIES

fSW fCLK - Clock Frequency (MHz) (kHz) 1 2 4 8 20 40 100 150 5.3 6.3 7.3 8.3 9.6 10.6 12.0 12.6 Bit resolution (eff.) 25 40 80 160 320 800 1600 4000 6000 Clock cycles/period 2.50 1.25 0.625 0.313 0.125 0.063 0.025 0.017 D resolution (%) 4.3 5.3 6.3 7.3 8.6 9.6 11.0 11.6 Bit resolution (eff.) 50 20 40 80 160 400 800 2000 3000 Clock cycles/period 5 2.50 1.25 0.625 0.250 0.125 0.050 0.033 D resolution (%) 3.3 4.3 5.3 6.3 7.6 8.6 10.0 10.6 Bit resolution (eff.) 100 10 20 40 80 200 400 1000 1500 Clock cycles/period 10 5 2.50 1.25 0.50 0.25 0.10 0.067 D resolution (%) 2.0 3.0 4.0 5.0 6.3 7.3 8.6 9.2 Bit resolution (eff.) 250 4 8 16 32 80 160 400 600 Clock cycles/period 25 12.5 6.25 3.125 1.250 0.625 0.250 0.167 D resolution (%) 1.0 2.0 3.0 4.0 5.3 6.3 7.6 8.2 Bit resolution (eff.) 500 2 4 8 16 40 80 200 300 Clock cycles/period 50 25 12 6.25 2.50 1.25 0.50 0.333 D resolution (%) 0.0 1.0 2.0 3.0 4.3 5.3 6.6 7.2 Bit resolution (eff.) 1000 1 2 4 8 20 40 100 150 Clock cycles/period 100 50 25 12.5 5.0 2.5 1.0 0.667 D resolution (%)

The pulse width of the digital controller can neighboring duty cycle values, the output voltage only be multiples of the clock period. The resolution is also affected. A further variable to important characteristics of the digital PWM define how coarse the output voltage adjustment engine can be defined as a function of the will be is the steady state operating duty ratio at switching frequency and the clock frequency as nominal input, output conditions (DNOM). shown in Table 2. 10

For every combination there are three Duty Cycle Resolution (DRES): numbers in the table. The first number is called 8 0.001 the effective number of bits and it signifies how 0.005 many bits are required in the counter to be able to 0.01 0.02 set up the desired switching frequency with a 6 given clock frequency. The second number indicates how many clock cycles are available in 4 a switching period. And the third number, which can be defined as: 2 = fCLK ⋅ DRES(%) 100 [%] Change Voltage Output , Normalized fSW 0 O,NOM 0 0.2 0.4 0.6 0.8 1 gives the duty cycle resolution in percentage V Steady State Operating Duty Cycle (D ) which is the most important parameter NOM determining the performance of the digital Fig. 6. The effect of duty cycle resolution on the controller. Due to the distinct values of the duty output voltage resolution as a function of ratio of the digital controller, the output voltage nominal operating duty ratio. of the converter can not be adjusted continuously. Depending on the difference between two

6-8 In Fig. 6, the curves represent the percentage While this value might satisfy the of output voltage change in response to changing requirements of the design (+2.2%), it is the converter’s duty ratio between two important to determine what the output voltage neighboring discrete values. It is important to would be at neighboring duty ratios: remember that the time difference between two f 250kHz V = V ⋅n ⋅ SW = 12V ⋅8 ⋅ = 3.00V neighboring duty ratio values is constant and it O(n=8) IN fCLK 8MHz equals 1/fCLK. As Fig. 6 emphasizes, the same = ⋅ ⋅ fSW = ⋅ ⋅ 250kHz = duty cycle step will result different output voltage VO(n=10) VIN n 12V 10 3.75V changes depending on the nominal operating duty fCLK 8MHz cycle of the converter. In other words, increasing the conduction time of the power supply’s main The calculations show a 0.375V or 11.1% switch by one clock period (1/fCLK) at narrow output voltage step in response to a duty cycle operating duty ratio will raise the converter’s change of one clock period which is clearly not output voltage more than the same change acceptable. A visual representation of the output applied at wider nominal duty cycles. Therefore, voltage and discrete duty cycle values around the in converters typically operating with narrow nominal output voltage is shown in Fig. 7. duty cycles – for example a 12V to 3.3V non- 4.5 isolated buck converter – it is desirable to have a higher speed (fCLK) digital controller even at 4.1 n=10 moderate switching frequencies. D =0.312 To further underline the impact of the duty 10 3.7 cycle resolution, consider the above mentioned V buck converter as an application example. The O,MAX Regulation 3.3 converter operates at 250kHz switching V Window frequency using an 8 MHz digital PWM engine. O,MIN

, OutputVoltage [V] n=9

The input is 12V and the output voltage is 3.3V. O 2.9 V n=8 D9=0.281 The required operating duty ratio would be: D =0.25 V 3.3 2.5 8 D = OUT = = 0.275 0.22 0.26 0.30 0.34 REQ V 12 IN Analog (D) and Discrete (D ) Duty Cycle The corresponding PWM pulse width is: X D Fig. 7. Output voltage vs. duty ratio in digitally = REQ = 0.275 = µ tON 1.1 s controlled power supply. fSW 250kHz This requires; Another instance where discrete duty cycle values can be observed is the effect of input n = t ⋅ f = 1.1µs ⋅8MHz = 8.8 ON ON CLK voltage change on the output voltage of the number of clock cycles. Since the digital converter. Utilizing the infinite resolution of controller can not put out fractional number of analog controllers, the output voltage is regulated clock cycles, the on-time will be the closest practically at a constant level, independently integer number of cycles, nine. This duty cycle from the input voltage. With only a finite number will yield an output voltage of: of duty ratios being available in digital control = ⋅ ⋅ fSW = ⋅ ⋅ 250kHz = the output voltage can not be held at a constant VO(n=9) VIN n 12V 9 3.375V fCLK 8MHz value. Fig. 8 shows the example converter’s output voltage as a function of VIN around the nominal 12V value.

6-9 3.6 VO,MAX 3.5 IN1 IN2 nn-1 3 21 3.4 IN3 MUX A-to-D 1 0 …. 1 1 0 IN4 + 2n-1 2n-2 22 21 20 3.3 IN5

V 3.2 O,MIN Fig. 9. Voltage measurement using ADC. , Output Voltage [V] Voltage Output ,

O The analog-to-digital converter can be V 3.1 n=10 n=9 n=8 characterized by the number of bits of its output D10=0.312 D9=0.281 D8=0.25 3.0 and by the time required to produce the result. 1011 12 13 14 The ADC’s number of bits is directly related to V , Input Voltage [V] IN the accuracy of the measurement because it Fig. 8. Output voltage vs. input voltage in defines the resolution. When the input signal to digitally controlled power supply. the ADC is equal to (or larger than) its reference voltage all output bits will be 1. From this Due to the finite number of possible duty relationship the resolution of the ADC can be ratios the converter’s output voltage will be calculated according to: proportional to the input voltage until the = VREF operating conditions will demand the next resADC 2n smaller duty cycle. At that moment the output where n is the number of bits of the analog- voltage suddenly drops to the new value to-digital converter. That means that the input corresponding to the new duty ratio as voltage range is divide into 2n number of equal demonstrated in Fig. 8. bands and the ADC “identifies” the band B. Digitizing Variables – Voltage Sense containing the amplitude of the input signal. In In addition to the effects of discrete time order to establish the resolution of the actual steps the various control variables are also measurement the gain and accuracy of the digitized in the digital controller. This introduces external resistive divider needs to be taken into another level of complexity in the design. First of account as well. For instance, measuring the 3.3V all it is important to note that the digital output of the earlier introduced example using an controller measures everything as a voltage input 8-bit ADC with a 1.25V reference will require a connected to an on-board analog-to-digital 3:1 divider in front of the input of the analog-to- converter, usually through a multiplexer. All digital converter. Notice that the 1.25V should voltages monitored by the ADC must be scaled to not be used as an equivalent of the 3.3V because the input voltage range of the ADC, generally potential over voltage conditions could not be between ground and the reference of the ADC. sensed. The 3:1 divider will allow measurement Typical reference levels are either 1.25V or 2.5V of the output voltage in the 0V to 3.75V range. and these references can be internal or external to Now the resolution of the output voltage the analog-to-digital converter. After the measurement can be established as: conversion, the measured voltage level will be = VFS resVo represented by a digital value as shown in Fig. 9. 2n where VFS is the full scale amplitude and n is the number of output bits of the ADC. In our example the output voltage resolution is: 3.75V res = = 14.6mV Vo 28

6-10 This means that the converter’s output conversion time is around 5µs. Since the ADC is voltage can change as much as 14.6mV before it an autonomous peripheral, the microcontroller or will become evident at the output of the analog- DSP can perform other tasks during the to-digital converter and the duty cycle could be conversion. modified. The ambiguity introduced by the The conversion time is important for two measurement resolution ultimately impacts the main reasons in power supply applications. The regulation accuracy in power supply applications. first problem is that the conversion time can be The worst case error can be calculated by the considered as a time delay. Its effect is similar to following expression: having a very slow comparator in an analog V controller. There are plenty of functions in a E (in%) = FS ⋅100 RES 2n ⋅V power supply where this is acceptable like under O voltage lockout, but it is certainly not adequate Substituting the already familiar values from where quick response to a fast changing our example yields: parameter is critical, such as for current 3.75V E (in%) = ⋅100 = ± 0.44% protection or even for peak current mode control. RES 8 ⋅ 2 3.3V In general, it can be said that digital controllers This inaccuracy is additional to the error can not replicate the instantaneous reaction of the introduced by the tolerance of the reference and analog controllers due to the time lag of the the resistive divider which scales the output ADC’s conversion time. voltage level to the input range of the ADC. The other aspect of the conversion time is Theoretically, using more bits in the analog- related to the bandwidth of the control loop. The to-digital converter increases the resolution and sample frequency, how often the output voltage consequently the measurement accuracy as can be measured, will be seriously impacted by shown in Table 3. the conversion time of the analog-to-digital converter. In an analog implementation the TABLE 3. ADC ACCURACY AS A output voltage is sampled in every switching FUNCTION OF BITS cycle. If similar performance is expected from ADC the digital controller, the switching frequency 8 10 12 14 16 Number of bits must be equal or less than the maximum frequency which can be supported by the ADC. ERES (in %) 0.444 0.111 0.028 0.007 0.002 Even then it should be assumed that the output voltage is the only parameter the ADC is Another property of the analog-to-digital measuring which is clearly not the case in most converter which deserves attention is the time power supply applications. needed between the command initiating the measurement and when the result is available in C. Digital Pulse Width Modulation the output register of the ADC. This period Now that some of the basic blocks and consists of two intervals, the actual time needed characteristics of a digital controller have been to convert the analog signal to a digital word plus introduced, the operation of the analog and the number of instructions used to process, store digital pulse width modulator can be compared. and read the result. Since most modern Fig. 10 illustrates the fundamental process to microcontrollers and DSPs can access the result obtain the operating duty ratio of a power supply in a single instruction cycle, the most important using an analog (top drawing) and a digital parameter is the conversion time. Usually the (bottom drawing) approach. conversion time is given indirectly by specifying The analog control circuit requires a the number of conversions in a second. For reference, an error amplifier and a comparator to example, 200ksps (kilo-samples-per-second) determine the required duty cycle. As shown in performance translates to 200,000 conversions in Fig. 10, the output voltage is compared to a a second, i.e. 200kHz. That means that the reference using a resistive divider at the inverting

6-11 input of the error amplifier. The control law is As mentioned before, the input voltage of the also implemented by the error amplifier by ADC at nominal output voltage must be less than selecting the appropriate R and C values to set VREF to accommodate output voltages above the the poles and zeros of the differential equations nominal value during transient operation. The governing the behavior of the negative feedback ADC then converts the output voltage to a loop. The actual duty cycle is produced by a representative digital word labeled as VO(D) in simple comparator by comparing the error Fig. 10. The Arithmetic and Logic Unit (ALU), voltage to an artificial ramp which also carries the digital core of the microcontroller or DSP the information of the operating frequency of the takes care of the rest of the functions. It can circuit. The duty cycle generated this way can be establish the switching frequency from the clock any value allowing the analog controller to frequency of the processor (fCLK) and it will regulate the output voltage of the power supply calculate a value for the power supply duty cycle exactly at the desired amplitude. (DD). The digital representation of the nominal output voltage and some of the previously VO(A) Compensation measured VO(D) values are stored in memory and available for a comparison to the most recent VERROR output voltage level produced by the ADC. The control law is also executed by the digital engine as programmed by the software. D Without going into digital control theory, the A Z-domain control function of our example buck + converter which implements the equivalent of V PWM REF f two poles and two zeros for a typical type 3 SW compensation can be written in the following form: V K1⋅ z 2 − K 2⋅ z + K3 O(A) G(Z) = 2 − ⋅ + f z K4 z K5 CLK This equation closely resembles the usual S- domain transfer function of the power supply. VO(D) The computations to execute this control law in ADC ALU DD the digital domain can be summarized by the next two equations where n refers to the present cycle, + fSW, PWM, n-1 and n-2 are the values from the previous two VREF Compensation calculations respectively. The first step is to calculate the error between the desired and measured output voltage: Fig. 10. Comparison of analog and digital PWM E(n) = V −V (n) implementation. O,NOM O Using the just calculated value of E(n) and its The digital implementation of the pulse width earlier values from the previous two cycles along modulator starts with a similar resistive divider with the respective duty cycle values (from the which scales the output voltage to the input memory of the digital controller) the new duty voltage range of the analog-to-digital converter. cycle D(n) can be computed:

D(n) = a2⋅ D(n − 2) + a1⋅ D(n − 1) + b2⋅ E(n − 2) + b1⋅ E(n − 1) + b0 ⋅ E(n)

6-12 The coefficients of the equation can be output is too high. The digital controller mimics obtained by simple mathematical manipulations the reaction of any analog controller under the from the S-domain transfer function or same circumstances and will try to compensate synthesized directly from the component values by decreasing the duty ratio. The minimum of the power supply. These constants are stored change in the duty ratio is a function of the clock in the memory of the digital controller and as period of the digital PWM engine. In Fig. 11 a such can be easily modified during debug or even situation is depicted where shortening the on- while the power supply is running according to a time of the main power switch by one clock specific mode of operation. period (1/fCLK) results a new output voltage in the VO=low band. This will initiate a correction D. Limit Cycle Oscillation asking for the next larger duty cycle value which To ensure stability with a digital controller, will bring the output voltage back to the VO=high there are two fundamental requirements which band. And the cycle starts again, the output must be satisfied. The first one is the traditional voltage will oscillate. The smoothing of the small signal stability criteria which is addressed output voltage waveform in Fig. 11 is by the appropriate selection of the various accomplished by the averaging L-C output filter constants in the control law equations. of the power supply. The second constraint involves the time The obvious problem in this example is that domain resolution of the digital PWM engine and the time domain resolution is too course with the voltage resolution of the analog-to-digital respect to the resolution of the analog-to-digital converter. This unique problem is demonstrated converter. This phenomenon is called limit cycle in Fig. 11. oscillation and it can happen regardless of

VO whether the design meets all conventional stability criteria. The solution to this dilemma is to follow a design procedure where the ADC VO=high resolution is selected first, based on the required

VO=OK VO,NOM accuracy of the output voltage regulation. The duty cycle resolution is then adjusted to the ADC

ADC resolution VO=low resolution by selecting an appropriate clock and switching frequency combination. D IV. PROGRAMMABLE FUNCTIONS AND VARIABLES PWM resolution The development of a suitable power supply Fig. 11. Demonstration of limit cycle oscillation controller is primarily driven by the answers for with digital control. three fundamental questions: Assume that the power supply is running in • What functions to provide? (in addition to steady state operation with a constant duty ratio fSW, and PWM) producing an output voltage which is in the zero • How to implement them? error bin (VO=OK). When the operating • When to execute them? conditions change – the input voltage increases or With an analog approach, the first two some of the load is removed – the output voltage questions are answered by selecting the PWM starts to climb. Slight output voltage variation is controller and some auxiliary components to allowed and will not change the duty cycle as match the intended features. Once the long as VO stays within the VO=OK band because components are chosen and interconnected, the the analog-to-digital converter will produce the functions and the control algorithm are fixed and same result. As soon as the output goes higher the circuit becomes dedicated to the particular than the upper threshold of the zero error bin, the application. Any change in functionality would ADC output will change which indicates that the require adding more components or redesigning

6-13 the interaction among the different sections of the - VOUT controller. Finally, the voltage levels and limits - VOVP are set according to the predefined or user - IOUT,MAX adjustable thresholds and by fixed external - POUT,MAX components. This will define permanently when - VIN,MIN the functions will be carried out. - VIN,MAX On the other hand, the hardware of the digital - IIN,MAX controller is designed almost independently of its - IPK,MAX functionality. Only the selection of the input - fSW parameters might impact the available functions - DMAX and their implementation. Practically, all three - V·s MAX questions are answered by the programming of - DMIN the microcontroller or DSP. The software can - tSS (soft-start time) integrate selected subroutines to address the A partial inventory of the possible functions necessary control functions. The control using these additional measurements and algorithm can be based on complex decisions variables is summarized in the following list: evaluated by the digital controller and it can be • Switching frequency modulation easily modified by changing a few lines of code • Input voltage monitoring (UVLO, line OVP) in the programming. The different thresholds and • Shutdown, Enable limits are also defined in the software as • Soft-start profile variables and their value can be modified easily. • Sequencing – sync. rectifier control Through this mechanism, many operating • D limit parameters of the power supply can be MAX • Volt-second clamp customized without ever changing any • Green mode operation (burst mode, D component value in the circuit. MIN limit) Accordingly, programmability and flexibility • Transient overload response are the most significant differentiators in favor of • the digital power supply controllers. Current limit profile • Output characteristic (droop, constant power) A. Miscellaneous Control Functions • Temperature protection (derating, shutdown) With a powerful processor, the digital • Communication controller is capable of performing many more Since these functions would be implemented functions beyond the basic voltage regulation in software, the behavior of the system could be task. By measuring just a few more working tailored to specific applications rather easily. parameters of the power supply, a host of That’s where the flexibility of the digital intelligent control and protection functions can be controller would be the most valuable in contrast implemented. Some of the data and variables to the hard wired responses of analog controllers. which can be easily made available for the digital Switching Frequency Modulation controller through its analog-to-digital converter Because the operating frequency is defined or by values stored as variables in memory are: by the digital controller, it can be managed • Input voltage through software. There are several applications • Average input current where variable frequency operation can be • Average output current beneficial. Off-line power supplies can take • Operating temperature advantage of spreading EMI noise spectrum by • Other output voltages in the system slowly modulating the switching frequency of the • Host supervisor with serial bus converter in a relatively narrow band around the communication capability nominal operating frequency. This could reduce • DC Transfer function of the converter input EMI filter requirements, offer smaller size • Variable examples: and lower cost. Another application where this

6-14 opportunity might be welcomed is to meet green START V*S mode power consumption limit in standby. In most green mode implementations high efficiency, low power standby mode is facilitated MEASURE V by reduced switching frequency or by burst mode IN operation, both achievable by controlling the switching frequency using the digital controller’s CALCULATE D software routines. VS Input Voltage Monitoring V S ROUTINE STATIC END V*S Knowing the input voltage of the converter allows the digital controller to accomplish some additional control functions. The most basic ones

are line under voltage lock out (UVLO) and line START DPWM over voltage protection (OVP). To realize these functions, the valid input voltage range of the READ converter is stored in the digital controller’s V memory and the measurement is compared to OUT those limits. When the input voltage is outside of the operating range, the power stage is disabled CALCULATE

D ROUTINE PWM and all other operations of the controller can be PWM suspended. This technique allows low power READ operation of the microcontroller or DSP because D its clock frequency can be significantly reduced. VS It is also possible for the microcontroller to enter NO standby mode between measurements since all DPWM>DVS other tasks are put on hold until the input voltage returns to the nominal range. YES SET COUNT=0 Some of the more sophisticated functions COUNT= COUNT+1 based on the actual input voltage level could be brown out protection when the converter’s input SET D =D power is limited during brown out conditions. LIM MAX NO Another option is to implement an advanced COUNT>5 volt-second clamp to protect the transformer from DYNAMICV S ROUTINE saturation in isolated topologies. When volt- YES second clamping is employed in analog SET D =D controllers, designers often face the trade off LIM VS between fast transient response and effective protection due to the duty cycle limiting effect of NO the volt-second clamp. The ultimate flexibility of D >D the digital control algorithm could help to PWM LIM overcome this trade-off according to the flow YES chart shown in Fig. 12. SET ROUTINE D =D MAX PWM LIM D

END D PWM Fig. 12. Advanced volt-second clamp routine.

6-15 Isolated converters frequently adhere to a The most frequently used current limit maximum duty cycle limit (DMAX) especially if techniques include: they employ a single ended topology. DMAX is • Constant output current usually set during the power stage design and • Foldback corresponds to operation at minimum input • Transient ride through (delayed shutdown) voltage. At that point DMAX=DVS, the volt-second • Hiccup (shut down & retry) duty ratio limit, calculated as a function of the • Shutdown (permanent lock out) input voltage. At higher input voltages the When foldback current limit is required, the volt-second limit reduces the maximum operating output current must be measured and controlled duty cycle according to: as a function of the output voltage. The digital = VOUT ⋅ N P ⋅ controller could implement the following DVS 1.2 VIN N S relationship: = + ⋅ In this equation the volt-second clamp is set IO (VO ) I MIN RLOAD(MIN ) VO 20% above the nominal duty ratio of the In addition, the maximum output current can converter as indicated by the 1.2 multiplier. The be limited as well by comparing the result of the lower of DMAX or DVS limits the actual duty ratio above equation to an absolute limit stored in the calculated by the controller based on the output parameter table in memory. voltage error (DPWM). In normal, steady state Transient current limit of the converter could operation none of these limits impact the be established in software by a simple routine operation of the power supply. similar to the one used for the dynamic override The software routine illustrated in Fig. 12 of the volt-second clamp (Fig. 12). Hiccup and would allow the converter to operate beyond the shutdown type current limit actions are even volt-second limit for 5 cycles to accommodate simpler and lend themselves for easy execution in fast transient response before cutting back the digital control. What will differentiate the digital allowable maximum duty ratio to protect the implementation from traditional analog circuits is converter. During the five transient cycles this the possibility to effortlessly adjust the current example uses DMAX to limit the maximum limit threshold either through the programming operating duty ratio but the software could be interface (communication) or as a function of easily modified to provide more protection if operating parameters like temperature. needed. Furthermore, it is conceivable that the controller Since the input voltage change is relatively could switch between the different over current slow, it will not be sampled in every switching protection methods based on a pre-programmed period to save computing resources. Therefore, algorithm during operation. One example for the static volt-second routine is independent from changing between different current limit methods the PWM calculation as shown in Fig. 12 and is the incorporation of constant output power once it is executed, its result can be used until the characteristic. Frequently done even with analog next calculation is completed. controllers in telecom rectifiers, in the nominal Current Sense range (for instance, between 43V and 58V The digital controller can also measure the output) the current limit is a function of the input, output or both currents of the power output voltage to utilize the maximum power supply. The collected current information can be throughput of the converter. At low output utilized to implement various types of current voltages, power limiting would cause excessive limiting methods or can be combined with other current stress, thus the control changes to limit parameters to customize the power supply’s the current at a safe maximum value (constant output characteristic under overload conditions. output current characteristic).

6-16

Soft-Start Operation The two most common soft-start methods used in integrated analog PWM controllers are ISS shown in Fig. 13. These techniques are called D(V ) open loop soft-start because the voltage SS regulation loop is open during the soft-start time CSS interval. That also means that control must be VCT asserted by some other means instead of the PWM voltage error amplifier. In both examples the comparators controlling variable is the voltage across the soft- ISS start capacitor, CSS. The top drawing depicts a voltage mode IPK(VSS) implementation since the control quantity is compared to a sawtooth waveform derived from CSS the oscillator. As the voltage across CSS slowly VCS ramps up, the operating duty cycle of the converter increases until the nominal value is Fig. 13. Typical soft-start circuits in analog reached. At that time the voltage regulation loop PWM controllers. becomes operational and takes over the duty Temperature Monitoring cycle control. According to the voltage mode Several microcontrollers and DSPs are operation just described, during soft-start the equipped with on-board temperature sense converter’s duty ratio is a simple function of the elements or can measure temperature using an capacitor voltage which linearly increases with external sensor. As implied in the current sense time. In other words the task at hand is to section, the temperature information can be increase the duty ratio from zero to D during NOM combined with an adjustable current limit the time defined by the value of the soft-start threshold to provide protection against capacitor. temperature related damage of the power supply. This could not be easier to implement in a In addition to derating the output power of the digital controller. The soft-start time can be given converter, over-temperature shutdown with and the software can impose a gradually programmable threshold is also possible. increasing maximum duty cycle limit on the PWM output to emulate the operation of the Presence of a Higher Intelligence analog circuit. The controller of a power supply is just as In the current mode implementation, as good as the algorithm it implements, regardless shown in the lower part of Fig. 13, the soft-start of whether it is analog or digital. In an analog capacitor voltage controls the maximum current controller the algorithm gets embedded in the of the main power switch. The PWM comparator hardware during the circuit development. Digital matches up the current sense voltage to the power supply control replaces a lot of hard wired linearly increasing CSS voltage. Similar to the responses with intelligent software based voltage mode operation, during soft-start the decisions which supervises the operation of the voltage loop is open. This algorithm implements power supply. One of the cornerstones of soft-start by increasing the peak current limit establishing intelligence is communication which from zero to full current capability during the is natural to digital controllers. time interval defined by the value of CSS. Again, this behavior can be replicated simply by ramping up the current limit threshold according to the required soft-start time stored in the program of the digital controller.

6-17 The first instance of communication is in the V. HARDWARE EXAMPLE programming, when the knowledge of the power The most computation intensive tasks for the supply designer gets “downloaded” into the digital controller are clearly the output voltage microcontroller or DSP. But communication can regulation and implementation of digital pulse be maintained and utilized during the entire width modulation. Also, these are the most lifetime of the power supply. The digital difficult, new theoretical areas of digital control controller can provide the interface between the for the practicing power supply designer. But converter and the external world. Established, before facing the first endeavors with Z- industry standard protocols make it easy to transformations, resolution issues and speed, connect to other equipments. Most digital control can provide tremendous benefits microcontrollers and DSPs offer one or more for power supplies as shown in the next circuit serial communication bus protocols implemented example. either in hardware or through software programming. Some of the potential suitable A. Digitally Assisted Power Supply standard buses and their basic characteristics for This circuit demonstrates an approach which power supply applications are: can provide a bridge between pure analog and 2 • I C – Inter-Integrated Circuit fully digital power supply control. The ! 2 wire, bi-directional bus converter’s specification is detailed next. ! 100kb/s, 400kb/s, 3.4Mb/s selectable VIN = 36 V to 75 V speed VIN,TURN-ON = 33 V ! device addressable bus VIN,TURN-OFF = 30 V • SMBus – System Management Bus VOUT = 12 V ! I2C like bus (2 wire, bi-directional) POUT = 100 W ! speed is between 10kb/s and 100kb/s IOUT,MAX = 8.3 A ! limited device addressing TAMB,MAX = 55°C • SPI – Serial Peripheral Interface fSW = 500 kHz ! 3 wire bus plus chip select (Enable) Isolation: 500 V ! 1Mb/s, 10Mb/s speed Communication: ! Master – slave arrangement • JTAG – for programming • Microwire • RS-232 (UART) – monitoring, adjustments ! version of SPI Microcontroller: MSP430F1232 ! variable length bit stream PWM controller: UCD8509 • CAN – Controller Area Network Form Factor: ¼ Brick ! 2 wire, differential bus Topology: Resonant Reset Forward ! up to 1Mb/s speed Once the communication is established the B. Circuit Descriptions power supply can talk and listen to the host The forward converter is an isolated topology computer of the larger system or it can accept and utilizes a simple two-winding transformer to commands from a human operator through a transfer power across the isolation boundary. small touch pad. This new opportunity makes Like in all forward based converters, the remote control and adjustments of the operating transformer operates in the first quadrant of the parameters and limits feasible. Furthermore the core’s magnetization curve. Accordingly, the digital controller can store and provide data about transformer core must be reset to its initial the operation of the unit for diagnostic purposes. demagnetized state before the next clock period Monitoring long term trends in the operating starts. In this converter the reset action is parameters can be a very useful tool to predict provided by the resonance between the pending failures of the power supply and to avoid magnetizing inductance of the transformer and down time of the system. the node capacitance where the primary winding connects to the drain of the switching power

6-18 transistor. Since the focus of this paper is to gain vary over a two to one range, the bootstrap familiarity with digital control, the detailed supply uses an averaging L-C filter to generate a power stage design is omitted. For completeness quasi regulated 12V rail. the schematic is provided in Fig. 14. The forward converter utilizes the The typical building blocks of the power SUM65N20-30, 200V, 30mΩ MOSFET from stage are easily recognizable in the schematic. In Vishay as the main switching transistor. Its line with industry standard design practices the current is measured by a 50:1 current sense converter has minimum on-board input transformer which is terminated by a 3Ω current capacitance, only 4uF for high frequency sense resistor and fed to the controller through a bypassing. The quarter brick requires additional low pass filter. energy storage capacitors on the system board Due to the 12V output and its simplicity, located close to the input terminals of the rectification is implemented by two Schottky module. diodes on the secondary side of the transformer. The power transformer is a planar magnetic Both diodes are equipped with a small R-C structure, manufactured by Payton Inc. The snubber to reduce the ringing on the switching primary number of turns is 7 and the secondary is waveforms. 5 turns. There is a third auxiliary transformer The averaging output filter is designed for winding which also has 5 turns and it is approximately 12A as opposed to the specified referenced to the primary side of the power 8.3A maximum to allow experimenting with supply. It is used for the bootstrap bias supply. different current limit strategies. The output When the converter is switching, the power inductor value is 10µH. There are three output consumption of the controller and gate drive capacitors in parallel, an 83µF polarized energy circuit exceeds the current capability of the high storage capacitor and two high frequency filter voltage bias circuitry which draws power directly components, 1µF and 0.1µF. from the input terminal during start up. The The schematic in Fig. 14 also indicates the bootstrap bias supply provides an efficient way to different signal connections to the control circuit power the primary side control circuit while the which is shown in Fig. 15. converter is running. Since the input voltage can

+VIN MBR0530 10uH CS+ 0.1uF 47n 3 150 50:1 +VOUT CS- 7.5 VIN 1n 7T 5T 82uF 4uF 0.1uF 470uH 7.5 1n +12V 16V 2x 5T -V 47uF BAS21 OUT -12V 2x 1uF MBR20100CT VDS MBR0530 GND +VO SUM65N20-30 OUT 5 -VO -V IN Fig. 14. 100-W resonant reset forward power stage.

6-19 OUT CS+ 10 1uF 1k +12V 5k 56p 10n 47uF 100p CS- -12V +VO VIN 1k MOC206 52.3k 9 8

14 13 12 11 10 2.7n 150pF 750 HV CS ILIM VDD OUT 72k PGND MODE UCD8509 ENA ISET 3V3 CLK CLF FB AGND 13.7k 180p TL431

1 2 3 4 5 6 7 -VO

750 1uF

2.5k 147k

MSP430F1232

1 TEST I/O-Program 28

2 VCC I/O-TestData 27 JTAG connector 3 26 I/O-ROSC I/O-Program PROGRAMMING/TEST VDS 4 VSS(GND) I/O-Program 25

100k 5 XOUT I/O-TimerA_CR 24 BYD77D 6 XIN I/O-TimerA_CR 23 15k 7 RST/NMI I/O-TimerA_CR 22 10k

1.1M 8 I/O-ADC0 I/O-ADCCLK 21 1k 9 I/O-ADC1 I/O-ADC4-Ref+ 20 10k 100p 11k 10 I/O-ADC2 I/O-ADC3-Ref- 19 1.15k 1k 11 I/O-ADC5 I/O-ADC7 18 1.07M 40k 1n 3.6k R T 12 I/O-SPIbus I/O-ADC6 17 20k 1k 13 I/O-SPIbus I/O-UART 16 27.4k 10k 10k 100p 14 I/O-SPIbus I/O-UART 15

1.8n RS232 Port

COMMUNICATION Fig. 15. Digitally assisted power supply controller of the forward converter.

6-20 The controller operates with a fixed, 500kHz Analog Functions – UCD8509 switching frequency and implements current The UCD8509 is a highly integrated analog mode control using the primary switch current companion chip to a microcontroller to information. The primary side control circuit is implement digitally assisted power supply comprised of two ICs representing the control. Its primary purpose is to provide high demarcation between analog and digital control speed, analog pulse width modulation and secure functions. The digital portion of the control over current protection. It also includes all algorithm is implemented in the MSP430F1232. auxiliary housekeeping function to service the The microcontroller is connected to the power microcontroller and a specialized interface to stage and powered through the UCD8509 type effectively communicate using only a few digital analog controller which was specifically signals. The simplified block diagram is developed for digital power supply control illustrated in Fig. 16. applications in single ended converters. The UVLO & START UP regulation of the power supply’s isolated output ENA 1 14 HV BIAS OK REG. is performed by the opto isolated error amplifier 3.3V section based on the popular TL431 integrated circuit. ISET 2 13 VDD

C. Functional Description AGND 3 VDD 12 OUT The division between analog and digital control functions is based on the capabilities of 3.3V 3V3 4 11 PGND the selected processor and the amount of BIAS REG. computational resources needed to perform the control functions. In general, the more high speed CLK 5 PWM 10 CS control functions are moved to the digital CURRENT domain, a higher performance, more expensive CLF 6 9 ILIM microcontroller or DSP is needed to execute the LIMIT control algorithm. The most difficult functions for the digital controller are the voltage FB 7 8 MODE regulation loop, the digital pulse width modulation, the implementation of peak current Fig. 16. UCD8509 simplified block diagram. mode control with slope compensation or input voltage feed forward in voltage mode control and In telecom or similar input voltage over current protection. These functions applications, an on-board start up regulator correspond to fast changing signals which have to provides initial bias to the chip which can be be measured and recalculated on the switching connected directly to the input power source. The frequency basis or require immediate action to start up regulator’s maximum input voltage is protect the power supply. The utilization of a 110V. Once the power supply is up and running, dedicated analog building block can remove the the start up regulator turns off and the auxiliary burden of these computation intensive tasks from power must be provided by a bootstrap power the processor and allow using a cost effective supply as shown in the schematic diagram in microcontroller. In addition, using analog circuits Fig. 14. The bootstrap voltage must be between for the basic high speed power supply functions 8V and 15V which is the recommended operating also permits the use of familiar analog control voltage range of the UCD8509. principles to ensure the stability of the power The on-board 3.3V regulator draws power supply. The development of an analog controller from the VDD rail and provides bias to the IC’s also presents the opportunity to optimize the internal circuits and to the microcontroller. The partitioning and the signal interface between the maximum external current consumption must be digital and analog portions of the controller. kept below 10mA, thus using a low power microcontroller is desirable.

6-21 The UCD8509 includes a high current output autonomous over current protection for the power to drive the gate of an external power MOSFET. stage without any help from the microcontroller. The gate driver switches between ground and the This function is implemented in the current limit actual VDD voltage and has approximately 4A block. For autonomous operation the UCD8509 sink and 2.5A source current capability. has a default, internally set 0.5V current limit The controller also accommodates a high threshold which can be overridden by the speed analog PWM section which can be set up microcontroller or by an external resistor network for voltage or peak current mode operation through the ILIM terminal. For added protection, according to the MODE input. The operating the current limit adjustment range is internally mode can be selected by shorting the pin to limited between ground and twice the default ground or to 3.3V, or by the microcontroller value, i.e. between 0V and 1V. In case the cycle driving the MODE pin directly. While the by cycle current limit circuit is activated, the UCD8509 has no oscillator, an internal local UCD8509 will set the current limit flag (CLF) ramp generator is employed for the pulse width output high which can be read by the digital modulation in voltage mode. The same ramp controller. The flag is automatically cleared generator is used to provide slope compensation before the beginning of the next switching period in current mode. The slope of the ramp is making it easy for the microcontroller to count adjusted by an external resistor connected to the the number of switching periods terminated by ISET pin. The converter’s operating duty cycle is the current limit circuit. controlled by the error voltage which has to be The operating principle of the UCD8509 and connected to the FB pin. the interaction between the microcontroller and One of the most important features of the the analog PWM block can be explained using UCD8509 is to provide instantaneous and the timing diagram in Fig. 17.

Start up Steady State Current limit UVLO & BIAS OK*

ENA

CLK

RAMP*

FB

PWM*

OUT

CLF

* - Internal signals

Fig. 17. UCD8509 timing diagram (voltage mode operation).

6-22 During initial start up the UCD8509 CLF signal goes high for the remainder of the establishes its own bias voltage (VDD) and the switching period and the information can be 3.3V bias for the microcontroller. During this managed by the microcontroller according to its time the CLF output is high, indicating for the software. digital circuit that the analog functions are not yet An important feature of the current limit available. When all internal voltages are at their block is its complete independence from the nominal level the CLF signal is cleared and the signals of the digital controller. The current limit operation can commence. At that time the event is latched and kept in the memory of the microcontroller is expected to enable the UCD8509 until the next switching period is operation by setting the enable signal high and initiated by the microcontroller. This technique start sending the CLK pulse train. can protect the power stage in case the digital The CLK signal carries two important pieces controller stalls. The CLK input can freeze in of information to supervise the operation of the either state, the current limit circuit will protect UCD8509. As shown in Fig. 17, coinciding with the power stage and keep the power switch off the rising edge of CLK signal the pulse width until the pulse train is restored and the next rising modulator is reset and the gate drive output turns edge of the CLK signal resets the current limit on indicating the beginning of the next switching circuit. period. Thus the switching frequency is Software Functionality determined by the rising edge of the waveform. Since the UCD8509’s control functionality is The width of the CLK pulse limits the maximum limited to pulse width modulation, peak current on-time of the gate drive output. In fact, the duty limiting and start up bias generation, all other ratio of the CLK signal is used as a variable control functions on the primary side of the maximum duty cycle clamp. According to the power supply must be executed by the digital functions programmed in the microcontroller, the controller. Accordingly, the MSP430F1232 width of the CLK pulse is continuously controls the following functions in the recalculated by the digital controller and can be demonstration power supply: used to implement several control functions. • Operating frequency Fig. 17 exemplifies how to use the CLK pulse • Input line UVLO width to implement soft-start. • During normal operation the converter’s duty Input line OVP • ratio is less than the limit imposed by the digital Absolute duty cycle limit – DMAX • controller, hence it is determined strictly by the Volt-second clamp – DLIM(VIN) • analog PWM circuit of the UCD8509. Therefore Soft-start – DLIM(tSS) the time domain resolution of the microcontroller • Current limit threshold adjustment is not a concern anymore. Assuming that the • Current limit profile (delayed shutdown based voltage regulation loop is also analog, as it is the on the number of allowable events) case in the example power supply in Fig. 14 and • Temperature shutdown 15, the small signal stability of the power supply • MOSFET over voltage protection can be ensured by obeying the familiar analog In order to perform these functions the rules. microcontroller needs to know the following In current limit, the UCD8509’s cycle-by- variables: cycle current limit comparator overrides both • fCLK – its own clock frequency duty cycle values – the pulse width of the CLK • fSW – switching frequency input and the duty cycle of the analog pulse width • VIN,ON – turn-on input voltage thresholds modulator. The gate drive pulse terminates when • VIN,OFF – turn-off input voltage thresholds the switch current reaches the current limit • DMAX – maximum allowable duty ratio based threshold. The threshold can be the default value on the reset requirements of the transformer or the adjusted voltage present at the ILIM pin. • DC transfer function – to calculate When the current limit circuit is activated the appropriate volt-second limit

6-23 • tSS – duration of the soft-start interval In addition to the values entered by the user, • TMAX – maximum board temperature the digital controller must measure and handle • VDS,MAX – highest acceptable drain-source four more inputs: voltage • VIN – input line voltage These numbers can be entered through the • VDS – drain to source voltage graphical user interface of the demonstration • TBOARD – board temperature software and will be incorporated in the • CLF – current limit flag executable code of the microcontroller. The The demonstration hardware measures two screen shot of the demonstration software’s user additional parameters for future expansion of the interface is pictured in Fig. 18. software functionality. These are VFB and IIN,AVE, the feedback voltage and the average input current, respectively.

Fig. 18. Graphical user interface of the demonstration software.

6-24 maximum input voltage transient, the gain of the Setting the Operating frequency resistive divider can be calculated as: The MSP430F1232 is set up with a core clock frequency of 8MHz which frequency = 2.5V = GINPUT 0.025 corresponds to the execution of the program 100V instructions. The microcontroller can be tricked This factor is implemented by the 1.07MΩ to operate its PWM timer at twice the clock and 27.4kΩ resistors which are connected to the frequency, which opportunity was utilized in this ADC6 input of the MSP430F1232 through an design. Based on fCLK=16MHz and fSW=500kHz, additional noise filter as shown in Fig. 15, the the switching period consists of: schematic diagram of the controller. 16 ⋅106 Hz The ADC of the MSP430F1232 is a 10-bit n = = 32 analog-to-digital converter, therefore the 100V ⋅ 3 500 10 Hz full scale input voltage range is represented by clock cycle of the PWM timer. Accordingly, 210=1,024 individual values and the measurement the minimum duty cycle adjustment can be resolution is: calculated as: 100V 1 res = ≅ 98mV ∆t = = 62.5ns INPUT 210 ⋅ 6 16 10 Hz As this number indicates it is really easy to or the duty cycle resolution is given as: accurately adjust the turn-on or turn-off input ∆ = ⋅ 3 ⋅ = D 500 10 Hz 62.5ns 0.03125 voltage levels of the power supply. The Because the pulse width modulation is still demonstration circuit uses the result of the input done in analog by the UCD8509, the voltage measurement to provide software microcontroller’s resolution impacts only the programmable line under and over voltage accuracy of the maximum duty ratio and the protection with user adjustable hysteresis and to volt-second limit. For these functions the implement an input voltage dependent duty ratio achieved resolution is sufficient. limit, also known as volt-second clamp. The V·s Since the core of the microcontroller runs clamp is based on the DC transfer function of the only with an 8 MHz clock frequency, every power stage and can be calculated as: switching period contains 16 instruction cycles = VOUT ⋅ N P ⋅ ≅ ⋅ 1 for program execution. DLIM (VIN ) 1.2 18.5 VIN N S VIN Maximum Duty Cycle where NP and NS are the primary and The power stage design allows a maximum secondary number of turns of the transformer and operating duty ratio of approximately 80% to the 1.1 multiplier indicates that the volt-second accommodate the reset time of the transformer. clamp is set 10% higher than the operating duty To provide some margin the controller is set up ratio of the converter. The working of the volt- to limit the duty ratio at 75% or 24 clock cycles second routine is demonstrated in Fig. 19 through of the PWM timer (32·0.75=24). 21. Input Voltage Measurement Knowing the actual input voltage value allows the digital controller to perform several housekeeping and protection functions. In this design the input voltage is measured by the on- board analog-to-digital converter. Since the ADC input is limited to the 0V – 2.5V range by the reference of the analog-to-digital converter, the anticipated input voltage range must be scaled down to meet this constraint. Assuming 100V

6-25 The converter’s steady state operating duty CLK ratio can be deciphered from the VDS waveform OUT of the switching transistor. The maximum allowable duty ratio (DLIM(VIN)) is calculated by the microcontroller and it is based on the actual input voltage level. Its value is represented by the duty ratio of the CLK waveform. As the three V DS figures demonstrate, the duty ratio of the CLK signal is approximately 10% higher than the operating duty cycle of the converter at all three I D input voltages. Soft-Start The soft-start time of the converter can be programmed through the software and will be Fig. 19. Operating waveforms at VIN = 36 V. implemented by the digital controller by gradually increasing the duty ratio of the converter. It is the same method outlined earlier CLK in the Soft-Start Operation section under OUT Miscellaneous Control Functions. The practical implementation starts by calculating the number of duty cycle values between zero duty cycle and DMAX. ⋅ 6 V fCLK 16 10 Hz DS SS = ⋅ D = ⋅0.75 = 24 STEPS MAX ⋅ 3 fSW 500 10 Hz If the duty cycle limit would be increased by one step in every switching period the converter ID would reach maximum duty cycle in 24 switching period or in 60us. This is an unusually fast start up and it is also questionable whether Fig. 20. Operating waveforms at VIN = 48 V. the output capacitor can be charged to the nominal level within this time interval. To

achieve a reasonable soft-start time in the CLK milliseconds range, each of the 24 duty cycle values between zero and DMAX has to be OUT maintained for several switching periods. For instance, if the soft-start time is given as tSS=5ms, each duty ratio must be valid for nSS number of switching cycles which can be obtained as: V ⋅ 3 DS = fSW ⋅ = 500 10 Hz ⋅ ≅ nSS tSS 0.005 104 SSSTEPS 24 The effect of the gradually increasing discrete

ID duty cycle values is demonstrated in Fig. 22. In order to show the step function in the output voltage waveform the soft-start time had to be extended to approximately 8 seconds. Fig. 21. Operating waveforms at VIN = 76 V.

6-26 To override the default 0.5V current limit threshold of the analog current limit circuit, its ILIM pin voltage needs to be overridden. For current limit adjustment the UCD8509 expects an analog voltage at the ILIM terminal which can be generated by the microcontroller. Since the MSP430F1232 has no digital-to-analog converter V O on-board, the function is implemented by four of its digital I/O ports and an external resistor network as shown in Fig. 24. 40k I/O-SPIbus 12 9 ILIM 20k I/O-SPIbus 13 1n Fig. 22. Output voltage waveform with 10k artificially long soft-start time. I/O-SPIbus 14 2.49k I/O-TimerA_CR 22

MSP430F1232 UCD8509

Fig. 24. Current limit adjustment using “poor man’s DAC”.

V The digital output ports are three state O outputs, they can be high impedance or connected either to GND or to the VCC voltage of the microcontroller. When all four outputs are high impedance, the default 0.5V threshold of the UCD8509 prevails. Assuming that pin 22 of the MSP430F1232 is connected to ground, to limit Fig. 23. Output voltage ramp up with 5ms soft- the maximum ILIM voltage below the 1V start time. maximum threshold of the UCD8509, the microcontroller can select from 27 individual The normal 5ms long soft-start waveform of current limit thresholds between 0V and 1V using the converter is shown in Fig. 23 and it the other three ports. demonstrates the usual monotonic ramp up of the During overload, the conduction time of the converter’s output voltage. power MOSFET is limited by the cycle-by-cycle Current Limit Operation current limit circuit. When the current sense Using the capabilities of the UCD 8509, the signal amplitude reaches the current limit digital controller is able to adjust the current limit threshold the gate drive output is immediately threshold and also the overload behavior of the terminated to protect the power stage. This event power supply. is indicated by the CLF pin of the UCD8509 going high and can be read by the microcontroller. The typical waveforms of the converter in current limit mode are shown in Fig. 25.

6-27 In order to eliminate any potential noise CLK coupling, its signal is filtered near the input pin OUT (pin 11 – I/O-ADC5) of the MSP430F1232. The shut down threshold as well as the hysteresis of the temperature protection is user adjustable using the parameter entry screen of the demonstration software. VDS MOSFET Over Voltage Protection The last protection function of the converter is based on the peak voltage stress of the primary CLF MOSFET. The maximum voltage across the drain source terminal of the device is scaled and peak rectified. Once the measured stress voltage Fig. 25. Current limit operation. reaches the user entered shutdown threshold the converter stops operating. The shut down is In this design the power supply is allowed to followed by an automatic restart, initiating the operate in current limit mode for a fixed number full soft-start routine. of switching cycles before it shuts down. The number of cycles in current limit mode before Software Algorithm shut down can be entered by the user through the Without going too deep into the fine details GUI of the demonstrations software. This of the software, one important characteristic of operating mode allows short periods of overload the controlling algorithm must be highlighted. In conditions – occurring typically during load most applications the available computational transients – without the need to increase the resources and data conversion speed necessitates steady state current limit of the power supply. that the execution of the software functions are distributed over several switching periods. Temperature Protection Accordingly, the functions are divided to two The demonstration power supply is equipped categories; basic functions which must be with a temperature shut down feature based on executed in every switching period and auxiliary the board temperature of the module. In order to routines which are scheduled over a longer get a better reading of the critical temperature of period. This scheduling technique is the power components, an external sensor is demonstrated in Fig. 26. favored over the built-in temperature sensor of the microcontroller. The thermistor is placed in close proximity to the power MOSFET.

IN IN IN DS IN,AVE limit LIM LIM IN limit IN DS BOARD DS IN,AVE BOARD Read V Read V Read V Read I Update D Update D Read T Check V Start MeasureV Start MeasureV Start MeasureV Check T Start Measure V Update Parameters Update Parameters Update Service RS-232 port Service RS-232 port Start Measure I Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Check UVLO & OVP Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Timebase & CLKset Check UVLO & OVP Timebase & CLKset Timebase & CLKset

T SW Fig. 26. Software scheduling example.

6-28 The diagram shows the program flow in This short description of the software does steady state operation. The basic time base and not attempt to cover all aspects of the software CLK signal generation functions are performed development, but rather to show the level of in every switching cycle since they are essential expertise required to write the program. When to the proper operation of the analog companion power supply engineers make the first steps circuit. In every third cycle the microcontroller towards digital control, it might be wise to initiates a signal measurement. The frequency of supplement their vast amount of power supply the ADC conversions is limited by the maximum know-how with the proficiency of a skilled speed of the analog-to-digital converter of the software engineer as it was the case in this microcontroller. Since the most important input project. parameter is the input voltage, every second measurement cycle is dedicated to the input VI. SUMMARY voltage measurement. In between the input This paper aimed to introduce digital power voltage measurements the other analog supply control to the practicing power supply parameters are measured in a rotating fashion. design community. Like most new technology, Once a measurement result is available, the digital control in power supplies is expected to microcontroller recalculates its internal variables start its proliferation slowly. But this is definitely and compares the measurement result against the a trend not to overlook in the years to come. limit values of the particular variable. In addition, At the same time, it is important to remember a significant amount of the microcontroller’s that the power supply is still a fundamentally resources are reserved for communication in the analog circuit. The knowledge of various power demonstration software because of the frequent supply topologies and related analog design update of the displayed results. expertise can not be substituted even by the most Some of the software functions are assisted advanced software algorithm. On the other hand, by specialized hardware resources in the digital implementation of the converter’s control MSP430F1232. For instance, no significant offers new opportunities to develop advanced resources are allocated to handle the CLF signal. features and make the power supply a more The number of current limit cycles is counted by visible, more integrated part of the system. the microcontroller’s capture & compare register While transitioning to full digital control which generates an interrupt when the allowed might require a completely different approach number of consecutive current limit cycles is and skill set in the controller design, the circuit reached. example of this paper presents a practical, intermediate step towards that final goal. As demonstrated by this converter, advanced features and protection functions, and communication capability can be integrated cost effectively and reliably in a quarter brick form factor.

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