International Journal of Science, Engineering and Technology A Peer Reviwed Journal

Volume 1 | Issue 1 | October – November 2013

For detailed manuscript submission guidelines, visit http://www.ijset.in/?pageid=110 Volume 1 | Issue 1 | October‐ November 2013

International Journal of Science, Engineering and Technology

Volume 1 | Issue 1| October‐ November 2013

Editorial Board

Editor in Chief

Dr. Kavita Sharma

Editorial Board Member

Dr. Anil Gupta

Dr. Priyanka Gupta

Mr. Saurabh Shukla

Mr. Naveen Upadhyay

Mr. Kshitiz Agarwal

Prof. Mohsin Jamal

(Dr.) Jitendra Joshi

Mr. Parvin Kumar

Dr. Sanjay Kumar

Dr. Raghvendra Kr. Mishra

Mr. Narendra Singh Rathore

(Dr.) Giriraj Kumar Patidar

Mr. Anoop Singhal

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Volume 1 | Issue 1 | October‐ November 2013

International Journal of Science, Engineering and Technology

Volume 1 | Issue 1| October‐ November 2013

CONTENTS

A Mechanics for Assuring Data Storage Security in Cloud Computing 3 Priya, Pratibha Gangwar, Mamta Gadoria VHDL Implementation for FSM Based Approaches of Traffic Light Controller 8 Nidhi Gopal, Madhuri Panwar, Pinky Gupta TAUR’S Model: An Analytical Solution for Drain Current in Undoped Body SDG 12 MOSFET Madhuri Panwar, Nidhi Gopal, Naveen Upadhyay Image Compression Technique Using Wavelet Transformation 16 Nidhi Gopal, Madhuri Panwar, Naveen Upadhyay Automatic Telephone Answering Machine With Image Processing 20 Richa Singh Rathore, Disha Malik 32‐bit Arithmetic Logical Unit (ALU) using VHDL 25 Disha Malik, Richa Singh Rathore Server Clustering Technology and Concept 31 Vaibhav Mathur M00383937, Computer Network, Middlesex University Cookies, and it’s tracking mechanism for User’s Identification 37 Vaibhav Mathur, M00383937, Computer Network, Middlesex University A Broadband Biconical Antenna for Wide Angle Reception 41 Saurabh Shukla, Naveen Upadhyay A Combination of Video Games and Artificial Intelligence 45 Jaya Sachan Accomplishment and Timing Presentation: Clock Generation of CMOS in VLSI 50 Manoj Kumar Choudhary

Dynamic Model Representation in the Locality Frequent Neural Networks 55 Jitendra Joshi, Ritu Nagwani, Renu Deswal, Priyanka Sharma

Future of V Band in Satellite Communication 60 Ashish Tyagi, Chandan Choudhary, Naveen Upadhyay

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A MECHANICS FOR ASSURING DATA STORAGE SECURITY IN CLOUD COMPUTING

1Priya, 2Pratibha Gangwar, 3Mamta Gadoria 1M. Tech. Scholar, Jayoti Vidyapeeth Women’s University, Jaipur, [email protected] 2M. Tech. Scholar, Jayoti Vidyapeeth Women’s University, Jaipur, [email protected] 3M. Tech. Scholar, Jayoti Vidyapeeth Women’s University, Jaipur, [email protected] ABSTRACT Cloud Computing has been visualized as the next generation architecture of IT Enterprise. In contrast to traditional solutions, where the IT services are under proper physical, logical and personnel controls, Cloud Computing moves the application software and databases to the large data centers, where the management of the data and services may not be fully trustworthy [3]. This unique attribute however, poses many new security challenges which have not been well understood. In this we focus on cloud data storage security, which has always been an important aspect of quality of service. To provide the correctness of users’ data in the cloud, we propose an effective and flexible distributed scheme with two salient features, opposing to its predecessors. By utilizing the homomorphic token with distributed verification of erasure‐coded data, our scheme achieves the integration of storage correctness insurance and data error localization, i.e., the identification of misbehaving server(s). Unlike most prior works, the new scheme further supports secure and efficient dynamic operations on data blocks, including: data update, delete and append. Extensive security and performance analysis shows that the proposed scheme is highly efficient and resilient against Byzantine failure, malicious data modification attack, and even server colluding attacks. Index Terms: Cloud Computing, Cloud Service Provider, Cloud data storage, Error localization 1. Introduction integrity of their data [2]. From the perspective of data Organizations today are increasingly looking towards security, which has always been an important aspect Cloud Computing as a new revolutionary technology of quality of service,. Considering various kinds of data promising to cut the cost of development and for each user stored in the cloud and the demand of maintenance and still achieve highly reliable and long term continuous assurance of their data safety, elastic services. The Cloud technology is a growing the problem of verifying correctness of data storage in trend and is still undergoing lots of experiments. Cloud the cloud becomes even more challenging. . The data promises huge cost benefits, agility and scalability to stored in the cloud may be frequently updated by the the business. All business data and software are users, including insertion, deletion, modification, stored on servers at a remote location referred to as appending, reordering, etc. To ensure storage Data centers [1]. Cloud Computing is an Internet‐based correctness under dynamic data update is hence of development. Users can now subscribe high quality paramount importance [3]. services from data and software that reside solely on remote data centers. The pioneers of Cloud 2. Problem Statement Computing Vendors are Amazon Simple Storage The proposed system has three important entities. Service (S3) and Amazon Elastic Compute Cloud (EC2) User: Users store data in the cloud and depend on the [5]. While these internet‐ based online services do cloud for all its computations on the data stored in the provide huge amounts of storage space and cloud. customizable computing resources, this computing Cloud Service Provider (CSP): CSP contains resources platform shift, however, is eliminating the and expertise in building and managing distributed responsibility of local machines for data maintenance cloud storage servers, owns and operates and leases at the same time. As a result, users are at the mercy of the live Cloud computing systems. their cloud service providers for the availability and

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Third Party Auditor (TPA): TPA has expertise and capabilities that users may not have, is trusted to assess, audit and expose risk of cloud storage services on behalf of the users upon request from the users. A special entity is considered to ensure the security and dependability of the Cloud Server referred to as

Adversary Model. The adversary is interested in Figure 1.1: Cloud data storage architecture continuously corrupting the user’s data files stored on individual servers. Once a server is comprised, an A. Limitations of Existing System : These adversary can pollute the original data files by techniques, while can be useful to ensure the storage modifying or introducing its own fraudulent data to correctness without having users possessing data, prevent the original data from being retrieved by the cannot address all the security threats in cloud data user [4]. storage, since they are all focusing on single server

scenario and most of them do not consider dynamic 3. Cloud Data Storage Architecture With Existing data operations. As a complementary approach, System researchers have also proposed distributed protocols From the perspective of data security, which has for ensuring storage correctness across multiple always been an important aspect of quality of service, servers or peers. Again, none of these distributed Cloud Computing inevitably poses new challenging schemes is aware of dynamic data operations. As a security threats for number of reasons. result, their applicability in cloud data storage can be 3.1 Firstly, traditional cryptographic primitives for the drastically limited.[4] purpose of data security protection cannot be directly adopted due to the users’ loss control of data under B. Proposed System Cloud Computing. Therefore, verification of correct In this paper, we propose an effective and flexible data storage in the cloud must be conducted without distributed scheme with explicit dynamic data support explicit knowledge of the whole data. Considering to ensure the correctness of users’ data in the cloud.. various kinds of data for each user stored in the cloud This construction drastically reduces the and the demand of long term continuous assurance of communication and storage overhead as compared to their data safety, the problem of verifying correctness the traditional replication‐based file distribution of data storage in the cloud becomes even more techniques. Whenever data corruption has been challenging. detected during the storage correctness verification, 3.2 Secondly, Cloud Computing is not just a third party our scheme can almost guarantee the simultaneous data warehouse. The data stored in the cloud may be localization of data errors, i.e., the identification of the frequently updated by the users, including insertion, misbehaving server(s) [4]. delete ion, modification, appending, reordering, etc. C. Advantages of Proposed System To ensure storage correctness under dynamic data 1. Compared to many of its predecessors, which only update is hence of paramount importance. provide binary results about the storage state across

the distributed servers, the challenge‐response protocol in our work further provides the localization of data error. 2. Unlike most prior works for ensuring remote data integrity, the new scheme supports secure and

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Volume 1 | Issue 1 | October‐ November 2013 efficient dynamic operations on data blocks, including: 3. Let f be the function and t be the token ; update, delete and append. 4. Index per proof is denoted as r; 3. Extensive security and performance analysis shows 5. Generate M k and C k ; that the proposed scheme is highly efficient and 6. For point G (j); j‐>1, n execute /*j server resilient against Byzantine failure, malicious data position*/ modification attack, and even server colluding attacks. 7. For round i‐>1, t execute /*i block index*/ 8. Derive i = f (i) and k (i) from master key. Compute D. Token correctness v(j) It achieves assurance for data storage correctness and 9. End for data error localization, using pre‐computed token. 10. End for Before sharing file distribution using pre‐computes a 11. Store all the Vis locally. certain number of shortest verification token are 12. End procedures generated that will ensure security for a block of data 5. Correctness Verification and Error Localization in a file in cloud storage. When the user wants to make Error localization is a key requirement for eradicate sure the storage correctness for the data in the cloud, errors in storage systems. However, many previous he challenges the cloud servers with a set of randomly schemes do not explicitly consider the problem of generated block indices. After getting assurance of data error localization. The challenges response the user it again asks for authentication by which the protocol in our work future provides the localization user is confirmed to be the authenticated user. Upon of data error. This only provides binary results about receiving assurance, each cloud server computes a the storage state across the distributed service in short “signature” over the specified blocks and predecessors. The response values from servers for returns them to the user. The values of these each challenge not only determine the correctness of signatures should match the corresponding tokens the distributed storage, but also contain information pre‐computed by the user. All servers operate over the to locate potential data error(s). Specifically, the same subset of the indices, the requested response procedure of the ith challenge response for a cross‐ values for integrity check must also be a valid check over the n servers is described as follows: codeword determined by a secret matrix. Suppose the  The client reveals the i as well as the ith key k (i) user wants to challenge the cloud server’s t times to to each servers make sure the correctness of data storage. Then, he  The server storing vector G aggregates those r must pre‐compute t verification tokens for each rows function, a challenge key and a master key are used.  Specified by index k(i) into a linear combination R To generate the ith token for server j, the user acts as  Upon receiving R is from all the servers, the user follows the details of token Generations are shown in takes away values in R. Algorithm 1.  Then the user verifies whether the received  Derive an arbitrary value i and a permutation key values remain a valid codeword determined by based on master permutation key. secret matrix.  Calculate the set of randomly‐chosen index. Because all the servers operate over the same subset  Calculate the token using encoded file and the of indices, the linear aggregation of these r specified arbitrary value derived. rows (R (1) i. . . R (n) i) has to be a codeword in the 4. Algorithm for Token Pre‐computation encoded file matrix. If the above equation holds, the 1. Block of data is represented as l; challenge is passed. Otherwise, it indicates that among 2. No. of .blocks is denoted as n; those specified rows, there exist file block corruptions.

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Once the inconsistency among the storage has been successfully detected, we can rely on the pre‐ computed verification tokens to further determine where the potential data error(s) lies in. Note that each response R (j) i is computed exactly in the same way as token v (j) i, thus the user can simply find which server is misbehaving by verifying.

6. Experimental Results

Fig.1.5 Misbehaving Server Model

7. Conclusion In this paper, we investigated the problem of data security in cloud data storage, which is essentially a distributed storage system. To ensure the correctness of users’ data in cloud data storage, we proposed an effective and flexible distributed scheme with explicit

Fig.1.2 Authorized Person Login dynamic data support, including block update, delete, and append. We rely on erasure‐correcting code in the file distribution preparation to provide redundancy parity vectors and guarantee the data dependability. By utilizing the homomorphic token with distributed verification of erasure coded data, our scheme achieves the integration of storage correctness insurance and data error localization, i.e., whenever data corruption has been detected during the storage correctness verification across the distributed servers, we can almost guarantee the simultaneous identification of the misbehaving server(s)[3]. Through detailed security and performance analysis, Fig.1.3 Cloud Data Storage we show that our scheme is highly efficient and resilient to Byzantine failure, malicious data modification attack, and even server colluding attacks. We believe that data storage security in Cloud Computing, an area full of challenges and of paramount importance, is still in its infancy now, and many research problems are yet to be identified. We envision several possible directions for future research on this area.

Fig.1.4 User Side Login

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References 1. Cong Wang, Qian Wang, and Kui Ren, Wenjing Lou,” Ensuring Data Storage Security in Cloud Computing” IEEE Paper. 2. Wang, K. Ren, W. Lou, and J. Li, “Towards publicly auditable secure cloud data storage services,” IEEE Network Magazine, vol. 24, no. 4, pp. 19–24, 2010. 3. Rampal Singh, Sawan Kumar, Shani Kumar Agrahari,”Ensuring Data Storage Security in Cloud Computing”, International Journal Of Engineering And Computer Science ISSN:2319‐7242. 4. S. Mohamed Saleem and P. Sasi Kumar,” Security Issues : Efficient Secured Data Storage Operations In Cloud Computing Environment”, vsrd international journal of computer science & information technology, vol. 2 no. 10 october 2012, issn no. 2231‐2471 (online), 2319‐2224 (print) © vsrd international journals : www.vsrdjournals.com 5. Vasu Raju, Raj Kumar, and Anand Raj,” Techniques for Efficiently Ensuring Data Storage Security in Cloud Computing” Vasu Raju et al, Int. J. Comp. Tech. Appl., Vol 2 (5), 1717‐1721 IJCTA | SEPT‐OCT 2011 Available [email protected] 1717 ISSN:2229‐6093. 6. Case study: http://eyeos.org/ cloud desktop. 7. Amazon.com, “Amazon Web Services (AWS),” Online at http://aws. amazon.com, 2008 8. http://searchcloudcomputing.techtarget.com/resource s#parentTopic4 9. K.Valli Madhavi, R.Tamilkodi, R.BalaDinakar,” Data Storage Security in Cloud Computing for Ensuring Effective and Flexible Distributed System”, International Journal of Electronics Communication and Computer Engineering Volume 3, Issue (1) NCRTCST, ISSN 2249 –071X. 10. M. A. Shah, R. Swaminathan, and M. Baker, “Privacy‐preserving audit and extraction of digital contents,” Cryptology ePrint Archive, Report 2008/186, 2008, http://eprint.iacr.org/.

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VHDL IMPLEMENTATION FOR FSM BASED APPROACH OF TRAFFIC LIGHT CONTROLLER

Nidhi Gopal1, Madhuri Panwar2, Pinky Gupta3

1M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, Indiia, [email protected]

2M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, [email protected]

3Assistant Professor, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, [email protected]

Abstract

Finite state model is the best method now‐a‐days for describing control systems, since it represents temporal behavior of systems, in the form of states and transitions between them. This modeling technique for sequential logic circuits is very helpful in designing circuits which have well defined inputs, containing all possible system states necessary conditions of transitions, and all possible outputs from each state. This paper deals with VHDL implementation for FSM based approach for traffic light control systems. Traffic light controller follows a timed FSM architecture. Since VHDL is a very powerful and flexible language, code for this FSM is made, and results are observed.

Index terms: Control systems, FSM, VHDL

1. INTRODUCTION TO FINITE STATE MACHINES elevator should go down 2 floors, u2 means that the elevator should go up 2 floors, and n means that the A Finite State Machine (FSM) is an example of a state‐ elevator should stay idle. From the figure, we can see oriented model. A state oriented model is that which that if the current floor is 2 (i.e. the current state is S ), represents the system as a set of states and a set of 2 transitions between them, which are triggered by and floor 1 is requested, then the output will be d1. external events. A state‐oriented model is most suitable for control systems, such as real time reactive systems, where the system’s temporal behavior is the most important aspect of the design. Basically, the FSM model consists of a set of states, a set of transitions between them, and the set of actions associated with these states, or, transitions. More formally, a FSM is a quintuple:‐ < S, I, O, f: S I → S, h: S I → O > where S= {s1, s2,…sl} is a set of states, I = {i1, i2,….im} is a

set of inputs and O= {o1, o2,….on} is a set of outputs, ‘f’ is a next state function, which determines the next state from current state and input, and ‘h’ is an output Figure 1: Finite State Model for an elevator function, which determines the outputs, also from the Controller current states and input. Note that each FSM has a state that is distinguished as a start state and a set of states 1.2 Types of FSM : distinguished as final states. There are two types of FSM models: Mealy Model and 1.1 Example Moore Model The figure below shows FSM that models an elevator 1. Mealy Model : controller in a building with three floors. In this model, a) It is a transition based model. the set of inputs, I= {r , r2, r3} represents the floor 1 b) In this, the output value depends on the requested. For example r2 means that floor 2 is state and input values (h:S I → O) requested. The set of outputs O= {d2, d1, n, u1, u2} represents the direction and number of floor the c) The example discussed above is an example of Mealy model. elevator should go. For example, d2 means that the

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d) Practically, it requires less state than Moore Traffic light system is a best way to manage traffic in model, because there may be multiple arcs cities. It helps in avoiding aaccidents and manage rules pointing to a single state, each arc having and regulation for the vehicles as well as humans. Traffic different output value. light controller is a main part of traffic control system.

2. Moore Model: a) It is a state based model. b) In this, the output values depends only on the states of FSM (h: S O) c) Practically, it requires more states, as all the output values would require its own state.

1.3 Controller architecture : Figure 3: 2‐way Traffic Light Controller showing Red, Yellow and Green colors

1) Three modes of operation: regular test, and standby. 2) In regular mode : Four states of operation, called RG (red in direction 1 and green in direction 2 ON), RY (Red in direction 1 and Figure 2: A generic FSM block Diagram yellow in direction 2 ON), GR(Green in direction The controller architecture of FSM is application specific 1 and red in direction 2 ON), and YR(Yellow in architecture. It is the simplest form, and a straight direction 1 and red in direction 2 ON), each with forward implementation of FSM defined by < S, I, O, f, an independent time duration. h>. 3) In test mode: Allow all preprogrammed times A controller consists of a register, and two to be overwritten (by a manual switch) with a combinational blocks (As shown in figure). The register small value, such that the system can be easily is usually called the “state register”, is designed to store tested during maintenance (1 second per the states in S, while the two combinational blocks, state). referred to as the “Next state function” and the “Output 4) In standby mode: If set (by a sensor accusing Function”, implements the function f and h. “Inputs” malfunctioning, for example, or by a manual and “Outputs” are representations of Boolean signals, switch) the system should activate the yellow that are defined by sets I and O. lights in both directions, remaining so while the There are two types of Controllers: standby signal is active. 1. Transition Based: Output function is dependent 5) High precision is not required in this kind of upon two parameters, namely, state registers and application, so assuume that the clock is a 60 Hz inputs. square wave derived from the power line itself 2. State based: Output function is dependent only on (otherwise, a regular crystal oscillator should State registers. be employed).

Note: Since the inputs and output are Boolean signals, in 2.1 Simulation: either case, this architecture is well suited to implementing controllers that do not require complex The state diagram for traffic light controller is shown in data manipulation. The controller synthesis consists of the figure. Also, in this, the time values change with the state minimization and encoding, Boolean minimization state and with the operating mode (regular or test). and technology mapping for the nest state and output Note that all transitions are timed only. The inputs are functions. clk, stby, and, test, while the output are r1, y1, g1, r2, y2 and g2 (red, yellow, and green lights in directions 1 and 2. FSM FOR TRAFFIC LIGHT CONTROLLER 2).

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A VHDL code for this FSM obeying the modified template introduced in this section. The time values were specified using GENERIC declaration.

Figure 4 : State‐ Transition Diagram for Traffic Light Figure 5: I/P‐ O/P Block Diagram CController

STATE OPERATING MODES

Regular Test Standby

Timer : Timer : Timer :

RG timeRG(30s) timeTEST ‐‐‐‐ (1s) Figure 6: RTL Schematic View

RY timeRY(5s) timeTEST ‐‐‐‐ (1s)

GR timeGR(45s) timeTEST ‐‐‐‐‐ (1s)

YR timeYR(5s) timeTEST ‐‐‐‐ (1s) Figure 7: Output Test bench Waveform Table 1: Table depicting Operating Modes of TLC 4. ACKNOWLEDGEMENT

The authors would like to thanks to Head of Departmant, Mr. Koushik Chakraborty, Jayoti Vidyapeeth 3. SIMULATION RESULTS Womens University, Jaipur and Dr. S. Lal, Dean‐ Engineering, Jayoti Vidyapeeth Womens University, After implementation of a VHDL code for two way traffic Jaipur for his continuous support and encouragement. Light controller, we’ve got the following simulation results. 5. REFERENCES

[1]. Circuit Design and Simulation with VHDL, by Volnei A. Pedroni.

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[2]. Specification and design of Embedded systems, by Daniel D. Gajski, Frank Vahid. [3]. WM El‐Medany, MR Hussain, “FPGA Based Advanced Real Traffic Light Controller”. 4th IEEE Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 6‐8 Sept. 2007 Page(s):100 – 105.

6. BIOGRAPHIES:

Nidhi Gopal did her B.tech in ECE from Jayoti Vidyapeeth Womens University, Jaipur, Rajasthan. She is pursuing M.tech in VLSI from JVWU. Her area of interest are Digital Image processing, IC designing etc.

Madhuri Panwar did her B.Tech in ECE from Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan. She is pursuing M.Tech in VLSI from JVWU. Her area of interest are Electronics devices and circuits, Microelectronics etc.

Pinky Gupta did her M.tech in VLSI from Banasthali Vidyapeeth, Jaipur, Rajasthan. She is currently working as assistant professor in JVWU, Jaipur, Rajasthan. Her areas of interests are CAD of IC’s etc.

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TAUR’S MODEL: AN ANALYTICAL SOLUTION FOR DRAIN CURRENT IN UNDOPED BODY SDG MOSFET

Madhuri Panwar1, Nidhi Gopal2, Naveen Upadhyay3

1M.Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, [email protected]

2M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, [email protected]

3Assistant Professor, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, [email protected]

Abstract

This paper presents a long channel drain current model for undoped SDG MOSFET which is based on Taur’s approach. The model is derived rigorously from the exact solution to Poisson’s and current continuity equation without the charge‐sheet approximation. The model involves implicit functions, iterations are required to solve the equations. It is shown that the results of the analytic model exhibit excellent agreement with two‐dimensional (2‐D) numerical simulation values, and yet, the expressions are continuous in all operation regions. Finally, the implementation in Matlab 7.5 is discussed to investigate the results.

Index Terms: Symmetric Double‐Gate, Drain–Current Model, Undoped Body.

1. INTRODUCTION integral without the charge sheet approximation this covers all regions of MOSFET Operation. AS CMOS scaling is approaching the limit imposed by

gate oxide tunneling, double‐gate MOSFET is 1.2DG‐MOS Structure becoming an intense subject of VLSI research because in theory it can be scaled to the shortest channel The DG MOSFETs are the devices, which are having length possible for a given gate oxide thickness [1].For two gates on either side of the channel i.e. the channel bulk MOSFETs, Pao‐Sah’s double integral based on is surrounded by the gate material on both the sides gradual‐channel approximation (GCA), although valid .One in upper side, known as top gate and another in all operation regions, cannot be carried out one is in the lower side of the channel, known as analytically due to the presence of both depletion and bottom gate . It gives better control of the channel by mobile charges in the integral [2]. This necessitates the gate electrodes .The channel is taken as undoped

the charge‐sheet approximation that would lead to or lightly doped one[4]. further simplification to obtain a piecewise explicit

current expression. However, charge‐sheet‐based models cannot properly describe volume inversion, a unique characteristic of double‐gate(DG) MOSFETs in the subthreshold region [3]. Contrary to bulk MOSFETs, depletion charges in DG MOSFETs are negligible because the silicon film is undoped (or

lightly doped). Thus, only the mobile charge term

needs to be included in Poisson’s equation. By Fig ‐1: Schematic diagram of a DG MOSFET extending this approach continuous analytic I‐V model for DG MOS has been derived directly from Pao‐Sah’s

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Fig. 1 shows the schematic diagram of a symmetric direction. Equation (1) can then be integrated twice to double‐gate MOSFET. Same voltage is applied to the yield the solution as 2kT t qn2 2 two gates having the same work function. At zero  ()xV  ln[ si i cos( )]...... (2) q 2 2 kT tsi gate voltage, the position of the silicon bands is si Where β is a constant of y (independent of x) to be largely determined by the gate work function. This is determined from the boundary condition because as long as the thin silicon is lightly‐ doped and tsi Vg   ()x  the depletion charge is negligible, the bands remain 2 d ox   si ...... (3) tsi tox dx x essentially flat throughout the thickness of the film 2 [5]. Here ox is the permittivity of oxide, Vg is the voltage applied to both gates, tsi and tox are the silicon and 2. TAUR’S MODEL FOR UNDOPED SDG‐MOSFET oxide thicknesses, and  is the work function of Consider an undoped (or lightly doped) SDG MOSFET both the top and bottom gate electrodes with respect shown schematically in Fig. 1. Poisson’s equation along to the intrinsic silicon. Substituting (2) into (3) leads to a vertical cut perpendicular to the Si film (Fig. 2) takes the following form with only the mobile charge q()VV  g 2 2sikT (electrons) term [6] ln( )lnln(c os)2 r tan...... (4) 2kT t 2 si qni d 2 q qV( )  ne kT ...... (1) dx2  i si t qn2  t where   si i eq 0 / 2kT and r  si ox ...... (5) 2 2kT si  oxtsi Now total mobbile charge per unit gate a rea is can be given as

Q  2( ddx / )2(2  kTq/)(2/ t )tan ...... (6) si xt si /2 si si

Using Pao‐Sah’s integral the expression for current can be given in terms of as

1 2 22S Idsds I 0 [t an   rtan ] ...... (7) 2 D

W 4 2kT Fig ‐2: Schematic band diagrams of an symmetric DG where I   si ( )2 and 0   /2 ds0 L t q nMOSFET along the vertical cut (AB). si

Where q is the electronic charge,  is the si By defining

permittivity of silicon, ni is the intrinsic carrier = ln  ln(cos )  2tan...r.....(8) density, ()x is the electrostatic potential and V is fr () the electron quasi‐Fermi potential. Here, we consider an nMOSFET with q  so that the hole density 1 2 22  1 gr()   tan  rtan ...... (9) kT 2 is negligible. Since the current flows predominantly from the source to the drain along the y‐direction, Thus by using above results in eqn (7) we can calculate the gradient of the electron quasi‐Fermi potential is also in the y‐direction. This justifies the gradual the drain current as done in following curves. channel approximation that V is constant in the x‐

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3. SIMULATIONS AND RESULTS Based on the above results and Equations we can obtain the results for and the drain currents as shown from fig 3‐‐5.

1) Variation of g r (  ) with f r () in linear scale.

Fig ‐5: Plot of gr versus f r with as a hidden

parameter.Currents are plotted on both logarithmic (left) and linear(right) scales.

All the above simulation results are in excellent agreement with that of the Y.Taur’s simulation results, which shows that we are correctly able to follow the Taur’s approach.

CONCLUSION

In conclusion an analytic drain current model for modeling of long‐channel SDG MOSFETs is presented Fig ‐3: Plot of gr versus fr with as a hidden which is implemented by using Matlab 7.5 and curves parameter in linear scale. is plotted that shows the results of Taur’s model is in complete agreement. Additional physical effects, e.g.,short‐channel effect, quantum effect, and mobility 2) Variation of g r () with f r () in model, need be incorporated into the long‐channel logarithmic scale. core to build a complete DG‐MOSFET compact model.

REFERENCES:

[1]. D. Frank, S. Laux, and M. Fischetti, “Monte Carlo simulation of a 30 nm dual‐gate MOSFET: How far can silicon go?,” 1992 IEDM Tech. Dig.,p. 553.

[2]. J. R. Brews, “A charge sheet model of the MOSFET,” Solid State Electron., vol. 21, no. 2, pp. 345– 355, Feb. 1978.

[3]. Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double‐gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861–2869, Dec. 2001.

Fig ‐4: Plot of gr versus fr with as a hidden [4]. S. Panigrahy,P. K. Sahu“Analytical Modeling of parameter in logarithmic scale. Double Gate MOSFET and Its Application” IJCSI International Journal of Computer Science Issues, g r (  ) f r () Special Issue, ICVCI‐2011, Vol. 1, Issue 1, November 2011. 3) Variation of with in both linear and logarithmic scale [5]. Yuan Taur , “An Analytical Solution to a Double‐ Gate MOSFET with Undoped Body”, IEEE Trans. Electron Devices Lett.ers ,VOL. 21, NO. 5, MAY 2000.

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[6]. Huaxin Lu, Yuan Taur “An Analytic Potential Model for Symmetric and Asymmetric DG MOSFETs” IEEE Trans. ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006.

BIOGRAPHIES:

Madhuri Panwar did her B.tech in ECE from Jayoti Vidyapeeth Women’s University, Jaipur, Rajasthan. She is pursuing M.tech in VLSI from JVWU. Her area of interest are Double Gate MOSFE ,Microelectronics etc.

Nidhi Gopal did her B.tech in ECE from Jayoti Vidyapeeth Womens University, Jaipur, Rajasthan. She is pursuing M.tech in VLSI from JVWU. Her area of interest are Digital Image processing, IC designing etc.

Naveen Upadhyay did his B.E. in ECE from University of Rajasthan, Jaipur in 2008. He is presently assistant professor in JVWU,Jaipur.He is a member of IEEE communication Society. His aera of interest are antennas,mobile communication etc.

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IMAGE COMPRESSION TECHNIQUE USING WAVELET TRANSFORMATION

1Nidhi Gopal, 2Madhuri Panwar, 3Naveen Upadhyay

1M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India Email‐ [email protected]

2M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India Email‐ [email protected]

3Assistant Professor, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, India, Email‐ [email protected]

ABSTRACT

Wavelet theory provides a unified framework for a number of techniques which have been developed independently for various signal processing applications. Wavelet transforms can be used as for multiresoluttion image compression at pixel level. Various other application of this theory is multi resolution image fusion, noise suppression, filtering, image restoration etc. This paper explores the use of current wavelet algorithm and programming for multi resolution image compression. The aim is to investigate how appropriate these wavelet transform algorithms are for compression and analysis of an image. Two different types of wavelet algorithms are selected and the results are evaluated by executing the programming and studying the difference in levels of output.

Index Terms: Digital Image Processing, Image compression, Multi resolution analysis, Wavelet transforms.

1. INTRODUCTION TO D.I.P purpose computer. Therefore, DSP is relatively convenient to develop and test, and the software Digital Image Processing is a wide field of processing is portable. and analysing images (or signals) in a digital form. In 2) DSP operations are based solely on additions and this modern world, we are surrounded by signals of multiplications leading to extremely stable various forms. Some signals are natural, but many processing capability‐for example, stability signals are man‐made. Signal carries information, both independent of temperature. useful and unwanted. Therefore, extracting and 3) DSP operations can easily be modified in real enhancing the useful information from a mix of time, often by simple programming techniques. conflicting information is the simplest form of Signal 4) Speed of operations in high frequency is the Processing. This technique (of extracting information) greatest advantage of DSP. is application dependent. The signals we encounter in practice are mostly the analog signals. These signals vary continuously with time, and amplitude, are processed, using electrical networks containing active and passive circuit elements. This approach is known as analog Signal Processing (ASP). Figure 1 : Digital Image processing using Wavelet transform A major drawback of ASP is its limited scope of The transform of a signal is just another form of performing complex signal processing applications. representing the signal. It does not change the Some important applications of DSP over ASP are: information content present in the signal. The Wavelet 1) Systems using the DSP approach can be Transform provides a time ‐ frequency representation developed using software running on a general‐ of the signal. It was developed to overcome the short

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Volume 1 | Issue 1 | October‐ November 2013 coming of the Short Time Fourier Transform (STFT), In quantum physics, the Heisenberg uncertainty which can also be used to analyze non‐stationary principle states that certain pairs of physical signals. While STFT gives a constant resolution at all properties, like position and momentum, cannot both frequencies, the Wavelet Transform uses multi‐ be known to arbitrary precision. The same principle resolution technique by which different frequencies holds in signal processing. We cannot locate both time are analyzed with different resolutions. The wavelet and frequency very precisely. The product of variation analysis is done similar to the STFT analysis. The signal in time and variation in frequency can be viewed as a to be analyzed is multiplied with a wavelet function rectangle with constant area and different transform just as it is multiplied with a window function in STFT, adjusts the width and height of the rectangle. The and then the transform is computed for each segment three transforms are shown in Figure 3. generated. However, unlike STFT, in Wavelet

Transform, the width of the wavelet function changes with each spectral component.

2. INTRODUCTION TO WAVELET TRANSFORMATION

A wave is an oscillating function of time or space and is periodic. In contrast, wavelets are localized waves.

1. They have their energy concentrated in time or

space & are suited to analysis of transient signals.

While Fourier Transform and STFT use waves to

analyze signals, the Wavelet Transform uses Figure 3: (a) Fourier Transform (b) STFT wavelets of finite energy. (c) Wavelet Transform

Fourier transform: The time information is completely lost. Frequency axis is divided uniformly. Frequency resolution can be very precise if we integrate along the whole time axis. Figure 2 : a) Sinusoidal wave of infinite energy,

b) Wavelet of finite energy STFT: Add a window to take the time domain information into consideration. The frequency 2. Wavelet transform is efficient for continuous and resolution depends on the time resolution, or the size moving signals of the window. We cannot zoom in a particular 3. The Wavelet Transform, at high frequencies, gives frequency range because the box is uniformly placed. good time resolution and poor frequency resolution, while at low frequencies, the Wavelet Wavelet transform: The S‐ parameter is inversely Transform give good frequency resolution and proportional to the frequency. As we see, if we want poor time resolution. to focus on low frequencies, larger S is used while 4. They are feasible if waves are of higher frequencies uses small. This flexibility increases a. Limited duration. the time‐ frequency analysis. b. Average value of zero. c. Varying frequency.

3. TIME FREQUENCY CONCEPT

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Figure 5: Haar wavelet transformation

Figure 4: Wavelet families (a) Haar (b) Daubechies (c) Coifletl (d) Symlet2 (e) Meyer (f) Morlet (g) Mexican Hat

Among these, Haar wavelet is one of the oldest and The scaling coefficient/ Low pass coefficient gives the simplest wavelet. Therefore, any discussion of wavelet averaged value, and the High pass coefficient gives starts with Haar wavelet. The wavelets are chosen the difference between Low pass and high pass based on their shape and their ability to analyze the frequencies. signal in a particular application. In Haar wavelet transformation, the scaling function 4. Wavelet Transformation φ(t) computes average, and the wavelet function ψ(t) computes details. The wavelet expansion involves two functions: 6. Decomposition Levels 1. Scaling functions or Father function, represented as φ(t). Through wavelet transformation, in order to have 2. Wavelet function or Mother function, perfect (or close) (precise) information content, and in represented as ψ(t). order to achieve the difficult task of feature extraction, the image is decomposed into several The two shapes are translated and scaled to produce levels, based on low pass and high pass divisions. wavelets at different locations and on different scales. These signals can be decomposed into many levels. It φ (t‐k) : where “k” is the scaling coefficient/ Low pass should be taken care that decomposition of signal coefficient must not increase the noise levels, and feature extraction is possible. Ψ (2jt‐k) : where “j” is the translation coefficient/ High pass coefficient 7. Observations

The wavelet transform, f (t) is written as linear A program of Image compression using HAAR combination of φ (t‐k) and Ψ (2jt‐k) : transformation in MATLAB was done, and its output in various levels was observed. j f (t)  ck ( t  k)  djk Ψ (2 t‐k) 1. Firstly, and original image as an input in taken, The scaling function contract/ expand the wavelet and the translation function changes the position of the and programming is done. wavelet.

5. HAAR Scaling and Wavelet Functions

Figure 6: Level 1 Haar

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2. The original .jpg image was decomposed into LL, 8. Acknowledgement LH, HL & LL sub bands. In this output, we can easily extract the average value of information. The authors would like to thanks to Head of Deptt, Mr. Koushik Chakraborty, Jayoti Vidyapeeth Women’s University, Jaipur and Dr. S.Lal, Dean‐ Engineering, Jayoti Vidyapeeth Women’s University, Jaipur for his continuous support and encouragement.

9. References

[1]. Digital Signal Processing, by Proakis and Monolakis

[2]. Digital Image processing, by Rafael C. Gonzalez

and Richard E. Woods Figure 7: Level 1 [3]. A.N. Akansu, R.A.Haddad and H. Caglur 3. Level 2 decomposition leads to further “Wavelet transform for multiresolution signal possibilities of feature extraction from LH, HL & decomposition”, Submitted IEEE, Trans.signal HH sub‐bands respectively. Proc.1990.

4. Level 3 decomposition leads to the output, i.e Biographies compressed image which can be reconstructed at Nidhi Gopal did her B.tech in the receiving end. ECE from Jayoti Vidyapeeth

Womens University, Jaipur, Rajasthan. She is pursuing M.tech in VLSI from JVWU. Her area of interest are Image processing, microelectronics, etc.

Madhuri Panwar did her B.tech in ECE from Jayoti Vidyapeeth Women’s University, Jaipur,

Rajasthan. She is pursuing Figure 8: Level 2 Haar M.tech in VLSI from JVWU. Her areas of interest are Double 5. The algorithm used in programming was Gate MOSFET, Microelectronics transferred into an FPGA chip, and then to the etc. computers. Further, the scaling and translating coefficient (instead of whole image) were sent to the receiving end. By inverse wavelet Naveen Upadhyay did his B.E. transformation, the original image was in ECE from University of reconstructed. Consequently this helped in Rajasthan, Jaipur in 2008. He is feature extraction and de‐ noising of image. presently assistant professor in JVWU, Jaipur.. He is a member of IEEE Communication Society. His area of interest are antenna, mobile communication etc.

Figure 9: Level 3 Haar

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Automatic Telephone Answering Machine with Image Processing

Richa Singh Rathore, Disha Malik2

1M.Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, INDIA, [email protected]

2M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, INDIA, [email protected]

ABSTRACT

An automatic telephone answering machine or system is electronic devices that answers automatically to an incoming telephone call and plays a prerecorded message and is capable of recording a message the caller want to leave. These systems include message recording system having remote access to message playback, automatic dialing, equipment to receive an alarm, automatic data entry‐answering systems and other common telephone devices being used along with modem equipments. The microcontroller typically controls a number of peripherals, components of the answering machine such as an LCD or LED display, an indicator light for recording and playback options, a DTMF receiver and an audio controller. A telephone answering machine must be capable of being remotely activated consisting of:  A switch deciding the mode of operation either automatic or normal mode.  Provision for receiving the calls automatically when in automatic mode.  Provision for recording the message to be delivered to the incoming user and also to record his message.  Storage for the message.  Microcontroller to deliver control signal as per the mode of operation. Commonly used telephone answering devices comprises of a number of features which allow a user to examine the presence of a call, seize calls, play back recorded voice messages, record an announcement etc. Triggering of a telephone answering machine done by counting the incoming ring signals and when the counts surpass a preset number set by the user. The machine is programmed in such a way that if the user does not attain his telephone within a specified time period which is the function of number of ring signals, the call is automatically answered and a message is played back to the caller as well as asks him to leave a message.

Index Terms: Answering machine, Incoming ring signal, Play Back, Call

1. INTRODUCTION processing system. It can be connected to multiple telephone lines. There might be also additional features 1.1 Definition like connect to another predefined number and forward

An automatic telephone answering machine can be the recorded message to the present location of identified as an electronic device which has the basic receiving end user. feature of answering a call in the absence of the 1.2 Components receiving user. It has some added features like plying back a pre‐recorded audio message to the caller. If the The ATAM device automatically answers an incoming caller wants to leave a voice message he can do so by telephone call, plays a prerecorded message and records accepting the option to record a message. The a message that the caller leaves. These systems include answering machine or system can be described as data message recording system having;

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 Remote access message playback therefore providing a competitive and feasible solution  Automatic dial up alarm receiving equipment for the embedded system in the least amount of time.  Automatic telephone message recording equipment 1.5 Specification  Automatic telephone call forwarding  The phone should use the POTS telephone equipment system.  Automatic answering data entry systems  Compatibility with other videophones that  The microcontroller to control a multiple follow the H.324 standard. number of peripherals, and basic components of an  Handle analog to analog communication (for answering machine compatibility with  Peripherals like an LCD or LED display, an Regular phones) and digital to digital communication indicator light for recording and playback options, a with other Video phones. DTMF receiver and an audio controller.  The phone gives users a “video” option, which

allows the users to send to each other images to be 1.3 Operation viewed on the videophone’s LCD screen every 12 The basic function performed by the answering seconds. machines is to automatically answer calls coming from  The phone can be used as a digital picture an incoming telephone line. In the absence of user of the frame by displaying stored images when idle. machine, when the call is unanswered up to a certain  The videophone has an answering machine time interval, a pre‐recorded outgoing message is being feature that can record both voice and images. played to the calling party. Then it asks for any message  The phone can store up to 30 one minute to the calling party and records the message he leaves. messages and 5 images per message. (1 image every 12 sec) A typical telephone answering machine is a separate  The phone uses MPEG compression on the device connected to a telephone line. This type of voice messages that it stores. It uses JPEG compression answering machines usually includes circuitry for the on any images that it stores. detection of a ringing signal on the telephone line  The phone has four modes. Playback, Playback signifying the existence of an incoming call. It answers Voice Only, playback Image Only, Call. the call by taking the line off‐hook, plays an outgoing message, records an incoming message if any, and hangs The phone contains the following buttons: up the line in order to respond to subsequent telephone calls.  Dial pad‐ For dialing numbers

1.4 Motivation  Mode‐ Switching between the 4 modes  Play/Reverse‐ Begin playing messages. If Our main goal is to provide a solution beyond the basic messages are already playing reverse the direction of functionality provided by a phone. In addition to play. implementing video and answering machine capabilities,  Delete/Undelete‐ Delete the current message other features are included by making use of basic after messages are done playing/ cancel delete. hardware components already included in the system,

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 Skip‐ Skip this message plays the next or And Then starts sending it images every 12 sec. previous message according to direction of play 2. Block Diagram (Forward/Backward).  Stop ‐ Stop message playback. The Block diagram of Automatic Answering Machine is  Record Announcement‐ Record the shown in Figure: 1 announcement. This Includes Main Controller Unit, Audio Unit, Video  Hear Announcement‐ Hear the announcement Unit, Camera, Display, Phone‐ Modem Interface.  Memo ‐ Record a memo as a voice message

 Video‐ The phone signals another Videophone

Figure 1: Block Diagram of Automatic Telephone Answering Machine

3. FLOW CHART

Flow chart of Automatic Telephone Answering Machine is shown in Figure 2. Which shows how it will work?

Figure 2: Flow Chart Representation of Automatic Telephone Answering Machine

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Finite State Machine (FSM)‐ A finite state machine is one that has a limited or finite number of possible states.

Figure 3: State Level Diagram of Finite State Machine

4. Components Audio compression and decompression unit‐ Image compression and decompression unit‐ Compression reduces the number of bits in total Compressing a file is the process by which a large file is required to represent the same information. converted to a smaller file, decompressing a process by Decompression refers to the opposite process of which a compressed file is converted back to its compression that is restored to its original quality. standard state. Controller Unit‐It controls communication and co‐ POTS ‐ Plain old telephone service. ordination between input/output devices.

Figure 4: Block Diagram

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5. Conclusions 3. H.263 Video Coding http://www‐ mobile.ecs.soton.ac.uk/peter/h263/h263.html  A videophone system has been designed based 4. H.261 Video Coding http://www‐ on ITU compatible standard. mobile.ecs.soton.ac.uk/peter/h261/h261html

 Operation function, feasibility, and structure 5. H.263+: Video Coding at Low Bit Rates, IEEE diagram have been provided and analyzed. Transactions on Circuits and Systems for Video Technology, Vol 8.  An example focused on baseline sequential No. 7, November 1998, Guy Cote, Berne Erol, Michael FDCT and IDCT based coding for image compression and Gallant, Faouzi Kossentini decompression is to demonstrate the typical JPEG image 6. The JPEG Still Picture Compression Standard, Gregory processing. Wallace, April 1991 Communications of the ACM 7. Digital Image Processing, Gregory Baxes, John Wiley &  VHDL simulation and synthesis has been made Sons, 1994 to generate a gate level structure to fulfill the required Audio Compression function. 1. A Tutorial on MPEG/Audio Compression, Davis Pan, 6. References IEEE Multimedia Journal, Summer 1995 System Parts General 1. SED1330F/1335F/1336F LCD Controller ICs Technical 1. ITU‐T Recommendation H.261 (1993) ‐ Video Manual, S‐Mos Systems, Inc, September, 1995, Version Codec for audiovisual services at px64 kbit/s 0.4 2. Telecommunication Transmission Handbook, 2. Interfacing a Hantronix 320x240 Graphics Module to Third Edition, Roger L. Freeman, Wiley Publishing, 1991 an 8‐bit Microcontroller, Hantronix, Application Note, 3. ITU‐T Recommendation H.324 (02/98) – 2000 Terminal for Low Bit‐Rate Multimedia Communication, 3. TMS320C54x DSP Reference Set Volume 5: Enhanced ITU Peripherals 4. ITU‐T Recommendation H.245 (6/4/96) – Line 4. TMS320C54x Serial Ports: Addendum to the Transmission of Non‐Telephone Signals, ITU TMS320C54x User’s Guide 5. Generic Coding of Moving Pictures and BIOGRAPHIES: Associated Audio, Recommendation H.26x, ISO, IEC, Richa Singh Rathore did her B.tech in 3/27/00 ECE from Krishna Girls Engineering College Kanpur. She is pursuing 6. Coding of Moving Pictures and Associated M.tech in VLSI from JVWU. Her area Audio, ISO/ IEC/ JTC1/ SC29/ WG11N0531, MPEG93, 9/ 93 of interest are Digital Image Processing, Digital System Design, 7. Coding of Moving Pictures and Associated Audio, ISO/ Intergated Circuit, VHDL etc. IEC/ JTC1/ SC29/ WG11N0403, MPEG93/ 479, 3 /27 /00 8. ITU‐T Recommendation V.34 (9/94) – Data Disha Malik did her B.tech in ECE Communication over the Telephone Network, ITU from G.L.Bajaj Institute of Technology and Management Video Compression Greater Noida. She is pursuing 1. Video Compression Techniques Over Low‐Bandwidth M.tech in VLSI from JVWU. Her area of interest are Digital Image Lines, RoaltAalmoes, August 27,1996 processing, Digital Computer 2. H.263 Video Coding Networking, VHDL etc. http://www.4i2i.com/h263_video_codec.htm

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32‐bit Arithmetic Logical Unit (ALU) using VHDL

Disha Malik1, Richa Singh Rathore2

1M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, INDIA, [email protected]

2M. Tech Scholar, Department of ECE, Jayoti Vidyapeeth Women’s University, Rajasthan, INDIA, [email protected]

ABSTRACT This paper involves the construction of 32‐bit ALU (Arithmetic Logical Unit) using VHDL using Xilinx Synthesis tool ISE 9.2i and implementation them on FPGA (Field Programmable Gate Array) using Spartan 3E. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. The ALU performs mathematical, logical, and decision operations in a computer and is the final processing performed by the processor.

An Arithmetic unit does the following task:  Addition  Addition with carry  Subtraction,  Subtraction with borrow,  Decrement  Increment  Transfer function. A Logic unit does the following task:  Logical AND  Logical OR  Logical XOR  Logical NOT operation. Here, ALU is designed using VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed signal systems such as field‐programmable gate arrays and integrated circuits.

KEYWORDS‐ FPGA, ALU, XILINX

1. INTRODUCTION in a computer and is the final processing performed by the processor. After the information has been processed Arithmetic Logic Unit, ALU is one of the many by the ALU, it is sent to the computer memory. In some components within a computer processor. The ALU computer processors, the ALU is divided into two performs mathematical, logical, and decision operations distinct parts, the AU (Arithmetic Unit) and the LU

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(Logical Unit). The AU performs the arithmetic named as "field‐programmable". The FPGA configuration operations and the LU performs the logical operations. is generally specified using a hardware description In computing, an arithmetic and logic unit (ALU) is language (HDL) VHDL (VHSIC hardware description a digital circuit that language) is a hardware description language used in performs integer arithmetic and logical operations. The electronic design automation to describe digital and ALU is a fundamental building block of the central mixed‐signal systems such as field programmable gate processing unit of a computer, and even the arrays and integrated circuits. simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside The key advantage of VHDL, when used for systems modern CPUs and graphics processing units (GPUs) design, is that it allows the behavior of the required accommodate very powerful and very complex ALUs; a system to be described (modeled) and verified single component may contain a number of ALUs. (simulated) before synthesis tools translate the design into real hardware (gates and wires). Another benefit is In the present day technology, there is an immense need that VHDL allows the description of a concurrent system. of developing suitable data communication interfaces VHDL is a dataflow language, unlike procedural for real time embedded systems. Field Programmable computing languages such as BASIC, C, and assembly Gate Array (FPGA) offers various resources, which can code, which all run sequentially, one instruction at a be programmed for building up an efficient embedded time. VHDL project is multipurpose and portable. Being system. A Field‐programmable Gate Array (FPGA) is an created for one element base, a computing device integrated circuit designed to be configured by the project can be ported on another element base, for customer or designer after manufacturing—hence it is example VLSI with various technologies.

1.1 BLOCK DIAGRAM

Figure 1: Block Diagram of 32‐Bit ALU

2. DESIGN OF 32‐ BIT ALU When designing the ALU we will follow the principle "Divide and Conquer" in order to use a modular design

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that consists of smaller, more manageable blocks, some at last a 32‐bit Ripple Carry Adder using eight numbers of of which can be re‐used. Instead of designing the 4‐bit 4‐bit Ripple Carry Adder. Then designed thirty two ALU as one circuit we will first design one bit ADDER, numbers of single‐bit 4:1 Multiplexer. The circuit has a 32‐ SUBTRACTOR, OR, AND, NOT, XOR, LEFT SHIFT, RIGHT bit parallel adder and thirty two multiplexers for 32‐bit SHIFT UNIT. These bit‐slices can then be put together to arithmetic unit. There are two 32‐bit inputs A and B and make a 32‐bit ADDER, SUBTRACTOR, OR, AND, NOT, 33‐bit output is RESULT. The size of each multiplexer is XOR, LEFT SHIFT, RIGHT SHIFT UNIT. 4:1. The two common selection lines for all thirty two multiplexers are S0 and S1.C‐in is the carry input of the 3. MODULES DESIGN OF 32‐BIT ALU parallel adder and the carry out is C‐out. The thirty two 3.1 32‐BIT ARITHMETICUNITS inputs to each multiplexer are B‐ value, Complemented B‐value, logic‐0 and logic‐1.The output of the circuit is An Arithmetic unit does the following task: Addition, calculated from the following arithmetic sum: Addition with carry, Subtraction, Subtraction with RESULT = A + Y + C‐in borrow, Decrement, Increment and Transfer function. At Where A is a 32‐bit number, Y is the 32‐bit output of first we start with making one bit Full Adder, then a 4‐bit multiplexers and C‐in is the carry input bit to the parallel Ripple Carry Adder using four numbers of Full Adder and adder.

Figure 2: 32‐Bit Arithmetic Unit 4. SIMULATED TIMING DIAGRAM OF ARITHMETIC UNIT

Figure 3: Timing Diagram

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4.1 32‐BIT LOGIC UNIT

A Logic unit does the following task: Logical AND, Logical OR, Logical XOR and Logical NOT operation. We design a logic unit that can perform the four basic logic micro operations: OR, AND, XOR and Complement, because from these four micro‐operations, all other logic micro‐operations can be derived. The logic unit consists of four gates and a 4:1 multiplexer. The outputs of the gates are applied to the data inputs of the multiplexer. Using to selection lines S0 and S1 one of the data inputs of the multiplexer is selected as the output. For a logic unit of 32‐bit, the output will be of 33‐bit with 33th bit to be High‐impedance. The common selection lines are applied to all the stages.

4.2 SIMULATED DIAGRAM OF LOGIC UNIT

Figure 4: Simulated Diagram of Logic Unit

Figure 5: Timing Diagram

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4.3 32‐BIT SHIFTER UNIT

Shifter unit is used to perform logical shift micro‐operation. The shifting of bits of a register can be in either direction‐ left or right. The content of a register that has to be shifted first placed onto common bus. This circuit uses no clock pulse. When the shifting unit is activated the register is shifted left or right according to the selection unit. For a shift unit of 32‐bit, the output will be of 33‐bit with 33th bit to be the outgoing bit.

Figure 6: Block Diagram of Shift Unit

4.4 SIMULATED TIMING DIAGRAM OF SHIFTER UNIT

Figure 7: Timing Diagram of Shifter Unit 4.5 FUNCTION OF ALU:

S3 S2 S1 S0 C‐in RESULT Operation

0 0 0 0 0 A+B Addition 0 0 0 0 1 A + B + 1 Addition with carry 0 0 0 1 0 A + B Subtraction with borrow 0 0 0 1 1 A + B + 1 Subtraction 0 0 1 0 0 A – 1 Decrement 0 0 1 0 1 A Transfer 0 0 1 1 0 A Transfer 0 0 1 1 1 A + 1 Increment 0 1 0 0 x A∙B AND 0 1 0 1 x A+B OR 0 1 1 0 x A⨁B XOR 0 1 1 1 x NOT A Complement 1 0 0 x x LSR A Shift Right 1 0 1 x x LSA A Shift Left

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5. SPARTAN‐3E FPGA FEATURES AND [4]. Xilinx, Spartan‐3E Starter Kit Board User Guide, EMBEDDED PROCESSING FUNCTIONS UG230 (v1.0) March 9, 2006. The Spartan‐3E Starter Kit board highlights the unique [5]. VHDL Tutorial, Ardent Computech, PVT. LTD., 2011. features of the Spartan‐3E

FPGA family and provides a convenient development 8. BIOGRAPHY Board for embedded processing applications. The board highlights these features: Disha Malik did her B.tech in Spartan‐3E FPGA specific features: ECE from G.L.Bajaj Institute of  Parallel NOR Flash configuration Technology and Management Greater Noida. She is  Multi‐Boot FPGA configuration from Parallel pursuing M.tech in VLSI from NOR Flash PROM JVWU. Her area of interest  SPI serial Flash configuration are Digital Image processing, Digital Computer Networking, Embedded development VHDL etc.  Micro‐Blaze™ 32‐bit embedded RISC processor Richa SinghRathore did her  Pico‐Blaze™ 8‐bit embedded controller B.tech in ECE from Krishna Girls Engineering College  DDR memory interfaces Kanpur. She is pursuing 6. CONCLUSION M.tech in VLSI from JVWU. Her areas of interest are In our paper “Design and Implementation of a 32‐bit Digital Image Processing, ALU on Xilinx FPGA using VHDL” we have designed Microelectronics, Intergated Circuit etc. and implemented a 32 bit ALU. Arithmetic Logic Unit is the part of a computer that performs all arithmetic computations, such as addition and subtraction, increment, decrement, shifting and all sorts of basic logical operations. The ALU is one component of the CPU (Central Processing Unit).

Here, using VHDL we have designed a 32 bit ALU which can perform the various arithmetic operations of Addition, Subtraction, Increment, Decrement, Transfer, logical operations such as AND, OR, XOR, NOT and also the shift operation.

7. RERERENCES [1]. T. K. Ghosh and A. J. Pal, Computer Organization and Architecture, Tata McGraw‐Hill Publishing Company Limited, New Delhi, 2009. [2]. Douglas L. Perry, VHDL Programming by Example, 4th ed., Tata McGraw‐Hill Publishing Company Limited, New Delhi, 2002. [3]. Xilinx, Spartan‐3E FPGA Family: Data Sheet, DS312 (v3.8) August 26, 2009.

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SERVER CLUSTERING TECHNOLOGY & CONCEPT

Vaibhav Mathur M00383937, Computer Network, Middlesex University, E‐mail: [email protected]

Abstract

Server Cluster is one of the clustering technologies; it is use for the improvement of the PC’s performance; cluster use for the high performance of computing system. It is based on the model of the cluster architecture. This model is refers that how servers manage in the cluster. Server Cluster is available for the Microsoft windows server. This model does not require any cabling, it support the standard Windows Server 2003 and Windows 2000. These windows server is use for the local storage and for the media connection.

Keywords: Cluster Server, load balancing, FTCS, Database Manager, Virtual IP, Asymmetric Cluster

1. INTRODUCTION Chase says “I’m not interested in license product. I’m Computer clustering use for PC’s or UNIX interested to develop the open source application, so workstations; these technology can help us to achieve after that these applications can help to further the 99.999 availability. The major companies such as universities and research labs. Microsoft, sun micro system are offering some The company IBM is much interested, Bill Tetzlafl, he is clustering packages. These packages are offer the an engineer at IBM, and very familiar with the scalability and availability. technology. If we talk about of our personal computers, a cluster stores all the data on a hard disk. These data are 2. THEORY manageable by the operating system. All of the 2.1 Technology clusters are located in a different location in the hard Windows Server 2003 introduced the technology disk. So, when someone read the file the hole file is name as server fault tolerant technologies. In this comes to you. But here you not aware that where is technology on or more application are running on the the cluster stored. So. The numbers of cluster which servers, these application are configuring to two or are stored in a hard disk are depending on the size of more application server. These applications provide the FAT. In DOS 4.0, the size of the FAT entries is 16 fault tolerance and load Balancing. bits and the maximum size is allowing is 65536. The procedure of this technology are if one server fails Researchers at Duke University are working on the and not operate, the another server will take the role. software called as cluster on demand. This is an This is the way that fault tolerance technology is operating system, which is use for the replaceable working in server clustering. component. All are the component configured In this technology every server runs the same according to the user of the need. application on the server, if any case one of the server Jess Chase is the professor of the Durham University; fails, the another server will automatically take the he worked in a software department. role. This is the concept of the “failover”. He says “All the software application and the Some big companies such as Microsoft, Here the operating system are separate in a particular software windows server 2003 operating system is help us to environment” , because when the server boot via provide the high availability and scalability. These network , the request goes to the database and applications are also help us to improve the database tells to the operating system to run , what performance of our business. High availability provides are the software and policies to load. the high percentage of the user application and the

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scalability is use to increase and decrease the capacity of computing. This is called as single quorum device cluster because every disk in the array can manage one node at a time. Cluster Server works as “When two or more These resources provide independent node, so that computers are working together, both are the each node can obtained the data, if one more nodes computers providing the high level of availability and are down. This type of connection is also called as bus. scalability and both are obtained in single computers. 3.2 Basic Architecture of Network Load Balancing Availability is increased when one computer result is Clusters failure and the workload to another computer. The windows server provides two types of clustering technologies: (1) Server Cluster (2) Network load Balancing 2.1.1 Server Cluster Server Clusters are designed for that application that have running for higher memory state or frequently update all the data. These applications are known as state full application. Microsoft SQL Server 2000 and messaging application such as Microsoft Exchange

Server 2003 are the example of state full application. Figure 2: Source: http://technet.microsoft.com/en‐ 2.1.2 Network Load Balancing us/library Network load balancing are called as the stateless Figure 2 shows a 8 hosts with the client are connected application because in this balancing they not have a to the Network Load Balancing Cluster. Every host run long state running memory. So, the data can change as a separate copy of the server application, if a host very frequently and the entire request has not been failed; incoming client request goes to the other hosts done. in the cluster. 3. ARCHITECTURE If one of the load increased, we needed the additional There are basically two types of clustering hosts. This server is very easy to install, manage and architecture maintain because there is no need to the additional 3.1 Basic Architecture for Server Clusters software, you can use the available software and The Figure 1 shows a 4 node server cluster; all the four hardware. nodes are connected to the quorum data (single This type of architecture works as a virtual network cluster device) adapter, every node represents a single cluster entities. In virtual adapter, every IP address and MAC address are different from each other. So the client uses only the virtual IP address. If the client sends a request to the cluster, all the nodes in the cluster will receive and process the message 4. PROCEDURE 4.1 EXPERIMENT Computer and the software used in the experiments

Figure 1: Source: http://technet.microsoft.com/en‐ are shown in Table 1 and the overview of the us/library environment is show in the figure 3 and 4

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A server cluster is also called as SH computers. The cluster work as a single IP cluster server, so that the cluster’s seen only the single computer by external clients. In the evaluation time only three types of servers are prepared, first one is the stand‐alone SH server, second one is the SH cluster server and the last one is x86 server.

Figure 3: The environment used in experiments

SH 7780 Stand‐alone (SH2007) CPU R8A77800 (SH4A,400MHz) Cache I : 32KB D:32KB Memory 128MB Disk HITACHI HTS 721010G9AT00 (2.5” IDE 100GB) Ethernet LAN9118 (10/100base‐TX)*2 Figure 4: FTCS Overview Device Kernel Linux 2.6.21(sh) The httperf benchmark is used as a benchmark, to Web Server Apache/2.2.6 measure the performance of the three types of server, X86 server when changing the http request rate. The httperf CPU Xeon L5410(2.33GHz *4) TDP : benchmark is able to adjust the http request rate and 50W the total number of connections which created, so Cache L1 I :32KB ,L1 D:32 KBL2 : 6MB first we set the total number of connections to 10 times, and the number of http request created by Memory 4 GB httperf benchmark [4] in a second. This results run in a Disk HP GB0500C8046 (3.5” SATA 10 second benchmark in a normal situation. 50 FTCS is used to make the SH Cluster in a single IP kernel Linux 2.6.18 (x86,64) address cluster server. The Fig 1.5 showed the Web Server Apache/2.2.3 overview of the FTCS behavior. In the FTCS based Client cluster every incoming packet to the cluster is CPU Intel Core2 Duo U7700 (1.33Ghz broadcast to all of the server nodes. At this there is * 2) one special node in the cluster known as master node. Memory 2 GB After the connection has been established, each node Ethernet 88E8055 PCIe Gigabit Ethernet searches its own TCP connection. Device Kernel Linux 2.6.25 (i386) Httperf Httperf‐0.8

Table: 1 Computers and Software Used in Experiment

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4.2 COMPONENTS Node Manager is also use to maintain a local disk of nodes, network and network interface in the cluster. For the regular communication of nodes all nodes in the cluster have the same list of functional nodes.

In the cluster configuration database, node manager is uses to check the information and determine that which nodes have been added to the cluster or remove from the cluster. At the same instance it also checks the node failure activity, it is does because of the sending and receiving messages, and it is called as heartbeats. If the node detects that a communication

failure with another node, it broadcast a messages to Figure 5: Source: http://technet.microsoft.com/en‐ the entire cluster, this is called as regroup event. us/library

4.2.3 Failover Manager and Resource Monitors Cluster Service runs on every node of a server cluster and controls all the server cluster operation. Multiple Failover Manager manage all the resource groups, for software components include in the cluster services example, when the failover manager start or stops it’s and they work together. These components manage all the resource dependencies and perform Fig 1.6 shows the Database Manager, Node Manager, certain action between resource and failover manager. Failover Manager, Resources Monitors and Global It also determines that which of the cluster have its Update Manager. own resource group because in the cluster, every Here the information is communicated between failover manager works together and reassign the Database Manager, Node Manager and Failover ownership of the resource group. Manager. The other, Global Update Manager is use to 4.2.4 Global Update Manager support the other three Managers by coordinating It is part of the internal cluster components, when a updates to the other nodes in the cluster. These four node is update, another node is appoint to monitor components are work together to make sure that all the update, this is happens on all the nodes. If the four nodes are maintained. appoint node is update locally, but the another node 4.2.1 Database Manager cannot be update, is removed from the list of the functional nodes, and change is mode on the available Database Manager maintains a local copy of cluster node. configuration database and runs on each node, so that 5. Solutions all the information of logical and physical items stores The solutions are provided is that; design your own in a cluster. If the cluster wants to changes, the global application infrastructure. Mean design a good server update manager replicate all changes to the other cluster which is interconnected to two or more nodes in the cluster. In this way all the consistent servers, thus all the resources provide availability, information is maintained, even if any case the node scalability or both. fails, the administrator have a source to changes the The other two Solutions are: cluster configuration before the node return to 5.1 Asymmetric Cluster service. Asymmetric Cluster is also known as standby server; it exists when another server is failure. These clusters 4.2.2 Node Manager provide the high availability and scalability for

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understand the read/write stores. Fig 1.7 shows that if Linux OS 54 (10.8%) 446 (89.2%) one of the nodes is unavailable, another node takes X86 Family 6 (1.2%) 438 (87.6%) the role of the failure node. Processor

Table 2: Number of the machine that are clusters, use Linux, and x86 architecture in top 500.

If we look table 2, In 2000, cluster architecture, Linux operating system, and x86 processors are fall of 2000 But if we talk about in 2009, dominant changes in each Figure 6: Asymmetric Cluster of these. 5.2 Symmetric Cluster When not sure about the system correctness, because In the Symmetric Cluster, every server known as the the system is very complex, its to0 hard to prove its primary server, when one of the servers fails, the correction, so only assumption can we make. When remaining server can continues to the process. one of the new synchronization problems is This is cost effective because more cluster resources developing, the problems which introduced is use, so in the failure condition additional load is development of distributed system. In this type of provide. synchronization, activity and request can exclude each other. For those customers who want to configure the integration services as a cluster resource, the section contains the necessary configuration instruction. But in Microsoft does not recommend the integration services to configure in a cluster server.

7. Conclusion Considering the Cluster Server, provide benefits such

Figure 7: Symmetric cluster as, you pay the same price of the cluster and you would share hosting. This will help us for the business 6. CRITICAL ANALYSIS purpose, because we save lots of money. You can Cluster Server has been used over a decade, the two purchase as much as computing power as much you processors name as Intel PIII (Tualatin) and the AMD want because you will have access to infinite number Athlon (Thunderbird) These are the world HPC of the cluster servers. To sum up the cluster server can Clustering .In twice a year one of the best historical always help aid the network server environment at a record of the HPC, because 500 machines are listed on much cheaper rate compared to that of buying an the site. All the performance such as operating actual server. This is what companies do in order to system, and architecture and the other factor that are function within a given budget they choose loosely recorded in the machine are included. coupled or tightly coupled cluster server systems in Attributes Fall 2000 Fall 2009 order to meet their need for processing information within their firm. Cluster 28 (5.6%) 417 (83.4) 8. References Architecture [1] Network World, Infrastructure, and Researchers power up server clusters. P.21 Jennifer Mears, 2003.

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[2] Published by Kusu , The cluster Decade, 7 feb, 2010 Hpccommunity.org [3] Published by Adar, Cluster Server Technology, July11, 2010 [4] D.Mosberger and T.Jin . Httperf for measuring web server performance. P.31‐37, 1998 [5] Felicia R.Blue for Clustered Hosting Buniness.com [6]Server Cluster review, technet.microsoft.com [7] Network World, Infrastructure, and Researchers power up server clusters. P.21 Deni Connor 2003

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Cookies, and It’s Tracking Mechanism for User’s Identification

Vaibhav Mathur

M00383937, Computer Network, Middlesex University, E‐mail: [email protected]

Abstract Conventional cookies, cache cookies are the part of the cookies; these are the data objects of the servers, which is store in the web browsers. Cookies are basically small files, it allows to the web server to store all the information in the user’s computer. In this paper I trying to show you how we authenticate to the users. Here cache cookies play an important role. For the privacy measure most of the people block our conventional cookies in their browsers. As I show, this technique is also help us to restore lost usability maintain their goof privacy and phishing & pharming.

Keywords: Cache cookies, Web browser personalization, pharming, phishing, privacy.

1. Introduction In the World Wide Web the web browsers and web A cache cookie work as ordinary cookie. It is common applications communicate to each other through form the server to contain the secret value from the HTTP. In the cookies, all the personal information of browsers of user’s. These cookies are helping us to the user is store. For example if Alice want to visit a authenticate to the user or most precisely her Bob website, so when Alice visit a website, the domain browser. There are two different versions of cookies server store a cookie in Alice browsers. When Alice in use [1]: version 0 cookies known as Netscape visits a website again the server automatically identify Cookies and the version 1 known as RFC 2965. The that cookie. The cookies are supported all modern version 0 cookies are the mostly used version it browsers and allow for a great flexibility, means they defines the set cookies header, and the header as show that how user can manage the sessions in the follows. web application. Set‐Cookie: name=vale [; expire=date] [;path=path] There are many types of cache cookie, these are work [;domain=domain] [;secure] as a, maintain the various cache in the browsers and access their content. Cache files is also help us to your Cookie: name = value browser to work faster .Behind of you PC, all the picture files, sound files and some text that your For example: browser browse are store. So if someone wants to Set‐Cookie: SID=123abcd; domain= vaibhav.ac.th share your pc make sure that all the browsing data are Cookie: SID=123abc cleaned.

Temporary Internet Files (TIF) is the example of the cache cookie. TIF work such an object like images, it accelerates all the browsing speed. So when you open a browser and its display that data object are present in temporary internet files, it can directly access to the data object rather than take it from the server.

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Cookies are not basically design for the authentication; it is design for the convenient way to pass the state. There are too many system they achieve the security goals, such as authenticator which added a feature like security password [2]. Here I apply a same approach to cache cookie.

As we know that the cookie are fully accessible by the domain server, so that are capable to attack such as

Figure 1: Web Server and the client exchange the pharming. In this pharming attack the browser can cookies directly connected to the web server which is combined to the domain, it is not connects to the In version 0, the cookies work as the identified, these spoofed site. are check the combination of the following attributes such as name, domain and path. The domain and the Here I trying to show you, how the user use the cache path attributes inform to the browser that the cookie cookies, when they use or not apply to the domain must be sent back to the server, when requesting URL server make sure that these stand to the pharming of a given domain and path. The expire and secure attack. New ceptual framework is the basic work, attributes are possibly not used. where cache cookie support s virtual memory structure. This structure is known as Cache‐Cookie The version 1 cookies are an extended version of the memory or CC‐memory. Netscape cookies. It is also identifying the cookies by name, domain and the path attributes as in the version The main advantage of the cache cookie is more 0, but it is also an ability to identify the cookies using space. It is virtually addressable memory. Its size port attributes as well. The web server set the cookie2 depends on the bit length of the browser as the name header instead of the Set cookie header. Always of the URLs. So, in the CC‐memory the server can take browser must return the same value because the web only the negligible portion and the attacker also read server must always specify the value of the name of only the negligible portion of the CC‐memory , the the attributes and the cookie version in the cookies. hole portion is not be feasible. Almost all modern browsers do not support the version1 cookie expect opera browser, so the version1 3. Cache Cookies Memory Management cookie not widely used by web developers. As I discussed that CC‐memory is the read‐write For example: memory which is the structure of the user browser. Version 1 cookies: These cache cookie are based on the temporary internet files, the same principle is apply in the entire Set‐Cookie2: SID=”123abc”; version=”1” cache cookie. Cookie: $version=”1” SID=”123abc” Here a server works as a variety of TIFs by giving them the URLs. For example a domain is www.abc.com can 2. Cache Cookies as authenticators

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work in a browser, But if the URL is different like Identifier –tree scheme is the best solution, because www.abc.com/computer.jpg its access the server to user identifier which is based Here computer.jpg is the any URL that complaint the on secret key that is takes by the server not for the string. So the server can create only the CC‐memory domain. structure, over the space of the URLs, e.g. www.abc.com/computer .jpg, where computer is the 4.1 Identifier trees index of the CC‐memory. Fig 1.2 show A identifier tree T. When you create A 3.1 TIF –based cache cookie identifier tree, a server can associated that every user joint the leaf in the tree. Where nodes S represent the As I explained TIF is the temporary Internet files, secrets in CC‐ memory. When server support to the which contain the object, here image are embedded in browser, the user set the secret cache cookie path web pages. These are those file where user want to from the root of the user leaf [2]. If someone wants to revisit the website, it is also showing the faster identify to the user, the server interact with the users, display. There is no expiration, but the disk is covering and the browser shows that which path is contain. the space. Here the server performs the depth search. This search is feasible only when server generated the In the TIF, As I mentioned that for example A is a identifier tree because the server known that where browser cache, if A is not present in cache, it will not the secret cache cookie are associated in the nodes of pill the A, but instead it takes a local copy. the tree.

3.2 C‐memory

Conventional cookies have optionally takes the paths. A cookie released this path when a browser sends a request to the URL. So for example when cookie is set the path www.abc.com/A, this path is released when the browser visits this URL is the form of Figure 2: This is a simple identifier tree www.abc.com/A/..... With the help of this path it is Source: http://ieeexplore.ieee.org/stamp/stamp.jspp possible to create a CC‐memory. This type of memory can also support a high virtual memory structure. 5. Critical Analysis

4. Scheme of user identification and authentication This research focuses on the problem of the web

users. As I showed that web server are not provide In this scheme, I show a tree based construction called that much information, we needed to some complex an identifier tree. These trees are also helps us to approaches to find out the information about the enable a server, so the identifier first identify the different users. This is done with the help of the visiting user via object, which is stored in the CC‐ cookies. Median Public opinion and the market memory. If we talk about the pharming attacks the research institute is the researches partner. When you attacker can successfully spoofs a domain name, and open a web pages sometimes advertisement are bypass these domain to the domain name controls. comes in the web pages. These advertisements are CC‐ memory is based on the history of the browser. managed by some specialized agencies. Some of the

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agencies send the cookie alongside to the image contains the advertisement. These advertisements manage by large scale of World Wide Web. They can build up to control the users profile and identify them by their details.

Some of the web browser allow to the user to switch off the cookies. So when the cookie is switch off the browser, will throw the cookie and sent it to the server. Some of the cookies have the password protected. This is use for the security purpose.

6. Conclusion

In this paper I shown about the cache cookie, how these cookie can support to identify the user identification. These cookies are also helping us to identify and track of the visited website. Some of the user can increase the level of the cookie because of the privacy concern. These are also use for the authentication purpose, user authentication help, to protect against the phishing & pharming attack.

7. References

[1] Brian Quinton, Cache Values, P.25, 24 Aug,1999

[2]http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arn umber=1624020

[3] J. Vijayan, Microsoft warns of digital certificates, computer world, 22march 2001.

[4]http://www.webopedia.com/DidYouKnow/Internet/ 2002/Cookies.asp

[5] http://www.rri.se/index.php?DN=26

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A BROADBAND BICONICAL ANTENNA FOR WIDE ANGLE RECEPTION

Saurabh Shukla1, Naveen Upadhyay2

1Scientist, DRDO, DARE, Karnataka, India, E‐mail: [email protected] 2Assistant Professor, Department of ECE, JVW University, Jaipur, INDIA, E‐mail: [email protected]

Abstract

A broadband Biconical antenna has been designed for the interception of electromagnetic waves in the frequency band of 2‐12 GHz. The aim of the design is to miniaturize the size of the Biconical antenna as much as possible without affecting the electrical performance of the antenna like VSWR, radiation pattern and gain. These types of broadband antennas are widely used for ESM applications. The designed antenna has return loss better than 10 dB across the frequency band with omnidirectional pattern. The omnidirectional pattern helps in achieving almost 3600 of azimuth coverage along with some degree of coverage in elevation plane. Such antenna can be used for the direction finding which can be further translated into angle of arrival (AOA) measurement of enemy targets. A CAD model has been designed and simulated by using CST microwave studio for the EM analysis. The simulated results like three dimensional radiation pattern, VSWR, Return loss and gain plots have been presented for discussion.

Index Terms: Biconical antenna, EM analysis, AOA and Omni‐directional.

1. INTRODUCTION conductors have common axis and the feed is provided along this axis. In other words, a Biconical antenna is a Federal Communication Commission (FCC) defined the broadband version of a simple dipole antenna which term Ultra Wide Band (UWB) in terms of the percentage exhibits bandwidth 3 octaves or more. It is described bandwidth with respect to the centre frequency. An that thickening the arms of dipole or monopole antenna antenna is termed as UWB if it satisfies the following results in increased bandwidth because the current condition: distribution remains no longer sinusoidal and therefore (fH – fL)/fC > 0.2 … (1) influences the input impedance of the antenna. And (fH – fL) > 500 MHz … (2) Theoretically, an infinite Biconical antenna is a frequency

independent antenna but for finite Biconical antenna Where, both input impedance and radiation pattern changes fL = lowest frequency of operation with frequency of operation. A Biconical antenna is a fH = highest frequency of operation broadband radiator with omnidirectional pattern in one fC = centre frequency of operation = (fH + fL)/2 plane and limited coverage in other plane. The

impedance of the feeding point of Biconical antenna is

generally chosen to be 50Ω because most of the coaxial Antenna is one of the most important components of connectors have 50Ω impedance. The impedance of a UWB communication. Biconical antenna was first Biconical antenna depends upon its conical geometry introduced by Schelkunoff [1]. Biconical antenna is a and impedance decreases with increase in conical broadband antenna which can operate over large geometry. In most of the Biconical antennas, the bandwidth. Biconical antenna consists of two conical impedance varies between 50‐75Ω based on the cone conductors, which are driven by alternating EM field. In a angle. typical Biconical configuration, both the conical

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The input impedance of a Biconical antenna with conical tan(α/2) = r/h … (5) length (l) and cone angle (α) is given by Papas and King [2] as: The other important design parameters have been optimized and their final values are given in Table‐1 for

Zin = Z0 (1‐β/δ)/ (1+β/δ) … (3) reference. Where, Z = characteristic impedance= 60 ln cot (α/4) … (4) o Parameter Name Optimized value

Gap (g) 4 mm The equation (4) suggests a relationship between the cone angle/flare angle and the characteristic impedance Cone Radius (r) 30 mm of a Biconical antenna. 0 Cone Angle (α) 100 2. BROADBAND BICONICAL ANTENNA Cone Height (h) 25 mm A Biconical antenna has been design and simulated to operate in 2‐12 GHz frequency range with maximum Conical Length (l) 39 mm VSWR 2.5:1 and Omni‐directional pattern in Azimuth plane. As shown in Fig‐1, the important parameters of a Table ‐1: Design Parameters Biconical antenna are cone angle (α), radius of the cone

(r), gap between the cones (g) and the conical length (l). Based on the optimized deesign parameters, a Biconical These parameters weree taken as variables and optimized antenna has been modeled in CST Microwave Studio as using the CST Microwave Studio to obtain the desired shown in Fig‐2. The modeled Biconical antenna is excited results. by a 50Ω coaxial connector. It shows that the two

metallic cones are separated from each other with the help of connector dielectric which maintains the gap [3] [4]. The conic sections are hollow and have a thickness of 1 mm.

Fig ‐1: Biconical antenna geometry

The parameters like conical length (l) or cone angle (α) can be derived from each other if other parameters like cone height (h) and cone radius (r) are defined. Based on the trigonometry, a relationship between cone height (h), cone angle (α) and cone radius (r) is given as: Fig ‐2: Bi‐conical antenna model

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The modeled antenna has been analyzed by using the This property is extremely useful when antenna is used CST Microwave Studio for obtaining the electrical as a sensing element for enemy radars. EM wave from performance parameters like return loss, VSWR, any direction in azimuth plane is well intercepted by such radiation Pattern and gain of the designed Biconical antennas due to omnidirectional pattern. antenna. The return loss plot, as shown in Fig‐3, suggests that the antenna is well matched with 50Ω coaxial connector in the frequency range of 2‐12 GHz. Moreover, it also recommends that the same feeding can be used for achieving larger bandwidth at different centre frequency.

Fig ‐5: Radiation Pattern of Biconical Antenna The half power beam width (HPBW) in elevation plane at different frequencies is tabulated under Table‐2. It can be concluded that the designed Biconical antenna can intercept the threat in ± 300 in elevation plane for a maximum loss of 3 dB. Fig ‐3: Return Loss of Biconical Antenna Frequency (GHz) HPBW The VSWR of the designed antenna is well within the 0 desired range i.e. 2.5:1 for the 6:1 bandwidth. VSWR plot 2 100 for the Biconical antenna has been presented in Fig‐4. 4 1250

6 900

8 830

10 970

12 660

Table ‐2: HPBW in elevation plane The Biconical Antenna offers moderate gain in the entire

frequency range. The simullated gain for the proposed Fig ‐4: VSWR of Biconical Antenna Biconical antenna is presented in Fig‐6. It is evident from

the gain plot that the gain increases linearly with the The radiation pattern of the antenna at 2 GHz is frequency with some exception. presented in Fig‐5. It is clear that if the antenna is kept in 0 vertical polarization, it provides 360 azimuth coverage.

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signal strength. The mechanical dimensions of the antenna are kept as small as possible to make it compact and hollow conic section makes it light weight and extremely useful for those platforms where volume is a constraint. The proposed design can be further optimized to achieve larger bandwidth i.e. 1‐18 GHz with omnidirectional radiation pattern.

4. ACKNOWLEDGEMENTS Fig ‐6: Biconical Antenna Gain Plot The author would like to thank Director, DARE for his

continuous support and encouragement for this work. The exceptions in the antenna gain appear due to the increase in HPBW of the antenna in elevation planes. If 5. REFERENCES: we compare Table‐2 and Fig‐6, it is clear that the frequency spots where the gain falls, the HPBW [1]. Schelkunoff S., Advanced Antenna Theory. N J: D. increases. It is a common phenomenon in a broadband Van Nostrand, Princeton, 1952. antenna and cannot be just controlled by design [2]. C. H. Papas, and R. W. P_ King, "Radiation from wide‐ parameters. angle conical antennas fed by a coaxial line," Proc. IRE , 3. CONCLUSION vol. 39, pp.49‐51, Jan. 1951. A broadband Biconical antenna has been reported in this [3]. Janett D. Morrow, “Shorted Biconical Antenna for paper. The simulated result suggests that the antenna Ultra‐Wideband Application”, in Proc. of IEEE Symp. pp. performs well within the frequency range of 2‐12 GHz. 143–146, 2003. The antenna can intercept enemy radar signals in 3600 0 azimuth plane along with ± 30 coverage in elevation [4]. S_ S. Sandler and R. W_ P. King, "Compact conical plane. The antenna also exhibits moderate gain ranging antenna for wideband coverage," IEEE Trans Antennas between 2‐4 dB which helps in improving the received Propagat, vol. 42, no 3, pp. 436‐439, Mar_ 1994.

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A Combination of Video Games and Artificial Intelligence

Jaya Sachan

M.Tech Scholar, Jayoti Vidyapeeth Women’s University, Jaipur, INDIA, E‐mail‐ [email protected]

Abstract

Al research and video games are a mutually beneficial combination. On the one hand, AI technology can provide solutions to an increasing demand to add realistic, intelligent behavior to the virtual creatures that populate a game world. On the other hand, as game environments become more complex and realistic, they offer a range of excellent test beds for fundamental AI research.

This paper will give an introduction to the area of applying AI techniques, such as learning, search and planning, to video games. The tutorial will focus on past and recent applications, open problems and promising avenues for future research, and on resources available to people who would like to work in this space. We will present concrete AI techniques used in games and give references to relevant work. We hope that the topic is relevant to both game developers looking for ways to improve their products, and researchers looking for realistic benchmarks to test new algorithms and ideas.

Keyword: Artificial intelligence research, video games, learning, planning and search

1. Introduction the complexity of real‐world situations while maintaining the controllability and traceability of computer In which area of human life is artificial intelligence (AI) simulations. As an example, consider the problem of currently applied the most? The answer, by a large driving a racing car under realistic race conditions. While margin, is Computer Games. This is essentially the only the full problem is too complex to be tackled right now big area in which people deal with behavior generated because it involves problems around limited actuators by AI on a regular basis. And the market for video games and noisy sensors in addition to the AI problem, is growing, with sales in 2007 of $17.94 billion marking a important aspects can be tackled working inside a state‐ 43% increase over 2006. However, growth is not only in of‐the‐art racing game simulation. As game designers sales but also in the diversity of content offered, ranging work hard to create more realistic worlds for their from educational games to first‐person shooters. In customers, AI researchers can benefit from access to addition, a fascinating convergence of media is taking benchmarks that accurately reflect real‐life problems. place with video games often having movie quality cut‐ Games exhibit many combinations of features that are scenes and narrative. important in current AI research. For example, a game environment can be either static or dynamic, there can 2. So, where does artificial intelligence come be either single‐agent or two‐player or multi‐agent into play? problems, transitions can be either deterministic or non‐ deterministic, and game worlds can be either fully We argue that both games and AI research can greatly known or partially observable. From a games benefit from each other. From a research point of view, perspective, one key problem is the creation of AI driven video games offer fascinating toy examples that capture

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agents that can interact with the player and be adaptive scale, for hundreds of units in the game engaged in so as to create a great interactive gaming experience. massive battles. SimCity, created by the company Maxis, These agents can take a variety of roles such as player’s was the first game to prove the feasibility of using A‐Life opponents, teammates or other non‐player characters. technologies in the field of computer games. Another Online planning and reinforcement learning have the milestone turned out to be the game Black and White, ability to create adaptive behavior, which might become created in 2001 by Lion head Studios, in which a key feature in future, games. This is useful to respond technologies of computer‐controlled characters' to changes in the human player strategy, the learning were used for the first time. environment, the current problem instance, etc. Games like Creatures and Black & White have attempted to 4. AI in FPS‐type Games build entire games around the concept of teaching FPS‐type games usually implement the layered structure behavior to adaptive AI agents. A few concrete of the artificial intelligence system. Layers located at the examples of AI challenges in games, which we plan to very bottom handle the most elementary tasks, such as cover in this tutorial, include driving a car in a racing determining the optimal path to the target (determined game, path finding on a map, planning the behavior of by a layer higher up in the hierarchy) or playing non‐player characters in a role‐playing game, resource appropriate sequences of character animation. The gathering in a real‐time strategy game, and planning the higher levels are responsible for tactical reasoning and strategy of a combat team in a first‐person shooting selecting the behavior which an AI agent should assume game. We anticipate that people from the AI community in accordance with its present strategy. Path‐finding will have a lot to contribute to the field of computer systems are usually based on graphs describing the games once the wealth of opportunities in this space has world. Each vertex of a graph represents a logical been understood. However, computer games offer a location (such as a room in the building, or a fragment of great variety of other challenges including problems in the battlefield). When ordered to travel to a given point, graphics, sound, networking, player rating and the AI agent acquires, using the graphs, subsequent matchmaking, interface design, narrative generation, navigation points it should consecutively head towards game world design, scripting etc. All of these areas in order to reach the specified target location. Moving would benefit from various learning and planning between navigation points, the AI system can also use paradigms. local paths which make it possible to determine an exact

3. Milestones in the Development of Artificial path between two navigation points, as well as to avoid Intelligence in Games dynamically appearing obstacles.

While discussing the evolution of artificial intelligence in The animation system plays an appropriate sequence of computer games, one definitely should mention the animation at the chosen speed. It should also be able to games which have turned out to be milestones in the play different animation sequences for different body development of intelligent behavior in games. One of parts: for example, a soldier can run and aim at the the most popular games of the 1990s was War Craft – a enemy, and shoot and reload the weapon while still game developed by the Blizzard studio. It was the first running. Games of this kind often employ the inverted game to employ path‐finding algorithms at such a grand kinematics system. An IK animation system can appropriately calculate the parameters of arm

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positioning animation so that the hand can grab an object located on, e.g., a table or a shelf. The task of modules from higher layers is to choose the behavior appropriate for the situation – for instance, whether the agent should patrol the area, enter combat, or run through the map in search of an opponent.

Once the AI system has decided which behavior is the Figure 1: Representation of the world in a RTS‐type game most appropriate for the given situation, a lower‐level module has to select the best tactics for fulfilling that task. Having received information that the agent should, for instance, fight, it tries to determine the approach that is the best at the moment – e.g., whether we should sneak up on the opponent, hide in a corner and wait for the opponent to present a target of itself, or perhaps just run at him, shooting blindly.

5. AI in RTS‐type Games

In RTS‐type games, it is possible to distinguish several modules of the artificial intelligence system and its Figure 2: Representation of the world in a FPS‐type game layered structure. One of the basic modules is an 6. AI in Sports Games effective path‐finding system – sometimes, it has to find a movement solution for hundreds of units on the map, Basically, in the case of most sports games, we are in split seconds – and there is more to it than merely dealing with large‐scale cheating. Take car racing games, finding a path from point A to point B, as it is also for instance. For the needs of the AI, from the geometry important to detect collisions and handle the units in the of the game map, only and only the polygons belonging battlefield avoid each other. Such algorithms are to the track of a computer‐controlled opponent should typically based on the game map being represented by a travel on and get distinguished. Two curves are then rectangular grid, with its mesh representing fixed‐sized marked on that track: the first represents the optimal elements of the area. On higher levels of the AI system's driving track, the second – the track used when hierarchy, there are modules responsible for economy, overtaking opponents. The whole track gets split into development or, very importantly, a module to analyze appropriately small sectors and, having taken the game map. It is that module, which analyses the parameters of the surface into account, each element of properties of the terrain, and a settlement is built based the split track gets its length calculated. Those on the assessment, e.g., whether the settlement is fragments are then used to build a graph describing the located on an island, thus requiring higher pressure on track, and to obtain characteristics of the road in the building a navy. The terrain analyzer decides when cities vehicle's closest vicinity. In effect, the computer knows should be built and how fortifications should be placed. it should slow down because it's approaching the curve,

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or knows that it's approaching an intersection and can, The predefined scenario of a computer‐controlled player e.g., take a shortcut. Two important attributes of is then acted out by the character animation system. Artificial Intelligence systems in such games is being able to analyze the terrain in order to detect obstacles lying 7. Choosing an Algorithm on the road, and strict co‐operation with the physics There are a lot of algorithms for finding the optimal path module. The physics module can provide information in a graph. The most simple of such algorithms, that the car is skidding, having received which the commonly called fire on the prairie, works by Artificial Intelligence system should react appropriately constructing consecutive circles around the starting and try to get the vehicle's traction back under control. point, with each step of the algorithm building another, wider circle. Consecutive circles and elements belonging to them are assigned larger and larger indices. As one can see in Figure 5, the circle with index 4 passes through our target point.

Figure 3: The method of presentation of reality in car race (segmentation and optimalisation of the track)

Figure 5: A simple path‐finding algorithm

Now, heading in the opposite direction and following Figure 4: The method of presentation of reality in car the rule that in each step we move to the nearest map race point located on the circle with a smaller index, we reach the starting point; the elements of our map we have Similar cheating can also be found in other sports returned through make up the shortest path between games. In most cases, a computer‐controlled player has the starting point and the destination. Examining the its complete behavior determined even before the way this algorithm works, one can see that, in addition beginning of the turn – that is, it will, e.g., fall over while to its great advantage – the simplicity – it also possesses landing (acrobatics, ski jumping etc.), have the wrong a severe drawback. The path the algorithm has found in velocity, start false etc. Additionally, in games simulating our example consists of only five elements of the game sports with scoring by judges, the scores are generated world, even though 81 fields of the map would have to according to the rules defined by the appropriate sports be examined in the worst‐case scenario. In case of a map bodies.

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consisting of 256x256 fields, it might mean having to examine 65536 map elements!

Enter A* and its primary advantage – minimization of areas being examined by consciously orienting the search towards the target. Keeping it brief, I could say that, when calculating the cost of reaching a point on the map, the A* algorithm adds to it some heuristics indicating the estimated cost of reaching the destination; this function is typically the distance to the destination from the point currently being examined.

8. References

 Steve Rabin, AI Game Programming Wisdom, ISBN: 1584500778  Steve Rabin, AI Game Programming Wisdom 2, ISBN: 1584502894  Game Programming Gems 1, 2 ,3, 4  Game Developer Magazine  Erich Gamma, Richard Helm, Ralph Johnson, John Vlissides, Design Patterns CD – Elements of Reusable Object‐Oriented Software

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Accomplishment and Timing Presentation: Clock Generation of CMOS in VLSI

Manoj Kumar Choudhary

Assistant Professor, E‐Mail: [email protected]

Department of Electronics and Communication Engineering

Baldev Ram Mirdha Institute of Technology (EAST)

ITS‐4, ITPark, EPIP Sitapura Jaipur‐ Rajasthan (INDIA).

Abstract Accomplishment independent timing issues in an oversampled system. This research paper present the oversampled input receiver accomplishment details and measured time results. The first section of this paper provides an impression of the sampling system included on the test chip. The timing accurateness is mainly bounded by the clock generators. This includes interpolation circuits for creating finely spaced clocks and architectural trade‐offs for structure multiphase clock generators with tunable production or output phases. The research concludes with test results for static phase and compensation techniques for two clock generators. Having explored methods to build clock generators. Then examines clocked input samplers that can imprison high‐speed signals while having a minimal impact on timing accuracy. Key Word: S‐RAM, Bandwidth, Clock Generators, PMOS, CMOS, DLL, PLL.

1. Introduction To better appreciate the trade‐offs and to test the compensation methods, a sampling receiver test chip designed and measured. A building block diagram of the test chip is shown in Figure 1.1. The part is made‐up in a standard0.25μm, five metal layer processes. It contains eight sampling channels that feed either an S‐RAM memory or an on‐chip histogram counter. The sampling rate per channel is 46 G samples/s with a 900MHz reference clock and 50 sampling phases [1]. The eight sampling channels generate 388 GB/s of digital data but to reduce the required bandwidth of the acquisition Figure 1.1: Block diagram: Testing of chip for SRAM memory, the data rate is reduced by oversampling only Memory

half the cycle. The memory is accomplished of storing 2. Clock Generation the resulting 244 GB/s data stream with no The clock generators drive the input sampling receivers supplementary loss of information. The chip contains and set the timing of the whole system. To compare two circuits that can be used to generate the finely design trade‐offs and performance, both a phase‐locked spaced (37ps) clocks. One uses a delay line with loop and delay‐locked loop were included on the test interpolation and the other uses an array of oscillators chip. The performance of the delay elements in the clock [2]. generators appreciably impacts the jitter performance, so this section starts with a description of a low‐jitter differential delay element [3]. The delay element is then changed into a tunable interpolator to permit fine phase spacing. The section continues with a discussion of the

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issues involving the amalgamation of tunable a delay understanding of about 0.05, which is an interpolators into a delay line and VCO to achieve a large enhancement by a issue part of twenty. modification range without compromising performance. The control loops and clock buffers are then described by the side of techniques to minimize the static phase offsets and jitter caused by these elements [4].

3. Basic Elements in Buffer The clock generators are implemented with Maneatis style self‐biased control loops and replica biased, variable delay, differential buffers with symmetric loads [5]. A buffer shown in Figure 2. The two PMOS devices that form the load structures are termed symmetric loads. If the output swing is equal to the bias voltage Vbp, then the resistance of the loads is symmetric about the crossing of the differential outputs. This reduces the

jitter caused by common‐mode provide clatter such as Figure 1.3: Replica bias generator for delay elements noise [6].

4. Delay‐Line Based Clock Generator The central part of the delay line is five differential delay elements. Interpolators split the five clock phases into twenty differential clocks. A single level of interpolation, as shown in Figure 1.4, minimizes jitter because it minimizes the delay through the clock paths as compared to techniques using multiple levels of interpolation [5]. The interpolation ratios are chosen to maximize the adjustment range of all the interpolators. Nevertheless, this topology is unsatisfactory because the interpolators on the ends have a limited adjustment

range of 1/8 a buffer delay one direction since their Figure 1.2: Differential delay element for buffer supposed position is within 12.5% of one of the input

phases. To maintain a reasonable adjustment range, not Vbp is drive by the control loop to set the delay of the only do the inputs to the interpolator need to have buffer. Vbn is energetically position by the replica biasing sufficient phase spacing, but the nominal weighting of circuit in Figure 1.3 to set the output signal move the interpolators must not be exceptionally off‐center backward and forward equal to Vbp which maintain the from 1/2. symmetric environment of the loads. The degree of difference topology, symmetric loads, and replica biasing yields a delay element with a low understanding to supply clatter such as noise. A typical inverter has a delay understanding of approximately 1, while this element has

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5. Ring Oscillator Based Clock Generator The before described interpolation techniques are also applicable to a conventional ring oscillator based VCO. Yang describes such a clock generator in with 24 phases for over sampling a 2.5 Gb/s SONET signal. However, given the need for interpolation, possibly a more interesting architecture is the array oscillator as described by Maneatis in. This structure uses multiple,

coupled ring oscillators to create equally phase shifted Figure 1.4: Initial exclamation plan for DLL clocks [7]. To those unknown with an array oscillator, the

operation can be confusing so it is briefly reviewed The modification range can be greater than before, at before proceeding with the details of adding phase the cost of better jitter, by using two levels of tuning to the structure. First, consider a series of interpolation, as shown in Figure 1.5 (a & b) . The design uncoupled ring oscillators as shown in Figure 1.6. In an in Figure 1.5 (a) interpolates with a 50%/50% ratio ideal environment, the ring oscillators will oscillate with between existing clock phases to generate new phases. identical frequencies, but with an arbitrary phase The interpolators with the shorted inputs delay the alignment. While this produces multiple output clocks, existing phases so they are properly interleaved with the the arbitrary phase alignment of the clocks makes this new phases. An alternate technique is to synthesize both solution uninteresting. To generate equally spaced of the new phases via interpolation as shown in Figure output clocks, a forced phase alignment between the 1.5 (b) which is identical to the original design shown in rings is required. This can be achieved by replacing each Figure 1.4 except with only two interpolators rather than of the single input buffers with a two‐input interpolator four. Topology (a) has enhanced phase spacing in the and coupling the rings together. presence of interpolation ratio errors as only half the phases are affected, but the interpolators with their inputs shorted in design (a) have no adjustment range. Topology (b) can have twice the DNL as (a) because the inputs to every other interpolators are reversed so adjacent phases are pushed in opposite directions. However, the interpolators in (b) do have a larger adjustment range of at least 0.25 of aFO‐4 delay.

Figure 1.6: Multiple uncoupled ring oscillators 6. Clock Drivers for DLL and PLL Because the buffer and interpolator cells are low‐swing, the clock signals need to be transformed to full‐swing previous to driving the samplers. The level converter and clock buffers used in both the DLL and PLL are shown in Figure 1.7. In the course of sharing the circuit and making a last‐minute sizing change in the array oscillator, the

current source in the differential pair was mis‐sized in Figure 1.5 (a & b): Interconnect techniques for phase the PLL [5]. The result was insufficient current to fully interpolation.

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swing the input to the first inverter, and can be performed in less than a few seconds. A correspondingly, marginal clock signals. Fortunately, a secondary measurement capability is provided by a clock few of the clock outputs did function sufficiently to multiplexer and output driver. Figure 1.8 shows the obtain jitter measurements presented later in this histogram counter and multiplexers as implemented on chapter. However, phase spacing measurements were the test chip. Because the input clocks to the histogram not possible. counter always consist of an even and odd clock, the multiplexers can be simplified by making one select between the even clocks and the other select between the odd clocks.

Figure 1.7: Low‐to‐high swing converter and clock buffers The delay through the converter roughly tracks that of Figure 1.8: Architecture for histogram measurements of the delay elements in the clock generators because the phase offsets differential pair is biased with same signal, Vbn. This biasing also implies that the slew rate of the input to the A 20‐bit counter counts system cycles so that each first inverter is also related to the operating frequency. histogram runs for an equal period of time. The counters At first glance, this appears fine; the rise and fall times are implemented as linear feedback shift registers (LFSR) remain roughly a constant percentage of the cycle time. to simplify design and minimize the area required However, this also means that the jitter scales with the compared to a regular binary counter. Decoding the clock period. A better solution is to bias the differential LFSR count into a binary value is performed off‐line by a pair with a fixed current so that the current mirror is fast workstation [9]. and the speed is independent of the frequency of the clock generator. 8. Conclusion Static phase errors, timing jitter, sampler input offset 7. Measurement of Phase Results voltage, and input capacitance are the primary Tunable interpolators in the clock generators make challenges of implementing a CMOS oversampled possible static tuning of clock phase offsets. To as it receiver with high timing accuracy. Because of should be program the interpolators, the static phase aggressive CMOS scaling, the most abundant resource spacing of the clocks have got to first be measured. The available to address these problems is transistors. Static test chip multiplexes sampler outputs into a single phase compensation is probably the most robust of the counter to avoid the need for separate counters on each implemented techniques and results indicate that set of adjacent phases [8]. This makes the measurement placing the nominal position of a clock edge to within a process longer because the size of the bins can no couple picoseconds is feasible. The phase tuning longer be measured in parallel, but instead must be algorithm is driven by histogram counters that precisely measured sequentially. Nevertheless, the measurement measure phase offsets without introducing additional

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timing errors. In the test chip, the primary limitation to 10. C. Yang et. al. “A 0.8‐m CMOS 2.5 Gb/s uniform phase spacing appears to be the complexity and Oversampling Receiver and Transmitter for Serial size of the current‐mode digital to‐ analog converters Links,” IEEE Journal of Solid State Circuits, vol. 31, used in the interpolators. no.12, pp 2015‐2023, Dec. 1996.

9. References 1. S. Kuge et. al. “A 0.18 mm 256Mb DDR‐SDRAM with low‐cost post‐mold‐tuning method for DLL replica,” in Dig. Tech. Papers ISSCC 2000. 2. J. Maneatis et. al. “Precise Delay Generation Using Coupled Oscillators,” IEEEJournal of Solid State Circuits, vol. 28, no. 12, pp. 1273‐1282, Dec. 1993. 3. M. Karlsson, and M. Vesterbacka, “A Robust Non‐ Overlapping Two‐Phase Clock Generator,” in Proc. of Swedish System on hip Conference SSoCC’03, Sundbyholms slott, Eskilstuna,Sweden, Mars 8‐9, 2003. 4. Tam, S., Limaye, D.L., and Desai, U.N., "Clock Generation and Distribution for the 130‐nm Itanium 2 Processor with 6‐MB On‐Die L3 Cache", in IEEE Journal of Solid‐State Circuits, Vol. 39, No. 4, April 2004. 5. J. Maneatis et. al. “Low‐jitter process‐independent DLL and PLL based on selfbiasedtechniques,” IEEE Journal of Solid State Circuits, vol. 31, no. 11, pp. 1723‐ 1732, Nov. 1996. 6. H. Ahn and D. J. Allstot, “A low‐jitter 1.9‐V CMOS PLL for Ultra‐ SPARC microprocessor applications,” IEEE J. Solid‐State Circuits, vol. 35, pp. 450–454, Mar. 2000. 7. G. Chien and P. R. Gray, "A 900MHz Local Oscillator using a DLL‐based Frequency Multiplier Technique for PCS Applications", in ISSCC Dig. Tech., pp. 202‐ 203, Papers , Feb. 2000. 8. G. Wei et. al. “A Variable‐Frequency Parallel I/O Interface with Adaptive Power‐Supply Regulation,” IEEE Journal of Solid State Circuits, vol. 35, no. 11, pp.1600‐1610, Nov. 2000. 9. B. Razavi, Ed., Phase‐Locking in High‐Performance Systems: From De‐ vices to Architectures. Piscataway, NJ: IEEE Press, 2003.

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Dynamic Model Representation in the Locality Frequent Neural Networks

1Jitendra Joshi, 2Ritu Nagwani, 3Renu Deswal, 4Priyanka Sharma 1Ph.D. Scholar, Jayoti Vidhyapeeth Women’s University, Jaipur, E‐mail: [email protected] 2B.Tech. Scholar, Jayoti Vidhyapeeth Women’s University, Jaipur, E‐mail: [email protected] 3B.Tech. Scholar, Jayoti Vidhyapeeth Women’s University, Jaipur, E‐mail: [email protected] 4B.Tech. Scholar,Jayoti Vidhyapeeth Women’s University, Jaipur, E‐mail: [email protected]

Abstract Dynamic model presentation is system identification and mathematical calculation of neural network. Dynamic system using neural networks involve the dynamic differential equation into each of the neural network processing elements to create a new type of neuron called a dynamic neuron. The dynamic model represents architecture of frequent neural network in different paradigm’s model. Index Terms: Dynamic Model, FNN, BMLP, TDL, LRNN, LF‐MLN, AF‐MLP, OF‐MLP

1. Introduction multilayer perceptron network (AF‐MLP). The third Dynamic model presentation is mathematical calculation structure is the Output Feedback multilayer perceptron of neural network and dynamic recurrent neural network (OF‐MLP) [3]. networks have shown themselves to be really useful for temporal processing, particularly for digital signal 2. LOCALITY FREQUENT NEURAL NETWORKS processing (DSP) and temporal pattern recognition of We are here interested in neural network architectures neurons. Dynamic system using neural networks involve that are able to learn temporal features in data for time the dynamic differential equation into each of the neural series prediction. In other words, we intend to deal with network processing elements to create a new type of the problem of Time Series Processing: field of statistics neuron called a dynamic neuron [1]. Two main methods regarding the analysis of data characterized by both exist to provide a static neural network with dynamic spatial and temporal dimensions. The FFNN is frequently behavior: the insertion of a buffer somewhere in the used in time series prediction. FFNN, however, has the network, i.e., implementing an explicit memory of the major limitation that it can only learn an input and past inputs, or the use of feedback. output mapping which is static. Thus it can be used to The first kind of dynamic network is a buffered perform a nonlinear prediction of a stationary time multilayer perceptron (BMLP), in which tapped delay series [4]. A time series is said to be stationary, when its lines (TDL’s) of the inputs are used. The latter approach statistics do not change with time. In many real world brings us to the so called locally recurrent neural problems, however, the time when certain feature in the networks (LRNNs) or local feedback multilayer networks data appears, contains important information. More (LF‐MLN) that will be the architectures we will be specifically, the interpretation of a feature in data may concentrated on [2]. depend strongly on the earlier features and the time Different architectures arise depending on The first they appeared. A common example of this phenomenon architecture is the IIR‐MLP proposed by Back and Tsoi. is speech. A good solution is to let time have an effect on The second architecture is the activation feedback the networks response. This can be achieved when the

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network has dynamic properties such that it will respond and in adaptive time‐delay neural networks. It can be to temporal sequences [5]. Dynamic recurrent neural shown that BMLP and FIR‐MLP are theoretically networks have shown themselves to be really useful for equivalent, since internal buffers can be implemented as temporal processing, particularly for digital signal an external one [8]. processing (DSP) and temporal pattern recognition. Two main methods exist to provide a static neural network with dynamic behavior: the insertion of a buffer somewhere in the network, i.e., implementing an explicit memory of the past inputs, or the use of feedback [6].

In both approaches, an arbitrary input x[t] may influence a future output y [t + h], so that ∂y[t + h] ∂x[t] is not equal to zero for some h. In the case of asymptotic Figure 2: Buffered multilayer perceptron with input stability, this derivative goes to zero when h goes to buffer. infinity. The value of h for which that derivative becomes The problem with implementing FIR‐MLPs as buffered negligible is called temporal depth, while the number of MLPs is that first layers sub networks must be replicated adaptable parameters divided by the temporal depth is (with shared weights) and so the complexity is much called temporal resolution. higher than considering the buffer internal. Therefore, buffered MLP and FIR‐MLP are different architectures 3. BUFFERED MULTILAYER PERCEPTRON WITH INPUT with regard to areal implementation. The main BUFFER disadvantage of the buffer approach is the limited past The first kind of dynamic network is a buffered history horizon thereby preventing modeling of arbitrary multilayer perceptron (BMLP), in which tapped delay long time dependencies between inputs and desired lines (TDL’s) of the inputs are used. The buffer can be outputs [9]. It is also difficult to set the length of the applied at the network inputs only, keeping the network buffer, given a certain application moreover to have internally static, as in buffered MLP (Figure 1): sufficient temporal depth, a long buffer, i.e., a large number of input weights, could be required, usually with a decrease in generalization performance and an increase in the overall computational complexity.

In other words, the buffer approach with no feedback has the maximum temporal resolution, at the cost of a low temporal depth. To adaptively balance temporal depth with temporal resolution, another buffer type, called gamma memory, can be adopted, for which the delay operator, used in conventional TDLs, is replaced by

Figure 1: Buffered multilayer perceptron with input a single pole discrete time filter [10]. Gamma memory is buffer. a dispersive delay line with dispersion regulated by an or at the input of each neuron, as in MLP with Finite adaptable parameter. Impulse Response filter synapses [FIR‐MLP](Figure 2), In addition to these advantages of temporal depth and sometimes called time‐delay neural network (TDNN), temporal resolution characteristics, it is known that

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neural networks with feedback have useful dynamic modeling behavior. Feedback has been implemented for the first time with the introduction of the so called fully recurrent neural networks (RNN); they are formed by a single layer of neurons fully interconnected with each other, or several such layers [10]. Such RNNs, however, exhibit some well known disadvantages: a large structural complexity (that is too many weights) and a slow and difficult training. As a matter of fact, they are very general architectures which can model a large class Figure 4: Elman’s network. of dynamical systems. Nevertheless, on specific problems, simpler dynamic neural networks, which make 5. INTERNALLY: INSIDE EACH NEURON use of available prior knowledge, can be better. Many The latter approach brings us to the so called locally efforts have been made with the aim of introducing recurrent neural networks (LRNNs) or local feedback temporal dynamics into the multilayer perceptron neural multilayer networks (LF‐MLN) that will be the model. These efforts have paid in terms of less complex architectures we will be concentrated on. In these architectures and easier training, with respect to the structures, classical infinite impulse response (IIR) linear RNNs. The major difference among the methods filters, also called autoregressive moving average developed for the purpose lies in how feedback is (ARMA) models, are used, either directly, or with some included in the network [11]. modifications [12]. Different architectures arise depending on how the ARMA model is included in the 4. Externally Structure of MLP Network network. The first architecture is the IIR‐MLP proposed As in the Narendra–Parthasarathy MLP, also known as by Back and Tsoi, where static synapses are substituted NARX network, where TDLs are also used for the by conventional IIR adaptive filters (Figure 5). outputs that are then brought back to the input of the network (Figure 3). Another example is the Elman’s network (Figure 4).

Figure 5: IIR‐MLP neuron structure

6. AF‐MLP NEURON STRUCTURE The second architecture is the activation feedback

multilayer perceptron network (AF‐MLP). The output of Figure 3: (a) Narendra–Parthasarathy MLP the neuron summing node is filtered by an autoregressive (AR) adaptive filter (all poles transfer function), before feeding the activation function. In the most general case, the synapses are FIR adaptive filters. The AF‐MLP is a particular case of the IIR‐MLP, when all

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the synaptic transfer functions of the same neuron have the same denominator. At last, there is architecture (Figure 8) that’s again a multilayer network, where each neuron has FIR filter synapses and an AR filter after the activation function (ARMLP). It is easy to see that this network is a particular case of the IIR‐MLP, followed by linear all‐pole filters [14, 15].

The major advantages of LFNNs with respect to buffered Figure 6: AF‐MLP neuron structure MLPs or fully recurrent networks can be summarized as 7. OF‐MLP NEURON STRUCTURE follows: The third structure is the Output Feedback multilayer 1) Well‐known neuron interconnection topology, i.e., the perceptron network (OF‐MLP), in which the IIR filter is efficient and hierarchic multilayer; modified in order to let the feedback loop pass through 2) Small number of neurons required for a given the nonlinearity, i.e., the onetime step delayed output of problem, due to the use of powerful dynamic neuron the neuron is filtered by a FIR filter whose output is models; added to the inputs contributions, providing the 3) Generalization of the popular FIR‐MLP (or TDNN) to activation. Again, in the general model the synapses can the infinite memory case; be FIR filters (Figure 7). 4) Pre‐wired forgetting behavior, needed in applications such as DSP, system identification and control; 5) Simpler training than fully recurrent networks; 6) Many training algorithms could be derived from filter theory and recursive identification.

8. CONCLUSION Figure 7: OF‐MLP neuron structure Dynamic model presentation is mathematical calculation Elman’s network is based on the introduction of context of neural network and dynamic recurrent neural units to include memory in a network, substituting the networks have shown themselves to be really useful for spatial metaphor of the external buffer with the temporal processing, particularly for digital signal recurrent context approach [13]. Context units are processing (DSP) and temporal pattern recognition of dynamic recurrent neurons placed in the first layer to neurons. A good solution is to let time have an effect on process the input signals, while the following layers are the networks response. This can be achieved when the supposed to be static. This architectural constraint has network has dynamic properties such that it will respond been chosen basically to simplify the learning phase. to temporal sequences.

9. REFERENCE

[1] G. C. Goodwin and R. L. Payne, Dynamic System Identification, Academic Press, New York, 1977. [2] K. Hornik, M. Stinchcombe and H. White, Multilayer Figure 8: Auto‐regressive MLP Feed‐forward Networks are Universal

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Approximators", Neural Networks Vol. 2. 1989. pp. 359‐ [15] K. S. Narendra and K. Pathasarathy, Identification 366. and Control of Dynamical Systems Using Neural [3] G. Cybenko, Approximation by Superposition of Networks, IEEE Trans. Neural Networks, Vol. 1. 1990. Sigmoidal Functions, Mathematical Control Signals [16] J. Sjöberg, Q. Zhang, L. Ljung, A. Benveniste, B. Systems, Vol. 2. pp. 303‐314, 1989. Delyon, P.‐Y. Glorennec, H. Hjalmarsson and A. Juditsky: [3] K. I. Funahashi, On the Approximate Realization of "Non‐linear black‐box modeling in system identification: Continuous Mappings by Neural Networks", Neural a unified overview", Automatica, 31:1691‐1724, 1995. Networks, Vol. 2. No. 3. pp. 1989. 183‐192. [17] E. A. Wan, Temporal Backpropagation for FIR Neural [4] M. Leshno, V. Y. Lin, A. Pinkus and S. Schocken, Networks, Proc. of the 1990 IJCNN, Vol. I. pp. 575‐580. Multilayer Feed‐forward Networks With a [18] R. J. Williams and D. Zipser, A Learning Algorithm Nonpolynomial Activation Function Can Approximate for Continually Running Fully Recurrent Neural Any Function, Neural Networks, Vol. 6. 1993. pp. 861‐67 Networks, Neural Computation, Vol. 1. 1989. pp. 270‐280. [5] J. S. Albus, A New Approach to Manipulator Control: [19] N. Murata, S. Yoshizawa and Shun‐Ichi Amari, The Cerebellar Model Articulation Controller Network Information Criterion ‐ Determining the (CMAC),Transaction of the ASME, Sep. 1975. pp. 220‐227. Number of Hidden Units for an Artificial Neural Network [6] Y. H. Pao, Adaptive Pattern Recognition and Neural Model, IEEE Trans. on Neural Networks, Vol. 5. No. 6. Pp. Networks, Addison‐Wesley, Reading, Mass., 1989, pp. 865‐871. 197‐222. [20] X. He and H. Asada, A New Method for Identifying [7] D. F. Specht, Polynomial Neural Networks, Neural Orders of Input‐Output Models for Nonlinear Dynamic Networks, Vol.3. No. 1 pp. 1990. pp. 109‐118, Systems, Proc. of the American Control Conference, [8] J. Park and I. W. Sandberg, Approximation and 1993. San Francisco, CA. USA. pp. 2520‐2523. Radial‐Basis‐Function Networks, Neural Computation, [21] S. Saarinen, B. Bramley and G. Cybenko, Ill‐ Vol 5. No. 2. 1993. pp. 305‐316. conditioning in Neural Network Training Problems, SIAM [9] S. Haykin, Neural Networks. A comprehensive Journal for Scientific and Statistical Computing, 1991. foundation, Second Edition, Prentice Hall, N. J.1999. [22] G. Horváth, B. Pataki and Gy. Strausz, Black box [10] M. H. Hassoun, Fundamentals of Artificial Neural Modeling of a Complex Industrial Process, Proc. of the Networks, MIT Press, Cambridge, MA. 1995. 1999 IEEE Conference and Workshop on Engineering of Computer Based Systems, Nashville, TN, USA. 1999. pp. [11] M. Brown and C.Harris, Neurofuzzy Adaptive 60‐66. Modelling and Control, Prentice Hall, New York, 1994. [23] J. Van Gorp, J. Schoukens and R. Pintelon, Learning [12] G. Horváth and T. Szabó, CMAC Neural Network with Neural Networks with Noisy Inputs Using the Errors‐In‐ Improved Generalization Property for System Modelling, Variables Approach, IEEE Trans. on Neural Networks, Vol. Proc. of the IEEE Instrumenation and Measurement 11. No.2. pp. 402‐414. 2000. Conference, Anchorage, 2002. [13] T. Szabóand G. Horváth, CMAC and its Extensions for Efficient System Modelling and Diagnosis, Intnl. Journal of Applied Mathematics and Computer Science, Vol. 9. No. 3, pp.571‐598, 1999. [14] J. Hertz, A. Krogh and R. G. Palmer, Introduction to the Theory of Neural Computation, Addison‐Wesley Publishing Co. 1991.

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Future of V Band in Satellite Communication

1Ashish Tyagi, 2Chandan Choudhary, 3Naveen Upadhyay 1M.Tech Scholar, ECE Department, SGV University, Jaipur‐ INDIA, Email: [email protected] 2M.Tech Scholar, ECE Department, ACEIT, Jaipur‐ INDIA, Email: [email protected] 3Assistant Professor, ECE Department, JVW University, Jaipur‐ INDIA, Email: [email protected]

Abstract

Satellite operations at V‐band in tropical and equatorial regions are constrained as a result of attenuation from rain. THE use of v band in satellite communication can enhance the communication capacity in GEO satellite system. Up to the past few years, geostationary telecommunication satellite systems have kept taking advantage of the satellite natural wide area coverage capability in a context broadband was the major issue. Now a day’s situation has changed long term perspectives for geostationary satellites are challenged by their capability to remain competitive, in terms of capacity versus cost and supported services, it should offer wide capacity, good availability, high flexibility, and guarantee the required quality of service in a cost efficient way. The major limitation is the effect of radio‐wave propagation through the lowest layers of the atmosphere. As the operating frequency is increased, the attenuation and scintillation effects of atmospheric gas, clouds and rain become more severe. Keywords— Rain attenuation, V‐band satellite communication system, fade duration.

higher frequency bands such as Ka (20‐30 GHz), Q/V 1. INTRODUCTION (40‐50 GHz) or EHF (20‐45 GHz) bands, where Satellite communication began in October 1957 with respectively, 1 GHz, 3 GHz and 2 GHz are allocated to the launch by the USSR of a small satellite called the Fixed Satellite Service (FSS). The first commercial Sputnik I. In the 1970s and 1980s there was a drastic satellites with Ka‐band transponders are today in development of GEO satellite systems for operation, and it is expected that the congestion in international , regional, and domestic telephone lower frequency bands like Ku‐band will push new traffic and video distribution. However the demand systems into moving progressively to Ka band and, in for satellite system grew steadily through this period a longer term, to Q/V band. Depending on the type of and the available spectrum in C band was quickly mission, Ka‐Q/V band satellite could be envisaged as, occupied, leading to expansion in to Ku band. At that for example, for two way broadband access services time the video distribution was rapidly increased, so characterized by a high asymmetrical traffic, using Ku band would soon be filled, and Ka band satellite part of the Ka‐band for user access while data system would be needed to handle the expansion of distribution service could take most advantage of digital traffic, especially wide band delivery of high wider bandwidth in Q/V band. Although Ka and Q/V speed internet data. For furtherer enhancing the bands are attractive from the point of view of the communication capacity C band was introduced in amount of frequency bandwidth that the satellite can satellite communication system, when it comes to potentially use, some important limitation could address the capacity issue in satellite communication, moderate the enthusiasm of using them if specific the first technique to consider is the multi‐beam techniques were not implemented in the satellite coverage, with a high number of beams that allow a system to guarantee the capacity, the availability and high degree of frequency reuse. In order to increase the quality of service. The major limitation is the effect even more that capacity, the second step is to utilize of radio‐wave propagation through the lowest layers

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of the atmosphere. As the operating frequency is 6 Q Band 30 to 50 GHz increased, the attenuation and scintillation effects of 7 U Band 40 to 60 GHZ atmospheric gas, clouds and rain become more severe [1], the direct consequence is the need to implement 8 V Band 50 to 75 GHz high system static margins, in order to insure a minimum outage duration of the service, for a given objective of link availability. However, technology A. C‐Band limitation (on both terrestrial and space segments) combined with cost efficiency requirements refrain The use of C‐Band frequencies in the early days of the from considering fixed static margins as the only mean industry had a combination of benefits. A major one to compensate propagation impairments at high was the relative immunity to rain degradations. frequency bands, and push towards the However, the sharing of the band with terrestrial implementation of Fade Mitigation Techniques (FMT) microwave facilities meant that frequency [2]. Those techniques allow systems with rather small coordination was required for every transmit earth static margin to be designed, while overcoming in real station, and the resolution of potential interference time cloud attenuation, some fraction of rain made the avoidance of interference a key element of attenuation, scintillation, and depolarization events. establishing sites for the C‐Band earth stations. The Among those techniques, adaptive modulation/coding size of a typical C‐Band very small aperture terminal are of high interest as they allow the performance of (VSAT) antenna was in the range of 2.4 meters. individual links to be optimized, and the transmission With the attendant cost limitations of frequency characteristics to be adapted to the propagation coordination and shielding, the economics were not in channel conditions and to the service requirements favor of high volume C‐Band VSAT networks where for the given link. Those techniques are expected to the VSAT was placed on the Premises of the end user. be promising in particular in point‐to‐point service There have been alternative approaches to this scenario. The aim of this paper is to present the main problem. One of these was the use of spread issues in designing FMTs for Ka‐Q/V band satellite spectrum techniques to mitigate the interference by communication systems. The conventional design of spreading. From a technical perspective, spread the physical layer of a satcom system is outlined and spectrum techniques work well when the incoming review of FMT concepts. interference is narrowband relative to the satellite signals. This is normally not the case in the microwave 2. FREQUENCY BAND IN SATELLITE COMMUNICATION band, and this probably explains the lack of success for Equatorial. S.No. Name of Band Frequency Range Today, C‐Band is still in use because the rain immunity allows high operational availability operations, but the 1 L Band 1 to 2 GHz limitations on large VSAT networks remain. The Cable

2 S Band 2 to 4 GHz Industry recognized as far back as the early 1970s that C‐Band earth stations at the head end of their system 3 C Band 4 to 8 GHz enabled satellite delivery of programming to reach thousands of cable subscriber without the necessity of 4 Ku Band 12 to 18 GHz building more than one or two C‐Band earth stations.

5 Ka Band 26 to 40 GHz B. Ku‐Band

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The first Ku‐Band only satellite was launched in 1980.7 The major limitation is the effect of radio‐wave The Ku‐Band markets took too long to develop, and propagation through the lowest layers of the SBS went into bankruptcy, but in the intervening atmosphere. As the operating frequency is increased, years, Ku‐Band has become the mainstay of the the attenuation and scintillation effects of industry. This is primarily because the domestic bands atmospheric gas, clouds and rain become more of (11.7‐12.2 GHz)/(14.0‐14.5 GHz ) are not shared, and severe, for utilizing the V band in these conditions we do not require frequency coordination. Blanket have to adopt a technology like FMT (Fade Mitigation licensing of Ku‐Band VSAT stations has helped, and Techniques). This technique allows system with rather today, thousands of these stations are in use. The small static margin to be designed, while overcoming band does have vulnerability in rain outage, being in real time cloud attenuation, some fraction of rain substantially higher than comparable links at C‐Band. attenuation, scintillation, and depolarization events. It also brings the antenna size down into the range of Among those techniques, adaptive modulation/coding 1m to 1.8 m in diameter. are of high interest as they allow the performance of individual links to be optimized, and the transmission C. Ka‐Band characteristics to be adapted to the propagation While the adoption of Ku‐Band took several years, it channel conditions and to the service requirements did happen, and the FCC made provision for logical for the given link. Those techniques are expected to growth of the industry. The next allocation set aside be promising in Particular in point‐to‐point services. for satellite communication in 1996 was the Ka‐Band 8 at (17.7‐20.2 GHz)/ (27.5‐30.0 GHz). The first orbital As far as Q/V band is concerned, it may be used in the assignments came in 1997. In 2003 the Ka band had future either for star network feeder links or for become more popular like; pointed throughput, backbone applications. In both cases, target smaller spot beams, dynamic band width allocation availability between 99.95 % and 99.99 % of the time and smaller antennas, as key elements of Ka band could be required. For these time percentages, in a system, and envisioned better satellite broadband conventional system design, several tens of dBs would service. Today, Wild Blue is offering high speed have to be compensated with a static margin, which is Internet access using Ka‐Band technology, with not possible due to technology limitations, leading to download speeds up to 1.5 Mbps and uploads speeds low availability only, even for a European coverage. up to 256Kbps. Therefore FMTs will have the following objectives at Q/V bands: on the one hand, how to improve system D. Q/V‐Band availability? On the other hand, how to increase In 1998, the FCC took another step to ensure logical system throughput? technological development of the satellite industry, The high attenuation experienced in tropical areas is with preliminary allocations at Q/V‐Band. 16 17 In 2003 caused by significantly higher rainfall rates compared , these frequency allocations (37.5‐38.5 GHz, 40.5‐41.5 to other parts of the world. Due to the intensification GHz and 48.2‐50.2 GHz) were finalized. There is some in the use of frequency spectrum, new and existing variation in terminology as many publications refer to satellite operators in the tropics may soon have no Q‐Band as (36–46 GHz) and V‐Band as (46–56 GHz). In other alternative but to progress up to frequencies as that sense, formally, the V‐Band actually has the uplink high as the V‐band. Nonetheless, the effects of rainfall bands while the downlink bands are located at Q‐ on satellite signals at such high frequencies in the Band. However, some FCC documents refer to the tropical region have not yet been fully detailed. collective allocation as a V‐Band allocation. Additional measured data, researches, experiments

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and investigations are considered essential in order to conditions are recovered so as to limit interference in obtain more insights in this issue. Measurements clear sky conditions and therefore to optimise satellite acquired from a microwave link establishment should capacity. In the case of transparent payloads, ULPC be able to offer some initial impressions of the V‐band can prevent from reductions of satellite EIRP caused link’s characteristics in the absence of an actual by the decreased uplink power level that would occur satellite‐Earth link. The information is deemed very in the absence of ULPC. EEPC can be used for critical for future Earth space communication link transparent configuration only. Indeed, the output design and can be exploited as preliminary power of a transmitting Earth station is matched to groundwork plan for the researchers as well as up‐link or down‐link impairments. In the case of engineers. regenerative repeaters, up and down links budgets are independent, so the concept of EEPC can not exist 3. FADE MITIGATION TECHNIQUE anymore. EEPC is used to keep a constant overall Making use of Fade Mitigation Techniques involves margin of the system. As for ULPC, transmitter power adapting in real time the link budget to the is increased to counteract fade or decreased when propagation conditions through some specific more favorable propagation conditions are recovered parameters such as power, data rate, coding etc. to limit interference and optimize satellite capacity. However, this real time adaptivity has an impact not With DLPC, the on‐board channel output power is only on carrier‐to‐noise ratios but also on carrier‐to‐ adjusted to the magnitude of downlink attenuation. interference ratios and on upper layers. Both aspects DLPC aims to allocate a limited extra‐power on‐board have therefore to be carefully studied. A lot of in order to compensate a possible degradation in term publications have been written up to now on the of down‐link C/N0 due to propagation conditions on a subject [3‐7] and a review of FMTs has been realized in particular region. In this case, all Earth stations in the the framework of COST 255 [2]. same spot beam benefit from the improvement of EIRP. OBBS technique is based on active antennas, FMT layer can be divided into 4 types:‐ which allows spot beam gains to be adapted to 1. Power Control: transmitting power level propagation conditions. Actually, the objective is to fitted to Propagation impairments, radiate extra‐power, and to compensate rain 2. Adaptive waveform: fade compensated by a attenuation only on spot beams where rain is likely to more efficient modulation and coding scheme, occur. 3. Diversity: fade avoided by the use of another 3.1 Adaptive waveform less impaired Link, These FMTs could be split into Adaptive Coding (AC), 4. Layer 2: coping with the temporal dynamics Adaptive Modulation (AM) and Data Rate Reduction of the fade. (DRR). The introduction of redundant bits to the

information bits when a link is experiencing fading, 3.1 Power control allows detection and correction of errors (FEC) caused Four types of Power Control FMT can be considered: by propagation impairments and leads to a reduction Up‐Link Power Control (ULPC), End‐to‐End Power of the required energy per information bit. Adaptive Control (EEPC), Down‐Link Power Control (DLPC) and coding consists in implementing a variable coding rate On‐Board Beam Shaping (OBBS). matched to impairments originating from propagation The aim of ULPC, the output power of a transmitting conditions. Earth station is matched to uplink impairments. As Adaptive Coding, the aim of Adaptive Modulation is Transmitter power is increased to counteract fade or to decrease the required energy per information bit decreased when more favorable propagation

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required corresponding to a given BER, which to re‐ sent the message without repeating the translates into a reduction of the spectral efficiency as request. C/N0 decreases. Further reduction can be obtained by 4. CONCLUSIONS a decrease of the information data rate at constant BER. The technique is called Data Rate Reduction. The objective of this paper is to present the view of Here, user data rates should be matched to Q/V bands in satellite communication system. By using propagation conditions : nominal data rates are used V band we can increase rapidly the communication under clear sky conditions. capacity and provide the wide coverage over 3.2 Diversity terrestrial and tropical regions. It can also provide the The objective of these techniques is to re‐route good communication to marine, aviation and industry information in the network in order to avoid purpose communication. Along with providing good impairments due to an atmospheric perturbation. communication, the major limitation is the effect of Three types of diversity techniques can be considered: radio‐wave propagation through the lowest layers of site (SD), satellite (SatD) and frequency FD) diversity. the atmosphere. As the operating frequency is These techniques are very expensive as the associated increased, the attenuation and scintillation effects of equipments have to be redundant. atmospheric gas, clouds and rain become more Frequency Diversity is a technique based on the fact severe. These effects can be reduce the technique like that payloads using two different frequency bands are FMT (Fade Mitigation Technique) which have been available onboard. When a fade is occurring, links are identified in this paper: power control, adaptive re‐routed using the lowest frequency band payload, Waveform, diversity and layer 2 FMT Although less sensitive to atmospheric propagation different in their principles, these FMT are impairments. complementary and combined use of different FMT is required when high impairments have to be mitigated, 3.3 Layer 2 first of all to improve system availability, secondly to FMT at layer 2 level are techniques which do not aim limit interference and thirdly to increase system at mitigating a fade event but instead rely on the re‐ capacity. transmission of the message. Two different techniques can be envisaged at layer 2 : Automatic REFERENCES Repeat Request (ARQ) and Time Diversity (TD). With [1] Salonen E. et al.: "Modelling and calculation of ARQ, the message is sent regularly untill the message atmospheric attenuation for low‐fade‐margin reaches successfully the receiver. ARQ with a random satellite communications", ESA Journal, Vol. 16, n° 3, or predefined time repetition protocol would be an 1992, pp. 299‐317. alternate solution. Time diversity can be considered as [2] COST 255 : "Radiowave propagation modelling for a FMT that aims to re‐send the information when the new satcom services at Ku‐band and above", COST 255 state of the propagation channel allows to get Final Report, Chapter 3, ESA Publications Division, SP‐ through. In this case, most often, there is no need to 1252, March 2002. receive the data file in real time and it is acceptable for the user point of view to wait for the end of the [3] Willis MJ., Evans BG. : "Fade countermeasures at propagation event (in general some tens of minutes) Ka‐band for OLYMPUS", Int. Jour. Sat. Com., Vol. or for a decrease of traffic. This technique benefits 6, June 88, pp. 301‐311. from the use of propagation mid‐term prediction model in order to estimate the most appropriate time [4] Tartara G. : "Fade countermeasures in millimetre‐ wave satellite communications : a survey of methods

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and problems", Proc. Olympus Util. Conference, 3rd Ka‐band Utilization Conference, Sorrento, Italy, 15‐ Vienna, Austria, April 1989. 18 Sept. 1997.

[5] Gallois A.P.: "Fade countermeasure techniques for [7] Castanet L. ‐ Lemorton J. ‐ Bousquet M. : "Fade satellite communication links", Int. Symp. On Comms Mitigation techniques for New SatCom services at Ku‐ Theory and Applications, July 1993. band and above : a Review", Fourth Ka‐band Utilization Conference, Venice, 2‐4 November 1998. [6] Acosta R.J. : "Rain fade compensation alternatives for Ka‐band communication satellites",

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