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Finite Field Polynomial Multiplier with Linear Feedback Shift Register

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Finite Field Polynomial Multiplier with Linear Feedback Shift Register Tamkang Journal of Science and Engineering, Vol. 10, No. 3, pp. 253-264 (2007) 253 Finite Field Polynomial Multiplier with Linear Feedback Shift Register Che-Wun Chiou1*, Chiou-Yng Lee2 and Jim-Min Lin3 1Department of Computer Science and Information Engineering, Ching Yun University, Chung-Li, Taiwan 320, R.O.C. 2Department of Computer Information and Network Engineering, Lung Hwa University of Science & Technology, Taoyuan, Taiwan 333, R.O.C. 3Department of Information Engineering and Computer Science, Feng Chia University, Taichung, Taiwan 407, R.O.C. Abstract We will present an one-dimensional polynomial basis array multiplier for performing multiplications in finite field GF(2m). A linear feedback shift register is employed in our proposed multiplier for reducing space complexity. As compared to other existing two-dimensional polynomial basis multipliers, our proposed linear array multiplier drastically reduces the space complexity from O(m2) to O(m). A new two-dimensional systolic array version of the proposed array multiplier is also included in this paper. The proposed two-dimensional systolic array multiplier saves about 30% of space complexity and 27% of time complexity while comparing with other two-dimensional systolic array multipliers. Key Words: Finite Field, Multiplication, Polynomial Basis, Systolic Array, Cryptography 1. Introduction of implementing multiplication operations depends on the representation of the field elements. There are three Arithmetic operations in a finite field play an in- main representation types of bases over GF(2m) fields, creasingly important role in error-correcting codes [1], namely, normal basis (NB), dual basis (DB), and polyno- cryptography [2], digital signal processing [3,4], and mial basis (PB). The major advantage of the NB multipli- pseudorandom number generation [5]. Two premier ari- ers [6-8] is that the squaring of an element could be com- thmetic operations over finite fields are addition and puted simply by a cyclic shift of the binary representa- multiplication. Addition operation is simple. Multiplica- tion. Thus, the normal basis multipliers could be very ef- tion operation requires more computational time and fectively applied on performing inverse, squaring, and higher circuit complexity. Many other complex arithme- exponentiation operations. The DB multipliers [9-13] tic operations, like exponentiation, division, and multi- require less chip area than other two types. However, the plicative inversion, can be therefore performed by apply- former two multipliers need basis conversion, while the ing multiplication operations repeatedly. Hence, it is im- latter type does not [36]. The polynomial basis represen- portant in a practical sense to develop fast multiplication tation has been widely used and leads to lots of efficient algorithms for these complex arithmetic operations. In implementations of multipliers. As compared to other recent years, the realization of multiplication operation two bases multipliers, the polynomial multipliers have in finite fields has received wide attentions, and several the feature of lower design complexity and their sizes approaches have been presented [6-36]. The complexity could be easily extended to desirable scales to meet vari- ous applications due to their simplicity, regularity, and *Corresponding author. E-mail: [email protected] modularity in architecture. 254 Che-Wun Chiou et al. Numerous architectures for PB multipliers have version of the proposed algorithm is then described in been presented [14-35]. The first parallel PB multiplier Section 4. The space and time complexities are discussed was suggested by Bartee and Schneider [14]. The PB in Section 5. Finally, a brief conclusion is given in Sec- multiplication operation for GF(2m) is often accompli- tion 6. shed in two steps: polynomial multiplication and modu- lar reduction. In practical, both steps are usually com- 2. Preliminaries bined together for performance reason. Mastrovito [15, 16] firstly proposed the architecture for performing such It is assumed that the reader is familiar with the basic combinational operations. Recently, several bit-parallel concepts of finite fields. The properties of finite fields PB multipliers have been proposed for VLSI implemen- are covered in detail in [1,2]. The properties of finite tation by using some specific classes of polynomials, fields are reviewed briefly as required in the following such as trinomials [17-23], all one polynomials (AOP) paragraphs. and equally spaced polynomials (ESP) [24-26], and The finite field GF(2m) can be viewed as a vector composite fields [27,28]. Yet these architectures still space of dimension m over GF(2). Suppose that the finite have certain shortcomings as regards cryptographic ap- field GF(2m) is generated by the irreducible polynomial m-1 m plication due to their high circuit complexity and long la- P(x) = p0 +p1x+…+pm-1x +x of degree m over tency. When the size of the finite field is getting large, the GF(2), where p0 =1. Then any element A in the Galois m 2 issue of modular multipliers design requires much more field GF(2 ) can be represented as A(x) = a0 +a1x+a2x m-1 attentions. To alleviate the long latency problem, most +…+am-1x , where x is an intermediate over GF(2). existing PB multipliers employ XOR trees to minimize The basis {1, x, x2,…, xm-1} is known as standard basis time complexity. Unfortunately, these circuits are not and often refered to as polynomial basis, conventional m suitable for VLSI systems, due to the irregular and non- basis or canonical basis. Since P(x) = 0, x =p0 +p1x+ m-1 p modular structure of XOR trees. To overcome this prob- …+pm-1x can be used to reduce the high order term x , lem, Lee [22] has proposed a regular and modular PB p ³ m, to a polynomial of degree less than m. Thus, xB(x) multiplier using irreducible trinomials with the space mod P(x) can be reduced by complexity of O(m2) and the time complexity of O(m). This multiplier could be easily extended and implemen- xB(x) mod P(x) 2 m ted using VLSI technologies. = b0x + b1x +…+bm-1x mod P(x) m-1 In this article, we will present a linear parallel-in par- = bm-1p0 + (bm-1p1 + b0)x +…+(bm-1pm-1 + bm-2)x allel-out PB array multiplier using general irreducible Let polynomials with a linear feedback shift register. The B(x)(1) = xB(x) mod P(x) (1) proposed PB multiplier requires the space complexity of O(m). In order to demonstrate that our proposed multi- Therefore, xiB(x) mod P(x) can be obtained as the fol- plier is superior to other existing two-dimensional sys- lowing formula tolic array multipliers, a new two-dimensional systolic array multiplier version of such multiplier is also pre- B(x)(i) = xB(x)(i-1) mod P(x) (2) sented. We will show that the proposed two-dimensional systolic array multiplier also saves both space and time Note that B(x)(0) = B(x). complexities while comparing with other existing two- Let the PB representation of B(x)(i) be dimensional systolic array multipliers. ()im=+ + 2 + 3 ++ - 1 The organization of this paper is as follows. In Sec- Bx() bii,0 b ,1 x b i ,2 x b i ,3 x ... b im ,- 1 x , Σ£ tion 2, we will provide some basic definitions and pre- where bi, j {}0,1 for 0 j m - 1. liminaries. In Section 3, we derive the one-dimensional m 2 m-1 parallel-in parallel-out PB multiplication algorithm us- According to x = p0 + p1x + p2x +…+pm-1x , the ing general irreducible polynomials and a linear feed- relation between B(X)(i+1) and B(X)(i) is depicted as back shift register. The two-dimensional systolic array follows: Finite Field Polynomial Multiplier with Linear Feedback Shift Register 255 + BX()(1)i m-1 caSi=££å () for0 j m-1 =+ +21 ++ m- jij bbxbxbxii++1,0 1,1 i + 1,2... im +- 1, 1 i=0 = xB() X ()i The cell Uj is responsible for accumulating the coeffi- 23m- 1 =+++++xb( b x b x b x ... b- x ) ii,0 ,1 i ,2 i ,3 im , 1 cient cj (0 £ j £ m-1). Another shift register E with m =+++++234mm- 1 + bxbxi,0 i ,1 bx i ,2 bx i ,3... b im ,-- 2 x b im , 1 x bits, Em-1Em-2…E1E0, is used for storing and rotating =+++++234 m-1 A(X) and is defined as follows: bxbxii,0 ,1 bx i ,2 bx i ,3... b im , -2 x +++++21m- bppxpxpxim,1--( 0 1 2 ... m 1 ) Em-1(i+1) = E0(i), and =++++ 2 £ £ bpbbpxbbpxim,10--()() i ,0,11 im i ,1,12 im - Ej(i+1) = Ei+1(i) for 0 j m-2. ++ + m-1 ... (bbpxim,2--- im ,1 m 1 ) The notation E (i) denotes the value of the bit E of the (3) j j register E at clock cycle i. Both registers S and E are initially loaded in parallel 3. The Proposed Multiplier with Linear with B(X) and A(X) in the following manners: Feedback Shift Register = Sbjj(0) , and m =££ Let A(x) and B(x) be any two elements in G(2 ), and E(jj0,for0jm-1 ) a the element C(x) be the multiplication of A(x) and B(x) in GF(2m), i.e., C(x) = A(x) ´ B(x) mod P(x). Referring to The following example is used to describe the hard- the Horner’s rule, the product C(x) = A(x) ´ B(x) mod P(x) ware implementation of the proposed linear array multi- can be obtained: plier structure. Cx()=´ Ax () Bx ()mod() Px Example 1: =+ +23 + An example with an irreducible polynomial P(X) = 1 aBxaxBxaxBxaxBx01() () 2 () 3 () 3 4 8 m-1 +x+x +x +x is given here to describe the hardware ++...axBx- ( ) m 1 implementation of the proposed array multiplier.
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