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TW2965 Datasheet DATASHEET FN8340 TW2965 Rev. 1.00 4-CH WD1 (960H)/D1 Compatible Video Decoders Nov 21, 2013 and Audio Codecs with Video Encoder Features Video Decoder Audio Codecs WD1 (960H) and D1 compatible video decoding Integrated five audio ADCs processing and one operation and each channel is programmable audio DAC NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N Provides multi-channel audio mixed analog output combination), PAL (60) support with automatic Support I2S/DSP Master/Slave interface for format detection record output and playback input Software selectable analog inputs allows any of 2 PCM 8/16-bit and u-Law/A-Law 8-bit for audio CVBS per one video ADC word length Built-in analog anti-alias filter Programmable audio sample rate that covers Four 10-bit ADCs and analog clamping circuit for popular frequencies of 8/16/32/44.1/48kHz CVBS input Fully programmable static gain or automatic gain Miscellaneous control for the Y channel Two-wire MPU serial bus interface Programmable white peak control for CVBS Integrated clock PLL for 144/108MHz clock channel output 4-H adaptive comb filter Y/C separation Embedded video encoder PAL delay line for color phase error correction Power save and Power down mode Image enhancement with peaking and CTI Low power consumption Digital sub-carrier PLL for accurate color decoding Single 27MHz crystal for all standards and both Digital Horizontal PLL for synchronization WD1 and D1 format processing and pixel sampling 3.3V tolerant I/O Advanced synchronization processing and sync 1.0V/3.3V power supply detection for handling non-standard and weak signal 128-pin LQFP package Programmable hue, brightness, saturation, contrast, sharpness Automatic color control and color killer ITU-R 656 like YCbCr(4:2:2) output or time multiplexed output with 36/72/144MHz for WD1 or 27/54/108MHz for D1 format FN8340 Rev. 1.00 Page 1 of 130 Nov 21, 2013 TW2965 Function Description X VIN1A 4H Comb e VD1[7:0] 6 c U AADDCC 5 Video Decoder a f 6 M VD2[7:0] r VIN1B . e T t VD3[7:0] B n I AIN1 AADDCC Decimation Filter VD4[7:0] e MPP1 c P a X VIN2A f MPP2 P 4H Comb r U ADC ADC e M Video Decoder t M MPP3 VIN2B n I MPP4 AIN2 AADDCC Decimation Filter r L CLKPO o L t k P a c r XTO k o e l c n X o VIN3A C XTI l 4H Comb e U AADDCC C Video Decoder G VIN3B M CLKNO e c t SCLK a s AIN3 AADDCC Decimation Filter f r o e SDAT H t n I IRQ VIN4A X 4H Comb U AADDCC Video Decoder ACLKR VIN4B M ASYNR e ADATR AIN4 AADDCC Decimation Filter c a f S ADATM r 2 e I t ACLKP n I ASYNP AIN5 Decimation Filter ADC ADATP AOUT DAC Interpolation Filter ENCLK Digital Video VYOUT DAC Encoder ED[7:0] FIGURE 1. TW2965 BLOCK DIAGRAM FN8340 Rev. 1.00 Page 2 of 130 Nov 21, 2013 TW2965 Ordering Information PART PART PACKAGE PKG. NUMBER MARKING (Pb-free) DWG. # TW2965-LA2-CR TW2965 LA2-CR 128 Lead LQFP (14mmx20mm) Q128.14X20F (Note 1) NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8340 Rev. 1.00 Page 3 of 130 Nov 21, 2013 TW2965 Table of Contents Video Decoder ............................................................................. 1 0x00(CH1)/0x10(CH2)/0x20(CH3)/0x30(CH4) – Video Audio Codecs .............................................................................. 1 Status Register................................................................... 62 Miscellaneous .............................................................................. 1 0x01(CH1)/0x11(CH2)/0x21(CH3)/0x31(CH4) – Function Description .................................................................. 2 BRIGHTNESS Control Register ........................................ 62 Ordering Information .................................................................. 3 0x02(CH1)/0x12(CH2)/0x22(CH3)/0x32(CH4) – Table of Contents ........................................................................ 4 CONTRAST Control Register ........................................... 62 Pin Diagram ................................................................................. 6 0x03(CH1)/0x13(CH2)/0x23(CH3)/0x33(CH4) – Analog Video/Audio Interface Pins .......................................... 7 SHARPNESS Control Register ......................................... 63 Digital Video/Audio Interface Pins ........................................... 8 0x04(CH1)/0x14(CH2)/0x24(CH3)/0x34(CH4) – Chroma System Control Pins ................................................................ 9 (U) Gain Register ............................................................... 63 Power and Ground Pins .......................................................... 9 0x05(CH1)/0x15(CH2)/0x25(CH3)/0x35(CH4) – Chroma Parametric Information ............................................................10 (V) Gain Register ............................................................... 63 ESD Rating ............................................................................10 0x06(CH1)/0x16(CH2)/0x26(CH3)/0x36(Ch4) – Hue AC/DC Electrical Parameters ................................................10 Control Register ................................................................. 64 Serial Host Interface Timing ..................................................13 0x07(CH1)/0x17(CH2)/0x27(CH3)/0x37(CH4) – Cropping Serial Host Interface Timing Diagram ...................................13 Register, High .................................................................... 64 CLKPO and Video Data Timing ............................................14 0x08(CH1)/0x18(CH2)/0x28(CH3)/0x38(CH4) – Vertical Digital Serial Audio Interface Timing .....................................15 Delay Register, Low ........................................................... 64 Analog Audio Parameters......................................................16 0x09(CH1)/0x19(CH2)/0x29(CH3)/0x39(CH4) – Vertical Video Decoder Overview ...................................................17 Active Register, Low .......................................................... 64 Analog Front End ...................................................................17 0x0A(CH1)/0x1A(CH2)/0x2A(CH3)/0x3A(CH4) – Sync Processor ......................................................................17 Horizontal Delay Register, Low ......................................... 65 Y/C Separation .......................................................................17 0x0B(CH1)/0x1B(CH2)/0x2B(CH3)/0x3B(CH4) – Color Demodulation ...............................................................17 Horizontal Active Register, Low ........................................ 65 Automatic Chroma Gain Control ........................................17 0x0C(CH1)/0x1C(CH2)/0x2C(CH3)/0x3C(CH4) – Color Killer ..........................................................................18 Macrovision Detection ....................................................... 65 Automatic standard detection ............................................18 0x0D(CH1)/0x1D(CH2)/0x2D(CH3)/0x3D(CH4) – Chip Component Processing .........................................................18 STATUS II .......................................................................... 66 Sharpness...........................................................................18 0x0E(CH1)/0x1E(CH2)/0x2E(CH3)/0x3E(CH4) – Standard Color Transient Improvement ............................................18 Selection ............................................................................. 66 Video Output Format .............................................................19 0x0F(CH1)/0x1F(CH2)/0x2F(CH3)/0x3F(CH4) – Standard Channel ID ..........................................................................19 Recognition ........................................................................ 67 Video Loss Output ..............................................................19 0x56(CH1/CH2/CH3/CH4) – HASYNC ............................ 67 ITU-R BT.656 like Format ..................................................20 0x57(CH1)/0X58(CH2)/0X59(CH3)/0X5A(CH4) – HBLEN68 Two Channel ITU-R BT.656 Time-multiplexed Format with 0x68(CH1/CH2/CH3/CH4) – HZOOM_HI ........................ 68 54/72MHz ...........................................................................21 0x69(CH1)/0X6A(CH2)/0X6B(CH3)/0X6C(CH4) – Four Channel 960H/720H Time-division-multiplexed HZOOM_LOW ................................................................... 68 Format with 108/144MHz ...................................................22 0xA0(CH1)/0xA1(CH2)/0xA2(CH3)/0xA3(CH4) – NT50 .. 68 Output Enabling Act ...........................................................23 0xA4(CH1)/0xA5(CH2)/0xA6(CH3)/0xA7(CH4) – ID Video Output Channel Selection........................................23 Detection Control ............................................................... 69 Extra Sync Output ..............................................................23 0xAA(CH1/CH2/CH3/Ch4) – Video AGC Control ............ 69 Audio Codec ...........................................................................26 0xAB(CH1)/0xAC)CH2)/0XAD(CH3)/0XAE(CH4) – Video Audio Clock Master/Slave mode .......................................28 AGC Control ......................................................................
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