Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques
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Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques Christos Vezyrtzis Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences COLUMBIA UNIVERSITY 2013 ©2013 Christos Vezyrtzis All Rights Reserved Abstract Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques Christos Vezyrtzis The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many appli- cations. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of “adaptivity” or “adaptability.” Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main con- tribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real- time delay line. Adaptive granularity brings about a significant improvement in the line’s power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP’s power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line’s granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware. Contents List of Figures vii List of Tables xvi 1 Introduction 1 1.1 Overview of classical DSP systems . .2 1.1.1 Structure and operation . .2 1.1.2 Signal encodings and formats . .4 1.2 Limitations of classical DSPs . .5 1.2.1 Effect of reduced signal amplitude . .6 1.2.2 Power waste during quiet inputs . .7 1.2.3 Dependence of the frequency response on the clock . .8 1.2.4 Limitation in the DSP resolution . .9 1.3 Research focus . 11 1.3.1 Research challenges . 12 1.4 Asynchronous design methodologies for continuous-time DSPs . 13 1.4.1 A CT DSP chip for multiple digital formats and sample rates . 15 i 1.4.2 Adaptive granularity management for delay lines . 17 1.5 Adaptive DSPs: level-crossing and companding DSPs . 19 1.5.1 A method for high-resolution processing of level-crossing encoded signals 20 1.5.2 Companding DSPs for MPEG-encoded audio . 21 1.6 Contribution of this thesis . 22 1.7 Structure of the thesis . 24 2 Background 26 2.1 Continuous time (CT) DSPs . 26 2.1.1 Introduction: CT DSP theory . 27 2.1.2 CT DSP implementations: previous work . 29 2.1.3 Limitations of previous CT DSP prototypes . 31 2.2 Asynchronous system design . 33 2.2.1 Asynchronous communication protocols . 35 2.2.2 Asynchronous data encoding . 36 2.2.3 Asynchronous controllers and burst-mode machines . 40 3 A Method for Processing Level-Crossing-Encoded Signals 42 3.1 Uniform sampling vs. level-crossing sampling . 43 3.2 Motivation for use of LCS DSPs . 46 3.3 Interpolation in LCS processing . 47 3.4 Method for processing LCS-encoded signals . 50 3.4.1 Basic principle . 51 3.4.2 Proper sampling and reconstruction . 52 ii 3.4.3 Implementation issues . 55 3.5 Simulation results . 60 3.6 Conclusions . 64 4 Designing a Modular and Scalable CT DSP: Initial Considerations 66 4.1 Overview of the CT digital FIR filter . 67 4.2 Data movement and storage . 69 4.2.1 Global storage . 70 4.2.2 Local (per-segment) storage . 72 4.3 Micro-architecture of the timing path of delay segments . 73 4.3.1 Serial vs. parallel structure . 74 4.3.2 Delay cell protocol: 2-phase vs. 4-phase . 76 4.4 Arithmetic blocks: multipliers and multi-way adder . 77 4.4.1 Asynchronous multiplier . 78 4.4.2 Multi-way adder . 78 4.5 Internal arithmetic considerations . 81 4.6 On-chip tuning . 82 4.7 Summary . 84 5 A CT DSP Chip with Open Input Format 86 5.1 Contribution of the designed chip . 87 5.2 Basic asynchronous cells . 88 5.3 CT digital FIR chip overview . 89 5.4 Delay line: implementing the timing path . 92 iii 5.4.1 Baseline delay cell . 93 5.4.2 Even and odd delay cells . 95 5.4.3 Operation modes and associated trade offs . 97 5.5 Delay segment: SRAM memory for local data storage . 99 5.6 FIR tap multiplier . 100 5.6.1 Improving on an earlier design . 102 5.7 Multi-way adder . 104 5.8 On-chip automatic tuning . 106 5.9 Tuning interface and FIR-length programming . 108 5.10 Design challenges . 110 5.11 Summary . 111 6 Measurement Results for the CT DSP Chip Prototype 112 6.1 Implementation details . 113 6.2 Test setup . 113 6.3 Frequency response measurements . 116 6.4 Power measurements . 118 6.5 Effect of automatic tuning . 122 6.6 Additional measurements . 122 6.6.1 Absence of aliasing . 123 6.6.2 Delay line operation modes . 124 6.6.3 Types and range of frequency responses . 125 6.7 Comparison to other DSP systems . 126 iv 6.8 Comparison to other reported results . 130 6.9 Summary . 131 7 A Methodology for Designing Real-Time Delay Lines with Dynamically-Adaptive Gran- ularity 132 7.1 Motivation for adaptive granularity . 134 7.1.1 Role of delay lines . 134 7.1.2 Prior designs and limitations . 135 7.2 Contribution: adaptive granularity delay lines . 136 7.3 Simplified view of an adaptive granularity delay line . 138 7.4 Bi-modal adaptive delay line: original approach . 141 7.4.1 Delay line . 142 7.4.2 Mode controller . 145 7.4.3 Asynchronous control line . 151 7.5 MTBF-type bug in the mode controller . 153 7.6 Bi-modal delay line with MTBF enhancement . 156 7.6.1 Mode controller . 158 7.7 Methodology extension for multiple granularity settings: a tri-modal delay line example . 163 7.7.1 Delay line . 164 7.7.2 Mode controller . 166 7.7.3 Asynchronous control line . 172 7.8 Simulation results . ..