WELCOME FROM THE MAYOR OF ORANGE COUNTY

2 WELCOME FROM 67th ECTC GENERAL AND PROGRAM CHAIRS

On behalf of the Program Committee and Executive Committee, it is our pleasure to welcome you to the IEEE 67th Electronic Components and Technology Conference (ECTC), held at the beautiful Walt Disney World Swan & Dolphin Resort, Lake Buena Vista, Florida, from May 30 to June 2, 2017. All ECTC meetings and events will be taking place in the Dolphin building of the resort. This premier international conference of the global microelectronic packaging industry is sponsored by the IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society. The ECTC Program Committee has selected 335 papers that will be presented in 36 oral sessions and five interactive presentation sessions, including one interactive presentation session exclusively featuring papers by student authors. The oral sessions will feature selected papers on key topics such as flip chip packaging, 3D/TSV technologies, wafer level packaging, design for RF performance and signal/power integrity, thermal and mechanical modeling, optoelectronics packaging, and materials and reliability. Interactive presentation sessions will showcase papers in a format that encourages more in-depth discussion and interaction with authors about their work. Authors from 22 countries are expected to present their work at the 67th ECTC, covering ongoing technological challenges with established disciplines or emerging topics of interest for our industry, such as additive manufacturing, heterogeneous integration, and flexible and wearable electronics. ECTC will also feature panel and special sessions with industry experts covering a number of important and emerging topic areas. On Tuesday, May 30 at 10 a.m., Vikas Gupta and Pradeep Lall will chair a session on “Material and Package Reliability Needs/Challenges for Harsh Environments.” That same day at 2 p.m., Bing Dang will chair a panel session on “Flexible Hybrid Electronics – Electronics Outside the Box,” where a panel of experts will discuss how innovation in device integration and packaging will bring together thinned silicon die with printed components to deliver electronics that conform to the shape of the human body and vehicles. Tuesday evening will also include the ECTC Panel Session at 7:30 p.m. on “Panel Fan-Out Manufacturing: Why, When, and How?” chaired by CPMT President Jean Trewhella and Young Gon Kim. Babak Sabi, Corporate Vice President and Director of Assembly and Test Technology Development, Intel Corporation, will be giving the invited keynote talk on “Advanced Packaging Opportunities and Challenges” at the ECTC Luncheon on Wednesday, May 31. Later that day and continuing to build on the success of the first-ever CPMT Women’s Panel and Reception held at the 65th ECTC two years ago, this year’s conference will also feature a panel discussion chaired by Kitty Pearsall on Wednesday, May 31, at 6:30 p.m. on “Emotional Intelligence (EI) – Link to Successful Leadership,” with participation from distinguished women leaders and technologists in our industry. All conference attendees are invited. Also on Wednesday at 7:30 p.m., Luke England will chair the ECTC Plenary Session titled “Packaging for Autonomous Vehicle Electronics,” featuring key technologists sharing their views on the evolutionary requirements for packaging and reliability challenges to support widespread implementation of self-driving vehicles on the road. On Thursday, June 1 at 8 p.m., the CPMT Seminar titled “3D Printing Tools, Technologies and Applications,” will be moderated by Venkatesh Sundaram and Yasumitsu Orii from the High-Density Substrates & Boards Technical Committee of the CPMT Society. Supplementing the technical program, ECTC also offers several Professional Development Courses (PDCs) and Technology Corner exhibits. Co-located with the IEEE ITherm Conference this year, the 67th ECTC will offer 18 PDCs, organized by the PDC Committee chaired by Kitty Pearsall. The PDCs will take place on Tuesday, May 30, and are taught by distinguished experts in their respective fields. The Technology Corner will showcase the latest technologies and products offered by leading companies in the electronic components, materials, packaging, and services fields. More than 100 Technology Corner exhibits will be open starting at 9 a.m. on Wednesday and Thursday. ECTC also offers attendees numerous opportunities for networking and discussion with colleagues during coffee breaks, daily luncheons, and nightly receptions. Whether you are an engineer, a scientist, a manager, a student, or an executive, ECTC offers something unique for everyone in the microelectronics packaging and components industry. We would like to take this opportunity to thank all our sponsors, exhibitors, authors, speakers, PDC instructors, session chairs, program committee members, as well as all the volunteers who have helped to make the 67th ECTC another resounding success. Once again, thank you for being a part of the 67th ECTC.

Henning Braunisch Mark D. Poliks General Chair Program Chair Intel Corporation Binghamton University

3 WELCOME FROM ECTC SPONSORING ORGANIZATION

On behalf of CPMT, it is my great pleasure and • To encourage diversity, networking, and professional development, CPMT privilege to welcome you to the 67th ECTC will host a Women’s Panel and Reception Wednesday at 6:30 p.m. on in Lake Buena Vista, Florida at the spectacular “Emotional Intelligence – Link to Successful Leadership,” chaired by Kitty Walt Disney World Swan & Dolphin Resort! Pearsall. All conference attendees are invited. CPMT will continue the women’s networking tables during the Wednesday and Thursday luncheons. The ECTC held its opening night 66 years ago and it hasn’t missed a single year yet! Today, • On Thursday, June 1, CPMT will sponsor an award luncheon session to ECTC has become the premier international present several prestigious IEEE and CPMT awards. conference where professionals not only get • After the traditional Gala reception on Thursday evening the CPMT High- a close-up look at every side of our industry, Density Substrates & Boards technical committee will host the seminar “3D but also share research and development in Printing Tools, Technologies and Applications,” moderated by Venkatesh technological breakthroughs across a wide Sundaram and Yasumitsu Orii. range of semiconductor packaging, electronics devices, design, materials, Friday will feature sessions on topics that range from the reliability of fan-out manufacturing, and modeling. WLP, automotive electronics and power module packaging to processing for The CPMT Society is proud to be a sponsor of ECTC and present these 3D integration – all showing cutting edge advances in these critical areas. program highlights: Lastly I would like to take this opportunity to thank our dedicated volunteers on the ECTC program committee for their hard work over the past year. • Opening Day: Tuesday, May 30, in addition to the ever popular Professional Also, appreciation goes to the session chairs, authors, speakers, and exhibitors Development Courses there will be two special sessions: “Material and who are instrumental to making the 67th ECTC a great success. As always I Package Reliability Needs/Challenges for Harsh Environments” chaired by look forward to the impact all these technical and networking events will make Vikas Gupta and Pradeep Lall and “Flexible Hybrid Electronics – Electronics on the CPMT Society, our industry, and our members. Outside the Box” chaired by Bing Dang. In the evening I will co-chair the ECTC CPMT Panel Session together with Young Gon Kim at 7:30 p.m. Here’s to four fast paced days of in-depth analysis, peer debate, and network on “Panel Fan-Out Manufacturing: Why, When, and How?” Tuesday’s expansion! program highlights the breadth and depth that ECTC delivers each year. Jean Trewhella, President, IEEE CPMT Society CONFERENCE POLICIES AND GUIDELINES

Badges Conference attendees MUST wear the official conference badge to be admitted to all training courses, sessions, meals, Technology Corner exhibits and all conference sponsored social functions. Medical Services For emergency medical services, locate any hotel phone, whether in your room or elsewhere in the hotel, and follow its directions for emergencies. Hotel “house” phones have been placed throughout the hotel and conference area for your convenience. If no phone can be located, please locate the nearest hotel staff or ECTC staff for assistance with your emergency. The closest available hotel staff person may be at the front desk. Personal Property The hotel’s safety deposit box is available for storing your valuables; particularly cash and jewelry. If there is a mini-safe in your room, you should consider using it. Smoking Policy Smoking is NOT permitted in the hotel. Please follow hotel policies and signs regarding this. Smoking is also NOT permitted at any ECTC activities including, but not limited to, functions, events, sessions, and / or seminars. Thank you for your consideration and cooperation. Recording presentations via photos or video is prohibited.

ECTC Mobile App ECTC is pleased to announce that a free mobile app is available again this year. The app provides information on schedules for our technical program and PDCs as well as exhibitors, sponsors, and general conference information and venue maps. The app also features tools to set your schedule so you don’t miss presentations important to you, social interaction functions, and the ability to provide ratings on presentations that are used in selecting candidates for best paper awards. The app is available for iOS and Android devices from their respective app stores by searching “2017 ECTC”. Look for login and password information on signage at ECTC! All Oral Session Paper Ratings this year will be received only through this Mobile App.

4 TABLE OF CONTENTS

Conference Policies & Guidelines ...... 4 Session 2: TSV Process, Characterization and Applications ...... 10 Session 27: Advances in Thermal Compression and Wirebonding . . . . .18 ECTC Mobile App Information ...... 4 Session 3: Flip Chip Assembly ...... 10 Session 28: Advanced Materials for Reliability Improvement ...... 19 ECTC Luncheon Speaker ...... 5 Session 4: Advanced Substrates and Integrated Devices ...... 11 Session 29: Warpage Control and Substrates ...... 19 iNEMI Committee Meetings ...... 5 Session 5: Emerging Sensors and Microsystems Packaging ...... 11 Session 30: RF Components and Module Integration ...... 19 CPMT Heterogeneous Integration Technology Roadmap Workshop ...... 5 Session 6: 5G, mmWave and Beyond ...... 11 Session 31: Auto Electronics Packaging and Power Modules ...... 20 Registration ...... 6 Session 7: Fan-Out Packaging Materials and Passives ...... 12 Session 32: Reliability Challenges in 2.5D/3D Interconnect ...... 20 PDC Instructors’ and Proctors’ Breakfast ...... 6 Session 8: Singulation Process Developments ...... 12 Session 33: Advanced Bonding and Soldering Technology ...... 20 Session Chairs & Speakers Breakfast ...... 6 Session 9: Fine Pitch Flip Chip Process Technologies ...... 12 Session 34: Waveguide Devices and Chip-to-Fiber Packaging ...... 21 Speaker Prep Room ...... 6 Session 10: Harsh Environment Interconnect Reliability ...... 13 Miscellaneous Information ...... 6 Session 11: Mechanical Modeling and Characterization of Interposers and Session 35: Thermomechanical and Thermal Characterization ...... 21 Luncheons ...... 6 Interconnections ...... 13 Session 36: Advances in Signal and Power Integrity ...... 21 ECTC Special Session ...... 7 Session 12: Advanced Optical Components and Modules ...... 13 Session 37: Interactive Presentations 1 ...... 22 Applied Reliability Special Session ...... 7 Session 13: Interconnect Advances in FO & WLP ...... 14 Session 38: Interactive Presentations 2 ...... 22 CPMT Women’s Panel & Reception ...... 7 Session 14: Heterogeneous Integration ...... 14 Session 39: Interactive Presentations 3 ...... 23 ECTC Panel Session ...... 7 Session 15: Flip Chip and Embedding in Substrates ...... 14 Session 40: Interactive Presentations 4 ...... 23 ECTC Plenary Session ...... 7 Session 16: 3D Materials and Processing ...... 15 Session 41: Student Interactive Presentations ...... 23 CPMT Seminar ...... 7 Session 17: Materials and Processes for Flexible and Wearable Devices . . 15 Technology Corner Booth Layout ...... 24 Professional Development Courses ...... 8 Session 18: Warpage, Electromigration and Mechanical Characterization . .15 Technology Corner Exhibits ...... 25-39 ECTC Student Reception ...... 8 Session 19: Recent Advances in FOWLP Technology ...... 16 ECTC Executive Committee ...... 40 General Chair’s Speaker Reception ...... 8 Session 20: MEMS and Sensor Technologies ...... 16 ECTC Program Committee ...... 40-42 Technology Corner Reception ...... 8 Session 21: 3D Cu-Cu and Micro Bump Bonding Technologies ...... 16 68th ECTC Call for Papers ...... 43 67th ECTC Gala Reception ...... 8 Session 22: Solder Joint & Interconnect Reliability, Characterization Continuing Education Units ...... 8 and Modeling ...... 17 Conference Sponsors ...... 44-45 2016 ECTC Best Paper Awards ...... 9 Session 23: Additive Manufacturing and Panel-Level Packaging ...... 17 Media Sponsors ...... 45 Texas Instruments Best Student Paper ...... 9 Session 24: Novel Methods to Assess Reliability ...... 17 Hotel Layout ...... 46 Committee Meetings ...... 9 Session 25: Characterization and Reliability of Fan-Out & WLP ...... 18 68th ECTC Dates and Location ...... 46 Session 1: Fan-Out Packaging Process and Integration ...... 10 Session 26: 3D Integration Processing and Reliability ...... 18 Conference at a Glance ...... 47

Conference organizers reserve the right to cancel or change this program without prior notice.

ECTC Luncheon IEEE CPMT Heterogeneous Keynote Speaker Integration Technology Roadmap Wednesday, May 31, 2017 12:00 Noon Workshop Northern Hemisphere D-E Tuesday, May 30, 2017 • 8:00 a.m. - 5:00 p.m. Advanced Packaging Opportunities Europe 4, Lobby Level and Challenges Our Industry has reinvented itself through multiple disruptive changes in technologies, products and markets. With the rapid migration of logic, memory and applications to Presenter: Babak Sabi, the cloud infrastructures, the internet of things (IoT) to internet of everything (IOE), smart devices every where, and autonomous automotive, the pace of innovation is Corporate Vice President and Director increasing to meet these challenges. of Assembly and Test Technology The Heterogeneous Integration Technology Roadmap (HIR), is sponsored by the Development, Intel Corporation IEEE CPMT Society, the Electron Devices Society (EDS), and Photonics Society together with SEMI and ASME EPPD. It will address the future directions of Industry reliance on advanced packaging has been accelerating over the last heterogeneous integration technologies and applications serving the future markets few years. This trend is expected to continue in the future. Heterogeneous and applications, so very crucial to our societies’ fields of interest and to our industries integration of multiple chips in a package supports Moore’s Law scaling and is and academic and research communities. In addition to HIR, two other roadmaps driving many challenges in package interconnect scaling, design environment, are under development within IEEE: International Technology Roadmap for Wide Band-Gap Semiconductors (ITRW) sponsored by the IEEE Power Electronics optical integration, electrical/thermal performance, and test. Babak Sabi, Society (PELS), and International Technology Roadmap for Devices & Systems Corporate Vice President and Director of Assembly and Test Technology (IRDS), an IEEE Standards Association Industry Connection Program sponsored by Development at Intel Corporation, will address future challenges and the Rebooting Computing Initiative. Collaboration is underway to harmonize across opportunities for advanced multi-chip packaging. the three roadmaps. This HIR is our technology roadmap. The workshop will be held at the 2017 ECTC Since 2009, Babak has been responsible for Intel’s packaging, assembly process, conference. We invite all the ECTC participants to attend this important working packaging materials, enabling technology, and test technology development. session for our profession and for our industry. The workshop is open to all. Prior to leading Assembly and Test Technology Development, Babak led the Registration is not necessary. There is no fee for attendance. Corporate Quality Network within Intel’s Technology and Manufacturing Group from 2002 to 2009. He also led a company-wide network of quality and reliability organizations responsible for product reliability, customer satisfaction, and quality business practices. Previously, Babak managed technology iNEMI Technical & Research development quality and reliability, and was responsible for silicon technology Committee Meeting certification, assembly, test, and board processes. Babak joined Intel in 1984, the same year he received his Ph.D. in solid state electronics from The Ohio Tuesday, May 30, 2017 State University. 9:30 a.m. - 5:30 p.m. • Oceanic 1- Lobby Level By Invitation Only

5 REGISTRATION, RECEPTIONS AND GENERAL INFORMATION

Registration Professional Development Course Instructors Breakfast ECTC registration will be open at the ECTC Registration Desk PDC Instructors and Proctors are required to attend a briefing located in the Walt Disney World DOLPHIN Resort, Conference breakfast. Center, Lobby Level, outside of Australia 3. 7:00 a.m. Tuesday – PDC Instructors Monday, May 29, 2017 • 3:00 p.m. – 5:00 p.m. and Proctor Briefing Tuesday, May 30, 2017 • 6:45 a.m. – 8:15 a.m.* (Room Location: Asia 1, Lobby Level) (AM PD Courses & Special Session only)* Session Chairs and Speakers Breakfast Tuesday, May 30, 2017 • 8:15 a.m. – 5:00 p.m. Session Chairs and speakers are required to attend a complimentary (All conference attendees) continental breakfast on the morning of their sessions/presentations. Wednesday, May 31, 2017 • 6:45 a.m. – 4:00 p.m. At this time, presentations will be transferred to the conference PC, Thursday, June 1, 2017 • 7:30 a.m. – 4:00 p.m. which is loaded with Microsoft Windows and Office. Friday, June 2, 2017 • 7:30 a.m. – 12:00 Noon 7:00 a.m. Wednesday thru Friday *The above schedule for Tuesday will be vigorously enforced (Room Location: Northern Hemisphere E 3 & 4, 5th floor) to prevent students from being late for their courses. Please Speaker Prep Room make sure to take advantage of the 6:45am start time on Speakers should prepare and review their digital presentations within Tuesday, May 30 as registration becomes very congested prior the allotted times below: to the start of morning Professional Development Courses. Door Registration Fees 7:00 a.m. – 5:00 p.m., Tuesday – Friday Door Registration with Proceedings on USB drive (Room Location: Europe 2, lobby level) IEEE Member JOINT Registration (It is extremely important to assure that your presentation, presentation (full ECTC + ITHERM conference) ...... $1100 software and computer work flawlessly with the digital projector provided.) IEEE Member Full Registration ...... $835 IEEE Member Speaker / Session Chair ...... $730 IEEE Member One Day ...... $550 IEEE Member Speaker One Day ...... $415 Exhibit Booth Attendant ...... $0 MISCELLANEOUS INFORMATION Non-Member JOINT Registration (full ECTC + ITHERM conference) ...... $1310 Hotel Concierge Non-Member Full Registration ...... $1025 The Hotel Concierge, located in the hotel lobby, can direct you to Non-Member Speaker / Session Chair ...... $730 various types of entertainment or restaurants, or give suggestions for Non-Member One Day ...... $550 that special night out. The Concierge can help to make your visit and Non-Member Speaker One Day ...... $415 conference experience a memorable one! Exhibit Booth Attendant ...... $0 Message Center Student ...... $315 Student Speaker ...... $315 Please use the hotel switchboard or the ECTC Registration Desk, located on the lobby level in the Australia 3 Foyer, to leave and pickup Exhibits Only ...... $25 messages. The hotel phone number is +1 (407) 934-4000. Tuesday Professional Development Courses IEEE Members and Non-Members Press Room Tuesday AM or PM Course with Luncheon ...... $500 Press Interviews will be scheduled on an as-requested basis. To Tuesday All-Day Courses with Luncheon ...... $710 coordinate an interview with conference leadership or presenting Tuesday Student All-Day Courses with Luncheon ...... $130 technical experts please contact ECTC Publicity Chair, Eric Perfecto, at Extra Luncheon Tickets for Each Day ...... $65 [email protected] or +1 (845) 475-1290. Extra Proceedings with Registration ...... $100

LUNCHEONS

Tuesday, May 30, 2017 Wednesday, May 31, 2017 Thursday, June 1, 2017 Friday, June 2, 2017 12:00 Noon 12:00 Noon 12:00 Noon 12:00 Noon (Northern Hemisphere D / (Northern Hemisphere (Northern Hemisphere (Northern Hemisphere DE Corridor, 5th floor) D & E, 5th floor) D & E, 5th floor) D & E, 5th floor) The Electronic Components The Electronic Components and The IEEE Components, Packaging The ECTC Program Chair will and Technology Conference Technology Conference will sponsor and Manufacturing Technology sponsor a luncheon for conference will sponsor a luncheon for all a luncheon for conference attendees. Society will sponsor a luncheon for attendees. You won’t want to Professional Development Courses Best and Outstanding Papers will be conference attendees. The CPMT miss it! attendees, proctors and PDC awarded. The guest speaker will be awards will be presented. committee members. Babak Sabi, Corporate Vice President There will be a raffle for attendees. and Director of Assembly and Test Technology Development, Intel Corporation.

6 2017 ECTC SESSIONS & SEMINARS – Open to all conference attendees

2017 APPLIED RELIABILITY 2017 CPMT WOMEN’S PANEL SPECIAL SESSION AND RECEPTION Material and Package Reliability Emotional Intelligence (EI) – Link Needs/Challenges for Harsh to Successful Leadership Environments Wednesday, May 31, 2017 Tuesday, May 30, 2017 6:30 p.m. – 7:30 p.m. 10:00 a.m. – 11:30 a.m. Southern Hemisphere 1V, 5th Floor Southern Hemisphere 1, 5th Floor Chair: Kitty Pearsall - Boss Precision, Inc. Chairs: Vikas Gupta - Texas Instruments, Inc. Speakers: and Pradeep Lall - Auburn University 1. Joanne Martin, JLM Consulting, LLC and former Vice President, IBM Corporation Speakers: 2. Rozalia Beica, Global Director New Business 1. Robert Smith, Boeing Research & Technology Development, The Dow Chemical Company 2. Przemyslaw Jakub Gromala, Bosch 3. Tanja Braun, Deputy Group Manager, 3. Steve Dunford, Schlumberger Fraunhofer Institute for Reliability and 4. Anton Z. Miric, Heraeus Deutschland GmbH & Co. KG Microintegration IZM 5. Nancy Stoffel, General Electric 6. Varughese Mathew, NXP Semiconductors

2017 ECTC SPECIAL SESSION 2017 ECTC PLENARY SESSION Flexible Hybrid Electronics – Packaging for Autonomous Electronics Outside the Box Vehicle Electronics Tuesday, May 30, 2017 Wednesday, May 31, 2017 2:00 p.m. – 3:30 a.m. 7:30 p.m. – 9:00 p.m. Southern Hemisphere 1, 5th Floor Southern Hemisphere 11 & 111, 5th Floor Chair: Bing Dang - IBM Corporation Chair: Luke England - GLOBALFOUNDRIES Speakers: Speakers: 1. Application and Market Projections – Venky 1. Benjamin Leever, Air Force Research Sundaram,Georgia Institute of Technology Laboratory, Materials & Manufacturing 2. Powertrain Electronics – Brent Richardson, Directorate Texas Instruments 2. James L. Zunino, U.S. Army RDECOM 3. Sensors – Frank Bertini, Velodyne ARDEC 4. Data Processing – Dongji Xie, Nvidia 3. Robert Smith, Boeing Research & Technology 5. Wireless Communication – Raj Pendse, 4. Girish Wable, Jabil Qualcomm Technologies, Inc. 5. John Knickerbocker, IBM Corporation

2017 ECTC PANEL SESSION 2017 CPMT SEMINAR Panel Fan-Out Manufacturing: 3D Printing Tools, Technologies Why, When, and How? and Applications Tuesday, May 30, 2017 Thursday, June 1, 2017 7:30 p.m. – 9:00 p.m. 8:00 p.m. – 9:30 p.m. Southern Hemisphere 11 & 111, 5th Floor Southern Hemisphere 11 & 111, 5th Floor Chairs: Jean Trewhella, CPMT President - Chairs: Venky Sundaram - Georgia Institute of GLOBALFOUNDRIES and Young Gon Kim Technology and Yasumitsu Orii - Nagase, Japan - Integrated Device Technology Speakers: Speakers: 1. Manos Tentzeris, Georgia Institute of Technology 1. Douglas Yu, TSMC 2. Humair Mandavia, Zuken SOZO Center 2. Tim Olson, DECA 3. Simon Fried, Nano Dimension Ltd. 3. Steffen Kroehnert, NANIUM 4. Takeshi Sato, Fuji Machine Mfg. Co., Ltd. 4. Rolf Aschenbrenner, IZM Fraunhofer 5. Steve Bezuk, Qualcomm Technologies, Inc.

7 ECTC STUDENT RECEPTION PROFESSIONAL DEVELOPMENT COURSES • TUESDAY, MAY 30, 2017 Tuesday, May 30, 2017 All courses take place on the 5th floor unless otherwise noted. 5:00 p.m. - 6:00 p.m. Host: Texas Instruments, Inc. Morning Courses 8:00 a.m. – 12:00 Noon Afternoon Courses 1:30 p.m. – 5:30 p.m. Outside at the Cabana Deck by Dolphin Pool; (Rain Back Up – Asia 1, Lobby Level) Northern Hemisphere E1 Northern Hemisphere E1 1. Achieving High Reliability of 10. Flip Chip Technologies ECTC welcomes our student attendees and Lead-Free Solder Joints – Material Course Leaders: Eric Perfecto – GLOBALFOUNDRIES; student presenters who bring their research Considerations Shengmin Wen – Synaptics Inc. results to our audience. The Student Reception Course Leader: Ning-Cheng Lee – Indium Corporation is an event where we provide guidance to students for their job search from industry Northern Hemisphere E2 Northern Hemisphere E2 leaders. In addition to the Student Reception, in 2. Wafer Level Chip Scale Packaging 11. Package Failure Analysis – Failure the Student Interactive Presentation Session, we Course Leader: Luu Nguyen – Texas Instruments, Inc. Mechanisms and Analytical Tools provide one-on-one access to students and their Course Leaders: Rajen Dias – Amkor Technology and research to our audience. We encourage you Deepak Goyal – Intel Corporation to attend the Student Interactive Presentation Session on Friday. This reception is sponsored Northern Hemisphere E3 Northern Hemisphere E3 by Texas Instruments. 3. LED Packaging, System, and 12. 3D IC Integration and 3D IC Reliability Considerations Packaging GENERAL CHAIR’S SPEAKERS RECEPTION Course Leader: Xuejun Fan – Lamar University Course Leader: John Lau – ASM Pacific Technology Ltd. Tuesday, May 30, 2017 6:00 p.m. - 7:00 p.m. Outside at the Crescent Terrace on the Swan Hotel side; (Rain Back Up – Northern Hemisphere Northern Hermisphere E4 Northern Hemisphere E4 D / DE Corridor) 4. Future of Device and Systems 13. Flexible Hybrid Electronics Packaging: Strategic Technologies, Mfg. Course Leader: Pradeep Lall – Auburn University Invited session chairs and speakers are Infrastructure, and Applications requested to attend the reception. Course Leader: Rao Tummala – Georgia Institute of Technology TECHNOLOGY CORNER RECEPTION Wednesday, May 31, 2017 Americas Seminar Americas Seminar 5:30 p.m. - 6:30 p.m. 5. Polymers and Nanocomposites for 14. Polymers for Electronic Packaging th Electronic and Photonic Packaging Course Leader: Jeffrey Gotro – InnoCentrix, LLC Northern Hemisphere A – C, 5 Floor Course Leaders: C. P. Wong – Georgia Institute of An Exhibitor Sponsored Reception will be held Technology; Daniel Lu – Henkel Corporation in Northern Hemisphere A – C, 5th Floor. All attendees and guests are invited.

Southern Hemisphere 111 Southern Hemisphere III 6. Integrated Thermal Packaging and 15. Emerging Interconnect and System 67th ECTC GALA RECEPTION Reliability of Power Electronics Integration Technologies Thursday, June 1, 2017 Course Leaders: Patrick McCluskey and Avram Bar- Course Leader: Muhannad Bakir – Georgia Institute of 6:30 p.m. Cohen – University of Maryland Technology Outside at the Lake Terrace on the Swan Hotel side; (Rain Back Up – Northern Hemisphere D – E)

Southern Hemisphere IV Southern Hemisphere IV All badged attendees and guests are invited to 7. Fundamentals of Electrical 16. Package Failure Mechanisms, attend our Gala Reception outside at the Lake Design and Fabrication Processes of Reliability, and Solutions Terrace. Interposers, Including Their RDLs Course Leader: Darvin Edwards – Edwards Course Leaders: Ivan Ndip, Markus Wöhrmann, and Enterprises Michael Töpper – Fraunhofer IZM CONTINUING EDUCATION UNITS The IEEE Components, Packaging, and Manufacturing Technology Society (CPMT) has been authorized Southern Hemisphere V Southern Hemisphere V to offer Continuing Education Units (CEUs) by the 8. Introduction to Mechanics Based 17. Ageing of Polymers and the Influence International Association for Continuing Education Quality and Reliability Assessment on Microelectronic Package Reliability and Training (IACET) for all Professional Development Methodology Course Leaders: Tanja Braun and Ole Hölck – Courses that will be presented at the 67th ECTC. Course Leaders: Shubhada Sahasrabudhe and Fraunhofer IZM CEUs are recognized by employers for continuing Sandeep Sane – Intel Corporation professional development as a formal measure of participation and attendance in “non-credit” self-study courses, tutorials, symposia, and workshops. Complete Southern Hemisphere I1 Southern Hemisphere I1 details, including voluntary enrollment forms, will be 9. Thermo-Electric Coolers: 18. Thermo-Electrical Co-Design of 3D available at the conference. All costs associated with Characterization, Reliability, and Chip Stacks ECTC Professional Development Course CEUs will Modeling Course Leaders: Ankur Srivastava and Avram Bar-Cohen be underwritten by the conference, i.e., there are no Course Leader: Jaime Sanchez – Intel Corporation – University of Maryland, and Jim Wilson – Raytheon additional costs for Professional Development Course attendees to obtain CEU credit.

Refreshment Breaks – 10:00 - 10:20 a.m. & 3:00 - 3:20 p.m. 8 Southern Hemisphere Foyer & Northern E Corridor 2016 ECTC BEST PAPER AWARDS BEST OF CONFERENCE PAPERS – 2016 OUTSTANDING PAPERS – 2016 The Electronic Components and Technology Conference is proud The winning authors for Conference Outstanding Session Paper to announce the “Best of Conference” papers selected from the and Interactive Presentation receive a personalized plaque 66th ECTC proceedings. The authors of the Best Session Paper commemorating their achievement and will share a check for share a check for US $2,500 and the authors of the Best Interactive US $1,000. Presentation share a check for US $1,500. The winning authors also Outstanding Session Paper receive a personalized plaque commemorating their achievement. Session 13, Paper 4 Best Session Paper Eternal Packages: Liquid Metal Flip Chip Devices Assane Ndieguene, Pierre Albert, and Julien Sylvestre – Université de Session 2, Paper 5 High-Frequency Analysis of Embedded Sherbrooke; Clément Fortin and Valérie Oberson – IBM Corporation Microfluidic Cooling Within 3-D ICs Using a TSV Outstanding Interactive Presentation Testbed Session 39, Paper 16 Hanju Oh, Xuchen Zhang, Gary S. May, and Muhannad S. Bakir – 20” x 20” Panel Size Glass IPD Interposer Georgia Institute of Technology Manufacturing Yu-Hua Chen, Chun-Hsien Chien, Yu-Chung Hsieh, Wei-Ti Lin, Wen-Liang Best Interactive Presentation Yeh, Chien-Chou Chen, Dyi-Chung Hu, Tzyy-Jang Tseng – Unimicron Session 37, Paper 2 Technology Corp.; Hobie Yun – Qualcomm Technologies, Inc. Constitutive Relations for Finite Element Modeling of SnAgCu in Thermal Cycling – How Wrong We Were! TEXAS INSTRUMENTS OUTSTANDING STUDENT Thaer Alghoul, Dustin Watson, Nardeeka Adams, Saif Khasawneh, Farhan INTERACTIVE PRESENTATION – 2016 Batieha, Chris Greene, and Peter Borgesen – Binghamton University The winning student receives a personalized plaque and a check INTEL BEST STUDENT PAPER – 2016 for US $500. The following paper was selected based on the The winning student receives a personalized plaque and a check for Texas Instruments Outstanding Student Interactive Presentation $2,500. The following paper was selected based on the Intel Best competition conducted at the 66th ECTC: Student Paper competition conducted at the 66th ECTC: Session 39, Paper 28 Session 30, Paper 2 2D Grating Pitch Mapping of a Through Silicon Via Non-Linear Finite Element Analysis on Stacked (TSV) and Solder Ball Interconnect Region Using Die Package Subjected to Integrated Vapor-Hygro- Laser Diffraction Thermal-Mechanical Stress Todd Houghton, Michael Saxon, Zeming Song, Hoa Nguyen, Hanqing Jing Wang and Seungbae Park, Binghamton University Jiang, and Hongbin Yu - Arizona State University

COMMITTEE MEETINGS • ASSOCIATED COMMITTEE MEMBERS ONLY

Tuesday, May 30, 2017 Wednesday, May 31, 2017 Thursday, June 1, 2017 Friday, June 2, 2017 9:30 a.m. – 5:30 p.m. 7:00 a.m. – 8:00 a.m. 7:00 a.m. – 8:00 a.m. 7:00 a.m. – 8:00 a.m. INEMI Meeting CPMT Materials & Processes TC CPMT Region 8 Meeting CPMT Nanotechnology TC Oceanic 1, Lobby Level Europe 3, Lobby Level Europe 4, Lobby Level Europe 3, Lobby Level

8:00 a.m. – 5:30 p.m. 7:00 a.m. – 8:00 a.m. 7:00 a.m. – 8:00 a.m. 7:00 a.m. – 8:00 a.m. IEEE CPMT Heterogeneous CPMT Energy Electronics TC CPMT RF & THz Technology TC CPMT Thermal & Mechanical TC Europe 5, Lobby Level Integration Roadmap Workshop Europe 4, Lobby Level Asia 1, Lobby Level Europe 4, Lobby Level 7:00 a.m. – 8:00 a.m. 4:30 p.m. – 5:30 p.m. CPMT High Density Substrates & 1:30 p.m. – 4:30 p.m. 9:00 p.m. – 10:30 p.m. CPMT Technical Committee Chairs Boards TC ECTC Executive Committee ECTC Interconnect Committee Europe 1, Lobby Level Europe 1, Lobby Level Europe 3, Lobby Level Europe 4, Lobby Level 6:00 p.m. – 7:00 p.m. 4:30 p.m. – 6:00 p.m. 4:45 p.m. – 5:45 p.m. Program Subcommittee Chairs & CPMT Officers and Directors Meeting ECTC Steering Committee Assistant Chairs Reception Oceanic 1, Lobby Level Europe 3, Lobby Level General Chair’s Suite (by invitation only) 5:30 p.m. – 6:30 p.m. ECTC 2017 Program Committee 9:00 p.m. – 10:30 p.m. Meeting ECTC Opto Committee Southern Hemisphere 1, 5th Floor Americas Seminar, 5th Floor 8:00 p.m. 67th ECTC Governing/Executive Committee Reception General Chair’s Suite

9 Program Sessions: Wednesday, May 31, 8:00 a.m. - 11:40 a.m.

Session 1: Fan-Out Packaging Process Session 2: TSV Process, Session 3: Flip Chip Assembly and Integration Characterization and Applications

Committee: Committee: Committee: Assembly & Manufacturing Advanced Packaging Interconnections Technology

Room: Southern Hemisphere I Room: Southern Hemisphere II Room: Southern Hemisphere III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Beth Keser – Intel Corporation Takafumi Fukushima – Tohoku University Valerie Oberson – IBM Corporation Mike Ma – Amkor Technology Taiwan (ATT) Tom Gregorich – SanDisk Mark Gerber – Advanced Semiconductor Engineering Inc.

1. 8:00 AM - Development of a Multi- 1. 8:00 AM - A Cost-Effective Via Last TSV 1. 8:00 AM - Key Properties for Successful Project Fan-Out Wafer Level Packaging Technology Using Molten Solder Filling for Ultra Thin Die Pickup Platform Automobile Application Stefan Behler – Besi Switzerland AG; Teng Wang and T. Braun, S. Raatz, U. Maass, M. van Dijk, H. Walter, Yuki Ohara, Yuki Inagaki, Masaki Matsui, and Kazushi Arnita Podpod – IMEC O. Hölck, K. F. Becker, M. Töpper, R. Aschenbrenner Asami – DENSO Corporation – Fraunhofer IZM; M. Wöhrmann, S. Voges, M. Huhn, K. D. Lang – Technical University Berlin; M. Wietstruck, R.F. Scholz, A. Mai, M. Kaynak – IHP

2. 8:25 AM - SLIM™, High Density Wafer 2. 8:25 AM - Accurate Depth Control of 2. 8:25 AM - Fine Pitch Cu Pillar with Bond Level Fan-Out Package Development with Through-Silicon Vias by Substrate Integrated on Lead (BOL) Assembly Challenges for Submicron RDL Etch Stop Layers Low Cost and High Performance Flip Chip Youngrae Kim, JaeHun Bae, MinHwa Chang, AhRa Jo, Matthias Wietstruck, Steffen Marschmeyer, Marco Package Ji Hyun Kim, SangEun Park, David Hiner, Mike Kelly, Lisker, Andreas Krueger, Dirk Wolansky, Philipp Kulse, Nokibul Islam, Vinayak Pandey, and KyungOe Kim – and WonChul Do – Amkor Technology, Inc. Alexander Goeritz, Thomas Voss, Andreas Mai, and STATS ChipPAC, Inc. Mehmet Kaynak – IHP Microelectronics; Mesut Inac – Technical University Berlin

3. 8:50 AM - Development of Novel High 3. 8:50 AM - Application of a Metallic Cap 3. 8:50 AM - Improvement of C2W Collective Density System Integration Solutions in Layer to Control Cu TSV Extrusion Bonding Reliability and UPH through FOWLP – Complex and Thin Wafer-Level SiP Golareh Jalilvand, Omar Ahmed, Keenan Bosworth, Innovations in Machine, Materials and and Wafer-Level 3D Packages Zhenlin Pei, Cullen Fitzgerald, and Tengfei Jiang – Methods André Cardoso, Alberto Martins, Hugo Barros, University of Central Florida Tomonori Nakamura, Farhan Shafiq, Tetsuya Otani, Elisabete Fernandes, Abel Janeiro, Paulo Cardoso, and Osamu Watanabe, Toru Maeda, and Yoshihito Leonor Dias – NANIUM S.A. Hagiwara – Shinkawa Ltd.; Keiji Honjo, Daichi Mori, Outa Egashira, Daisuke Handa, and Tamotsu Owada – Dexerials Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C

4. 10:00 AM - Fan-Out Chip on Substrate 4. 10:00 AM - Development of TSV Electro- 4. 10:00 AM - Thermo-Compression Bonding Device Interconnection Reliability Analysis plating Process for Via-Last Technology and Mass Reflow Assembly Processes of 3D Ian Hu, Ying-Chih Lee, Wei-Hong Lai, Meng-Kai Shih, Gilho Hwang and Kalaiselvan Ravanethran – Institute Logic Die Stacks Chin-Li Kao, David Tarng, and Ching-Pin Hung – Ad- of Microelectronics, A*STAR Pascale Gagnon, Christian Bergeron, Richard Langlois, vanced Semiconductor Engineering, Inc. Stéphane Barbeau, Steve Whitehead, Katsuyuki Sakuma, Raphael Robertazzi, Christy Tyberg, Matthew Wordeman, and Michael Scheurmann – IBM Corporation

5. 10:25 AM - Embedded Si Fan-Out: A 5. 10:25 AM - Reliability Evaluation of 5. 10:25 AM - Chip Shooter to Enable Fine Low-Cost Wafer Level Packaging Technology Copper (Cu) Through-Silicon Via (TSV) Pitch Flip Chip Without Molding and De-Bonding Processes Barrier and Dielectric Liner by Electrical Jie Fu, Manuel Aldrete, and Milind Shah – Qualcomm Daquan Yu, Zhenrui Huang, Zhiyi Xiao, Li Yang, and Characterization and Physical Failure Technologies, Inc. Min Xiang – Huatian Technology (Kunshan) Electronics Analysis (PFA) Co., Ltd. Jiawei Marvin Chan and Chuan Seng Tan – Nanyang Technological University; Xu Cheng, Kheng Chooi Lee, and Werner Kanert – Infineon Technologies

6. 10:50 AM - Process Development and 6. 10:50 AM - Vertical Delay Modeling of 6. 10:50 AM - Assembly Challenges for Material Characteristics of TSV-Less Copper/Carbon Nanotube Composites in a 75x75mm Large Body FCBGA with Emerging Interconnection Technology for FOWLP Tapered Through Silicon Via High Thermal Interface Material (TIM) Wen-Wei Shen, Yu-Min Lin, Hsiang-Hung Chang, Tzu-Ying Kuo, Madhav Rao – International Institute of Information Fletcher (Cheng-Piao) Tung, Max (Chin Yu) Lu, Huan-Chun Fu, Yuan-Chang Lee, Shu-Man Lee, Ang-Ying Lin, Technology Bangalore Albert (Chang Yi) Lan, and Steward (Chi An) Pan – Shin-Yi Huang, Tao-Chih Chang – Industrial Technology Research Siliconware Precision Industries Co., Ltd. Institute; Alvin Lee, Jay Su, Baron Huang, Dongshun Bai and Xiao Liu – Brewer Science; Kuan-Neng Chen Chen – NCTU

7. 11:15 AM - First Demonstration of Panel 7. 11:15 AM - Latency, Bandwidth and 7. 11:15 AM - Fine Pitch Interconnect Glass Fan-Out (GFO) Packages for High I/O Power Benefits of the SuperCHIPS Rework for Lead-Free Flip Chip Packages Density and High Frequency Multi-Chip Integration Scheme Malak Kanso, David Danovitch, and Elodie Nguena – Integration SivaChandra Jangam, Saptadeep Pal, Adeel Bajwa, Sherbrooke University; Richard Langlois and Christian Tailong Shi, Vanessa Smet, Venky Sundaram, Rao Tummala, Sudhakar Pamarti, Puneet Gupta, and Subramanian Bergeron – IBM Corporation and Chintan Buch – Georgia Institute of Technology; Iyer – University of California, Los Angeles Yoichiro Sato – Asahi Glass Co., Ltd.; Lutz Parthier – Schott; Frank Wei and Cody Lee – Disco Corporation 10 Program Sessions: Wednesday, May 31, 8:00 a.m. - 11:40 a.m.

Session 4: Advanced Substrates and Session 5: Emerging Sensors and Session 6: 5G, mmWave and Beyond Integrated Devices Microsystems Packaging

Committee: Committee: Committee: Materials & Processing Emerging Technologies High-Speed, Wireless & Components

Room: Southern Hemisphere IV Room: Southern Hemisphere V Room: Americas Seminar

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Tieyu Zheng – Microsoft Corporation Bharat Penmecha – Intel Corporation Kemal Aygun – Intel Corporation Yu-Hua Chen – Unimicron Ramakrishna Kotlanka – Analog Devices Lih-Tyng Hwang – National Sun Yat-Sen University

1. 8:00 AM - A Novel Organic Substrate with 1. 8:00 AM - Phototriggerable, Transient 1. 8:00 AM - First Demonstration of 28 GHz Enhanced Thermal Conductivity Electronics: Component and Device and 39 GHz Transmission Lines and Antennas Xiaoliang Zeng, Yimin Yao, Yougen Hu, Kun Guo, Jiajia Fabrication on Glass Substrates for 5G Modules Sun, and Rong Sun – Shenzhen Institutes of Advanced Gerald Gourdin, Oluwadamilola Phillips, Jared Atom O. Watanabe, Muhammad Ali, Bijan Tehrani, Technology; Jianbin Xu and Ching-Ping Wong – Schwartz, Anthony Engler, and Paul Kohl – Georgia Jimmy Hester, P. Markondeya Raj, Venky Sundaram, Chinese University Hong Kong Institute of Technology Manos M. Tentzeris, and Rao R. Tummala – Georgia Institute of Technology; Hiroyuki Matsuura – NGK Spark Plug; Tomonori Ogawa – Asahi Glass Co., Ltd.

2. 8:25 AM - Infusing Inorganics into the 2. 8:25 AM - Novel High Temperature 2. 8:25 AM - Integrated Antenna-in- Subsurface of Polymer Redistribution Layer Capacitive Pressure Sensor Utilizing SiC Package on Low-Cost Organic Substrate for Dielectrics for Improved Adhesion to Metals Integrated Circuit Twin Ring Oscillators Millimeter-Wave Wireless Communication Shreya Dwarakanath, Pulugurtha Markondeya Raj, Maximilian C. Scardelletti, Philip G. Neudeck, David J. Applications Collen Z. Leng, Venky Sundaram, Mark D. Losego, Rao Spry, Roger D. Meredith, Jennifer L. Jordan, Norman Cheng-Yu Ho, Ming-Fong Jhong, Po-Chih Pan, Chen- R Tummala, and Vanessa Smet – Georgia Institute of F. Prokop, Michael J. Krasowski, Glenn M. Beheim, and Chao Wang, Chun-Yen Ting, and Chih-Yi Huang – Technology Gary W. Hunter – NASA Glenn Research Center Advanced Semiconductor Engineering, Inc.

3. 8:50 AM - Development of Solder Resist 3. 8:50 AM - An Experimental Magnesium 3. 8:50 AM - Aerosol-Jet Printed Quasi- with Improved Adhesion at HTSL (175 deg C Ion Battery Cell Made of Flexible Materials Optical Terahertz Filters for 3000 Hours) and Crack resistance at TST Todd Houghton, Gamal Eltohamy, and Hongbin Yu – Christopher Oakley, Amanpreet Kaur, Jennifer for Automotive IC Package Arizona State University A. Byford, and Premjeet Chahal – Michigan State Chiho Ueta, Kazuya Okada, Toko Shiina, Tadahiko University Hanada, and Nobuhito Itoh – Taiyo Ink Mfg. Co., Ltd.

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C

4. 10:00 AM - Bondable Copper Substrates 4. 10:00 AM - Fractal-Structured, Wearable 4. 10:00 AM - High Performance Chip-Par- With Silver Solid Solution Coatings for High- Soft Sensors for Control of a Robotic Wheel- titioned Millimeter Wave Passive Devices on Power Electronic Applications chair via Electrooculograms Smooth and Fine Pitch InFO RDL Yongjun Huo and Chin C. Lee – University of Saswat Mishra, Yongkuk Lee, Dong Sup Lee, and Che-Wei Hsu, Chung-Hao Tsai, Jeng-Shien Hsieh, California, Irvine Woon-Hong Yeo – Virginia Commonwealth University Kuo-Chung Yee, Chuei-Tang Wang, and Douglas Yu – Taiwan Semiconductor Manufacturing Company, Ltd.

5. 10:25 AM - On-Chip Integrated Solid- 5. 10:25 AM - Micro-Hermetic Packaging 5. 10:25 AM - Directional Through Glass State Micro-Supercapacitor Technology for Active Implantable Neural Via (TGV) Antennas for Wireless Point-to- Muhammad Amin Saleem, Rickard Andersson, and Interfaces Point Interconnects in 3D Integration and Vincent Desmaris – Smoltek AB; Bo Song and C.P Kaustubh Nagarkar, Nancy Stoffel, Eric Davis, and Packaging Wong – Georgia Institute of Technology Jeffrey Ashe – General Electric Co.; Xiaoxiao Hou and Seahee Hwangbo, Hyowon An, Sheng-Po Fang, and David Borton – Brown University Yong-Kyu Yoon – University of Florida; Aric B. Shorey and Abbas M. Kazmi – Corning, Inc.

6. 10:50 AM - Development of CPU Package 6. 10:50 AM - Biopackaging of Minimally 6. 10:50 AM - RF Characterization and Embedded with Multilayer Thin Film Invasive Ultrasound Assisted Clot Lysis Modeling of 10 µm Fine-Pitch Cu-Pillar on a Capacitor for Stabilization of Power Supply Device for Stroke Treatment High Density Silicon Interposer Tomoyuki Akahoshi, Daisuke Mizutani, Kei Fukui, Seigo Ramona Damalerio, Ming-Yuan Cheng, Weiguo Hélène Jacquinot, L. Arnaud, A. Garnier, F. Bana, J.C. Yamawaki, Hidehiko Fujisaki, Manabu Watanabe, and Chen, Liang Lou, and Songsong Zhang – Institute of Barbe, and S. Cheramy – CEA-Leti Masateru Koide – Fujitsu Laboratories, Ltd. Microelectronics, A*STAR

7. 11:15 AM - Panel-Based Integrated 7. 11:15 AM - A Low-Profile Flow Sensing 7. 11:15 AM - Miniature 2.4-GHz Switched Passive Device for RF Application System for Monitoring of Cerebrospinal Beamformer Module in IPD and its Ming Hung Chen, Tze Hsin Chiang, Jia Hao Zhang, Fluid with a New Ventriculoamniotic Shunt Application to Very-Low-Profile 1D and 2D Hsu Chiang Shih, Sheng Chi Hsieh, Teck Chong Lee, Yanfei Chen, Stephanie Greene, Puneeth Shridhar, Scanning Antenna Arrays and Chih Pin Hung – Advanced Semiconductor and Youngjae Chun – University of Pittsburgh; Chia-Hao Chen, Wei-Ting Fang, and Yo-Shen Lin – Engineering, Inc. Connor Howe and Woon-Hong Yeo – Virginia National Central University Commonwealth University; Emery Stephen – Magee- Womens Hospital of UPMC 11 Program Sessions: Wednesday, May 31, 1:30 p.m. - 5:10 p.m.

Session 7: Fan-Out Packaging Materials Session 8: Singulation Process Session 9: Fine Pitch Flip Chip Process and Passives Developments Technologies

Committee: Committee: Committee: Advanced Packaging Assembly & Manufacturing Technology Interconnections

Room: Southern Hemisphere I Room: Southern Hemisphere III Room: Southern Hemisphere II

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Luke England – GLOBALFOUNDRIES Garry Cunningham – NGC David Danovitch – University of Sherbrooke Bora Baloglu – Amkor Technology Li Jiang –Texas Instruments Li Li – Cisco Systems, Inc.

1. 1:30 PM - Development of Liquid, 1. 1:30 PM - Expanding Film and Process for 1. 1:30 PM - Cu-SnAg Interconnects Granule, and Sheet Type Epoxy Molding High Efficiency 5 Sides Protection and FO- Evaluation for the Assembly at 10µm and Compounds for Fan-Out Wafer Level WLP Fabrication 5µm Pitch Package Kazutaka Honda, Naoya Suzuki, Toshihisa Nonaka, Divya Taneja, Marion Volpert, Gilles Lasfargues, Boris Kenichi Ueno, Kazuhiro Dohi, Kazuyoshi Muranaka, Hirokazu Noma, and Yoshinobu Ozaki – Hitachi Bouillard, Aurelie Vandeneynde, Tarik Chaira, Yannick Akira Nakao, and Yuki Ishikawa – Sanyu Rec Co., Ltd. Chemical Co., Ltd. Goiran, David Henry, Bertrand Chambion, and Sylvie Jarjayes – CEA-Leti; Fiqiri Hodaj – University Grenople Alps, SIMAP

2. 1:55 PM - Ultra-Low Temperature FOWLP 2. 1:55 PM - Laser Multi Beam Full Cut 2. 1:55 PM - Scaling Cu Pillars to 20µm Pitch Process for the Embedding of Low Thermal Dicing of Wafer Level Chip-Scale Packages and Below: Strategic Role of Surface Finish Budget Sensors and Components Using SU-8 Jeroen van Borkulo, Eric Tan, and Richard van der Stam and Barrier Layers as Dielectric – ASM Pacific Technologies Ting-Chia Huang, Vanessa Smet, Pulugurtha Raquel Pinto, André Cardoso, Sara Ribeiro, and Carlos Markondeya Raj, and Rao Tummala – Georgia Institute Brandão – NANIUM S.A.; João Gaspar, Rizwan Gill, of Technology; Robin Taylor, Gustavo Ramos, Rick Helder Fonseca, and Margaret Costa – INL; Filipe Nichols, Arnd Kilian, and Maja Tomic – Atotech Cardoso and Mariana Antunes – Magnomics

3. 2:20 PM - Integrated Copper Heat Slugs 3. 2:20 PM - Plasma Dicing 300mm Framed 3. 2:20 PM - Thermal Compression Bonding: and EMI Shields in Panel Laminate (LFO) Wafers - Analysis of Improvement in Die Understanding Heat Transfer by in situ and Glass Fan-Out (GFO) Packages for High Strength and Cost Benefits for Thin Die Measurements and Modeling Power RF ICs Singulation Pieter Bex, Teng Wang, Vladimir Cherman, Melina Venky Sundaram, Bartlet Deprospo, Nahid Gezgin, Richard Barnett – SPTS Technologies, Ltd. Lofrano, Giovanni Capuz, Erik Sleeckx, and Eric Beyne Atomu Watanabe, P. Markondeya Raj, Fuhan Liu, – IMEC Waylon Puckett, Samuel Graham, and Rao Tummala – Georgia Institute of Technology; Kyle Byers and Sean Garrison – Honeywell Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

4. 3:30 PM - Implementation of Thick Cop- 4. 3:30 PM - Plasma Dicing Fully Integrated 4. 3:30 PM - A Study on Nano-Sized Silica per Inductor Integrated into Chip Scaled Process-Flows Suitable for BEOL Advanced Content and Size Effect in Non Conductive Package Packaging Fabrications Films (NCFs) for Ultra Fine-Pitch Cu-Pillar/ S.B. Yang, C.C. Chen, W.L. Huang, T.L. Yang, G.C. Frank Wei and Tomotaka Tabuchi – DISCO Sn-Ag Micro-Bump Interconnection Huang, T.Y. Chou, C.C. Hsu, C.L. Chang, H.L. Huang, Corporation; Thierry Lazerand, Christopher Johnston, HanMin Lee, SeYong Lee, SeMin Cho, YoungHyun C.C. Chou, C.Y. Ku, C.H. Chen, C.S. Chen, K.C. Liu, Kenneth Mackenzie, and Marco Notarianni – Plasma- Yu, Jong-Ho Park, and Kyung-Wook Paik – Korea Alex Kalnitsky, Marvin Liao – Taiwan Semiconductor Therm, LLC Advanced Institute of Science and Technology Manufacturing Company, Ltd.

5. 3:55 PM - Passive Devices Fabrication 5. 3:55 PM - Stealth Dicing Challenges for 5. 3:55 PM - Accelerated SLID Bonding on FOWLP and Characterization for RF MEMS Wafer Applications for Fine-Pitch Interconnects with Porous Applications Daniel Ismael Cereno, and Sunil Wickramanayaka – Microstructure Chunmei Wang, King Jien Chui, Xiangyu Wang, Institute of Microelectronics, A*STAR Jörg Meyer, Iuliana Panchenko, Steffen Bickel, and Laura Teck Guan Lim, and Mingbin Yu – Institute of Wambera – Technical University Dresden; Wieland Microelectronics, A*STAR; Gilbert See and Gu Yu – Wahrmund and M. Jürgen Wolf – Fraunhofer IZM, Applied Materials ASSID

6. 4:20 PM - Compression Molding 6. 4:20 PM - A Novel Pick-Up and Place 6. 4:20 PM - Low Temperature Ni/Sn/Ni Encapsulants for Wafer-Level Embedded Process for FO-WLP Using Tape Expansion Transient Liquid Phase Bonding for High Active Devices: Wafer Warpage Control by Machine Device Temperature Packaging Application by Epoxy Molding Compounds Shinya Takyu, Naoya Okamoto, Tadatomo Yamada, Imposing Temperature Gradient Kihyeok Kwon, Yoonman Lee, Junghwa Kim, Joo Toshiaki Menjo, and Masatomo Nakamura – LINTEC Yi Zhong, Wei Dong, Mingliang Huang, Haitao Ma, Young Chung, Kyunghag Park, Yong-Yeop Kim, Corporation and Ning Zhao – Dalian University of Technology; C.P. Donghwan Lee, and Sang Kyun Kim – Samsung SDI Wong – Georgia Institute of Technology

7. 4:45 PM - Additive Manufacturing of 7. 4:45 PM - Investigation of Production 7. 4:45 PM - Interfacial Reaction and Magnetic Components for Heterogenous Quality and Reliability Risk of ELK Wafer Microstructural Evolution between Au-Ge Integration WLCSP Package Solder and Electroless Ni-W-P Metallisation in Yi Yan, Lanbing Liu, Guo-Quan Lu, and Chao Ding Pei-Haw Tsao, T.M. Chen, Y. L. Kuo, C. M. Kuo, Steven High Temperature Electronics Interconnects – Virginia Tech; Luu Nguyen and Jim Moss – Texas Hsu, M. J. Lii, and L. H. Chu – Taiwan Semiconductor Li Liu – Wuhan University of Technology, Wuhan, China; Jinzi Cui Instruments, Inc.; Yunhui Mei – Tianjin University Manufacturing Company, Ltd. – Auburn University; Jing Wang – Wolfson School of Mechanical, Electrical and Manufacturing Engineering, Loughborough University; Zhaoxia Zhou and Changqing Liu – Loughborough University 12 Program Sessions: Wednesday, May 31, 1:30 p.m. - 5:10 p.m.

Session 10: Harsh Environment Session 11: Mechanical Modeling and Session 12: Advanced Optical Interconnect Reliability Characterization of Interposers and Interconnections Components and Modules

Committee: Committee: Thermal/Mechanical Committee: Applied Reliability Simulation & Characterization Optoelectronics

Room: Southern Hemisphere IV Room: Southern Hemisphere V Room: Americas Seminar

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Tim Chaudhry – Amkor Technology, Inc. Kuo-Ning Chiang – National Tsinghua Stephane Bernabe – CEA Leti René Rongen – NXP Semiconductors University Shogo Ura – Kyoto Institute of Technology Tony Mak – Wentworth Institute of Technology

1. 1:30 PM - Effect of Processing Variables 1. 1:30 PM - Hybrid Approach to Conduct 1. 1:30 PM - Low Loss Channel-Shuffling on the Mechanical Reliability of Copper Failure Prognostics of Automotive Electronic Polymer Waveguides: Design and Fabrication Pillar SnAg/Cu Solder Joints Control Unit Kohei Abe, Yutaro Oizumi, Yoichi Taira, and Takaaki Mohammed Genanu, Babak Arfaei, and Eric Cotts Bulong Wu, Dae-Suk Kim, and Bongtae Han – Ishigure – Keio University – Binghamton University; Francis Mutuku and James University of Maryland; Alicja Palczynska, Przemyslaw Wilcox – Universal Instruments; Eric Perfecto – Jakub Gromala, and Alexandru Prisacaru – Robert GLOBALFOUNDRIES Bosch GmbH

2. 1:55 PM - Visualization of Microstructural 2. 1:55 PM - Semiconductor Power Package 2. 1:55 PM - A Very High-Density On-Board Evolution in Lead Free Solders During Bonding Interconnects Reliability Simulation Optical Module Realizing >1.3 Tb/s/inch² Isothermal Aging Using Time-Lapse Imagery under Transient Thermal Loads Kazuya Nagashima, Toshinori Uemura, Atsushi Izawa, Sudan Ahmed, Nianjun Fu, Jeffrey Suhling, and Pradeep Qiuxiao Qian, Roger Stout, and Yong Liu – ON Yozo Ishikawa, and Hideyuki Nasu – Furukawa Electric Lall – Auburn University Semiconductor

3. 2:20 PM - Failure Mechanism and Kinetics 3. 2:20 PM - Correlation of Dielectric Film 3. 2:20 PM - Design and Demonstration of Studies of Electroless Ni-P Dissolution in Pb- Flex Fatigue Resistance and Package Resin a Photonic Integrated Glass Interposer for Free Solder Joints under Electromigration Cracking Failure Mid-Board Optical Engines Pilin Liu, Alan Overson, Chaitra Chavali, and Deepak Joseph Ross, Nicolas Pizzuti, Steven Ostrander, and Marcel Neitz and Sebastian Marx – Technical University Goyal – Intel Corporation Kamal Sikka – IBM Corporation Berlin; Markus Wöhrmann and Henning Schröder – Fraunhofer IZM; Ruiyong Zhang and Mohamed Fikry – Amphenol FCI

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

4. 3:30 PM - Pad Cratering Based Failure 4. 3:30 PM - Development of FE Models and 4. 3:30 PM - Optoelectronic Chip Assembly Criterion for the Life Prediction of Board Measurement of Internal Deformations of Process of Optical MCM Level Cyclic Bending Test Fuze Electronics Using X-Ray MicroCT Data Masao Tokunari, Koji Masuda, Hsiang-Han Hsu, Qiming Zhang, Jeffery C. C. Lo, and Shi-Wei Ricky Lee with Digital Volume Correlation Takashi Hisada, Shigeru Nakagawa, Richard Langlois, –Hong Kong University of Science and Technology Pradeep Lall and Nakul Kothari – Auburn University; Patrick Jacques, and Paul Fortier – IBM Corporation John Deep and Jason Foley – US Air Force Research Labs; Ryan Lowe – ARA Associates

5. 3:55 PM - Road Test and Reliability 5. 3:55 PM - Dynamic Stress Measurements 5. 3:55 PM - 3D Packaging of Embedded Analysis of Electronic Modules of Electronic Devices During Active Opto-Electronic Die and CMOS IC Based on Dongji Xie, Joe Hai, Jack Huang, Manthos Economou, Operation Wet Etched Silicon Interposer and Zhongming Wu – Nvidia Corporation Markus Feisst, Eike Moeller, and Jürgen Wilde – Chenhui Li, Barry Smalbrugge, Teng Li, Ripalta Stabile, University of Freiburg, IMTEK and Oded Raz – Eindhoven University of Technology

6. 4:20 PM - Effects of the Inter-Metallic 6. 4:20 PM - Smart Packaging: A Micro- 6. 4:20 PM - Self-Alignment with Copper Compounds Microstructure on Electro- Sensor Array Integrated to a Flip-Chip Pillars Micro-Bumps for Positioning Optical Migration of Sn-Bi Solder System Package to Investigate the Effect of Devices at Submicronic Accuracy Kei Murayama, Mitsuhiro Aizawa, and Takashi Kurihara Humidity in Microelectronic Packages Yézouma Dieudonné Zonou, Stéphane Bernabe, – Shinko Electric Industries Company, Ltd. Aurore Quelennec, Umar Shafique, and Dominique Daivid Fowler, Mireille Francou, and Olivier Castany Drouin – Université de Sherbrooke; Éric Duchesne – CEA-Leti; Philippe Arguel, – Laboratory for Analysis – IBM Corporation; Hélène Frémont – Université de and Architecture of Systems, CNRS Bordeaux

7. 4:45 PM - Effect of Board and Package 7. 4:45 PM - Nondestructive, In Situ 7. 4:45 PM - Thermal Management Type on Board Level Vibration Using Mapping of Die Surface Displacements in Characterization of Microassemblied High Vibrational Spectrum Analysis Encapsulated IC Chip Packages Using X-Ray Power Distributed-Feedback Broad Area Jeroen Jalink, Romuald Roucou, Jeroen Zaal, Joachim Diffraction Imaging Techniques Lasers Emitting at 975nm Lesventes, and Rene Rongen – NXP Semiconductors Nima E. Gorji, Rajani K. Vijayaraghavan, and Patrick J. Roberto Mostallino, Michel Garcia, Alexandre Larrue, McNally – Dublin City University; Brian K. Tanner – Yannick Robert, Eric Vinet, Michel Lecomte, Olivier Durham University; Andreas N. Danilewsky – Albert Parillaud, and Michel Krakowski – III-V Lab; Yannick Ludwigs University Deshayes and Laurent Bechou – University of Bordeaux 13 Program Sessions: Thursday, June 1, 8:00 a.m. - 11:40 a.m.

Session 13: Interconnect Advances in Session 14: Heterogeneous Integration Session 15: Flip Chip and Embedding FO & WLP in Substrates

Committee: Committee: Advanced Packaging Joint with Committee: Interconnections Assembly & Manufacturing Technology Advanced Packaging

Room: Southern Hemisphere II Room: Southern Hemisphere III Room: Southern Hemisphere I

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Lei Shan – IBM Corporation John Knickerbocker – IBM Corporation Markus Leitgeb – AT&S Dingyou Zhang – Qualcomm Technologies, Inc. Chunho Kim – Medtronic Corporation Steffen Kroehnert – Nanium S.A.

1. 8:00 AM - SLIM™ Advanced Fan-Out 1. 8:00 AM - A Versatile Platform Towards 1. 8:00 AM - Solder Mobility for High-Yield Packaging for High Performance Multi-Die High Reliability Compact Package for Digital Self-Aligned Flip-Chip Assembly Solutions Chips Yves Martin, Swetha Kamlapurkar, Jae-Woong David Hiner, Moh Kolbehdari, Michael Kelly, Young Christine Ferrandon, Laetitia Castagné, Brahim Kholti, Nah, Nathan Marchack, and Tymon Barwicz – IBM Rae Kim, Won Chul Do, JaeHun Bae, MinHwa Chang, Guillaume Waltener, Vincent Puyal, Romain Lemaire, Corporation and AhRa Jo – Amkor Technology, Inc. Jean-Charles Souriau, and Gilles Simon – CEA-Leti; Lionel Toffanin – ST Microelectronics; T. Lacrevaz – IMEP-LAHC Laboratory; J. P. Peltier – e2v

2. 8:25 AM - 28nm CPI (Chip/Package 2. 8:25 AM - Glass Based 3D-IPD Integrated 2. 8:25 AM - Large Scale Cryogenic Interactions) in Large Size eWLB (Embedded RF ASIC in WLCSP Integration Approach for Superconducting Wafer Level BGA) Fan-Out Wafer Level Teck Chong Lee, Yung-Shun Chang, Sheng-Chi High-Performance Computing Packages Hsieh, Pao-Nan Lee, Yu-Chang Hsieh, and Che- Rabindra Das, Vladimir Bolkhovsky, Sergey Tolpygo, Kang Chen, Linda Chua, Won Kyung Choi, Seng Guan Ming Hsu – Advanced Semiconductor Engineering, Pascale Gouker, Leonard Johnson, Eric Dauler, and Chow, and Seung Wook Yoon – STATS ChipPAC, Inc. Inc.; Long-Ching Wang and Lijuan Zhang – Marvell Mark Gouker – MIT Lincoln Laboratory Semiconductor

3. 8:50 AM - Multi DOE Study on 28nm 3. 8:50 AM - Breakthrough in Cu to Cu 3. 8:50 AM - Dense and Highly Elastic (RF) WLP Package to Investigate BLR Pillar-Concave Bonding on Silicon Substrate Compressible MicroInterconnects (CMIs) for Performance of Large WLP Die with 0.35mm with Polymer Layer for Advanced Packaging, Electronic Microsystems Ball Pitch Array 3D, and Heterogeneous Integration Paul K. Jo, Muneeb Zia, Joe L. Gonzalez, and Muhannad Rey Alvarado, Beth Keser, Tong Cui, Ahmer Syed, Yu-Tao Yang, Ting-Yang Yu, Shu-Chiao Kuo, and S. Bakir – Georgia Institute of Technology Steven Xu, and Brian Roggeman – Qualcomm Kuan-Neng Chen – National Chiao Tung University; Technologies, Inc. Tai-Yuan Huang, Kai-Ming Yang, Cheng-Ta Ko, Yu-Hua Chen, and Tzyy-Jang Tseng – Unimicron

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C

4. 10:00 AM - Warpage and Thermal 4. 10:00 AM - Heterogeneous Interposer 4. 10:00 AM - New Resin Materials for High Characterization of Fan-Out Wafer-Level Based Integration of Chips with Copper Power Embedding Packaging Pillars and C4 Balls to Achieve High Speed Michael Guyenot, Christiane Mager, and Roumen John Lau, Ming Li, DeWen Tian, Nelson Fan, Eric Kuah, Wu Kai, Margie Interfaces for ADC Application Ratchev – Robert Bosch GmbH; Thomas Gottwald Li, JiYuen Hao, Ken Cheung – ASM Pacific Technology Ltd.; Zhang Li and Andy Heinig, Michael Dittrich, Fabian Hopsch, and and A. Khoshamouz – Schweizer Electronic; Sascha Kim Hwee Tan – Jiangyin Changdian Advanced Packaging Co., Ltd.; Rozalia Robert Trieb – Fraunhofer IIS/EAS Kreuer – Isola Beica – Dow Chemical; Yu-Hua Chen – Unimicron; Sze Pei Lim and Ning Cheng Lee – Indium Corporation, Koh Sau Wee, Jiang Ran and Cao Xi – Huawei Technologies Co. Ltd.

5. 10:25 AM - A Novel 3D IC Wafer-Level 5. 10:25 AM - “FlexTrate®” - Scaled 5. 10:25 AM - Advanced Embedded Package for New Wave MEMS Heterogeneous Integration on Flexible Packaging for Power Devices Che-Hau Huang, Ying-Te Ou, and Yung-Hui Wang – Biocompatible Substrates Using FOWLP Naoki Hayashi, Miki Nakashima, Hiroshi Demachi, Advanced Semiconductor Engineering, Inc; Sebastian Tak Fukushima, Arsalan Alam, Saptadeep Pal, Zhe Shingo Nakamura, Tomoshige Chikai, Yukari Imaizumi, Schuler-Wakins, Ralf Reichenbach, David Polityko, and Wan, Siva Jangam, Goutham Ezhilarasu, Adeel Bajwa, Fumihiko Taniguchi, Yoshihiko Ikemoto, Mitsuru Ooida, Uwe Hansen – Robert Bosch GmbH and Subramanian Iyer – University of California, Los and Akito Yoshida – J-Devices Corporation Angeles

6. 10:50 AM - First Demonstration of 6. 10:50 AM - Metal Contamination 6. 10:50 AM - Development of Large-Size Photoresist Cleaning for Fine Line RDL Evaluation of Via-Last Cu TSV Process Using CPU Package Structure Using Embedded Yield Enhancement by an Innovative Ozone Notchless Si Etching and Wet Cleaning of the Thin Film Capacitor Package Substrate Treatment Process for Panel Fan-Out and First Metal Layer Masateru Koide, Kenji Fukuzono, and Manabu Watanabe – Interposers Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi, Fujitsu Advanced Technologies Limited; Daisuke Mizutani, Atul Gupta, Eric Snyder, Christiane Gottschalk, James Gunn, and and Masahiro Aoyagi – Advanced Industrial Science Tomoyuki Akahoshi, Seigo Yamawaki, and Kei Fukui Kevin Wenzel – MKS Instruments; Hao Lu, Yuya Suzuki, Venky and Technology; Hidekazu Kikuchi, Azusa Yanagisawa, – Fujitsu Laboratories, Ltd.; Hedehiko Fujisaki – Fujitsu Sundaram, and Rao Tummala – Georgia Institute of Technology and Akio Nakamura – LAPIS Semiconductor Interconnect Technologies Ltd.

7. 11:15 AM - Process and Reliability of 7. 11:15 AM - A Highly-Miniaturized System 7. 11:15 AM - Laminate Chip Embedding Large Fan-Out Wafer Level Package Based Integration Approach for an IOT Contact- Technology - Impact of Material Choice and Package-on-Package Less Power Module Processing for Very Thin Die Packaging Srinivasa Rao Vempati, David Ho, Mian Zhi Ding, Srikrishna Sitaraman, Shaoyong Wang, Tony Contreras, Angela Kessler, Andreas Munding, Thorsten Scharf, Ser Choong Chong, Sharon Lim PS, Tai Chong Jian Wang, Mingjie Fan, Yuming Song, and Terry Bowen Boris Plikat, and Klaus Pressel – Infineon Technologies Chai, Daniel Ismael, and Ye Yong Liang – Institute of – Tyco Electronics Microelectronics, A*STAR

14 Program Sessions: Thursday, June 1, 8:00 a.m. - 11:40 a.m.

Session 16: 3D Materials and Session 17: Materials and Processes Session 18: Warpage, Electromigration Processing for Flexible and Wearable Devices and Mechanical Characterization

Committee: Committee: Committee: Thermal/Mechanical Materials & Processing Emerging Technologies Simulation & Characterization

Room: Northern Hemisphere IV Room: Southern Hemisphere V Room: Americas Seminar

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Myung Jin Yim – Intel Corporation C. S. Premachandran – GLOBALFOUNDRIES Xuejun Fan – Lamar University Mikel Miller – Draper Laboratory Chelakara Vaidyanathan – Ciena Corporation Jiantao Zheng – Qualcomm Technologies, Inc.

1. 8:00 AM - High Productive 3D Stacking 1. 8:00 AM - Nanoparticle Based Printed 1. 8:00 AM - Model for Interaction of EMC Process Sensors on Paper for Detecting Chemical Formulation with Operating Current and Kazutaka Honda, Hirokazu Noma, Hitoshi Onozeki, Species Reliability of Cu-Al Wirebonds Operating in Shizu Fukuzumi, and Yoshinobu Ozaki – Hitachi Jack Lombardi, Mark Poliks, Wei Zhao, Shan Yan, Ning Harsh Environments Chemical Co., Ltd. Kang, Jing Li, Jin Luo, Chuan-Jian Zhong, Ziang Pan, Pradeep Lall, Shantanu Deshpande, and Yihua Luo – Madina L. Zabran, Sandeep S. Mittal, Kanad Ghose – Auburn University; Luu Nguyen – Texas Instruments, State University of New York at Binghamton; Mihdhar Inc. Almihdhar and Benjamin Hsiao – Stony Brook University

2. 8:25 AM - Direct Bonding and Debonding 2. 8:25 AM - Phototriggerable Transient 2. 8:25 AM - Interfacial Delamanination of Approach of Ultrathin Glass Substrates for Electronics: Materials and Concepts Mold Compound in Fan-Out Packages High Temperature Devices Oluwadamilola Phillips, Jared Schwartz, Anthony V.N.N. Trilochan Rambhatla, David Samet, P Messaoud Bedjaoui and Sylvain Poulet – CEA-Leti Engler, Gerald Gourdin, and Paul Kohl – Georgia Markondeya Raj, Satomi Kawamoto,, Rao R. Tummala, Institute of Technology and Suresh K. Sitaraman – Georgia Institute of Technology

3. 8:50 AM - Wafer-Level Vacuum-Packaged 3. 8:50 AM - Synthesis of a Soft 3. 8:50 AM - Non-Linear Viscoelastic Piezoelectric Energy Harvesters Utilizing Nanocomposite for Flexible, Wearable Modeling of Epoxy Based Molding Two-Step Three-Wafer Bonding Bioelectronics Compound for Large Deformations Nan Wang, Chengliang Sun, Li Yan Siow, Hongmiao Fabrice Fondjo and Jong-Hoon Kim – Washington Encountered in Power Modules Ji, Darmayuda I Made, Peter Chang, Qingxin Zhang, State University; Dong Sup Lee, Connor Howe, and Przemyslaw Gromala, Alexandru Prisacaru, and Yuandong Gu, and Lionel You Liang Wong – Institute Woon-Hong Yeo – Virginia Commonwealth University Mateus Jeronimo – Robert Bosch GmbH; Hyun-Seop of Microelectronics, A*STAR Lee, Yong Sun, and Bongtae Han – University of Maryland

Refreshment Break: 9:15 a.m. - 10:00 a.m. Northern Hemisphere A-C

4. 10:00 AM - Advances in Thin Wafer 4. 10:00 AM - BiCMOS Integrated Microflu- 4. 10:00 AM - Warpage Modeling and Char- Debonding and Ultrathin 28-nm FinFET idic Packaging by Wafer Bonding for Lab- acterization of the Viscoelastic Relaxation Substrate Transfer on-Chip Applications for Cured Molding Process in Fan-Out Pack- Alain Phommahaxay, Anne Jourdain, Goedele Potoms, Mesut Inac – Technical University Berlin; Arnaud ages Greet Verbinnen, Erik Sleeckx, Eric Beyne, and Gerald Pothier - Univeristy of Limoges/CNRS; Matthias Shu-Shen Yeh, Po-Yao Lin, Kuang-Chun Lee, Jin- Beyer – IMEC; Alice Guerrero, Dongshun Bai, Kim Wietstruck, Alexander Göritz, Barbaros Cetindogan, Hua Wang, Wen-Yi Lin, Ming-Chih Yew, Po-Chen Yess, and Kim Arnold – Brewer Science Canan Baristiran-Kaynak, Steffen Marschmeyer, Lai, Shyue-Ter Leu, and Shin-Puu Jeng – Taiwan Mirko Fraschke, Thomas Voss, Andreas Mai, Mehmet Semiconductor Manufacturing Company, Ltd. Kaynak, and Cristiano Palego – IHP Microelectronics

5. 10:25 AM - Thermally Reversible and 5. 10:25 AM - Enhanced Thermal 5. 10:25 AM - Wafer Form Warpage Crosslinked Polyurethane Based on Diels- Performance Polyimide (PI) for Improved Characterization Based on Composite Factors Alder Chemistry for Ultrathin Wafer Flexible Electronic Application Including Passivation Films, Re-Distribution Temporary Bonding at Low-Temperature Manuela Loeblein, Theo Levert, Emiliano Pallecchi, Layers, Epoxy Molding Compound Utilized in Jinhui Li, Qiang Liu, Guoping Zhang, and Rong Sun Siu Hon Tsang, and Edwin Hang Tong Teo – Nanyang Innovative Fan-Out Package – Shenzhen Institutes of Advanced Technology; Technological University Cheng-Hsiang Liu, Lu-Yi Chen, Chang-Lun Lu, Hung- Chingping Wong – Chinese University of Hong Kong; Chi Chen, Cheng-Yi Chen, and Shou-Chi Chang – Bin Zhao – Shanghai Micro Electronics Equipment Siliconware Precision Industries Co., Ltd.

6. 10:50 AM - Synchrotron X-Ray 6. 10:50 AM - Nanolaminated CoNiFe 6. 10:50 AM - Co-Design for Low Warpage Microdiffraction Investigation of Scaling Cores with Dip-Coated Fluoroacrylic and High Reliability in Advanced Package Effects on Plasticity and the Correlation to Polymer Interlamination Insulation: with TSV-Free Interposer (TFI) TSV Extrusion Fabrication, Electrical Characterization, and Faxing Che, Masaya Kawano, M.Z. Ding, Yong Han, Laura Spinella, Jang-hi Im, and Paul Ho – University Performance Reliability and S. Bhattacharya – Institute of Microelectronics, of Texas, Austin; Tengfei Jiang – University of Central Minsoo Kim and Mark G. Allen – University of A*STAR Florida; Nobumichi Tamura – Lawrence Berkeley Pennsylvania; Jooncheol Kim – Georgia Institute of National Laboratory Technology

7. 11:15 AM - Development of High 7. 11:15 AM - Test-Protocol for Assessment 7. 11:15 AM - Finite Elements for Frequency Device Using Glass or Fused Silica of Flexible Power Sources in Foldable Electromigration Analysis with 3D Integration Wearable Electronics under Stresses of Daily Elena E. Antonova and David C. Looman – ANSYS Shintarou Takahashi, Yoichiro Sato, Kohei Horiuchi, and Motion During Operation Inc. Motoshi Ono – Asahi Glass Co., Ltd. Pradeep Lall and Hao Zhang – Auburn University

15 Program Sessions: Thursday, June 1, 1:30 p.m. - 5:10 p.m.

Session 19: Recent Advances in FOWLP Session 20: MEMS and Sensor Session 21: 3D Cu-Cu and Micro Bump Technology Technologies Bonding Technologies

Committee: Committee: Committee: Materials & Processing Advanced Packaging Interconnections

Room: Southern Hemisphere IV Room: Southern Hemisphere I Room: Southern Hemisphere II

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Praveen Pandojirao-S – Johnson & Johnson Joseph W. Soucy – Draper Katsuyuki Sakuma – IBM Corporation Yi Li – Intel Corporation Allyson Hartzell – Veryst Engineering Ho-Young Son – SK Hynix

1. 1:30 PM - Innovative Excimer Laser Dual 1. 1:30 PM - Fabrication of 3D Hybrid Pixel 1. 1:30 PM - Morphology of Low- Damascene Process for Ultra-Fine Line Multi- Detector Modules Based on TSV Processing Temperature All-Copper Interconnects layer Routing with 10µm Pitch Micro-Vias for and Advanced Flip Chip Assembly of Thin Formed by Dip Transfer Wafer-Level and Panel-Level Packaging Read Out Chips Luca Del Carro, Jonas Zuercher, Thomas Brunschwiler, Markus Woehrmann, Robert Gernhardt, Karin Hauck, Kai Zoschke, Hermann Oppermann, Thomas Fritzsch, Mario Rothermund, and Sebastian Gerke – IBM Corporation; Tom Michael Toepper, and Tanja Braun – Fraunhofer IZM; and Ulf Oestermann – Fraunhofer IZM; Pawel Grybos, Krzysztof Kasinski, Wildsmith – Intrinsiq Materials; Gustavo Ramos – Habib Hichri and Markus Arendt – Suss MicroTec; Piotr Maj, and Robert Szczygiel – AGH University of Science and Technology; Atotech Klaus-Dieter Lang – Technical University Berlin Steve Voges and Klaus-Dieter Lang – Technical University Berlin

2. 1:55 PM - Forming a Vertical Interconnect 2. 1:55 PM - A Novel Technology for 2. 1:55 PM - Enabling Chip-to-Substrate Structure Using Dry Film Processing for Fan- Creating Sensors and Actuators in Processor All-Cu Interconnections: Design of Out Wafer Level Packaging Packages Engineered Bonding Interfaces for Improved Yew Wing Leong, Hsiang-Yao Hsiao, David Soon Wee Feras Eid, Qing Ma, Sasha Oster, Georgios Dogiamis, Manufacturability and Low-Temperature Ho, Boon Long Lau, and Huamao Lin – Institute of Thomas Sounart, and Johanna Swan – Intel Bonding Microelectronics, A*STAR Corporation Ninad Shahane, Kashyap Mohan, Antonia Antoniou, Pulugurtha Markondeya Raj, Vanessa Smet, and Rao Tummala – Georgia Institute of Technology; Gustavo Ramos, Arnd Kilian, and Robin Taylor – Atotech; Frank Wei – Disco Corporation

3. 2:20 PM - Embedded Trench 3. 2:20 PM - Stress-Compensating MEMS 3. 2:20 PM - Low-Temperature and Redistribution Layers (RDL) by Excimer Laser Sensor Assembly Low-Pressure Cu-Cu Bonding by Pure Cu Ablation and Surface Planer Processes Harald Etschmaier, Anderson Singulani, and Coen Tak Nanosolder Paste for Wafer-Level Packaging Yuya Suzuki, Rao Tummala and Venky Sundaram – ams AG; Kai Zoschke, Hermann Oppermann, and Junjie Li, Tielin Shi, Xing Yu, Chaoliang Cheng, Jinhu – Georgia Institute of Technology; Habib Hichri, Danny Jaeger – Fraunhofer IZM Fan, Guanglan Liao, and Zirong Tang – Huazhong Markus Arendt, and Lee Seongkuk – Suss MicroTec; University of Science and Technology Frank Wei, Ye Chen, and Kwon Sang Lee – Disco Corporation; Ognian Dimov, Deepak Arora, and Sanjay Malik – Fujifilm Electronic Materials Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

4. 3:30 PM - Temporary Bonding and 4. 3:30 PM - 3D Monolithic Metal Orifice 4. 3:30 PM - Dual Damascene Compatible, Debonding Technologies for Fan-Out Wafer- Plate For SERS Application: A Showcase of Copper Rich Alloy Based Surface Passivation Level Packaging Low Cost MEMS Packaging Mechanism for Achieving Cu-Cu Bonding at Qi Wu, Xiao Liu, Kuo Han, Dongshun Bai, and Tony Ning Ge, Steven Simske, Jarrid Wittkopf, Kevin 150°C for 3D IC Integration Flaim – Brewer Science Dooley, Anita Rogacs, Helen Holder, Steven Barcelo, Asisa Kumar Panigrahi, Tamal Ghosh, Siva Rama Robert Ionescu, and Dennis Lazaroff – Hewlett Krishna Vanjari, and Shiv Govind Singh – Indian Institute Packard Inc. of Technology, Hyderabad

5. 3:55 PM - Development and Evaluation 5. 3:55 PM - A Phase Sensitive Measurement 5. 3:55 PM - Thermal and Electrical of Carrier Glass Substrate for Fan-Out WLP/ Technique for Boosted Response Speed of Performance of Direct Bond Interconnect PLP Process Graphene FET Gas Sensor Technology for 2.5D and 3D Integrated Kazutaka Hayashi, Shigeki Sawamura, and Shuhei Yumeng Liu, Takeshi Hayasaka, Yong Cui, Jiachen Yu, Circuits Nomura – Asahi Glass, Co., Ltd.; Naoya Suzuki and Yoshihiro Kubota, Huiliang Liu, Xiaoqian Li, Kaiming Akash Agrawal, Shaowu Huang, Guilian Gao, Liang Masaaki Takekoshi – Hitachi Chemical Co., Ltd. Hu, and Liwei Lin – UC Berkeley, BSAC; Vaishno Wang, and Laura Mirkarimi – Invensas Corporation Dasika and Luu Nguyen – Texas Instruments, Inc.

6. 4:20 PM - Warpage Suppression during 6. 4:20 PM - Comparison of Packaging 6. 4:20 PM - Electrical Performance of High FO-WLP Fabrication Process Concepts for High-Temperature Pressure Density 10 µm Diameter 20 µm Pitch Cu- Masaaki Takekoshi, Keisuke Nishido, Yuhei Okada, Sensors at 500 °C Pillar with Chip to Wafer Assembly Naoya Suzuki, and Toshihisa Nonaka – Hitachi Nilavazhagan Subbiah, Surajit Ghosh, Juergen Wilde, Lucile Arnaud, Arnaud Garnier, Rémi Franiatte, Alain Chemical Co., Ltd. and Roderich Zeiser – University of Freiburg, IMTEK Toffoli, Stéphane Moreau, Franck Bana, and Séverine Chéramy – CEA-Leti

7. 4:45 PM - Impact of Process Control on 7. 4:45 PM - High Vacuum and High 7. 4:45 PM - Critical Factors Affecting UBM/RDL Contact Resistance for Next- Robustness Al-Ge Bonding for Wafer Level Structural Transformations in 3D IC Micro Generation Fan-Out Devices Chip Scale Packaging of MEMS Sensors Joints Patrik Carazzetti, Frantisek Balon, Mike Hoffmann, Jinghui Xu, Zhipeng Ding, Vivek Chidambaram, Hong-Wei Yang, H.Y. Yu, and C. Robert Kao – Juergen Weichart, Andreas Erhart, and Ewald Strolz – Hongmiao Ji, and Yuandong Gu – Institute of National Taiwan University Evatec AG; Kay Viehweger – Fraunhofer IZM-ASSID Microelectronics, A*STAR

16 Program Sessions: Thursday, June 1, 1:30 p.m. - 5:10 p.m.

Session 22: Solder Joint & Interconnect Session 23: Additive Manufacturing Session 24: Novel Methods to Assess Reliability, Characterization and Modeling and Panel-Level Packaging Reliability

Committee: Thermal/Mechanical Committee: Committee: Simulation & Characterization Emerging Technologies Applied Reliability

Room: Americas Seminar Room: Southern Hemisphere V Room: Southern Hemisphere III

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Yong Liu – ON Semiconductor Florian Herrault – HRL Laboratories, LLC Sridhar Canumalla – Microsoft Corporation Erkan Oterkus – University of Strathclyde W. Hong Yeo – Virginia Commonwealth Keith Newman – AMD University

1. 1:30 PM - Peridynamic Solution of 1. 1:30 PM - Will Low-Cost 3D Additive 1. 1:30 PM - Condition Monitoring Algorithm Wetness Equation with Time Dependent Manufactured Packaging Replace the Fan- for Piezoresistive Silicon-Based Stress Sensor Saturated Concentration in ANSYS Out Wafer Level Packages? Data Obtained from Electronic Control Units Framework Tobias Tiedje, Sebastian Lüngen, Martin Schubert, Alexandru Prisacaru, Alicja Palczynska, and Przemyslaw Cagan Diyaroglu and Erdogan Madenci – University Marco Luniak, Krzysztof Nieweglowski, and Karlheinz Jakub Gromala – Robert Bosch GmbH; Bongtae Han of Arizona; Selda Oterkus and Erkan Oterkus – Bock – Technical University Dresden – University of Maryland; G.Q. (Kouchi) Zhang – Delft University of Strathclyde University of Technology

2. 1:55 PM - A Modified Acceleration Factor 2. 1:55 PM - 3D Printing as a New Packaging 2. 1:55 PM - Mechanical Characterization of Empirical Equation for BGA Type Package Approach for MEMS and Electronic Devices SAC Solder Joints at High Temperature Using Min-Hsuan Hsu and Kuo-Ning Chiang – National Tsing Gabrielle Aspar, Baptiste Goubault, Olivier Lebaigue, Nanoindentation Hua University; Chang-Chun Lee – National Chung Gilles Simon, Léa Di Cioccio, Yves Bréchet, and Jean- Sudan Ahmed, Md Hasnine, Jeffrey C. Suhling, and Hsing University Charles Souriau – CEA-Leti Pradeep Lall – Auburn University

3. 2:20 PM - Effect of Mean Temperature 3. 2:20 PM - 3D Printed High Frequency 3. 2:20 PM - New Method to Separate on the Evolution of Strain-Amplitude in SAC Coaxial Transmission Line Based Circuits Failure Modes by Transient Thermal Analysis Ball-Grid Arrays During Operation under Michael Craton, Jennifer A. Byford, Vincens Gjokaj, of High Power LEDs Thermal Aging and Temperature Excursions Premjeet Chahal, and John Papapolymerou – Michigan Alexander Hanss, E. Liu, Gordon Elger, Maximilian Pradeep Lall, Kazi Mirza, and Jeff Suhling – Auburn State University Schmid, and Dominik Müller – Technische Hoch- University; David Locker – US ARMY AMRDEC schule Ingolstadt; Udo Karbowski and Robert Derix – Lumileds

Refreshment Break: 2:45 p.m. - 3:30 p.m. Northern Hemisphere A-C

4. 3:30 PM - Characterization of Dual Side 4. 3:30 PM - Design and Demonstration of 4. 3:30 PM - Improving Terahertz Signal Molding SiP Module Highly Miniaturized, Low Cost Panel Level Travel Distance for Fault Isolation Jin-Yuan Lai, Tang-Yuan Chen, Ming-Han Wang, Meng- Glass Package for MEMS Sensors Hemachandar Tanukonda Devarajulu, Mayue Xie, Kai Shih, David Tarng, and Chih-Pin Hung – Advanced Chintan Buch, Daniel Struk, Klaus-Jürgen Wolter, Peter Chengqing Hu, and Deepak Goyal – Intel Corporation; Semiconductor Engineering, Inc J. Hesketh, Venkatesh Sundaram, and Rao Tummala Eiji Kato and Masaichi Hashimoto – Advantest – Georgia Institute of Technology; Catherine Shearer Corporation and James Haley – EMD-Ormet Circuits; Mel Findlay – KWJ Engineering; Marc Papageorge – SPEC Sensors

5. 3:55 PM - Flip Chip Solder Joint Pad 5. 3:55 PM - Miniature Heterogeneous Fan- 5. 3:55 PM - Effective Evaluation Method: Optimizations for Connectivity SiP Out Packages for High-Performance, Large- A New Delamination Test Method for MUF Applications Format Systems (Molded Underfill) Package Quan Qi and Carlton Hanna – Intel Corporation Carl Prevatte, Matthew A. Meitl, Erich Radauscher, David Junghwa Kim, Seung Han, Woochul Na, SoYoon Kim, Gomez, Kanchan Ghosal, Salvatore Bonafede, Brook Ki Hyeok Kwon, Deokhoon Park, Donghwan Lee, and Raymond, Tanya Moore, António Jose Trindade, and Sang Kyun Kim – Samsung SDI Christopher A. Bower – X-Celeprint; Paul Hines – Micross Advanced Interconnect Technology

6. 4:20 PM - Anisotropic and Multiscale 6. 4:20 PM - Extremely High Temperature 6. 4:20 PM - Measuring Sodium Migration in Constitutive Framework for the Reliability of and High Pressure (x-HTHP) Endurable Mold Compounds Using a Sodium Amalgam Microscale Interconnects Based on Damage SOI Device & Sensor Packaging for Harsh Electrode as an Infinite Source Mechanics Environment Applications Stefan Schwab and Michael Nelhiebel – Kompetenzzentrum Zhengfang Qian – Shenzhen University; Hongtao Chen Keng Yuen Au and Eva Wai Leong Ching – Institute of Automobil- u. Industrieelektronik; Julia Appenroth, Peter – Harbin Institute of Technology Microelectronics, A*STAR Weinberger, Herbert Hutter, Maximilian Bonta, and Andreas Limbeck – Technische Universität Wien; Sabine Holzer, Michael Bauer, and Stefan Miethaner – Infineon Technologies

7. 4:45 PM - SACQ Solder Board Level 7. 4:45 PM - A Study on the Novel Nylon 7. 4:45 PM - A New Method for Prediction Reliability Evaluation and Life Prediction Anchoring Polymer Layer (APL) Anisotropic of Corrosion Processes in Metallization Model for Wafer Level Packages Conductive Films (ACFs) for Ultra Fine Pitch Systems for Substrates and Electrical Wei Lin, Quan Pham, Bora Baloglu, and Michael Chip-On-Glass (COG) Applications Contacts Johnson – Amkor Technology, Inc. Dal-jin Yoon, Sang-Hoon Lee, and Kyung-Wook Paik – Sandy Klengel, Tino Stephan, and Uwe Spohn – Korea Advanced Institute of Science & Technology Fraunhofer IMWS

17 Program Sessions: Friday, June 2, 8:00 a.m. - 11:40 a.m.

Session 25: Characterization and Session 26: 3D Integration Processing Session 27: Advances in Thermal Reliability of Fan-Out & WLP and Reliability Compression and Wirebonding

Committee: Committee: Committee: Applied Reliability Advanced Packaging Interconnections

Room: Southern Hemisphere V Room: Southern Hemisphere I Room: Southern Hemisphere II

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Lakshmi N. Ramanathan – Microsoft Rozalia Beica – Dow Electronic Materials Matthew Yao – GE Energy Management Corporation Dean Malta – Micross Advanced Interconnect William Chen – Advanced Semiconductor Toni Mattila – Aalto University Technology Engineering, Inc.

1. 8:00 AM - The Paradoxical Role of 1. 8:00 AM - Sub-Micron Electrical 1. 8:00 AM - Heterogeneous Integration Sulphur in Molding Compounds: Influence Interconnection Enabled Ultra-High I/O at Fine Pitch (2-10 µm) Using Thermal on High Temperature Reliability of Cu-Al Density Wafer Level SiP Integration Compression Bonding Wirebond Interconnects Chung Jung Wu, Tung Liang Shao, Hsiao Yun Chen, Adeel Ahmad Bajwa, SivaChandra Jangam, Saptadeep Amar Mavinkurve, Leon Goumans, Bongkoj Sheng Tsung Hsiao, Yi Li Hsiao, Chih Hang Tung, Chen Pal, Niteesh Marathe, Tingyu Bai, Takafumi Fukushima, Bumrungkittikul, Mark-Luke Farrugia, Erik van Olst, Hua Yu, and Wei Heng Lin – Taiwan Semiconductor Mark Goorsky, and Subramanian Iyer – University of Michiel van Soestbergen, and Rene Rongen – NXP Manufacturing Company, Ltd. California, Los Angeles Semiconductors

2. 8:25 AM - Mechanistic Investigation and 2. 8:25 AM - Temporary Bonding and 2. 8:25 AM - Reliable Cu-Cu Prevention of Al Bond Pad Corrosion in Cu De-Bonding for Multichip-to-Wafer 3D Thermocompression Bonding by Low Wire-Bonded Device Assembly Integration Process Using Spin-On Glass and Temperature Sintered Cu Nanowires Oliver Chyan, Nick Ross, Alex Lambert, Seare Berhe, Hydrogenated Amorphous Si Li Du, Tielin Shi, Zirong Tang, and Guanglan Liao – and Muthappan Asokan – University of North Texas; Murugesan Mariappan, Takafumi Fukushima, and Huazhong University of Science and Technology Mahmud Chowdhury, Shawn O’Connor, and Luu Mitsumasa Koyanagi – Tohoku University Nguyen – Texas Instruments, Inc.

3. 8:50 AM - Use Condition Risk Assessment 3. 8:50 AM - Cu/Adhesive Hybrid Bonding 3. 8:50 AM - Effect of Metallic Materials for Moisture Related Failures at 180 °C in H-Containing HCOOH Vapor Films on the Properties of Copper/Tin Min Pei, Sibasish Mukherjee, Nitin Uppal, and Milena Ambient for 2.5D/3D Integration Micro-Bump Thermo-Compression Bonding Vujosevic – Intel Corporation Ran He, Masahisa Fujino, Masatake Akaike, and Yong Guan, Qinghua Zeng, Jing Chen, Yufeng Jin, and Tadatomo Suga – University of Tokyo; Taiji Sakai and Wei Meng – Peking University; Shenglin Ma – Xiamen Seiki Sakuyama – Fujitsu Semiconductor University

Refreshment Break: 9:15 a.m. - 10:00 a.m. Southern Hemisphere Foyer

4. 10:00 AM - Drop Impact Reliability Test 4. 10:00 AM - 3D Packaging Challenges for 4. 10:00 AM - Thermal Bond Reliability of and Failure Analysis for Large Size High Den- High-End Applications High Reliability New Palladium-Coated Cop- sity FOWLP Package on Package Rahul Agarwal, Sukeshwar Kannan, and Luke England per Wire Zhaohui Chen, Faxing Che, Mian Zhi Ding, David Soon – GLOBALFOUNDRIES; Rick Reed, Yong Song, Motoki Eto, Ryo Oishi, and Takashi Yamada – Nippon Wee Ho, Tai Chong Chai, and Vempati Srinivasa – SangHyoun Lee, WangGu Lee, and JinKun Yoo – Micrometal Corporation; Tomohiro Uno and Tetsuya Institute of Microelectronics, A*STAR Amkor Technology, Inc. Oyamada – Nippon Steel & Sumitomo Metal; Teruo Haibara – Nippon Micrometal Corporation

5. 10:25 AM - The Comparative Study To 5. 10:25 AM - A Novel Method for Air-Gap 5. 10:25 AM - Correlation Study of Enhance Board Level Reliability Performance Formation around Via-Middle (VM) TSVs Pd Metallurgical Distributions and RF of Wafer Level Package at 0.25 mm Pitch for Effective Reduction in Keep-Out Zones Characteristics of Pd Coated/Doped Ag-alloy Using Micro-Ball Drop and Electroplated (KOZ) Wire Bonds Solder Technology King-Jien Chui, Woon Leng Loh, Xiangyu Wang, Yi-Jung Sung and Lih-Tyng Hwang – National Sun Yat- Kuei Hsiao Kuo, Yi Sin Ting, Chui Feng Weng, Feng Zhaohui Chen, and Mingbin Yu – Institute of Sen University; Chang-Yi Feng – NXP Semiconductors; Lung Chien, Katch Wan, Chun Sheng Ho, and Rick Lee Microelectronics, A*STAR Eson Chuang – Precision Packaging Materials Corp. – Siliconware Precision Industries Co., Ltd.

6. 10:50 AM - Quality and Reliability 6. 10:50 AM - Warpage Study of Large 2.5D 6. 10:50 AM - Advances in Wire Bonding Assessment of Cu Pillar Bumps for Fine Pitch IC Chip Module Technology for 3D Die Stacking and Fan-Out Applications Chieh-Lung Lai, Hung-Yuan Li, Sam Peng, Terren Lu, Wafer Level Package Othmane Jerhaoui, Stephane Moreau, David Bouchu, and Stephen Chen – Siliconware Precision Industries Ivy Qin, Oranna Yauw, Gary Schulze, Aashish Shah, Gilles Romero, Denis Marseilhan, Thierry Mourier, and Co., Ltd. Bob Chylak, and Nelson Wong – Kulicke and Soffa, Arnaud Garnier – CEA-Leti Inc.

7. 11:15 AM - Effect of Prolonged Storage 7. 11:15 AM - Board Level Reliability 7. 11:15 AM - Development of Packaging up to 1-Year on the High Strain Rate Optimization for 3D IC Packages with Extra Technology for High Temperature Resistant Properties of SAC Leadfree Alloys at Large Interposer SiC Module of Automobile Application Operating Temperatures up to 200°C Laurene Yip, Ganesh Hariharan, Raghu Chaware, Kohei Tatsumi, Tomonori Iizuka, Kazuhito Kamei, and Masakazu Inagaki – Pradeep Lall, Di Zhang, Vikas Yadav, and Jeff Suhling Inderjit Singh, and Tom Lee – Xilinx, Inc. Waseda University; Akihiro Imakire and Masayuki Hikita – Kyushu Institute – Auburn University; David Locker – US Army of Technology; Rikiya Kamimura – FAIS; Nobuaki Sato, Hiroaki Narimatsu, AMRDEC Kazutoshi Ueda and Koji Shimizu – Mitsui High-tec Inc.; Kazuhiko Sugiura and Kazuhiro Tsuruta – DENSO Corporation; Keiji Toda – Toyota 18 Program Sessions: Friday, June 2, 8:00 a.m. - 11:40 a.m.

Session 28: Advanced Materials for Session 29: Warpage Control and Session 30: RF Components and Reliability Improvement Substrates Module Integration

Committee: Committee: Committee: Materials & Processing Assembly & Manufacturing Technology High-Speed, Wireless & Components

Room: Southern Hemisphere IV Room: Southern Hemisphere III Room: Americas Seminar

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Kwang-Lung Lin – National Cheng Kung Paul Tiner – Texas Instruments Craig Gaw – NXP Semiconductor University Paul Houston – Engent Wendem Beyene – Rambus Inc. Bing Dang – IBM Corporation

1. 8:00 AM - High Performance Insulating 1. 8:00 AM - Innovative Advances in 1. 8:00 AM - Next Generation High-Q Adhesive Film for High-Frequency Copper Electroplating for IC Substrate Compact Size IPD Diplexer for RF Front End Applications Manufacturing SiP Junya Sato, Shin Teraki, Masaki Yoshida, and Hisao Kousik Ganesan, Yang Sun, Chandrashekhar Pendyala, Sheng-Chi Hsieh, Pao-Nan Lee, Chen-Chao Wang, Kondo – NAMICS Corporation Thomas Heaton, Radek Chalupa, Marcel Wall, Teck Chong Lee, and Hsu-Chiang Shih – Advanced Suddhasattwa Nad, and Rahul Manepalli – Intel Semiconductor Engineering, Inc. Corporation; Amaneh Tasooji – Arizona State University

2. 8:25 AM - Epoxy/Cyanate Ester 2. 8:25 AM - Reflow Warpage Induced 2. 8:25 AM - Self-Actuating 3D Printed Copolymer Material for Molding Compounds Interconnect Gaps between Package/PCB Packaging for Deployable Antennas in High-Temperature Operations and PoP Top/Bottom Packages Ryan Bahr, Manos Tentzeris, Abdullah Nauroze, and Chia-Chi Tuan, Fan Wu, Kyoung-Sik Moon, and Ching- Kaiqiang Peng, Wei Xu, Zhenkai Qin, Lei Feng, Linlin Wenjing Su – Georgia Institute of Technology Ping Wong – Georgia Institute of Technology Lai, and Wei Hu Koh – Huawei Technologies

3. 8:50 AM - High Thermal Conductivity 3. 8:50 AM - Warpage Tuning Study for 3. 8:50 AM - A Simple and Efficient RF Mold Compounds for Advanced Packaging Multi-Chip Last Fan-Out Wafer Level Technique for the TSV Characterization Applications Package Xiao Sun, Stefaan Van Huylenbroeck, Geert Van der Makoto Shibuya and Luu Nguyen – Texas Instruments, Hung-Yuan Li, Allen Chen, Sam Peng, George Pan, Plas, and Eric Beyne – IMEC; Cesar Roda Neve – M3 Inc. and Stephen Chen – Siliconware Precision Industries Systems Co., Ltd.

Refreshment Break: 9:15 a.m. - 10:00 a.m. Southern Hemisphere Foyer

4. 10:00 AM - Enhanced Thermal Conductiv- 4. 10:00 AM - Warpage Characterization of 4. 10:00 AM - The Smallest Form Factor GPS ity of the Underfill Materials using Insulated Glass Interposer Package Development for Mobile Devices Core/Shell Filler Particles for High Perfor- Meng-Kai Shih, Charles Hsu, Yungshun Chang, Karenyu Eb Andideh, Chuck Carpenter, Jason Steighner, Mike mance Flip Chip Applications Chen, Ian Hu, David Tarng, CP Hung, and Teck Lee – Yore, James Tung, Lynda Koerber, David Schnaufer, Jeff Tae-Ryong Kim, Kisu Joo, and Se Young Jeong Advanced Semiconductor Engineering, Inc. Moran, Suwanna Jittinorasett, Bharati Ingle, Anousa – Ntrium, Inc.; Boo Taek Lim and Boung Ju Lee – Sengsavanh, and Otto Berger – Qorvo, Inc. National Nanofab Center; Sung-Soon Choi – Korea Electronics Technology Institute; Myung Jin Yim – Intel Corporation; Euijoon Yoon – Seoul National University

5. 10:25 AM - High Thermal Performance 5. 10:25 AM - The Influence of Resin 5. 10:25 AM - Transparent Antennas for Package with Anisotropic Thermal Coverage on Reliability for Solder Joints Wireless Systems Based on Patterned Indium Conductive Material Formed by One-Pass Reflow Using Resin Tin Oxide and Thin Flexible Glass Ian Hu, Jia-Rung Ho, Jin-Feng Yang, Meng-Kai Shih,, Reinforced Low Temperature Solder Paste Mark Poliks, Yi-Lin Sung, Jack Lombardi, Robert David Tarng, and Chih-Pin Hung – Advanced Atsushi Yamaguchi, Yasuo Fukuhara, Andy Behr, Malay, Charles R. Westgate, and Jeremiah Dederick Semiconductor Engineering, Inc. Naomichi Ohashi, Yasuhiro Suzuki, and Hirohisa Hino – Binghamton University; Ming-Huang Huang, Sean – Panasonic Corporation Garner, Scott Pollard, and Colin Daley – Corning, Inc.

6. 10:50 AM - The Reduction of Outgas 6. 10:50 AM - Analysis of System-Level 6. 10:50 AM - Transfer Function from Pre-Applied Underfill Materials by Reliability of Single-Chip Glass BGA Reconfigurable Cavity Bandpass Filter Optimizing the Combination of Base Resin Packages with Advanced Solders and Embedded with Metallic Grid and Flux Compound Polymer Collars Shang-Yu Hung, Guann-Pyng Li, Mark Bachman, Kohei Higashiguchi, Takenori Takiguchi, Masashi Vidya Jayaram, Scott McCann, Bhupender Singh, Hsiang-Yu Chan, and Yu Guo – University of Okaniwa, Katsutoshi Ihara, Tsuyoshi Kida, Shu Yoshida, Pulugurtha Markondeya Raj, Vanessa Smet, and Rao California, Irvine and Toyoji Oshima – Mitsubishi Gas Chemical Tummala – Georgia Institute of Technology; Hiro Matsuura and Yutaka Takagi – NTK/NGK

7. 11:15 AM - Study of Capillary Underfill 7. 11:15 AM - A Comprehensive Study on 7. 11:15 AM - Capillary Condensation Based Filler Separation in Advanced Flip Chip Stress and Warpage by Design, Simulation Wireless Volatile Molecular Sensor Packages and Fabrication of RDL-First Panel Level Saranraj Karuppuswami, Amanpreet Kaur, and Marie-Claude Paquet – IBM Corporation; David Fan-Out Technology for Advanced Package Premjeet Chahal – Michigan State University; Danovitch, Papa Souare, and Julien Sylvestre – Puru Lin, Cheng-Ta Ko, Yu-Hua Chen, Wei-Tse Ho, Nophadon Wiwatcharagoses – Mongkut’s University Université de Sherbrooke Chi-Hai Kuo, Kuan-Wen Chen, and Tzyy-Jang Tseng – of Technology Unimicron Technology Corp.

19 Program Sessions: Friday, June 2, 1:30 p.m. - 5:10 p.m.

Session 31: Auto Electronics Packaging Session 32: Reliability Challenges in Session 33: Advanced Bonding and and Power Modules 2.5D/3D Interconnect Soldering Technology

Committee: Committee: Interconnections Joint with Committee: Advanced Packaging Applied Reliability Materials & Processing

Room: Southern Hemisphere I Room: Southern Hemisphere II Room: Southern Hemisphere IV

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Jianwei Dong – Dow Electronic Materials Nathan Lower – Rockwell Collins, Inc. Kimberly Yess – Brewer Science Christophe Zinck – ASE Dongji Xie – NVIDIA Corporation Qianwen Chen – IBM Corporation

1. 1:30 PM - Novel Polymer Substrate-Based 1. 1:30 PM - Reliability Challenges in 2.5D 1. 1:30 PM - Novel Large-Area Attachment 1.2 kV/ 40A Double-Sided Intelligent Power and 3D IC Integration for High-Temperature Power Electronics Module Li Li, Paul Ton, Mohan Nagar, and Pierre Chia – Cisco Module Application Xin Zhao, Yifan Jiang, Bo Gao, and Douglas Hopkins Systems, Inc. Chunlei Liu, Fabian Mohn, Juergen Schuderer, and – North Carolina State University; Kenji Nishiguchi - Daniele Torresin – ABB Switzerland Ltd. Risho Kogyo Co., Ltd.; Yoshi Fukawa - TOYOTech LLC

2. 1:55 PM - Advanced Packaging Need for 2. 1:55 PM - High Frequency Electrical 2. 1:55 PM - Bismuth-Based Transient Liquid Automotive In-Cabin Application Performance and Thermo-Mechanical Phase (TLP) Bonding as High-Temperature Nokibul Islam, Ming-Che Hsieh, and Kang KeonTaek – Reliability of Fine-Pitch, Copper-Metallized Lead-Free Solder Alternatives STATS ChipPAC, Inc. Through-Package-Vias (TPVs) in Ultra-Thin Junghyun Cho, Roozbeh Sheikhi, and Sandeep Glass Substrates Mallampati – Binghamton University; Liang Yin and Sukhadha Viswanathan, Timothy B. Huang, Kaya Demir, P. Markondeya David Shaddock – General Electric Co. Raj, Fuhan Liu, Venky Sundaram, and Tummala Rao – Georgia Institute of Technology; Tomonori Ogawa – Asahi Glass Co., Ltd.

3. 2:20 PM - Reliability of eWLB (embedded 3. 2:20 PM - Reliability Evaluations on 3D ID 3. 2:20 PM - Silver Sinter Paste for SiC wafer level BGA) for Automotive Radar Package Beyond JEDEC Bonding with Improved Mechanical Applications Raghunandan Chaware, Laurene Yip, Inderjit Singh, Properties Daniel Yap, Kim Sing Wong, and Luc Petit – Kenny Ng, Michael Shen, and Antai Xu – Xilinx, Inc. Wolfgang Schmitt and Ly May Chew – Heraeus STMicroelectronics; Yaojian Lin, Roberto Antonicelli, Deutschland GmbH & Co. KG and Seung Wook Yoon – STATS ChipPAC, Inc.

Refreshment Break: 2:45 p.m. - 3:30 p.m. Southern Hemisphere Foyer

4. 3:30 PM - Packaging Innovations for High 4. 3:30 PM - Remarkable Suppression of 4. 3:30 PM - Diffusion Barrier Effect of Ni- Voltage (HV) GaN Technology Local Stress in 3D IC by Manganese Nitride- W-P and Ni-Fe UBMs during High Tempera- Dibyajat Mishra, Vivek Arora, Luu Nguyen, Shoichi Based Filler with Large Negative CTE ture Storage Iriguchi, Hiroyuki Sada, Laura Clemente, Sueann Lim, Hisashi Kino, Takafumi Fukushima, and Tetsu Tanaka – Li-Yin Gao and Zhi-Quan Liu – Chinese Academy Hung-Yun Lin, Siva Gurrum, Alok Lohia, J. Sauser and Tohoku University of Sciences; Li Liu, Jing Wang, Zhao-Xia Zhou, and S. Spencer – Texas Instruments, Inc. Chang-Qing Liu – Loughborough University

5. 3:55 PM - Thin-Film Magnetic Inductors 5. 3:55 PM - Electrical Characterization of 5. 3:55 PM - Study of C2W Bonding Using Cu for Integrated Power Management CMP-Less Via-Last TSV under Reliability Pillar with Side-Wall Plated Solder Annamalai Arasu Muthukumaraswamy, King-Jien Chui, Stress Conditions Ling Xie, Sunil Wickramanayaka, Vasarla Nagendra Wei Yi Lim, Serine Soh, Jun Yu, Yew Wing Leong, Mingbin Yu – Institute of Microelectronics, A*STAR Sekhar, and Daniel Ismael Cereno – Institute of Huamao Lin, and Sunil Wickramanayaka – Institute of Microelectronics, A*STAR Microelectronics, A*STAR

6. 4:20 PM - Feasibility Investigations on 6. 4:20 PM - A Novel Failure Analysis 6. 4:20 PM - Fabrication and Selective Laser Melting for the Development Technique for Semiconductor Packaging by Characterization of Nanoporous Metallic of Microchannel Cooling in Power Xenon Difluoride Gas Interconnects Using Electrospun Nanofiber Electronics Hongqing Zhang Zhang, Frank Pompeo, and Tom Template and Electrochemical Deposition Aarief Syed-Khaja, Antonio Perinan Freire, Christopher Wassick – IBM Corporation Sheng-Po Fang, Seahee Hwangbo, Hyowon An, and Kaestle, and Joerg Franke – Friedrich Alexander Yong-Kyu Yoon – University of Florida University

7. 4:45 PM - POL-kw Modules for High 7. 4:45 PM - Alternative 3D Small Form 7. 4:45 PM - Ga Liquid Metal Embrittlement Power Applications Factor Methodology of System in Package for Fine Pitch Interconnect Rework Liang Yin, Kaustubh Nagarkar, Arun Gowda, for IoT and Wearable Devices Application Elodie Nguena, David Danovitch, and Malak Kanso Christopher Kapusta, Paul Gillespie, Tammy Johnson, Mike Tsai, Albert Lan, Chi Liang Shih, Terence Huang, – University of Sherbrooke; Richard Langlois – IBM Risto Tuominen, and Donna Sherman – General Ryan Chiu, S. L. Chung, J. Y. Chen, Frank Chu, Cheng Corporation Electric Co.; Shingo Hayashibe, Hitoshi Ito, and Tadashi Kai Chang, Sheng Ming Yang, Daniel Chen, and Arai – Shinko Electric Industries Co., Ltd. Nicholas Kao – Siliconware Precision Industries Co., Ltd. 20 Program Sessions: Friday, June 2, 1:30 p.m. - 5:10 p.m.

Session 34: Waveguide Devices and Session 35: Thermomechanical and Session 36: Advances in Signal and Chip-to-Fiber Packaging Thermal Characterization Power Integrity

Committee: Committee: Thermal/Mechanical Committee: Optoelectronics Simulation & Characterization High-Speed, Wireless & Components

Room: Southern Hemisphere III Room: Southern Hemisphere V Room: Americas Seminar

Session Co-Chairs: Session Co-Chairs: Session Co-Chairs: Ping Zhou – LDX Optronics, Inc. Pradeep Lall – Auburn University Zhaoqing Chen – IBM Corporation Hiren Thacker Przemyslaw Gromala – Robert Bosch GmbH Amit P. Agrawal – Keyssa Inc.

1. 1:30 PM - Design, Fabrication and 1. 1:30 PM - The Combined Effect of 1. 1:30 PM - Active and Passive Techniques Connectorization of High-Performance Mechanical Package Stress and Humidity on for Noise Sensitive Circuits in Integrated Multimode Glass Waveguides for Board- Chip Corrosion Probability Voltage Regulator Based Microprocessor Level Optical Interconnects Georg Lorenz and Michél Simon-Najasek – Fraunhofer Power Delivery Lars Brusberg, Davide Fortusini, Wei Jiang, Aramais IMWS; Achim Lindner – TDK-Micronas GmbH Amit Jain, Sameer Shekhar, and Yan Z. Li – Intel Zakharian, Sergey Kuchinsky, Christian Fiebig, Shenping Corporation Li, Andrey Kobyakov, and Alan Evans – Corning, Inc.; Henning Schröder – Fraunhofer IZM

2. 1:55 PM - Axially Tapered Circular Core 2. 1:55 PM - Mechanical Characterization of 2. 1:55 PM - High Voltage Capacitors for Polymer Optical Waveguides Enabling Highly Anodic Bonding Using Chevron Microchannel Next-Generation Power Modules in Electric Efficient Light Coupling David C. Woodrum, Mohammed Nasr, Xuchen Vehicles Takaaki Ishigure, Kenji Katori, Hoshihiko Toda, and Zhang, Muhannad S. Bakir, and Suresh K. Sitaraman – Robert Spurney, Himani Sharma, P. M. Raj, and Rao Kazuki Yasuhara – Keio University Georgia Institute of Technology Tummala – Georgia Institute of Technology; Naomi Lollis – AVX Corporation

3. 2:20 PM - First Demonstration of Single- 3. 2:20 PM - Package-Level Si Micro-Fluid 3. 2:20 PM - Package and Printed Circuit Mode Polymer Optical Waveguides with Cooler with Enhanced Jet Array for High Board Design of a 19.2 Gb/s Data Link for Circular Cores for Fiber-to-Waveguide Performance 3D Systems High-Performance Computing Coupling in 3D Glass Photonic Interposers Yong Han, Boon Long Lau, and Gongyue Tang – Sungjun Chun, Jose Hejase, Junyan Tang, Jean Audet, Rui Zhang, Fuhan Liu, Venky Sundaram, and Rao Institute of Microelectronics, A*STAR; Seow Meng Dale Becker, Daniel Dreps, Glen Wiedemeier, Megan Tummala – Georgia Institute of Technology Low and Jason Goh – BeCe Pte. Ltd. Nguyen, Lloyd Walls, Francesco Preda, and Daniel Douriet – IBM Corporation

Refreshment Break: 2:45 p.m. - 3:30 p.m. Southern Hemisphere Foyer

4. 3:30 PM - 3D Optical Coupling Techniques 4. 3:30 PM - A Unified and Versatile Model 4. 3:30 PM - Signal and Power Integrity on Polymer Waveguides for Wafer and Board Study for Moisture Diffusion Analysis of High-Speed Links with Silicon Level Integration Liangbiao Chen, Jenny Zhou, Hsing-wei Chu, and Interposer Sebastian Lüngen, Sujay Charania, Tobias Tiedje, Xuejun Fan – Lamar University Wendemagegnehu Beyene, Nitin Juneja, Yeon-Chang Krzystof Nieweglowski, Sebastian Killge, Lukas Lorenz, Hahm, Ravi Kollipara, and Joohee Kim – Rambus, Inc. Johann W. Bartha, and Karlheinz Bock – Technical University Dresden

5. 3:55 PM - Position Dependence of 5. 3:55 PM - Microstructure Simulation and 5. 3:55 PM - Novel Parallel Resonance Peak Coupling Efficiency of Grating Coupler in Thermo-Mechanical Behavior Analysis of Measurement and Lossy Transmission Line Waveguide Cavity Copper Filled through Silicon Vias Using Modeling of 2-T and 3-T MLCC Capacitors Shogo Ura, Kazuki Mori, Ryo Tsujimoto, and Junichi Coupled Phase Field and Finite Element for PDN Application Inoue – Kyoto Institute of Technology; Kenji Kintaka Methods Larry Smith, Javid Mohamed, Jaemin Shin, and Tim – National Institute of Advanced Industrial Science & Shui-Bao Liang, Chang-Bo Ke, Han Jiang, Min-Bo Michalka – Qualcomm Technologies, Inc. Technology Zhou, and Xin-Ping Zhang – South China University of Technology

6. 4:20 PM - Efficient, Easy-to-Use, Planar 6. 4:20 PM - On the Process/History 6. 4:20 PM - Eye-Diagram Estimation Fiber-to-Chip Coupling Process with Angle- Dependence of Package Mechanical Methods for Voltage- and Probability- Polished Fibers Performance Dependent PAM-4 Signal on Stacked Djorn Karnick, Nils Bauditsch, Lars Eisenblätter, Mingji Wang, Lou Nicholls, MiNa Mo, MinJae Lee, Through-Silicon Vias Thomas Kühner, Marc Schneider, and Marc Weber – Quan Pham, and Yong Song – Amkor Technology, Inc. Junyong Park, Jonghoon J. Kim, Sumin Choi, Youngwoo Karlsruhe Institute of Technology (KIT) Kim, and Joungho Kim – Korea Advanced Institute of Science & Technology; Heegon Kim – MST

7. 4:45 PM - Novel, High-Throughput, Fiber- 7. 4:45 PM - Systematic Approach to Design 7. 4:45 PM - Signal Integrity Modelling in to-Chip Assembly Employing Only Off-the- High Power FPGA Package for Current- Inhomogeneous Waveguide/PCB of Arbitrary Shelf Components Carrying Capability Shape Using Broadband Green’s Function Nicolas Boyer, Alexander Janta-Polczynski, Stephan Hong Shi, Siow Chek Tan, Jae-Gyung Ahn, Gamal Kung-Hau Ding – Air Force Research Laboratory; Tien- Martel, Swetha Kamlapurkar, Sebastian Engelmann, Refai-Ahmed, and Suresh Ramalingam – Xilinx, Inc. Hao Liao and Leung Tsang – University of Michigan Paul Fortier, and Tymon Barwicz – IBM Corporation; Jean-Francois Morissette – Université de Sherbrooke; Ted Lichoulas – AFL Telecommunications 21 Interactive Presentations: Wednesday, May 31, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m., and Thursday, June 1, 9:00 a.m. - 11:00 a.m.

Wednesday, May 31, 2017 15) A New Method for 3D Microstructure Fabrica- 11) Numerical Simulations of Joint-to-Joint Tem- Session 37: Interactive Presentations 1 tion via Ionic Wind perature Variation during Thermo-Compression 9:00 AM - 11:00 AM Shangru Zhou, Guoliang Li, Huai Zheng, and Sheng Liu – Bonding Committee: Interactive Presentations Wuhan University Depayne Athia and Michael Mayer – University of Waterloo; Room: Northern Hemisphere Foyer 16) A Unique Temporary Bond Solution Based on Alireza Rezvani, Horst Clauberg, and Ivy Qin – Kulicke and Session Co-Chairs: a Polymeric Material Tacky at Room Temperature Soffa, Inc. Rao Bonda – Amkor Technology and Highly Thermally Resistant Application Exten- 12) The Complete Packaging Reliability Studies John Hunt – Advanced Semiconductor sion from 3D-SIC to FOWLP through One Digital Image Correlation System Engineering, Inc. Alain Phommahaxay, Goedele Potoms, Julien Bertheau, Yuling Niu and Jing Wang – State University of New York at Deborah S. Patterson – Principal, Patterson Pieter Bex, Fabrice Duval, Arnita Podpod, Teng Wang, Greet Binghamton; Seungbae Park – State University of New York, Group Verbinnen, Gerald Beyer, Erik Sleeckx, Eric Beyne – IMEC; Binghamton Andy Tseng – JSR Micro Atsushi Nakamura – Fujifilm Electronic Materials Europe N.V.; 13) Resistometric Characterization of the Interface Yoshitaka Kamochi – Fujifilm Corporation 1) Package-Level EMI Shielding Technology with between Au Wire Bonds to AlCuW Bond Pads Silver Paste for Various Applications 17) 3D Printed Out-of-Plane Antennas for Use on Steve Kilgore and Craig Gaw – NXP Semiconductors Kisu Joo, Tae-Ryong Kim, Jung Woo Hwang, Jin-Ho Yoon, and High Density Boards 14) Comparison and Consistency of On-PCB Se Young Jeong – Ntrium Incorporation; Myung Jin Yim – Intel Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Microstrip Line Modeling by 3D Fullwave and 2D Corporation Amanpreet Kuar, Jennifer Byford, James Lennon, and Premjeet Quasi-Static Approaches for High Speed Packaging Chahal – Michigan State University 2) Effects of Current Stress for Low Temperature System Signal Integrity Simulations Cu/Sn/Cu Solid-State-Diffusion Bonding Wednesday, May 31, 2017 Zhaoqing Chen – IBM Corporation Jian Cai, Qian Wang, and Zijian Wu – Tsinghua University; Session 38: Interactive Presentations 2 15) Real-Time Diagnosis of Wire Degradation Junqiang Wang and Dejun Wang – Dalian University of 2:00 PM - 4:00 PM Based on Digital Signal Analysis Technology Committee: Interactive Presentations Jinwoo Lee and Daeil Kwon – Ulsan National Institute of Room: Northern Hemisphere Foyer 3) High Throughput Low Stress Air Jetting Carrier Science & Technology Session Co-Chairs: Release for RDL First Fan-Out Wafer Level Packag- Nam Pham – IBM Corporation Thursday, June 1, 2017 ing Patrick Thompson – Texas Instruments, Inc. Session 39: Interactive Presentations 3 Hao Tang, Gary Shi, and Raphael He – Micro Materials Inc.; Eric Beyne – IMEC 9:00 AM - 11:00 AM Ming Yin, Wei Zhang, and My Nguyen – Zhejiang Microtech; Richard Rao – MicroSemi Committee: Interactive Presentations Mike Chang and Sheng-Shu Yang – ITRI 1) Exploring DDR4 Address Bus Design for High Room: Northern Hemisphere Foyer 4) 48×10 Gbps Cost-Effective FPC Based On-Board Speed Memory Interface Session Co-Chairs: Optical Transmitter with PGA Connector Nanju Na, Juan Wang, Sean Long, Changyi Su, Thomas To, and Mark Eblen – Kyocera America, Inc. Teng Li, Gonzalo Guelbenzu de Villota, Chenhui Li, R. Patty Yong Wang – Xilinx, Inc. Swapan Bhattacharya – Engent Inc. Stabile, and Oded Raz – Eindhoven University of Technology; Tz-Cheng Chiu – National Cheng Kung Sander Dorrestein – TE Connectivity 2) Demonstration of High Electrical Reliability of University Sub-2 Micron Cu Traces Covered with Inorganic Frank Wei – Disco Japan 5) A Novel Wafer Level Integration of Liquid-Metal Dielectrics for Advanced Packaging Technologies Injection based TSV and Integrated Passive Devices Hiroshi Kudo, Ryohei Kasai, Jyunichi Suyama, Mitsuhiro Takeda, 1) Electrical Transmission Properties of HBM In- Tao Zheng, Gaowei Xu, and Le Luo – Shanghai Institute of Yumi Okazaki, Haruo Iida, Daisuke Kitayama, Toshio Sasao, terface on 2.1-D System in Package Using Organic Microsystem and Information Technology Kouji Sakamoto, Hiroaki Sato, Shouhei Yamada - Dai Nippon Interposer Yutaka Uematsu and Nobuyuki Ushifusa – Hitachi, Ltd.; 6) Next Generation Plating Technologies for FO- Printing Co., Ltd. Hitoshi Onozeki – Hitachi Chemical Co., Ltd. Panel Level Packaging 3) The Comparison of Package Design and Electri- Ralph Zoberbier, James Welsh, Christian Ohde, and Henning cal Analysis in Mobile Application 2) The Use of Single Layer MIS in Modern Assembly Huebner – Atotech Deutschland GmbH Tsun-Lung Hsieh, Po-Chih Pan, Chih-Yi Huang, Ming-Fong Kohan Lin, Albert Lan, Mark Liao, and Boxiang Fang – Siliconware Precision Industries Co., Ltd. 7) A Density Staggered Cantilever for Micron Jhong, and Chen-Chao Wang – Advanced Semiconductor Length Gravity Probing Engineering, Inc.; Yuan-Hsi Chou – University of Texas, Austin 3) Physical and Electrical Characterization of 3D Qidong Wang and Liqiang Cao – Institute of Microelectronics/ 4) Multi-band Harmonic RF Tags for Barcode Ap- Embedded Capacitor: A High-Density MIM Capaci- Stanford University; Alexander D. Rider, David C. Moore, plications in a Cluttered Environment tor Embedded in TSV Charles P. Blakemore, and Giorgio Gratta – Stanford University Saranraj Karuppuswami, Mohd Ifwat Mohd Ghazali, Ye Lin and Chuan Seng Tan – Nanyang Technological University 8) Scalability and Yield in Elastomer Stamp Micro- Amanpreet Kaur, and Premjeet Chahal – Michigan State Transfer-Printing University 4) Electrical and Thermal Simulation of SWIFT™ David Gomez, Kanchan Ghosal, Matthew A. Meitl, Salvatore 5) High-Band AlN Based RF-MEMS Resonator for High Density Fan-out PoP Technology Bonafede, Carl Prevatte, Tanya Moore, Erich Radauscher, TSV Integration Curtis Zwenger, Bora Baloglu, George Scott, and Mike Antonio Jose Trindade, and Christopher A. Bower – Nan Wang, Yao Zhu, Chengliang Sun, Mingbin Yu, Geng Li Kelly – Amkor Technology, Inc.; WonChul Do, JiHun Yi, and X-Celeprint Chua, Srinivas Merugu, Navab Singh, and Yuandong Gu – WonGeol Lee – Amkor Technology, Korea Institute of Microelectronics, A*STAR 9) Dynamic Strain of Ultrasonic Cu and Au Ball 5) High Reliability Challenges with Cu Wire Bonding Bonding Measured In-situ by Using Silicon Piezore- 6) Equalization Enhancement Approaches for for Automotive Devices in the AEC-Q006 sistive Sensor PAM4 Signaling for Next Generation Speeds JunHo Jeon, SungHo Jeon, SeokHo Na, Mina Mo, Kwangmo Keiichiro Iwanabe, Kenichi Nakadozono, Mamoru Sakamoto, Jiayi He, Nana Dikhaminjia, Mikheil Tsiklauri, and James Lim, DaeByoung Kang, and JinYoung Kim – Amkor Technology, and Tanemasa Asano – Kyushu University Drewniak – Missouri University of S&T; Bhyrav Mutnury and Inc. Arun Chada – Dell, Inc. 10) High Transmittance Broadband THz Polarizer 6) Development of Die Attachment Technology Using 3D-IC Technologies 7) Data Transfer Performance Analysis and En- for Power IC Module by Introducing Indium into Nai-Chen Chi, Ting-Yang Yu, Hsin-Cheng Tsai, Chih-Wei Luo, hancement of Critical 3D Interconnects in a 3D Sintered Nano-Silver Joint Chun An Yang and C. Robert Kao – National Taiwan Kuan-Neng Chen, and Yu-Tao Yang – National Chiao Tung SIP based on Communication Channel Modeling University; Hiroshi Nishikawa – Osaka University University; Shiang-Yu Wang – Academia Sinica Methodology Min Miao, Zhensong Li, Xiaoyang Duan, and Tianfang Chen – 7) Effect of Nickel-Coating Modified CNTs on the 11) High Accuracy Thermal Compression Bonding Beijing Information Science and Technology University; Xiaole Dopant Dispersion and Performance of BGA Solder Technology for Large-Sized Substrate Cui, Yufeng Jin, Huan Liu, and Xin Sun – Peking University Joints Noboru Asahi, Toshiyuki Jinda, Yoshihito Mizutani, Koichi Imai, Huayu Sun and Yan-Cheong Chan – City University of Hong Hikaru Tomita, Mikio Kawakami, Masafumi Senda, Katsumi 8) A Characterization Method for Interfacial Kong; Xiao Hu – HiSilicon Technologies; Fengshun Wu – Terada, and Yasunori Hashimoto – Toray Engineering Co., Ltd. Delamination of Copper/Epoxy Mold Compound Specimens Under Mixed Mode I/III Loading Huazhong University of Science and Technology 12) Real-Time Color-Tunable White LEDs Through V N N Trilochan Rambhatla, David Samet, Scott R. McCann, 8) Assessing the Reliability of High Temperature Combination of Phosphor Patterns and Adaptive and Suresh K. Sitaraman – Georgia Institute of Technology Solder Alternatives Liquid Lens 9) Low Temperature Ultrasonic Bonding of Cu/ Maan Z. Kokash, Rajesh S. Sivasubramony, Jorge L. Then Huai Zheng and Sheng Liu – Wuhan University; Zefeng Zhang Sn Microbumps with Au Layer for High Density Cuevas, Angelo F. Zamudio, and Peter Borgesen – Binghamton and Peng Yang – Huazhong University of Science & Technology Interconnection Applications University; Alfred A. Zinn, Randall M. Stoltenberg, Jerome 13) Yield Comparison of Die-First Face-Down and Qinghua Zeng, Yong Guan, Jing Chen, and Yufeng Jin – Peking Chang, Y.-L. Tseng, and Dan Blass – Lockheed Martin Die-Last Fan-Out Wafer Level Packaging University 9) High Performance Silver Alloy Bonding Wire for Amy Lujan – SavanSys Solutions LLC 10) Chip-Scale SERF Atomic Magnetometer without Memory Devices 14) Multi Beam Full Cut Dicing of Thin Si IC Wafers Magnetic Shield Tetsuya Oyamada, Tomohiro Uno, and Takashi Yamada – Jeroen van Borkulo, Paul Verburg, and Richard van der Stam – Ling Lu, Jintang Shang, Zhihua Pan, and Yu Ji – Southeast Nippon Steel & Sumitomo Metal Corporation; Daizo Oda – ASM Pacific Technologies University Nippon Micrometal Corporation

Wednesday & Thursday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 10-17 for location. 22 Interactive Presentations: Thursday, June 1, 9:00 a.m. - 11:00 a.m. and 2:00 p.m. - 4:00 p.m., and Friday, June 2, 8:30 a.m. - 10:30 a.m.

10) Low Pressure Solid-State Bonding Using Silver 7) Cu-In-Microbumps for Low-Temperature Bond- 6) A Study on the Fine Pitch Flex-on-Flex (FOF) Preforms for High Power Device Packaging ing of Fine-Pitch-Interconnects Assembly Using Flux Added Nanofiber Solder Jiaqi Wu and Chin C. Lee – University of California, Irvine Steffen Bickel, Iuliana Panchenko, Joerg Meyer, and Volker Anisotropic Conductive Films (ACFs) and Thermo- Compression Bonding Method 11) Fabrication, Characterization and Comparison Neumann – Technical University Dresden; Wieland Ji-Soo Lee, Ji-Hye Kim, and Kyung-Wook Paik – Korea Ad- of FR4-Compatible Composite Magnetic Materials Wahrmund and M. Juergen Wolf – Fraunhofer IZM vanced Institute of Science & Technology for High Efficiency Integrated Voltage Regulators 8) Via-in-Trench: A Revolutionary Panel-Based 7) Infrared (IR) Soldering of Metallic Nanowires with Embedded Magnetic Core Micro-Inductors Package RDL Configuration Capable of 200-450 Jirui Wang, Fan Gao, and Zhiyong Gu – University of Mas- Mohamed Bellaredj, Sebastian Mueller, Anto Davis, Paul Kohl, IO/mm/layer, an Innovation for More-than-Moore sachusetts, Lowell and Madhavan Swaminathan – Georgia Institute of Technology; System Integration Yasuhiko Mano – Ibiden Fuhan Liu, Chandrasekharan Nair, Hao Lu, Rui Zhang, Hang 8) Stretchable and Electrically Conductive Compos- 12) The Novel Failure Mechanism of the Polymer Chen, Venky Sundaram, and Rao Tummala – Georgia Institute ites Fabricated from Polyurethane and Silver Nano/ Microstructures Ball Interconnected CBGA under Board Level Ther- of Technology; Atsushi Kubo and Tomoyuki Ando – Tokyo Bo Song, Kyoung-sik Moon, and C. P. Wong – Georgia Institute mal Mechanical Stress Ohka Kogyo; Kwon Sang Lee – Disco Corporation Jeffrey ChangBing Lee, Cheng-Chih Chen, Dem Lee, Cherie of Technology Chen, and Alice Lin – iST-Integrated Service Technology, Inc. 9) Simulation Analysis of a Conformal Patch Sensor 9) Numerical and Experimental Study of Fan-Out for Skin Tension and Swelling Detection Wafer Level Package Strength 13) Development of Double Side Protection Process Ruiqi Lim, Ming-Yuan Cheng, Ramona Damalerio, and Weiguo with Bump Support Film (BSF) and Backside Coat- Cheng Xu and Zhaowei Zhong – Nanyang Technological Chen – Institute of Microelectronics, A*STAR University; Won Kyoung Choi – STATS ChipPAC, Inc. ing Tape for WLP Masanori Yamagishi, Tomotaka Morishita, Motoki Nozue, 10) Effect of Material Properties of Double Layer 10) Effects of Passivation Layer and Electroplating Akinori Sato, Keisuke Shinomiya, and Shinya Takyu – Lintec Non Conductive Films (D-NCFs) on the Reflow Reli- Parameters of Copper Film on Wafer Warpage dur- Corporation ability of Ultra Fine-Pitch Cu-Pillar/Sn-Ag Micro ing Thermal Process Bump Interconnection Gong Cheng, Heng Li, Weibo Zhang, Gaowei Xu, and Le Luo – 14) Design of Miura Folding-Based Micro-Super- Shanghai Institute of Microsystem and Information Technology capacitors as Foldable and Miniaturized Energy SeYong Lee, JiWon Shin, and Kyung-Wook Paik – Korea Storage Units Advanced Institute of Science & Technology; Woojeong Kim 11) Development of Mechanical Locking Micro- Bo Song, Yun Chen, Kyoung-sik Moon, and C. P. Wong – and Taejin Choi – Doosan Anchor Structures for a QFN Package Application Yu-Lung Huang, Wei-Chih Lin, Mano Ajayan, and Bao-Hui Georgia Institute of Technology 11) Wafer-Level Micro Alkali Vapor Cells with Chang Chien – National Sun Yat-Sen University 15) Assembly and Reliability Challenges for Next Anti-Relaxation Coating Compatible with MEMS Generation High Thermal TIM Materials Packaging for Chip-Scale Atomic Magnetometers 12) Reliability of Cu/NiFe and Cu/Ni Metaconduc- Chi-An Pan, Chi-Tung Yeh, Wei-Chun Qiu, Rong-Zheng Lin, Yu Ji, Jintang Shang, Qi Gan, and Lei Wu – Southeast University tor Devices for RF Applications Liang-Yih Hung, Kong-Toon Ng, C. F. Lin, C. Key Chung, Don- Timothy Clingenpeel and Yong-Kyu Yoon – University of 12) Low-Temperature High-Throughput Assembly Florida Son Jiang, and C. S. Hsiao – Siliconware Precision Industries Technology for Transducer Array in Medical Imag- Co., Ltd. 13) A New Fan-Out Package Structure Utilizing the ing Applications Self-Alignment Effect of Molten Solder to Improve 16) Low Temperature Curable Polyimide Film Hoang-Vu Nguyen, Nu Bich Duyen Do, and Knut the Die Shift and Enhance the Thermal Properties Properties and WLP Reliability Performance with Aasmundtveit – University College of Southeast Norway Hwan-Pil Park, Jae-Yong Park, Gwancheol Seo, and Young-Ho Various Curing Conditions Kim – College of Engineering / Hanyang University Yu Chuan (Steven) Chen, Katch Wan, Chen An Chang, and 13) Highly Efficient and Stable Quantum Dot Light Rick Lee – Siliconware Precision Industries Co., Ltd. Emitting Diodes Optimized by Micro-Packaged 14) Toughening Underfills by Stress-Absorbing Core- Luminescent Microspheres Shell Fillers 17) The Effect of Polymer Rebound on SnBi58 Kai Wang and Xiaowei Sun – Southern University of Science Chia-Chi Tuan, Kyoung-Sik Moon, and Ching-Ping Wong – Solder ACFs Joints Cracks during a Thermo-Com- and Technology; Xiaobing Luo – Huazhong University of Georgia Institute of Technology pression Bonding Science and Technology; Sheng Liu – Wuhan University Shuye Zhang and Kyung-Wook Paik – Korea Advanced 15) Thermal Characteristic of Sn-MWCNT Nano- Institute of Science & Technology Friday, June 2, 2017 composite Solder in LED Package Session 41: Student Interactive Presentations Choong-Jae Lee, Jae-Jung Moon, Kwang-Ho Jung, and Seung- Thursday, June 1, 2017 Boo Jung – Sungkyunkwan University Session 40: Interactive Presentations 4 8:30 AM - 10:30 AM 2:00 PM - 4:00 PM Committee: Interactive Presentations 16) An Evaluation of Effects of Molding Compound Properties on the Reliability of Ag Wire Bonded Committee: Interactive Presentations Room: Northern Hemisphere Foyer Components Room: Northern Hemisphere Foyer Session Co-Chairs: Keisuke Yazawa – Purdue University; Carol Handwerker, John Session Co-Chairs: Yang Liu – IBM Corporation Blendell, Alexander Campbell, Wenhao Chen, Azzedin Jackson, Ibrahim Guven – Virginia Commonwealth Li Ming – ASM and Matthew Parsons – Purdue Univesity; Peng Su – Juniper Vaidyanathan Chelakara – Ciena Corporation University Networks Mark Poliks – Binghamton University Suresh K. Sitaraman – Georgia Institute of Nancy Iwamoto – Honeywell Technology 17) A Nonlinear Transmission Line Based Harmonic Jai Agrawal – Purdue University RF Tag 1) Stress Analysis of Flexible Packaging for the In- Mohd Ifwat Mohd Ghazali, Saranraj Karuppuswami, Amanpreet 1) Equivalent Thermal Conductivity Model Based tegration of Electronic Components within Woven Kaur, and Premjeet Chahal – Michigan State University Full Scale Numerical Simulation for Thermal Man- Textiles agement in Fan-Out Packages 18) Numerical Analysis and Optimization of Ther- Menglong Li, John Tudor, Russel Torah, and Steve Beeby – mal Performance of LED Filament Light Bulb Ningyu Wang, Yudan Pi, Wei Wang, and Yufeng Jin – Institute University of Southampton of Microelectronics, Peking University Jie Liu, Huai Zheng, and Sheng Liu – Wuhan University; Chunlin 2) Signal Integrity Analysis of Silicon/Glass/Organic Xu – Huazhong University Of Science And Technology 2) Local Stress Analysis by XRD Single Crystal Interposers for 2.5D/3D Interconnects 19) Effective and Efficient Modeling of Differential Method and Kossel Diffraction Applied to a Flip Sumin Choi, Joungho Kim, Junyong Park, and Daniel H. Jung – Vias Using Semi-Empirical Approach Chip Structure Korea Advanced Institute of Science & Technology; Heegon Fanghui Ren – Oregon State University; Kevin Cai, Chunchun Anne-Laure Lebaudy, Manuel Fendler, and Wiyao Kpobie – Kim – Missouri S&T; Kiyeong Kim – Samsung Electronics Sui, Jayaprakash Balachandran, and Bidyut Sen – Cisco Systems, CEA-Leti; Raphaël Pesci – Ecole Nationale Supérieure des Arts Inc. et Métiers Company, Ltd. 3) A Study on the Fabrication of Electrical Circuits 20) Design of Low-Profile Integrated Transformer 3) Study of Annular Copper Filled TSVs of Sensor and Inductor for Substrate-Embedding in 1-5kW and Interposer Chips for 3D Integration on Fabrics using Cu pattern Laminated B-stage adhesive Films for Electronic Textile Applications Isolated GaN DC-DC Converters Cao Li and Peng Fei – Huazhong University of Science & Haksun Lee, Vanessa Smet, Pulugurtha Markondeya Raj, and Seung-Yoon Jung and Kyung-Wook Paik – Korea Advanced Technology; Sheng Liu and Huai Zheng – Wuhan University Rao Tummala – Georgia Institute of Technology Institute of Science & Technology 4) Investigations on the Pumping Behaviors of Cop- 21) Stretchable Capacitive Strain Sensors Based on a per Filler in Through-Silicon-vias (TSV) 4) Electrically Testing Non-Underfilled Flip Chip Novel Polymer Composite Blend Fei Su, Ruixia Yao, Tenghui Li, and Xiaoxu Pan – Beijing Assemblies- Impacts on Interconnect Integrity Todd Houghton, Jignesh Vanjaria, Thomas Murphy, and Hong- University of Aeronautics and Astronautics Antoine Cloutier and David Danovitch – Université de bin Yu – Arizona State University Sherbrooke; Benoit Foisy – IBM Corporation 5) Warpage Prediction Methodology of Extremely 22) Thermal and Mechanical Analysis of 3D Glass Thin Packages 5) Effects of Anisotropic Conductive Films (ACFs) Packaging for Automotive Cameras Zhongli Ji, Yangming Liu, Anna Wu, Ning Ye, Hem Takiar, and Gap Heights on the Bending Reliability of Chip- Daniel Struk, Peter Hesketh, Chintan Buch, Klaus Wolter, and Peng Chen – SanDisk in-Flex (CIF) Packages for Wearable Electronics Rao Tummala – Georgia Institute of Technology 6) A Design Study of 5G Antennas Optimized Using Applications 23) Miniaturization of Planar Packaged Inductor Genetic Algorithms Ji-Hye Kim, Tae-Ik Lee, Dal-Jin Yoon, Taek-Soo Kim, and Using NiZn and Low Cost Screen Printing Technique VIncens Gjokaj, John Doroshewitz, Jeffrey Nanzer, and Kyung-Wook Paik – Korea Advanced Institute of Science & Colin Pardue, Mohamed F. Bellaredj, Anto K. Davis, and Madha- Premjeet Chahal – Michigan State University Technology van Swaminathan – Georgia Institute of Technology Thursday & Friday Refreshment Breaks: 9:15 a.m. - 10:00 a.m. and 2:45 p.m. - 3:30 p.m. • See pages 14-21 for locations. 23 2017 TECHNOLOGY CORNER EXHIBITS AND INTERACTIVE PRESENTATIONS Technology Corner Exhibits Wednesday, May 31 9:00 a.m. - 12:00 Noon / 1:30 p.m. - 6:30 p.m. Thursday, June 1 9:00 a.m. - 12:00 Noon / 1:30 p.m. - 4:00 p.m. Northern Hemisphere A – C Interactive Presentation Sessions Wednesday, May 31 Session 37: 9:00 a.m. - 11:00 a.m. / Session 38: 2:00 p.m. - 4:00 p.m. Thursday, June 1 Session 39: 9:00 a.m. - 11:00 a.m. / Session 40: 2:00 p.m. - 4:00 p.m. Friday, June 2 Session 41: 8:30 a.m. - 10:30 a.m. Northern Hemisphere Foyer, 5th Floor

24 TECHNOLOGY CORNER EXHIBITORS

3D Systems Packaging Research AGC Center (PRC) 4375 NW 235th Avenue Processing Adhesive (WPA) is a temporary film Georgia Institute of Technology Hillsboro, OR 97124 format high temperature bonding adhesive for 813 Ferst Drive, NW Phone: +1 714-745-3193 thin wafer processing of bonding device wafer to Atlanta, GA 30332-0560 Fax: +1 503-844-9308 carrier wafer. Additionally, our newest research Phone: +1 404-894-9097 www.agcem.com has yielded higher performing and lower cost Fax: +1 404-894-3842 Contact: Vern Stygar solderable flexible circuit substrate materials to www.prc.gatech.edu Email: [email protected] replace polyimide-based organic copper-clad Contact: Dr. Venky Sundaram Booth 309 laminates in high frequency microwave circuits. Prof. Rao R. Tummala AGC is a leader of glass, fluorinated polymers and Email: [email protected] quartz for the world’s automotive and electronics Akrometrix, LLC [email protected] device industries. AGC provides specialized 2700 NE Expressway Booth 320 formulations of alkali-free alumino-borosilicate Building B, Suite 500 The 3D Systems Packaging Research Center glass with a wide range of CTE’s suitable for Atlanta, GA 30345 (PRC) at the Georgia Institute of Technology LED, MEMS, and glass interposer for the next Phone: +1 404 486-0880 Ext. 21 is an Industry-Centric Global Academic Center generation high frequency electronic substrates. Fax: +1 404-486-0890 dedicated to leading-edge research, education of Our high volume capability for glass EN-A1 and www.akrometrix.com highly-interdisciplinary students and global industry value-added services such as vias drilling, AR Contact: Eric Moen +1-770-807-4707 collaborations in the System-on-a-Package coatings, and via fill technologies makes AGC a Email: [email protected] (SOP) vision to enable highly miniaturized, mega- valuable partner for your next generation mobile, Booth 220 functional systems in a single package. Led by Prof. IoT or Life Science product. AGC’s premier Akrometrix manufactures, sells, and services Rao Tummala, the PRC’s research encompasses synthetic quartz with unparalleled formulation worldwide: Thermal warpage metrology systems advanced 3D systems packaging technologies control results in the lowest insertion loss and -50°C to 300°C; Thermal strain metrology including: electrical, mechanical and thermal nearly zero autofluorences of any materials systems 25°C to 300°C; Low cost room design; ultra-thin and ultra-high density glass now available on the market. Because of AGC’s temperature warpage metrology systems; Unique interposers and packages; ultrafine pitch chip-level synthetic quartz has unparalleled low loss, software solutions and reports to enable effective and board-level interconnections; passive and outstanding the electrical performance for high use of warpage/strain data; Test services for active components and integration into power, frequency circuits can be achieved. In addition thermal warpage and strain metrology RF, photonic and analog modules. The PRC AGC’s synthetic quartz low auto fluorescence model for industry collaboration is enabled by a makes this AGC’s AQ an excellent substrate for Alpha Novatech, Inc. world-class team of cross-disciplinary academic photonic applications in Lab on a Chip reactors. 473 Sapena Ct. #12 and research faculty, students, visiting industry AGC’s fluorinated polymer is ideally suited for Santa Clara, CA 95054 engineers, and supply-chain manufacturers. The dielectric coatings, or creating micro or nano- Phone: +1 408-567-8082 current industry consortium at PRC consists of sized vias for Lab on a Chip applications in the Life Fax: +1 408-567-8053 the most comprehensive industry ecosystem Science technologies sector. AGC’s fluorinated www.alphanovatech.com of material and tool suppliers, substrate and polymer is highly transparent to 250 nanometers. Contact: Glenn Summerfield assembly manufacturers, and end users in a Email: [email protected] wide variety of consumer and high performance AI Technology Inc. Booth 402 applications including high performance cloud 70 Washington Rd. Alpha Novatech, Inc. is your partner for Thermal computing and networking. New applications Princeton Junction, NJ 08550 Solutions. We offer a wide variety of standard being integrated into the consortium are new era Phone: +1 609-799-9388 heat sinks and accessories. Our product line of automotive electronics that include connectivity Fax: +1 609-799-9308 includes natural convection, forced convection, and infotainment, autonomous driving and www.aitechnology.com and active heat sinks. We also offer various all-electric cars requiring high power and high Contact: Maurice LeBlon attachment methods and hardware for almost temperature electronics. Companies can join Email: [email protected] any application. In addition, we can offer free heat the PRC consortium for a single membership fee Booth 202 sink thermal simulations, standard or custom heat to access all the programs. Benefits to industry For over 30 years, AI Technology, Inc. (AIT) has sinks in prototype to production quantities, quick include intellectual property rights, technology provided adhesive films, available as electrically and easy customization without NRE fees, while transfer, access to students for recruiting, one- conductive or non-electrically conductive, with featuring short lead times. Standard parts are on-one company-to-faculty relationships, state- low to zero interface stress for ultimate reliability carried in stock. Lead times for custom parts of of-the-art R&D facilities, advanced technology and, representative of our Thermal Interface 1–2 weeks are possible for initial quantities. prototypes, and more. Materials (TIM) product line, unparalleled thermal management. AIT manufactures TIM in AMICRA Microtechnologies GmbH Advance Reproductions Corp numerous form factors, such as greases, gels and Wernerwerkstr. 4 100 Flagship Dr. variously sized dry or tacky pads. AIT’s adhesive 93049 Regensburg, Germany North Andover MA, 01845 films are critical to commercial and industrial Phone: +49-941-208209 0 Phone: +1 978-685-2911 semiconductor, electronic and microelectronic Fax: +49-941-208209 9 www.advancerepro.com applications. Our diverse product line includes www.amicra.com Contact: Don Robinson molecularly flexible epoxy adhesives for die and Contact: Dr. Johann Weinhaendler Email: [email protected] substrate attach and bonding, adhesives and Email: [email protected] Booth 411 underfills for multi size die bonding, DAF and Booth 504 Advance Reproductions Corporation is a leading DDAF for stack-chip packaging and flip-chip AMICRA Microtechnologies is a worldwide supplier of superior, large-area and optical bonding and underfilling and high temperature leading supplier of high precision Die Attach Photomasks and Phototools. Innovative by single and multi chip module die bonding past Equipment specializing in submicron placement nature we strive tirelessly to collaborate with 230ºC. AIT’s non-adhesive products include accuracy (±0.3µm@3s). Equipment offering our customers on their complex requirements. conformal coatings for ultimate moisture and/ supports both Die Attach and Flip Chip bonding Our seasoned staff of experts and our creative or humidity protection as well as UV resistant processes including the following capability: in-situ approach to each and every request is what sets but PVDF transparent coatings with or without eutectic bonding, dynamic alignment, heated us apart. Working with unique requirements and corrosion retardants. AI Technology, Inc. (AIT) tool, pulse heating, laser heating, volumetric and complex patterning requests as well as offering stands behind our time-tested products, however jet dispensing, active bond force control, high prototypes and high volume patterning we we are continually innovating new materials speed solutions, in-situ UV curing, 550x600mm welcome the challenge.www.advancerepro.com solutions. Released in 2015, AIT’s Wafer bonding area, quantitative tilt calibration system,

25 etc. Market focus: Opto, Silicon Photonics, AOC, industry leader in advanced packaging with AT&S Americas VCSEL, Laser Diode, WLP, 2.5D/3D IC, TSV, development and production of large scale and 1735 N. First St., Suite 245 TCB, Fan-out/EWLP. Other products: High complex 2.5/3D system solutions. Amkor’s San Jose, CA 95112 Speed Wafer Inking and inspection, Gel Fill Line comprehensive manufacturing capability, scale and Phone: +1 408-573-1211 and Custom Solutions. vision continue to strengthen our position as the Fax: +1 408-573-1911 “provider of choice” for semiconductor assembly www.ats.net Amkor Technology, Inc. and test. For more information, visitwww.amkor. Contact: Adriana Pace 2045 E. Innovation Circle com. Email: [email protected] Tempe, AZ 85284 Booth 208 Phone: +1 480-821-5000 ASE Group AT&S is a leading HDI and IC substrate producer www.amkor.com 1255 E. Arques Ave. offering Embedded Component Packaging Contact: Debi Polo Sunnyvale, CA 94085 (ECP®) technology for embedding passives and Email: [email protected] Phone: +1 408-636-9500 bare ICs inside the laminate for IC packages Booth 400 Fax: +1 408-636-9485 and printed circuit boards. Embedding provides Amkor Technology is one of the world’s www.aseglobal.com increased component density and smaller body largest and most accomplished providers of Contact: Patricia MacLeod size; improved signal integrity with embedded semiconductor packaging and test services. Email: [email protected] capacitors located just microns directly below Founded in 1968, Amkor pioneered the Booths 523, 525 the IC; thermal management with filled copper outsourcing of IC assembly and test and is a With a proven track record spanning over vias directly on the die backside; improved shock strategic manufacturing partner for the world’s three decades, ASE, the OSAT market & drop robustness; and hidden components leading semiconductor companies, foundries leader, continues its tradition of manufacturing for security and reverse engineering resistance. and electronics OEMs. Our solutions enable our expertise through orchestrated collaboration Additional components can be mounted on the customers to focus on semiconductor design and with customers, suppliers and partners, alike. top and bottom surfaces and connected to the wafer fabrication while utilizing Amkor as their Alongside a broad portfolio of established embedded components by copper-plated laser turnkey provider and their packaging technology technologies, ASE is also delivering innovative micro-vias. AT&S has six manufacturing sites in innovator.Amkor’s current operations include advanced packaging, System-in-Package and Austria (2), China (2), India, and South Korea. more than 10M ft2 of floor space with production MEMS solutions to meet growth momentum Embedding is available in the Leoben (Austria) facilities, product development centers and across a broad range of end markets. For more factory and in 2017 will also be available in the sales & support offices located in key electronics about our advances in Wire Bond, System- Shanghai (China) factory. FC-BGA substrates manufacturing regions in Asia, Europe and the in-Package, Wafer Level Packaging, Fan Out, are produced in the Chongqing (China) United States. Our broad package portfolio Flip Chip, MEMS & Sensors, and, 2.5D & 3D factory. AT&S announced participation in the includes leadframe, ball grid array, chip scale technologies, all ultimately geared towards Horizon 2020 EU Research and Innovation and wafer level packaging. Also supported are applications to improve lifestyle and efficiency, program to develop GaN-based modules specialty packaging with unique development please visit :www.aseglobal.com. targeting the production of demonstrator GaN and high volume production requirements power switches and CMOS drivers, as well as (e.g., MEMS, sensors and SiP). Amkor is an new magnetic core materials that will enable

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Advantages include: Wear Sense Move • Low-temperatureBSI.T15140 series bonding it. it. it. 25°C to ≤ Advantages 100°C Include: i) Bonding ii) Curing BSI.T16117 series i) Bonding ii) Curing • Increased throughput• Low temperature bonding 25°C to ≤ 100°C • High-temperature• Increased throughput survivability ≤ •350°C High temperature survivability ≤ 350°C • Increased adhesion• Increased at adhesion at all interfaces • Post bond TTV ≤ 5% of the nominal bond-­‐ iii)iii) BacksideBackside iv) iv) DebondingDebonding all interfaces Innovative IC, System-in-Package, and processingprocessing line thickness • Post-bond total thickness MEMS packaging portfolio for today’s • Reduced baking & cleaning +mes variation ≤ 5% of the nominal miniaturization, mobility, and IoT needs. • Compa+ble with mechanical or laser bond-line thicknessdebonding • Reduced baking & cleaning times v)v) Cleaning Cleaning • Compatible with mechanical Wire Flip 2.5D WLP Fanout SiP or laser debonding Bond Chip & 3D

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26 switching frequencies up to 200 MHz. Camtek, USA, Inc. temperature and ambient pressure bonding. Self- AT&S is also participating in the Panel-Level 48389 Fremont Blvd., Ste. 112 alignment using capillary force is also developed Packaging Consortium to implement fan-out Fremont, CA 94538 for high precision, high throughput chip-to-wafer panel-level packaging (FOPLP). Phone: +1 510-624-9905 bonding. With the support of its internal IC design Fax: +1 408-987-9484 teams LETI provides industrial partners with a Binghamton University www.camtek.com unique environment for validating new concepts Small Scale Systems Integration and Contact: Tommy Weiss through models, new design tools, test vehicles Packaging (S3IP) Center Email: [email protected] and implementing fully functional demonstrators P.O. Box 6000 Booth 119 such as wide I/O memory standard, 60 GHz Binghamton, NY 13902-6000 Camtek USA Inc. provides total inspection and RF SOCs for video data transfer or photonic Phone: +1 607-777-7270 metrology for 3DIC and the advanced packaging interposers. Recently CEA-LETI has developed Contact: Steve Czarnecki market. We provide automated solutions CoolCube, an original technique for stacking Email: [email protected] dedicated for enhancing production processes transistors sequentially in the same process flow Booth 317 and yield in the semiconductor fabrication and for 3D-VLSI. The technology is designed to allow The S3IP is a research and development packaging industry. Camtek’s solutions range a connection of the stacked active layers on a organization that addresses research challenges from micro to nano by applying its technologies nanometric scale, with a very high density, due in electronics packaging system design, process to the industry-specific requirements. Camtek’s to their alignment by a standard lithographic development, prototyping, and manufacturing innovations have made it a technological leader. process. CEA-LETI is embedded in a dynamic and for academia and the microelectronics industry. Camtek has sold more than 3,000 AOI systems in international ecosystem that include European Located at Binghamton University, the Center 34 countries around the world, winning significant and Global leaders. brings together partners from government, market share in all its served markets. Camtek is industry and academia, providing opportunities for part of a group of companies engaged in various Circuits Multi-Projets (CMP) collaborations that will advance microelectronics aspects of electronic packaging including advanced 46 Avenue Felix Vialet research and development, with particular focus substrates based on thin film technology, sample 38000 Grenoble on electronics packaging design and manufacturing preparation and digital material deposition. France technology; thermal analysis and management for Camtek’s uncompromising commitment Phone: +33 476 57 46 17 electronics; characterization of materials, surfaces, to excellence is based on Performance, Fax: +33 476 47 38 14 and physical interfaces for electronics devices Responsiveness and Support. cmp.imag.fr and assemblies; and failure analysis and reliability Contact: Dr. Olivier Guiller improvement for electronics. Subject areas Canon USA Email: [email protected] addressed include packaging of microelectronics, 3300 North 1st St. Booth 517 2.5D/3D chip assemblies, power electronics, and San Jose, CA 95134 In the past few years CMP has been developing its integrated photonics. Phone: +1 408-468-2000 advanced packaging offers for prototyping. Both www.usa.canon.com/industrial active and passive Silicon interposer solutions are Cadence Design Systems, Inc. Contact: Doug Shelton now available to designer as well as wafer-level 2655 Seely Ave. Email: [email protected] post-processing for process modules integration San Jose, CA 95134 Booth 418 (such as TSV and µ-pillars), enabling Silicon to Phone: +1 408-943-1234 Canon USA Industrial Products Division provides Silicon assemblies for 3D-IC applications. Since Fax: +1 408-758-6610 advanced wafer & panel process equipment for 1981, CMP is a Multi-Project Wafer service www.cadence.com applications including semiconductor, power organization in ICs, Photonic ICs and MEMS for Booth 100 device, advanced packaging & display. Canon prototyping and low volume production. CMP Cadence enables global electronic design provides cost-effective processing solutions enables prototypes fabrication on industrial innovation and plays an essential role in the including i-line & KrF optical lithography, processes at very attractive costs and offers it creation of today’s integrated circuits, packages, nanoimprint lithography & Canon Anelva great technical expertise in providing MPW and and PCBs. Cadence® IC packaging and cross- deposition equipment including the new FPA- related services for Universities, Research Labs domain co-design automation provide efficient 3030EX6 and FPA-3030i5+ steppers that are and Industrial companies prototyping. CMP can solutions in system-level co-design and advanced designed to extend advanced process capability handle low volume production, approximately mixed-signal packaging, delivering the automation for ≤ 200 mm wafer processes. Canon also has from some dozens to some thousands pieces. and accuracy to expedite the design process. a variety of panel based lithography & deposition Advanced industrial technologies are made Cadence also offers an integrated system design solutions that can be extended to a variety of available in CMOS, SiGe BiCMOS, HV-CMOS, solution for TSMC’s advanced wafer-level applications. Contact [email protected] SOI, MEMS, 3D-IC, etc. CMP distributes the Integrated Fan-Out (InFO) packaging technology. for more info. design rules for each technology and the standard The solution includes implementation, signoff, cell libraries for each specific software tool (design and electro-thermal analysis tools that enable CEA LETI kits) free of charge and supports several CAD concurrent multi-chip optimization for designs 17 Rue des Martyrs software tools for both Industrial Companies incorporating InFO technology. With complex 38054 Grenoble cedex 9, France and Universities. More than 1000 Institutions advanced packages, designers are faced with Phone: +1 626 537 7270 from more than 70 countries have been served, power integrity (PI) and signal integrity (SI) www.leti.fr/en more than 7000 projects have been prototyped issues driven by increasing IC speeds and data Contact: Hughes Metras through a thousand runs, and 71 different transmission rates combined with decreases Email: [email protected] technologies have been interfaced. in power-supply voltages and denser, smaller Booth 307 geometries. Stacked die and packages, higher CEA-LETI is an institute providing R&D and CPS Technologies Corporation pin counts, and greater electrical performance Prototyping services in the field of Micro and 111 S. Worcester St. constraints are making the physical design of Nanotechnologies. Capabilities include 8” and Norton, MA 02766 semiconductor packages more complex. To 12” wafer process flows for advanced CMOS, Phone: +1 407-341-3359 address these issues, Cadence provides advanced 3D stacking, MEMS and Silicon Photonics. Based Fax: +1 508-222-0220 PI and power-aware SI Sigrity™ tools that can be in Grenoble, France, CEA-LETI has offices in www.alsic.com used throughout the design process. the US and Japan. Over the past ten years CEA- Contact: Tim Davis LETI has developed a wide range of expertise in Email: [email protected] the fields of silicon interposers and high density Booth 419 interconnects to address the needs of the CPS Technologies Corporation is the worldwide semiconductor industry in market segments such leader in the design and high-volume production as mobile telephones and low power computing. of AlSiC (aluminum silicon carbide) for high Leti is working on hybrid bonding, wafer-to- thermal conductivity (up to 1000 W/mK with wafer or chip-to wafer integration. Pitch of few embedded Pyrolytic Graphite) and device microns is envisioned, without underfill, room compatible thermal expansion. AlSiC thermal

2713 management components manufactured by CPS process that enables 200mm and 300mm wafers providing solutions, products and technical include hermetic electronic packages, heat sinks, to be managed simultaneously. Deca’s process service necessary for next-generation electronics. microprocessor & flip chip heat spreader lids, significantly reduces cycle time and permits Dow’s portfolio includes metallization, dielectric, Thermal substrates, IGBT base plates, cooler multiple design iterations with minimal investment, lithography and assembly materials designed to baseplates, Pin Fin baseplates for hybrid electric thereby enabling the adoption of wafer level meet the most demanding needs for advanced vehicles, microwave & optoelectronic housings. interconnect technologies for a wide array of semiconductor packaging applications, such as semiconductor device types. bumping, copper pillars and redistribution layer CST of America, Inc. (RDL), passivation and underbump metallization 492 Old Connecticut Path, Suite 500 DISCO Hi-Tec America, Inc. (UBM) used for the latest fan-out wafer level Framingham, MA 01701 3270 Scott Blvd. packaging (FOWLP), flip chip, system in package Phone: +1 508-665-4400 Santa Clara, CA 95054-3011 (SiP), and 2.5D/3D chip packages. Fax: +1 508-665-4401 Phone: +1 408-987-3776 www.cst.com Fax: +1 408-987-3785 Dynaloy – a Subsidiary of Eastman Contact: Megan Schmidt www.discousa.com Chemical Company Email: [email protected] Contact: Aris Bernales 6445 Olivia Ln. Booth 308 Email: [email protected] Indianapolis, IN 46226 CST of America, Inc. is the leading supplier of Booth 410 Phone: +1 317-788-5694 3D electromagnetic simulation tools in North For over 40 years, DISCO Hi-Tec America, Fax: +1 317-788-5690 America. CST’s products aid in the microwave/ Inc. has been a leader in the semiconductor www.dynaloy.com RF and high speed design of many consumer, industry in cutting (Kiru), grinding (Kezuru), Contact: Diane Scheele industrial, aerospace and research level and polishing (Migaku) technologies. DISCO’s Email: [email protected] components and systems including interconnects, focus has expanded beyond mechanical dicing Booth 513 packages, materials, wireless devices, and vehicles. to include laser and plasma singulation. DISCO Dynaloy develops, manufactures, and markets The software has an excellent 3D interface with continues to be the leader in wafer thinning world class advanced cleaning solutions for the robust imports from all the major CAD and and polishing/stress relief with technologies semiconductor industry. Thoroughly removing EDA vendors. Huge cost savings are possible by such as SDBG enabling thinning of die to 20um photoresist and other residues is a critical part reducing or eliminating the hardware prototype or less. To support the increasing complexity of enhancing device performance. In short, stage of a design. Key results can be analyzed and in today’s packages, DISCO has also released cleaning matters in this fast-paced and competitive optimized based on user goals. equipment capable of laser via drilling in non- industry. That’s why Dynaloy offers custom silicon transparent materials, silicon carbide ingot and stock formulations to tackle the full range CVInc slicing (KABRA), and laser lift off. In order to of jobs, from the least complicated to the most 990 N. Bowser, Suite 860 support research and development efforts, joint challenging. Whether you’re removing photoresist Richardson, TX 75081 development initiatives, and next generation or residue, Dynaloy’s portfolio includes products Phone: +1 972-664-1568 product prototyping, DISCO Hi-Tec America’s for unique cleaning applications in the wafer level Cell: +1 214-557-1568 KKM Services lab in Santa Clara offers capability packaging market. Dynaloy offers the solutions Fax: +1 972-664-1569 to process materials with our latest advanced for silicon post-etch residue removal , Cu µ-pillar www.covinc.com cutting, grinding, and polishing technologies.” bumping and fan-out wafer-level packaging Contact: Terence Q. Collier (FO-WLP) photoresist removal. Our professional Email: [email protected] DOWA International Corp. staff is committed to helping engineers achieve Booth 417 4320 Stevens Creek Blvd. Suite 125 optimum performance through creative product CVI offers advanced packaging turn-key solutions San Jose, CA 95129 development, chemical expertise, unmatched for assembly and bumping. Quick turn solutions Phone: +1 408-236-7560 technical support and steadfast customer service. included single die bumping, partial wafers, www.dowa-electronics.co.jp/en/index. As a subsidiary of Eastman Chemical Company, complete wafers and reball on CSP and BGA’s. html Dynaloy and Eastman combine responsiveness, Bumping materials include solder alloys, gold Contact: Hiromichi Asahara material science expertise and vast resources to stud bumps and copper pillars. Plating capabilities Email: [email protected] be a world leader in cleaning technologies. include ENIG/ENIPIG/eCu and electrolytic Booth 103 plating (Cu, Sn, Ni, Pb, Au and Pd) . Custom DOWA is a Japanese material company of EV Group, Inc. QFN designs and modules (including open cavity). nonferrous metal and the largest supplier of Ag 7700 S. River Parkway Dummy die, substrates and interposers in silicon, powder in the world. We offer Nano Ag sintering Tempe, AZ 85284 quartz, and alumina. Custom preforms for board paste for bonding applications. The advantages Phone: +1 480-305-2400 repair and modification. of our Nano Ag paste are 1) High Thermal Fax: +1 480-305-2401 Conductivity (>200W/mK), 2) Low Sintering www.evgroup.com DECA Technologies Temperature (175C-250C), 3) Sinter without Contact: Carl Mann 7855 S. River Parkway, Suite 111 Pressure, and 4) High Shear Strength. We offer Email: salesNorthAmerica@evgroup. Tempe, AZ 85284 variety of paste lineup and we can customize com Phone: +1 480-345-9895 our paste for your applications. For more detail Booth 405 www.decatechnologies.com information, please visit booth#103. EV Group (EVG) is a leading supplier Contact: Garry Pycroft of equipment and process solutions for Email: garry.pycroft@ Dow Electronic Materials the manufacture of semiconductors, decatechnologies.com 455 Forest Street microelectromechanical systems (MEMS), Booth 200 Marlborough, MA 01752 compound semiconductors, power devices, Deca Technologies is an electronic interconnect Phone: +1 508-481-5970 and nanotechnology devices. Key products solutions provider that offers fan-in and fan-out www.dowelectronicmaterials.com include wafer bonding, thin-wafer processing, wafer level chip scale packaging (WLCSP) services Contact: Mark Markowski lithography/nanoimprint lithography (NIL) and to the semiconductor industry. Integrating solar Phone: +1 774-641-4969 metrology equipment, as well as photoresist and semiconductor technology, we leverage [email protected] coaters, cleaners and inspection systems. unique equipment, processes and operational Booth 420 Founded in 1980, EV Group services and methods inspired by SunPower to address Dow Electronic Materials, a global supplier of supports an elaborate network of global some of the significant barriers to the continued materials and technologies to the electronics customers and partners all over the world. More adoption and growth of next generation industry, brings innovative leadership to the information about EVG is available atwww. interconnects. Our portfolio of proprietary, game- semiconductor, interconnect, finishing, display, evgroup.com. changing electronic interconnect solutions delivers photovoltaic, LED and optics markets. From leadership capabilities in performance, cost and advanced technology centers worldwide, technology allied to a flexible manufacturing teams of talented Dow research scientists and application experts work closely with customers,

28 29 ficonTEC FlipChip International Fraunhofer Institute for Reliability 25 Calle Canela A Division of Huatian Technology and Microintegration IZM San Clemente, CA 92673 3701 E. University Dr. Gustav-Meyer-Allee 25 Phone: +1 949-388-5800 Phoenix, AZ 85034 13355 Berlin, Germany +1 949-300-7715 Phone: 602-431-4780 Phone: +49 30-46403-100 Fax: +1 949-388-1489 Fax: 602-431-6020 Fax: +49 30-46403-111 www.ficontec.com www.flipchip.com www.izm.fraunhofer.de Contact: Soon Jang Contact: Tony Curtis Contact: Georg Weigelt Email: [email protected] Email: [email protected] Email: [email protected] Booth 109 Booth 415 Booth 117 ficonTEC provides a wide range of micron- and FlipChip International - Huatian (FCI-HT): FCI-HT Invisible – but indispensable – nowadays nothing submicron-precision test-and-measurement, supplies turnkey semiconductor assembly and test works without highly integrated microelectronics vision inspection, and assembly automation services to the consumer, automotive, industrial and microsystem technology. Reliable and systems for opto-electronic devices, fiber-optic and medical industries. FCI-HT supports a wide cost-effective assembly and interconnection components, micro-optic devices, among range of customers, frequently partnering with technologies are the foundation of integrating others. Such automation systems for applications them to engineer customized solutions including these in products. Fraunhofer IZM, a worldwide include, but are not limited to, submicron- expedite bumping and backend services on Multi- leader in the development and reliability analysis precision LDB and die bonding, LDB stacking- Project Wafers. FCI-HT is a leader in wafer level of electronic packaging technologies, provides its unstacking, submicron-precision micro-lens packaging with patented technologies spanning customers with tailor-made system integration assembly (e.g., FAC, SAC, mirror, etc.), OE from Cu Pillar Bumping, Spheron™ Wafer Level technologies on wafer, chip and board level. Our component attachment, and integrated photonic Chipscale Packaging, and ChipsetT™ Embedded research also ensures that electronic systems are device assembly. ficonTEC is the recognized Die Packaging. FCI-HT is a division of Huatian more reliable, so that we can accurately predict industry leader in SiPh device test, inspection, and Technologies (HT). HT is among the top 6 lifecycle. assembly automation systems for various product OSATs in the world with over one billion dollars development and production requirements. in annual revenue. It is listed on the Shenzhen FUJIFILM ELECTRONIC MATERIALS Systems are designed with numerous assembly Stock Exchange Market. Huatian has six ISO/ 80 Circuit Dr. processes in view for high-throughput, high-yield TS16949 factories located in the US and China North Kingstown, RI 02852 precision automation production environment. offering a complete range of semiconductor Phone: +1 800-553-6546 ficonTEC’s system products and platforms packaging and turnkey services. +1 480-987-7028 are pre-engineered for specific applications, www.fujifilmusa.com where each application can be optimized for Fraunhofer Center for Applied Contact: Sanjay Malik the unique needs of each customer, maximizing Microstructure Diagnostics CAM Email: [email protected] their investment, and resulting in a competitive Heideallee 19 Booth 510 advantage. ficonTEC also prides in assisting its 06120 Halle (Saale), Germany FUJIFILM Electronic Materials is a leading customers with developing their devices that are Phone: +49 345-55 89 130 supplier of advanced materials to the electronics conducive to automation through collaborative Fax: +49 345-55 89 101 industry. We offer full complement of advanced product and/or process development activities, www.cam.fraunhofer.de photoimageable and non-photoimageable leveraging its extensive experiences in optical Contact: Prof. Dr. Matthias Petzold polyimide and PBO materials designed to meet device/component processing technology. Please Email: matthias.petzold@iwmh. current and future packaging requirements, as come and discuss ficonTEC’s capabilities for your fraunhofer.de well as temporary bonding materials tailored for application(s) at our booth. Booth 218 demanding wafer thinning applications. Fujifilm We are a leading service provider of failure is demonstrating its innovative iACF anisotropic Finetech diagnostics and material assessment for conductor technology drawn from our 560 E. Germann Rd., Suite 103 industry including semiconductor technologies, proprietary printing and metal substrate expertise. Gilbert, AZ 85297 microelectronic components, microsystems Phone: +1 480-893-1630 and nanostructured materials. We consider Georgia Tech – Institute for www.finetechusa.com the entire work flow from non-destructive Electronics and Nanotechnology Contact: Jim Bishop or Robert Avila defect localization over high precision target 345 Ferst Dr. NW Email: [email protected] preparation to cutting edge nanoanalytics Atlanta, GA 30318 Booth 503 supplemented by micro-mechanical testing, finite Phone: +1 404-894-5100 Finetech supplies sub-micron accuracy bonders element modeling and numerical simulation. We Fax: +1 404-894-5028 for die attach, advanced packaging and micro support cooperation partners in introducing www.ien.gatech.edu assembly applications. Manual, motorized and innovative materials and technologies, improving Contact: Dean Sutter automated models provide high process flexibility manufacturing process steps, securing reliable Email: [email protected] within one platform -utilizing a modular, flexible field use of components, analyzing field returns, Booth 518 design. Bonding technologies include thermo- and consequently optimizing manufacturing yield, Research, education, training, and shared- compression, ultrasonic, eutectic, epoxy, sintering, product quality, reliability, and cost efficiency. user facilities in the complementary fields of ACF/ACP, Indium and precision vacuum Due to our close collaboration with leading electronics and nanotechnology provides the die bonding. Applications areas cover optical microelectronics manufacturers, we are able to foundation for a broad range of advances in packages, sensors, Si photonics, microLEDs, support test and diagnostics equipment suppliers healthcare, telecommunications, computing, C2W, Cu pillar, focal plane arrays, chip-on-glass, in exploring and evaluating upcoming markets and consumer, industrial, transportation, agricultural, chip-on-flex and more. Finetech also provides future application fields. We provide innovative environmental, and national security applications. precision dispensers and advanced rework solutions for microstructure and failure diagnostics IEN is well known for its deep expertise in systems for today’s challenging applications. instrumentation, problem-adapted analysis work electronic design, modeling and simulation as The deep process knowledge we have gained flows and industry-compatible applications. well as in technologies for devices, components, through decades of experience adds value to sensors, energy harvesting, packaging, and our equipment. Our engineers work with test, as well as being a provider of shared-user customers to create effective solutions for specific facilities that are open to academia and industry applications - they understand that “one size” that support the needed fabrication, packaging, does not necessarily fit all. measurement and characterization of these technologies.

29 GLOBALFOUNDRIES Heraeus Electronics brands, such as Araldite® adhesives, Kerimid® 2600 Great America Way 301 N. Roosevelt Ave. laminating systems, Arathane® polyurethane Santa Clara, CA 95054 Chandler, AZ 85226 adhesives and potting systems and Euremelt® Phone: +1 408 462 3900 Phone: +1 480-589-0971 hot melt adhesives, are pioneers in the industry, www.globalfoundries.com www.heraeus-electronics.com serving customers for more than 50 years. Our Contact: Ajit Dubey Contact: James Wertin customers benefit from sound technical expertise Email: marketing@globalfoundries. Email: [email protected] and products that are tailor-made to meet their com Booths 312 & 314 requirements. Booth 515 Heraeus Electronics provides an innovative GLOBALFOUNDRIES is the world’s first product portfolio and trusted expertise in i3 Electronics, Inc full-service semiconductor foundry with a matching for High Performance electronics. With 1701 North Street truly global footprint. Launched in 2009, the our knowledge in electronic packaging materials; Endicott, NY 13760 company has quickly achieved scale as the higher density, longer product life and superior Phone: +1 866-820-4820 second largest foundry in the world, providing reliability in harsh conditions can be realized. Our Fax: +1 607-755-7000 a unique combination of advanced technology Materials Solutions will shorten your development www.i3electronics.com and manufacturing to more than 250 customers. cycles, lower development costs, and bring next Contact: Victor Hemingway With operations in Singapore, Germany and the generation products to market faster. Please Email: victor.hemingway@ United States, GLOBALFOUNDRIES is the only visit us to see our latest developments in Solder i3electronics.com foundry that offers the flexibility and security of Pastes, Sinter Pastes, Adhesives, Bonding Wires, Booth 304 manufacturing centers spanning three continents. Hybrid Thick Film Pastes, Metal and Metal i3 Electronics, Inc., headquartered in Endicott, The company’s five 300mm fabs and five 200mm Ceramic Substrates. NY, is a vertically integrated provider of high fabs provide the full range of process technologies performance electronic solutions consisting of from mainstream to the leading-edge. Hitachi Chemical Co., Ltd. design and fabrication of printed circuit boards & GLOBALFOUNDRIES is owned by Mubadala 1-9-2, Marunouchi, Chiyoda-ku, advanced semiconductor packaging; high speed Development Company.. Tokyo 100-6606 JAPAN laminate expertise; advanced assembly services; Phone: +81-3-5533-6646 reliability & signal integrity reliability lab services; HD MicroSystems, LLC Fax: +81-3-5533-6983 high speed back plane & press fit assembly; 250 Cheesequake Road www.hitachi-chem.co.jp and flex, rigid-flex & 2.5 & 3D die assembly. i3 Parlin, NJ 08859 Contact: Shotaro Kato product lines meet the needs of markets including Phone: +1 800-346-5656 Email: [email protected] aerospace & defense, medical, high performance www.hdmicrosystems.com Booth 107 computing, industrial, telecom, semiconductor Email: [email protected] Hitachi Chemical is a leading company in & test and alternative energy, with highly reliable Booth 319 providing various materials used in advanced products built in robust manufacturing operations. HD MicroSystems is a joint venture of Hitachi semiconductor assembly packages such as Chemical and DuPont Electronics specializing wafer level and panel level fan-out packages, 3D IBM Canada Ltd. in liquid polyimide (PI) and polybenzoxazole packages, etc. In addition to those materials, 23 Airport Blvd (PBO) dielectric coatings. HDM will highlight Hitachi Chemical provides “Open Laboratory” Bromont, Quebec new low stress and low temperature cure located in Japan where any customers can utilize Canada J2L 1A3 polymeric materials for front-end wafer and advanced manufacturing and analytical equipment Phone: +1 450-534-6496 back-end advanced packaging technologies for to achieve an accelerated development for Cell: +1 450-531-2474 Flip Chip, WLP, as well as interlayer dielectrics complex, advanced structures. The Open www.ibm.com/assembly (ILD), stress buffer coatings (SB), redistribution Laboratory will relocate to more convenient Contact: Luc Comtois dielectrics layers (RDL) and wafer bonding location, closer to Tokyo, in 2018. Our sales Email: [email protected] adhesives (temporary and permanent) for 3D/ offices are located around the world, with Booth 406 TSV applications. technical engineers stationed to support IBM Bromont is a world leader in semiconductor customers in case of need. Please contact us if packaging technology, products and services. Henkel Electronic Materials you are interested in “Open Laboratory” and Now available to customers worldwide, we 14000 Jamboree Rd. materials such as die bonding films, encapsulants invite you to take advantage of our experience, Irvine, CA 91626 (including compression molding and liquid system level mindset, and skilled engineers to Phone: +1 714-368-8000 type encapsulants), temporary adhesives, execute your most advanced packaging and Fax: +1 714-368-2265 re-distribution layer materials, substrate materials test solutions. Tap into our deep competencies www.henkel.com/electronics and much more. as the industry continues to shift to custom Contact: Janna Watzske SoCs and SiPs. IBM is known for its multi-chip Email: [email protected] Huntsman Advanced Materials packaging and heterogeneous integration. We Booth 302 10003 Woodloch Forest Dr. offer full turnkey solutions from modelling and Henkel Adhesive Electronics is a division of The Woodlands, TX 77380 characterization through Burn-in and test. Our global materials innovator, Henkel Corporation. Phone: +1 888-564-9318 test capability spans digital, analog, mixed signal, Headquartered in Irvine, California with sales, Fax: +1 281-719-4032 RF as well as multi-site programming, test pattern service, manufacturing and advanced R&D centers www.huntsman.com/advanced_ conversion, and load board design. We provide around the globe, Henkel AE is focused on materials high quality mechanical, thermal and electrical developing next-generation materials for a variety Contact: Petharnan Subramanian design (including high speed/SERDES, signal of applications in semiconductor packaging, Email: petharnan_subramanian@ integrity and power integrity), ensuring effective industrial, consumer, displays and emerging huntsman.com execution of new and updated platforms. Services electronics market sectors. A leader in die attach, Booth 204 include materials and process characterization, underfill, solder, molding, printable ink and Huntsman Advanced Materials provides optimized substrate design, and failure analysis thermal management materials, Henkel AE has engineered solutions for our customers using while package platforms range from large organic developed some of the industry’s most innovative a wide range of high-performance thermoset substrates using high density interconnect to and enabling electronic material solutions. chemistries and formulations. Everyday our silicon and glass interposers, and the coreless scientists work with designers and engineers to technologies. We invite you to discuss your next bring lightweight, high-strength, durable products generation requirements – our developments in to market and help solve increasingly complex areas such as silicon photonics are unrivaled. IBM design issues. In the electronics market we will help you deliver differentiated solutions while provide advanced organic protective solutions providing personalized, expert support to meet to build, structure and assemble printed circuit even the toughest application goals. boards and to encapsulate, insulate and bond electrical and electronic components. Our

30 Interconnect Systems, Inc. Kulicke & Soffa LINTEC of AMERICA INC. 741 Flynn Rd. 1005 Virginia Ave. 15930 S. 48th Street Suite 110 Camarillo, CA 93012 Fort Washington, PA 19034 Phoenix, AZ 85048 Phone: +1 805-482-2870 Phone: +1 215-784-6786 Phone: +1 480-966-0784 Fax: +1 805-482-8470 Contact: Paul Keehn www.lintec-usa.com www.isipkg.com Email: [email protected] Contact: Stuart Campbell Contact: Ken Roberson Booth 102 Email: [email protected] Email: [email protected] Kulicke & Soffa Industries is a leading provider Booth 112 Booth 520 of semiconductor packaging and electronic LINTEC is a worldwide leader in adhesive Interconnect Systems, Inc. (ISI), specializes in assembly equipment and solutions supporting the technologies. For 30+ years LINTEC, through high-density module packaging and advanced global automotive, consumer, communications, the Adwill brand of products, has created system-level interconnect solutions. ISI offers computing and industrial segments. As a pioneer equipment and materials to solve difficult design, qualification, and testing, coupled with fully in the semiconductor space, K&S has provided semiconductor process issues. With a catalog integrated in-house manufacturing. Capabilities customers with market leading packaging of hundreds of tapes, a myriad of equipment, include: high-density PCB design, fine pitch SMT, solutions for decades. In recent years, K&S has and decades of application experience LINTEC flip chip, wirebond assembly, IC packaging, expanded its product offerings through strategic is positioned to help. Whether you are looking custom molding, over molding, and automated acquisitions and organic development, adding for a tape, need equipment to mount, peel, optical inspection. advanced packaging to handle the most advanced or UV cure, or would like assistance from our TCB and FOWLP applications, electronics applications labs in Phoenix and Dallas to tackle Invensas assembly, wedge bonding and a broader range of a difficult issue; our staff stands ready to assist 3025 Orchard Parkway expendable tools to its core Ball Bonder offerings. you to provide the Adwill Advantage. Need to San Jose, CA 95134 Combined with its extensive expertise in process reduce costs or address reliability issues in wafer Phone: +1 408 321 6000 technology and focus on development, K&S level chip scale packages (WLCSP)? Please visit Fax: +1 408 321 8257 is well positioned to help customers meet the our Interactive Presentation “Development of www.xperi.com challenges of packaging and assembling the next- Double Side Protection Process with Bump Support Contact: Andrew Kim generation of electronic devices. Film (BSF) and Backside Coating Tape for WLP” at Email: [email protected] Thursday 9-11 A.M. in the Northern Hemisphere Booth 306 Kyocera America Foyer. Invensas, a wholly owned subsidiary of Xperi 1401 Route 52, Suite 203 Corporation (Nasdaq: XPER), is the world’s Fishkill, NY 12524 LPKF Laser & Electronics leading provider of advanced semiconductor Phone: +1 845-896-0480 12555 SW Leveton Dr. packaging and 3D interconnect technologies Contact: Tony Soldano Tualatin, OR USA that enable the next generation of electronics Email: [email protected] Phone: +1 503-454-4200 products to be smaller, faster, lower power and Booth 414 www.lpkfusa.com contain more functionality. Invensas solutions Kyocera International, Inc., Semiconductor Contact: Stephan Schmidt can be found in DRAM memories, image Components Group offers an extensive array of Email: [email protected] sensors, RF devices, MEMS sensors, processors organic FC-CSP / FC-BGA / SHDBU packages, Booth 214 and mixed signal devices currently in high complex ceramic modules, embedded PWB, LPKF Laser & Electronics is a manufacturer of volume production at leading OEMs, ODMs, and high-density PCBs for numerous applications laser systems for the electronics manufacturing. and IDMs and integrated into in billions of including RF/MW, ASICs, MPUs, graphics LPKF’s newest system, the Vitrion 5000 is electronic products around the world, including processors, data centers, power semiconductors, designed solely for creation of high quality smartphones, tablets, laptops, PCs and data phased array radar, telecom, avionics and space. through glass vias (TGV) at very high production center servers. Invensas technologies include rates. The laser class 1 system is compatible with ZiBond®, a low temperature wafer-to-wafer or Lasertec USA Inc. glass wafers up to 18” as well as glass panels with die-to-wafer bonding, Direct Bond Interconnect 2025 Gateway Place, Suite 430 a maximum dimension of 20” by 20”. The system (DBI®) wafer-to wafer or die-to-wafer bonding San Jose, CA 95110 is able to produce via holes as with an 1:10 with electrical interconnect, Bond Via Array™ Phone: +1 408-437-1441 aspect ratio and can handle substrate thicknesses (BVA®) advanced Package-on-Package and Fax: +1 408-437-1430 between 50 and 300 micrometers. In addition, System-in-Package solutions, and xFD® multi-die www.lasertec.co.jp/en/index.html LPKF offers its laser direct structuring technology face-down packaging technology. Contact: Yuji Asakawa (LDS) for the laser-based additive creation Email: [email protected] circuitry on 3D injection molded plastics parts for JSR Micro, Inc. Booth 519 the use in sensor housings and micro-packaging. 1280 N. Mathilda Ave. Lasertec Corporation, founded in 1960, Sunnyvale, CA 94089 has grown into a world leading innovator of Malico Inc. Phone: +1 408-543-8800 inspection and metrology equipment serving 5, MingLung Road Fax: +1 408-543-8964 the global semiconductor and related industries. Yang-Mei, Taiwan 32663 www.jsrmicro.com Guided by its corporate philosophy, “Create Phone: +886-3-4728155 Email: [email protected] unique solutions; Create new value,” Lasertec Fax: +886-3-4725979 Booth 403 has created several new tools to help companies www.malico.com JSR’s unique THB series of negative tone thick developing and manufacturing the next generation Email: [email protected] film photoresists for RDL, micron bump, and Cu of semiconductors – 3DICs with TSV technology. Booth 511 pillar applications, along with our WPR series Tools being highlighted at ECTC 2017 are Malico is the leading manufacturer for Thermal of dielectric coatings are ideal for WL-CSP, Flip the BGM300, BIM300, and the EZ300. The Solutions. We offer both standard and Chip, TSV, and other packaging technologies. BGM300 is an IR based metrology tool capable customized heat sinks. Our product line includes JSR materials provide excellent throughput, large of measuring all the critical depths/thicknesses passive, active, heat pipe embedded, copper process margins, high aspect ratio solutions for needed for wafer specific grind, polish and etch embedded and liquid cooling solutions. We offer film thicknesses from <10 to >100 micrometers process optimizing to enable the highest yielding design and simulation assistance. Our vertical while being processed in standard TMAH TSV wafers. The BIM300 is based on Lasertec’s integrated production line ensures our customer developer. Additionally, JSR offers exceptional proprietary confocal optics and is an ideal receive the highest quality service at the shortest materials in the temporary bonding space – solution for measuring and inspecting revealed lead time and in most cost effective way. contact us to learn more. vias, bumps and other critical elements found throughout the TSV wafer finishing. The EZ300, an edge inspection and analysis system, is the latest addition to Lasertec’s product portfolio and provides unmatched analysis capability on wafer edge issues.

31 Mentor, A Siemens Business users of semiconductor devices. In business for C-VI. Hermeticity of the packages is less than 8005 SW Boeckman Rd. more than 35 years, our comprehensive array 10-10 atm cc/sec per MIL-STD-883, method Wilsonville, OR 97070 of high-reliability capabilities serve the global 1014, condition A4. MSI is ISO-9001 certified. Phone: +1 503-547-3000 defense, space, medical, industrial, and fabless Compliance includes RoHS, REACH, and DFAR. www.mentor.com/pcb semiconductor markets. Micross possesses the Standard deliveries start in just 2 WEEKS! Contact: Jen Chausse sourcing, packaging, assembly, test, and logistics Email: [email protected] expertise needed to support an application Mitsui Chemicals America Booth 521 throughout its entire program cycle. 61 Metro Drive Mentor® is the worldwide market leader in PCB San Jose, CA 95110 systems design, High Density Advanced Packaging Mini-Systems, Inc. (MSI) Phone: +1 408-487-2888 solutions and analysis technologies. Mentor will 20 David Rd. www.mc-tohcello.co.jp/english/ be showcasing Xpedition Package Integrator with North Attleboro, MA 02760 Contact: Jeff Wishes HyperLynx, a holistic solution for IC/Package/ Phone: +1 508-695-0203 Email: [email protected] Board cross-domain prototyping, planning, Fax: +1 508-695-6076 Booth 113 optimization, layout and electrical analysis . www.mini-systemsinc.com ICROS™ Tape has been the world’s top Visit booth 521 to learn more about Mentor’s Contact: Craig Tourgee protective tape used in semiconductor wafer technologies and best practices for IC/Package/ Email: [email protected] backgrinding (BG) for many decades. In Board co-design or by attending Mentor technical Booth 203 order to meet the strict requirements of the presentations. Mini-Systems, Inc. (MSI) is a world class leader semiconductor market, we optimize the whole in the manufacture of high-reliability passive production process from material design to final Micross Advanced Interconnect components and hermetic packages. For over inspection. Everything takes place within state-of- Technologies 49 years MSI has been delivering superior the-art clean room production environments with 3021 E. Cornwallis Rd. quality products for Military, Aerospace, strict quality controls in place every step of the P.O. Box 110283 Communications, Medical and Industrial way. The result is ICROS™ Tape, an ultraclean Research Triangle Park, NC 27709 applications. MSI manufactured products consist tape with superior TTV (total thickness variation). Fax: +1 919-354-3580 of precision: Thin/Thick film Chip Resistors/ Today, ICROS™ Tape is not only used for BG www.micross.com/advanced- Networks, QPL Resistors to MIL-PRF-55342, process but also for many other processes in interconnect-technology.aspx MOS Chip Capacitors, Chip Attenuators, Full semiconductor manufacturing flow, such as dicing, Contact: Alan Huffman Line of RoHS Compliant Products, QPL Jumpers packaging process, tape for metal lift off process, Email: [email protected] to MIL-PRF-32159/Mounting Pads, Glass- protective tape for etching, tape for CMOS Booth 316 to-metal seal packages, and Custom Design image sensor handling, and protection tape for Micross is the leading one-source, one-solution Packages. Resistors values from 0.1 Ohm to back metalizing. ICROS™ Tape is now being provider of bare die & wafers, wafer bumping 100GOhm and operating frequencies up to 40 developed for latest generation semiconductor & advanced interconnect technologies, custom GHz. Absolute tolerances starting at 0.005% and process, such as TSV wafer BG and dicing, fan- packaging & assembly, component modification TCRs as low as ±2ppm/°C. Sizes start at 0101. out WLP, Panel Level Package and many other services, electrical & environmental testing, The hermetic packages meet or exceed package processes. and Hi-Rel products to manufacturers and evaluation requirements per MI-PRF-38534, Table

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32 MRSI Systems Nanium S. A. Nikon Metrology, Inc. 101 Billerica Ave. Avenida 1º de Maio 801 12701 Grand River Ave. N. Billerica, MA 01862 4485-629 Vila do Conde, Portugal Brighton, MI 48116 Phone: +1 978-667-9449 Phone: +351 252 24 6301 Phone: +1 810-220-4360 www.mrsisystems.com Fax: +351 252 24 6001 Fax: +1 810-220-4300 Contact: Dan Crowley www.nanium.com www.nikonmetrology.com Email: [email protected] Contact: Antonio Barny Contact: Andrew Smith Booth 318 Email: [email protected] Email: [email protected] Die bond and dispense solutions from MRSI Booth 501 Booth 311 Systems, with accuracies to one micron NANIUM (www.nanium.com) is an outsourced Nikon Metrology, Inc. offers the most complete for eutectic, epoxy, flip chip, and thermo- semiconductor packaging, assembly and test and innovative metrology product portfolio, with compression die bonding. MRSI Systems is a provider, and a world-leader in 300mm Wafer- state-of -the-art vision measuring instruments leading supplier of high precision dispense and Level Packaging. The company provides Wafer- x-ray machines with CT options, and a complete assembly equipment for the semiconductor and Level Chip Scale Packaging (WLCSP) and was line of 3D metrology options. These reliable and microelectronics industry, offering systems for among the first in the world to offer Wafer-Level innovative solutions respond to the advanced the manufacture of Microwave, Optical, MCMs Fan-Out (WLFO) in high volume manufacturing. inspection requirements of manufacturers active and MEMS devices. Entering our third decade Today, NANIUM stands as a leader in WLFO, in aerospace, electronics, automotive and other of advanced packaging application experience, a technology that combines minimal form-factor industries. To learn more about our innovative MRSI Systems products support all standard with superior performance, high integration products and to view all our product lines please interconnect technologies. The ultra-precision density, and high reliability. Since inception, visit our website. MRSI Systems MRSI-M3 with 1 micron accuracy NANIUM has shipped over 1 billion WLFO capability for photonic and 3D packaging packages. NANIUM delivers world-class services Nitto Inc. applications and the MRSI-705 Die Bonders and always customizes Solutions according to Bayside Business Park specialize in thin die handling and accuracies the customers’ needs. Its WLFO technology 48500 Fremont Blvd. to 5 microns. The MRSI Systems MRSI-175Ag is flexible and can accommodate embedded Fremont, CA 94538 Epoxy Dispenser is the leader for high precision integration solutions ranging from single- to multi- Phone: +1 510-445-5400 conductive epoxy dispensing including 125 micron die, system-in-package and package-on-package Fax: +1 510-445-5480 dots using a variety of dispense technologies. with passives integration, and serve markets such www.nitto.com Your Standard in Precision Automation. as mobile communication, medical, security, Contact: Yasuko Ferris wearables and automotive radars, to name a Email: [email protected] Nagase America Corporation few. Based in Portugal, NANIUM’s facilities Booth 211 2880 Lakeside Drive, Suite 320 include over 20,000 sqm of cleanroom area. The Nitto Denko is a global supplier of materials and Santa Clara, CA 95054 company offers in-house capabilities for the entire equipment for semiconductor manufacturing, Phone: +1 408-567-9728 development chain, from package design to the represented by the following products: ELEP Fax: +1 408-567-9729 flexibility to tailor and test solutions. NANIUM holder tapes for back-grinding and dicing; high www.nagasechemtex.co.jp/en/ has sales offices in Dresden, Germany, and temperature resistant masking tape; NEL machines Contact: Ippei Yamai Boston, MA, USA (Taper/Detaper/ Wafer Mounter with or without Email: [email protected] peeling function/ UV machine) for thin wafer Booth 303 Neu Dynamics Corp. application; ELEPMOUNT (2-in-1: DAF+Dicing Nagase ChemteX is a leading company for 110 Steamwhistle Dr. Tape conductive/non-conductive) for thin stacked semiconductor encapsulant of epoxy resin, Ivyland, PA 18974 chip package; REVALPHA thermal-release tape especially Liquid Molding Compound (LMC) for Phone: +1 215-355-2460 for various applications, such as dicing, grinding FOWLP, Non-Conductive Paste (NCP) for Fine Fax: +1 215-355-7365 and MLCC production process; clear molding pitch FC-PKG, Underfill for Pb-free. Engineered www.neudynamics.com compound and sheet encapsulating resin. Materials Systems, Inc. technology focus on Contact: Don Johnson electronic materials and negative photoresist for Email: [email protected] Nordson DAGE semiconductor, circuit assembly, photovoltaic, Booth 216 2747 Loker Avenue West printer head, camera module, disk drive, printed Neu Dynamics offers encapsulation molding Carlsbad, CA 92010 electronics and photonics assembly product lines. systems for micro BGG and PBGA array devices, Phone: +1 925-246-1662 These Nagase Group companies create continual Top and Bottom Transfer as well as multi-plunger www.nordsondage.com improvements guiding its customers into the mold tooling for the latest in small outline devices Contact: Aram Kardjian future. (TQFP, TSSOP, MSOP, QFN, LGA, etc.) and Email: [email protected] molded Optoelectronic packages, Automatic Booth 305 NAMICS Technologies, Inc. and semi-automatic trim and form dies and Nordson DAGE is the market leading provider 2055 Gateway Place, Suite 480 systems supplied with trim presses (both Servo of award winning wire pull, ball and die shear test San Jose, CA 95110 and Hydraulic driven). Neu Dynamics further systems along with X-Ray and AOI inspection Phone: +1 408-516-4611 offers contract transfer molding services. Our fully systems. They are recognized as the industry Fax: +1 408-516-4617 equipped molding lab allows for mold tryouts, standard. The recently released 4800 bond tester www.namics.co.jp/e pilot runs and low to medium volume production. brings the latest developments in automated Contact: Tony Ruscigno Neu Dynamics is also capable of building high wafer testing technology to users testing wafers Email: [email protected] precision injection molds specializing in insert and from 100mm to 450mm in diameter. When Booth 401 overmolding applications. Our sister company, combined with an integrated wafer handling NAMICS CORPORATION is a leading source NDC International, is a distributor of a wide device the 4800-INTEGRA™ can test multiple for underfills, encapsulants, adhesives, and range of back-end semiconductor assembly wafers consecutively. Additionally, the multi- insulating and conductive materials used by packaging equipment and materials, and custom function cartridge (MFC) can be used for producers of semiconductor devices, passive automation solutions. automated application changing within a test components and solar cells. eadquartered in pattern or simply very quick cartridge changes Niigata, Japan with subsidiaries in the USA, in manual operation. Automation on non-wafer Europe, Taiwan, Singapore, Korea and China, samples can also be conducted on the 4000Plus NAMICS serves its worldwide customers with which performs shear tests up to 200kg, pull enabling products for leading edge applications. tests up to 100kg and push tests up to 50kg. The all-purpose 4000 and 4000 Optima systems are capable of manual pull testing up to 50kg and shear tests to 200kg with accuracies up to 0.05% as standard. Paragon software offers ease of use and intelligent automated testing with a focus on

33 user experience. The 4000HS high speed bond Ormet Circuits Panasonic Factory Solutions Co. of tester is used for pull and shear testing of solder 6555 Nancy Ridge Dr. #200 America spheres to identify brittle fractures at speeds up San Diego, CA 92121 1701 Golf Road, Ste 3-1200 to 4m/sec in shear and 1.3m/sec pull. Phone: +1 858-831-0010 Rolling Meadows, IL 60008 Fax: +1 858-455-7108 Phone: +1 847-637-9600 NTK Technologies, Inc. www.ormetcircuits.com Fax: +1 847-637-9601 3979 Freedom Circle Dr., Suite 320 Contact: Michael Matthews www.panasonicfa.com Santa Clara, CA 95054 Email: [email protected] Contact: Tae Yi Phone: +1 408-727-5180 Booth 121 Email: [email protected] Fax: +1 408-727-5076 Ormet Circuits Inc. is proud to join EMD Booth 505 www.ntktech.com Performance Materials, an affiliate of Merck Panasonic Factory Solutions Company of America Contact: Mariel Stoops KGaA, Darmstadt, Germany. The combined (PFSA) develops and supports innovative Email: [email protected] Performance Materials (PMI) portfolio includes manufacturing processes around the core of Booth 212 high-tech performance chemicals for applications circuit manufacturing technologies and computer- NTK Technologies is a leader in IC Ceramic in fields such as: Displays, Integrated Circuits, integrated manufacturing software—thereby, Packaging. For nearly half a century, NTK has Lighting Applications, Solar & Energy, Coatings, contributing to the growth and prosperity of our developed specialized technologies to provide Semiconductor Packaging. Customer sectors in customers’ businesses regardless of their mix or advanced ceramic IC packaging solutions for consumer electronics, lighting, printing technology, volume. mature and start-up semiconductor companies. plastics applications and integrated circuits NTK’s technical centers support design make use of materials and solutions from EMD Panasonic Industrial Devices Sales Co. optimization and simulation services through all Performance Materials. Thanks to comprehensive Division of Panasonic Corp. NA development and production stages -- prototype, investments in research & development, we are 10900 N. Tantau Ave., Suite 200 small volume, and volume manufacturing. With constantly extending our leading position as an Cupertino, CA 95014 global service centers, NTK offers a wide range innovator and reliable partner. Our future growth Phone: +1 408-861-3946 of packaging materials and design services for integrates key materials consisting of high purity Fax: +1 408-861-3990 CMOS/CCD Image Sensors, Opto, FPGA, chemicals used in wafer fabrication to sustainable www3.panasonic.biz/em/e/guidance CPU, MPU, MCM, RF, LED Substrates, Hi-Rel, materials for advanced back end solutions. Booth 507 Satellite, Automotive and Medical applications. Since the founding of our company in 1918, we Wafer Probe Substrates utilizing multilayer PAC TECH USA at Panasonic have been providing better living for co-fired ceramic and multilayer thin film available. 328 Martin Ave. our customers, always making ‘people’ central Optimum package designs for 10G to 400G. Santa Clara, CA 95050 to our activities, and thus focusing on ‘people’s As one of the industries’ largest packaging Phone: +1 408-588-1925 x 246 lives’. Going forward from this, and based on manufacturers, NTK’s products and services have Fax: +1 408-588-1927 our innovative electronics technology, we will evolved to match the roadmaps of mainstream www.pactech.com continue to provide a wide variety of products, and advanced IC packaging applications. Contact: Richard McKee systems and services. Email: [email protected] Ntrium Inc. Booth 301 Plasma-Therm, LLC Lvl 2, 54-42 Dongtanhana 1-gil, Packaging Technologies GmbH (group member 10050 16th St. N. Hwaseong-si, Gyeonggi-do, 18423 of NAGASE & CO. Ltd.) is headquartered in St. Petersburg, FL 33716 Republic of Korea Nauen, Gremany with wholly owned subsidiaries: Phone: +1 727-577-4999 Phone: +82-31-8889068 PacTech USA Packaging Technologies Inc. in Fax: +1 727-577-7035 Fax: +82-31-8889555 Silicon Valley, USA, and PacTech ASIA Sdn. Bhd. www.plasmatherm.com www.ntrium.com in Penang, Malaysia. PacTech is comprised of two Email: [email protected] Contact: James Lee unique advanced packaging units: EQUIPMENT Booth 408 Email: [email protected] MANUFACTURING: PacLine 300 A50- Plasma-Therm® is a leading provider of advanced Booth 213 Automatic ENIG & ENEPIG plating tools. SB2-Jet: plasma processing equipment. Plasma-Therm Ntrium is presented with the opportunity Laser solder jetting equipment; Ultra-SB: Wafer- systems perform critical process steps in to converge Nano-material technology and level solder ball transfer systems; LAPLACE: the fabrication of integrated circuits, micro- the Microelectronics packaging technology Laser assisted flip-chip bonders SUBCONTRACT mechanical devices, solar power cells, lighting, of Automotive/Semiconductor/Mobile/ SERVICES: Flip Chip and Wafer Level Package and components of products from computers IT products, to ignite bright minds that solve Bumping Services including ENIG or ENEPIG and home electronics to military systems and technical problems customers face, to provide for UBM (solder bumping) or OPM (wirebond). satellites. Specifically, Plasma-Therm systems collaborate and innovative solutions. EMI Shielded Other services include AOI, X-Ray, Repassivation, employ innovative technology to etch and deposit Package is a solution to reduce local noise RDL, Wafer Thinning, Backmetal, Laser Marking, thin films. The company’s Mask Etcher® series for interference caused by high frequency chips inside Dicing, and Tape and Reel. photomask production has exceeded technology the high-end devices. Spray Coating is one of roadmap milestones for more than 15 years. the best solutions for on-package EMI Shielding, Palomar Technologies Inc. Plasma-Therm’s Singulator® systems bring the because of its excellent SE (Shield Effectiveness) 2728 Loker Avenue West precision and speed of plasma dicing to chip- Performance. It has (1) Good Adhesion to Carlsbad, CA 92010 packaging applications. Manufacturers, academic Package (2) Conformal Shielding Coverage on Phone: +1 760-931-3600 and governmental institutions depend on Plasma- both Top and Side walls (3) Coating Thickness Fax: +1 760-931-5191 Therm equipment, designed with “lab-to-fab” Controllability for Thinner Device and Higher SE www.palomartechnologies.com flexibility to meet the requirements of both Performance (4) Lower Cost and Simpler Process Contact: Katie Schirmer R&D and volume production. Plasma-Therm’s than PVD (5) Free from Backside (Ball Grid and Email: [email protected] products have been adopted globally and have Land Grid) Contamination. Booth 500 earned their reputation for value, reliability, and Palomar Technologies, a former subsidiary of world-class support. Plasma-Therm’s status as a Hughes Aircraft, is the global leader of automated preferred supplier of plasma process equipment high-accuracy, large work area die attach and has been recognized with VLSIresearch Customer ball and wedge wire bonding equipment and Satisfaction awards for 17 consecutive years, precision contract assembly services. Customers including “RANKED 1st” awards from 2012 to utilize the products, services and solutions 2016. from Palomar Technologies to meet their needs for optoelectronic packaging, complex hybrid assembly and micron-level component attachment.

34 Promex Industries Inc. capacity during times of under-capacity. Cost- Rudolph Technologies 3075 Oakmead Village Drive effective means of performing tests on an irregular 16 Jonspin Road Santa Clara, CA 95051 or infrequent basis. A productive and beneficial Wilmington, MA 01887 Phone: +1 408-496-0222 way to “test drive” the equipment before Phone: +1 978-253-6200 www.promex-ind.com committing to a purchase. Fax: +1 978-658-6349 Contact: Rosie Medina www.rudolphtech.com Email: [email protected] Quik-Pak, a Division of Promex Email: [email protected] Booth 215 10987 Via Frontera Booth 413 Promex provides heterogeneous assembly San Diego, CA 92127 Rudolph Technologies is a leader in the design, processing integrating conventional surface Phone: +1 858-674-4676 development, manufacture and support of defect mount technology (SMT) with semiconductor Fax: +1 858-674-4681 inspection, advanced packaging lithography, microelectronic packaging and assembly methods www.icproto.com process control metrology, and data analysis for flip chip or chip/wire devices. The company Contact: Casey Krawiec systems and software used by semiconductor operates a 30,000 sq. ft. assembly facility with Email: [email protected] device manufacturers worldwide. Rudolph’s Class 100 and 1000 clean rooms in Silicon Valley Booth 215 product suite offers hardware and software that is ISO 13485:2003, ISO 9001:2008 certified, Quik-Pak, a division of Promex, provides IC solutions for the demanding requirements of the ITAR registered and compliant to regulatory packaging, assembly, and wafer preparation advanced packaging market, including 2D/3D requirements for medical products. With a services in its ISO 9001:2008 and ITAR registered bump inspection, RDL and overlay metrology, highly skilled engineering team, Promex combines facility in San Diego, California. Quik-Pak and a lithography stepper specifically designed for broad technical capabilities, advanced packaging, manufactures over molded QFN/DFN packages the back-end. Turn data into useful information and microelectronics assembly expertise with and pre-molded air cavity QFN packages that with Rudolph’s proprietary software solutions scalable manufacturing capacity to produce new provide a fast, convenient solution for prototype including run-to-run control, fault detection and medical and bioscience products from concept to to full production needs. Same-day assembly classification and yield management systems. production. services are provided to shorten time to market. Due to customer demand, Quik-Pak Samtec, Inc. PURE TECHNOLOGIES now provides high volume IC assembly services 2223 Owen St 177 US Hwy # 1, No. 306 utilizing its automated assembly and molding New Albany, IN 47150 Tequesta, FL 33469 USA equipment for production runs in the 10,000s Phone: +1 812-944-6733 Phone: +1 404-964-3791 of units. In addition to wire bond assembly, the Fax: +1 812-948-5047 Fax: +1 877-738-8263 company assembles flip chips, BGAs, stacked die, www.samtec.com Int’l Fax: +1 973-273-2132 sensors, MEMS, and chip-on-board and chip-on- Contact: Glenn Dixon www.puretechnologies.com flex assemblies. Email: [email protected] Contact: Jerry Cohn Booths 313 & 315 Email: [email protected] Royce Instruments LLC Known as the worldwide service leader for Booth 205 831 Latour Court, Suite C electronic connectors and cables, Samtec has Pure Technologies manufactures low (0.02, 0.01 Napa, CA 94558 focused on leading edge high speed products cph/cm2), ultra-low (0.005, 0.002 cph/2) and Phone: +1 707-255-9078 and services for the last two decades. The super ultra-low (<0.001 cph/cm2) alpha emitting Fax: +1 707-255-9079 tremendous success in these areas has driven Tin (Sn), Lead-Free (including all SAC) alloys, www.royceinstruments.com Samtec to further move into faster and smaller Pb, Pb/Sn , Bi and virtually all alloys for over 23 Contact: Bill Coney arenas. They now provide full turnkey solutions years. These ALPHALO® products are available Email: bconey©royceinstruments.com for your entire signal chain from IC, through the in various shapes and sizes – ingots, anodes, slugs, Booth 502 package, and through substrates, connectors pellets, foil, rods, bricks, PbO and SnO powder, Consider Royce Instruments your preeminent and cables. Samtec can help you design, model, etc. for wafer-level packaging, interconnects, supplier for Bond Testing and Die Sorting layout, and assemble your IC package. Advanced electroplating and sphere and powder/paste equipment. Our equipment provides outstanding Semiconductor, MEMS, and Sensor substrate manufacturing. ALPHA-LO® reduces/eliminates accuracy to meet a full range of bond test and design, Flip chip, die attach, wire bonding, soft errors from alpha particle emissions from die sorting requirements. Because bond testing dam, encapsulation, transfer molding, and lid solders, enhances performance reliability and die sorting are our sole focus, we are attach, Modeling and prototyping, Electrical and reduces corporate liability. All materials able to dedicate ourselves to developing and testing and debug, In-house mid-board optical/ are guaranteed and certified to be at secular supplying leading, high-precision solutions for photonic engine design, manufacturing, and equilibrium and are tested and retested over time our customers. The Royce 600 Series Bond packaging, and New capabilities in glass before shipping to insure that the alpha emission Test Instruments brings unparalleled networking interposers and substrates with low loss electrical rate is stable and will not increase over time. capability and scalability to the bond test market. characteristics, biomedical microstructuring, and With a choice of 3 bond testers, Royce offers an 2.5D package integration. QualiTau instrument solution to meet the evolving needs 830 Maude Ave. of manufacturers and institutions worldwide. Sanyu Rec Company Ltd. Mountain View CA, 94043 Royce Die Sorters (AutoPlacer MP300, DE35- 3-5-1 Doucho, Takatsuki Phone: +1 650-282-6226 ST and our new AP+) offer fully-automatic and Osaka 569-8558, Japan Fax: +1 650-230-9192 semi-automatic die sorting solutions for today’s Phone: +81-8-0578-13684 www.qualitau.com challenging applications, including die as small www.sanyu-rec.jp Email: [email protected] as 200 um square or 50 um thick. Our new Contact: Hiroshi Yamada Booth 416 automated die sorter, the AP+ has the capability Email: [email protected] QualiTau offers a variety of reliability test to handle the output mediums your process Booth 115 equipment for characterization and development requires (carrier tape, waffle pack, Gel-Pak, Sanyu Rec Company Ltd. is a Japanese electronics of new materials used in the manufacturing of JEDEC tray, film frame, grip ring, and custom material supplier to the semiconductor market Integrated Circuits, as well as process monitoring trays) and place to output while maintaining input place including LED market. With creative and process qualification. The MIRA, Infinity, ACE, to output traceability at the die level. development and numerous proprietary and Multi-Probe reliability test systems perform technologies, SANYU REC contributes to these tests for Hot Carrier Injection (HC), Dielectric growth fields which are driven by environmental Breakdown (TDDB), and electromigration(EM) considerations and mobile applications. SANYU of interconnects, TSV, Solder Bump (8 amperes REC has provided a variety of products centering max) at test temperatures of up to 450°C. on encapsulation materials like liquid MUF QualiTau’s Test Lab service is ideal for both (mold underfill) material to the market. Capillary fabless companies and foundries seeking: Reliable, underfill, die attach materials, and mold sheets independent evaluation and analysis. “Virtual” are also in our main product lines. Not only these materials but also VPES (vacuum printing

35 equipment) and pressure oven are in our product Semiconductor Equipment Corp. SHENMAO AMERICA, Inc. lines to offer comprehensive solutions to the 5154 Goldman Avenue 2156 Ringwood Ave. customers, which distinguishes us from our Moorpark, CA 93021 San Jose, CA 95131 competitors. SANYU REC is continuing our effort Phone: +1 805-529-2293 Phone: +1 408-943-1755 in development of unique and new technologies. Fax: +1 805-529-2193 Fax: +1 408-684-5477 Among such, LED is one of the areas SANYU www.semicorp.com www.shenmao.com REC is promoting the shift to. Contact: Don Moore Contact: Hans Schiesser Email: [email protected] Email: [email protected] SavansSys Booth 206 Booth 514 10409 Peonia Court Semiconductor Equipment Corporation, is SHENMAO America, Inc. is the American Austin, TX 78733 a manufacturer and distributor of manual, subsidiary of SHENMAO Technology, Inc. of Phone: +1 512-402-9943 semiautomatic, and automatic equipment for TaoYuan City 328, Taiwan. Shenmao is a global www.savansys.com the Photonics, Semiconductor, MEMS, SMT and leader in manufacturing solder materials for over Contact: Amy Palesko Hybrid Industries. Back end products include 44 years with 10 manufacturing, technical, and Email: [email protected] flip-chip bonders, ultrasonic die bonders, laser sales support facilities located around the world. Booth 210 diode bonders, eutectic die bonders, manual SHENMAO America, Inc. manufactures solder SavanSys is the industry standard choice for pick & place, epoxy die bonders, die rework, paste in San Jose, CA, USA, also supporting a electronics manufacturing cost modeling. The dicing tape, manual and automatic dicing tape wide range of products for the Semiconductor company began in the mid-nineties with a focus applicators, UV tape curing system, backgrinding Packaging and PCB Assembly industries. on multi-chip module and PCB fabrication and tape, backgrinding tape applicators, backgrinding SHENMAO produces SMT Solder Paste, Laser assembly before expanding into electronics tape peelers, and die ejectors. Front end products Soldering Paste, Wave Solder Bar, Solder Wire packaging. SavanSys provides both cost modeling include semiautomatic and fully automatic with/without Flux, Liquid and Paste Flux, Solder services and software products and maintains an cassette, SMIF, RSP, FOSB, FOUP, and EUV pod Preforms, Semiconductor Packaging Solder extensive library of manufacturing activity costs. cleaning systems and cleaning wafers for vacuum Spheres, Wafer Bumping Solder Paste, Dipping Projects range from multi-year ventures focused and e-chucks. Flux, LED Die Bonding Solder Paste, Plating on detailed supply chain modeling to one-time Anode and Solar PV Ribbon. 11 of the 12 largest projects comparing a new technology to the Senju Comtek EMS Companies are valued customers that are current industry standard. All SavanSys projects 2989 San Ysidro Way continuously using SHENMAO Technology, Inc. and products use activity based cost modeling, Santa Clara, CA 95051 Solder Materials with great success. OSAT’s, which is a bottom-up approach to cost that Phone: +1 408-963-5300 EMS and OEM’s qualify/re-qualify our products aggregates individual cost contributors (labor, Fax: +1 408-963-5399 for many years. For more information please material, throughput, equipment cost, etc.) for www.senju-m.co.jp/en contactwww.shenmao.com every step in a process flow. Contact: Ayano Kawa Email: [email protected] Shin-Etsu MicroSi, Inc. SCHOTT North America, Inc. Booth 412 10028 S. 51st St. 400 York Avenue Senju Comtek Corp. is an American subsidiary Phoenix, AZ 85044 Duryea, PA 18642, USA of Senju Metal Industry Co. (SMIC) of Tokyo, Phone: +1 480-893-8898 Contact: Dave Vanderpool Japan. Senju is a global leader in solder materials Fax: +1 480-893-8637 Phone +1 407-288-7695 and related processing equipment with over two www.microsi.com Fax +1 407-321-8847 dozen manufacturing, technical, and sales support Email: [email protected] www.us.schott.com facilities located around the world. Senju Comtek Booth 310 Email: [email protected] has two solder paste manufacturing locations in Shin-Etsu MicroSi, Inc. is a wholly owned Booth 508 USA (San Jose, CA and Chicago, IL) supporting subsidiary of Shin-Etsu Chemical Ltd. Shin-Etsu SCHOTT Advanced Optics is a valuable partner a wide range of products for the semiconductor MicroSi is a world class supplier of packaging for its customers in developing products and and PCBA industries. materials for the semiconductor industry. With customized solutions for applications in optics, a global support network- Sales Engineers, R&D, lithography, astronomy, opto-electronics, life SET North America Manufacturing, Quality Assurance, and Logistics- sciences, and research. With a product portfolio 343 Meadow Fox Ln. we are able to quickly develop and provide new of more than 120 optical glasses, special materials Chester, NH 03036 technologies to benefit our customers. This and components, we master the value chain: from Phone: +1 603-548-7870 allows our clients to meet their ever changing customized glass development to high-precision Fax: +1 603-887-2000 technical, commercial and environmental needs optical product finishing and metrology. SCHOTT www.set-na.com by implementing Shin-Etsu MicroSi’s technology. is one of the world’s leading suppliers of thin Contact: Matt Phillips Shin-Etsu MicroSi is known for supplying high and ultra-thin glass wafers and substrates made Email: [email protected] performance Thermal Interface Materials, of different materials in sizes of between 4” and Booth 120 Underfills, Molding Compounds, High Purity 12”, in thicknesses down to 25 µm, with various To enable high-density interconnect, SET- Silicone Encapsulants, and Die Attach Materials. surface qualities and customized features. The North America offers surface preparation and use of proprietary production processes, a wide high-accuracy bonding tools with unparalleled Shinkawa USA, Inc. selection of different materials, and continuous performance. For removing native oxides, residual 1177 S. Porter Court expansion of state-of-the-art processing organics or other bond inhibitors, the ONTOS7 Gilbert, AZ 85296 capabilities make SCHOTT’s wafer offerings Atmospheric Plasma Surface Preparation tool Phone: +1 480-831-7988 unique in the industry. Process Capabilities include cleans and passivates bonding surfaces to provide www.shinkawa.com/en/ polishing, structuring, edge treatment, ultrasonic high-quality bonds with superior electrical and Contact Doug Day washing, and clean room packaging. SCHOTT’s mechanical integrity. This tool is also effective in Email: [email protected] portfolio of Thin and Ultra-Thin glasses includes: activating surfaces to enhance wetting and wicking Booth 512 AF 32® eco, an alkali-free flat glass with a CTE for aqueous processes or underfill materials. Shinkawa is a leading supplier of flip chip, wire matched to silicon; D 263® eco, a high CTE The device bonders manufactured by SET are bonding and die bonding equipment. The wide and high transmission glass; SCHOTT AS 87 globally renowned to deliver unsurpassed bonding range of equipment supports various applications eco, world’s first ultra-thin and toughenable glass; accuracy (±0.5 μm) at high temperatures and including IoT and infrastructure (server/memory), B 270® i, a crown glass with extremely high CTE; forces for chips and substrates ranging from tiny, as well as mobile and communication devices. and MEMpax®, an anodic bondable glass with fragile components up to 300 mm wafers. With Shinkawa provides key innovative solutions for a CTE corresponding to silicon. The portfolio is a product portfolio ranging from manually loaded future packaging technology with high-accuracy supplemented by FOTURAN® II, SCHOTT’s versions to fully-automated operation, SET offers TCB flip chip bonders and ultra-high throughput unique photo-sensitive glass. bonding and nanoimprint solutions with high flip chip bonders for the mass reflow process flexibility and field-proven reliability. (C4/C2). In the field of die and wire bonding, Shinkawa provides ultra-thin die pick up

36 technology and unique wire shape technology advanced etch, PVD, and CVD wafer processing TATSUTA USA Inc. for RF, PoP and many other devices. Founded in equipment and solutions for the global 5201 Great America Parkway, 1959 in Tokyo and now with a strong presence in semiconductor and micro-device industries, Suite 320 the semiconductor market, Shinkawa services and with focus on the Advanced Packaging, MEMS, Santa Clara, CA 95053 supports a diverse network of global customers high speed RF device, power management Phone: +1 408-850-7166 and partners all over the world. and LED markets. With the addition of SPTS, Fax: +1 408-562-5745 Orbotech is able to offer a broader range of www.tatsuta.com Shinko Electric America process solutions for Advanced Packaging, which Contact: Mike Sakaguchi 1280 East Arques Avenue MS 275 includes Orbotech’s Inkjet solutions for die level Email: [email protected] Sunnyvale, CA 94085 printing of package marking, underfill dams and Booth 106 Phone: +1 408-232-0493 isolation layers. SPTS has manufacturing facilities TATSUTA is leading provider of EMI shielding Fax: +1 408-955-0368 in Newport, Wales and Allentown, Pennsylvania, conductive material for semiconductor industry. www.shinko.com and operates across 19 countries in Europe, TATSUTA provides innovative solutions for Contact: Michael Hudgens North America and Asia-Pacific. conformal and compartment shielding with Email: [email protected] micron size copper and silver conductive paste. Booth 421 STATS ChipPAC TATSUTA is also provide unique high reliability SHINKO Electric Industries Co., LTD., is a 46429 Landing Parkway metallizing paste for TMV filling, low temperature leading manufacturer of products used in the Fremont, CA 94538 cure type conductive paste for circuitry printing assembly of IC’s such as Organic Substrates, Phone: +1 510-979-8000 and 3D SMT For more details, please visit our Etched and Stamped Leadframes, TO Packages Fax: +1 510-979-8001 booth 106. We will provide solutions for your and Integrated Heatspreaders. We manufacture www.statschippac.com applications. a full line of Organic Substrate structures including Contact: Lisa Lavin coreless options offering enhanced electrical Email: [email protected] TechSearch International Inc. performance and package miniaturization. Booth 101 4801 Spicewood Springs Rd., Suite 150 SHINKO also provides subcontract IC assembly STATS ChipPAC is a leading OSAT provider Austin, TX 78759 services with an emphasis on packaging solutions of semiconductor design, wafer bump, probe, Phone: +1 512-372-8887 such as PoP, SiP as well as advanced technologies packaging and test solutions for well-established Fax: +1 512-372-8889 such as Molded Core Embedded Package market segments such as communications, www.techsearchinc.com (MCeP®) and Camera Module assembly and consumer and computing as well as emerging E-mail: [email protected] test. Our headquarters and primary production markets in automotive electronics, Internet of Contacts: Becky Travelstead plants are located in the greater Nagano, Japan Things (IoT) and wearable devices. With a global Booth 300 area. In addition to our production facilities we manufacturing presence spanning Singapore, TechSearch International, Inc. has a 28-year also provide the ultimate in service and solutions South Korea, and China and a broad technology history of market and technology trend analysis for customers, with Sales and Engineering support portfolio ranging from leadframe and laminate focused on semiconductor packaging, materials, Worldwide. Come visit us at booth 421 to learn packages to advanced fan-out and fan-in wafer and assembly. Research topics include WLP, more about our latest product offerings for fine level technology, flip chip interconnect, MEMS and FO-WLP, Flip chip, CSPs including stacked die, pitch interconnection, miniaturization and high sensors, System-in-Package (SiP) and 2.5D/3D BGAs, 3D ICs with TSVs, 2.5D interposers, and density mounting for 3D assembly. packaging, STATS ChipPAC provides customers System-in-Package (SiP), embedded components, with innovative and cost-effective semiconductor ADAS and automotive electronics, and panel- Sonoscan, Inc. solutions. STATS ChipPAC differentiates itself based processing. In conjunction with SavanSys 2149 East Pratt Blvd. through innovative packaging solutions that Solutions, wire bond, flip chip, WLP, and 3D IC Elk Grove Village, IL 60007 meet increasing market demands for higher cost models are offered. TechSearch International Phone: +1 847-437-6400 performance, functionality and processing professionals have an extensive network of Fax: +1 847-437-1550 speeds with a significant reduction in space in an more than 16,000 contacts in North America, www.sonoscan.com electronics device. Asia, and Europe and travel extensively, visiting Contact: Jack Richtsmemer major electronics manufacturing operations and Email: [email protected] TAIYO INK MFG. CO., LTD research facilities worldwide. Booth 209 2675 Antler Drive Founded in 1973 and headquartered in Chicago, Carson City, NV 89701 TECNISCO, LTD. IL, Sonoscan®, Inc. is a worldwide leader and Phone: +1 408-821-2705 2-2-15, Minami-Shinagawa, innovator in Acoustic Micro Imaging (AMI) www.taiyo-hd.co.jp/en/ Shinagawa-ku Tokyo, 1400004, Japan technology. Sonoscan manufactures and markets Contact: Dan Okamoto Phone: +81-3-3472-6963 acoustic microscope instruments and accessories Email: [email protected] Fax: +81-3-3472-1316 to nondestructively inspect and analyze products. Booth 111 www.tecnisco.co.jp/en/ Our C-SAM® scanning acoustic microscope TAIYO INK MFG. CO., LTD has more than Contact: Haruka Aizawa provides unmatched accuracy and robustness 90% market share of solder resist products on Email: [email protected] setting the standard in AMI for the inspection of IC-Packaging industry. Recently, TAIYO INK Booth 110 products for hidden internal defects such as poor MFG. CO., LTD introduced two important TECNISCO is process service provider of bonding, delaminations between layers, cracks products to the market. The first product, precision component. Since established, we and voids. In addition, Sonoscan offers analytical AZ1, provides very robust TST crack resistance have expanded the technical process field and services through regional testing laboratories with higher Tg best for large body FCBGA generated “Cross-edge” micro processing in Asia, Europe and the U.S. and educational and automotive BGA products. The other which means cross over the 5 (Kiru, Kezuru, workshops for beginners to advanced on AMI new product, SR3, offers very low CTE (15- Migaku, Metalize, and assembling) cutting technology. 20ppm) with high modulus (>10GPa) ideally edge technologies for supporting in the field of for coreless/thin core applications. Also, based Opto-telecommunication, Industrial lasers and SPTS Technologies on our expertise in photo-imageable dielectric MEMS devices for medical industries. We are Ringland Way technology, we started to offer a photo- doing processing services and able to supply Newport NP18 2TA UK imageable dielectric dry film material as a build-up customized parts that are manufactured with Phone: +44 1633 414000 material for BGA substrates or interposers, or as metal, ceramic, glass and silicon by its advanced www.spts.com an insulation material for embedded applications. high-precision processes and composite Contact: Wendy Davis Furthermore, this material can replace PI/PBO technologies. TECNISCO’s expertise includes: Email: [email protected] for WLP / PLP products with greater advantage. Dicing, Sandblasting, Milling (CNC machining), Booth 201 For more details, please visit our booth 111. Our Assembling (AuSn, AuGe, AgCuIn, AgCu), SPTS Technologies, an Orbotech company, engineer will meet you there to answer all of your Polishing, Bonding, Metallization (Plating, designs, manufactures, sells, and supports questions including those about our material for Sputtering, Vapor deposition) for producing such your applications. as CuW, CuMoCu, CuAlNCu, Cu heatsinks (for

37 High power laser diode ) and Structured glass processing, and creation of a 2.5/3D IC process Towa USA Corporation wafer (for MEMS and Medical divice). workflow and methodology, etc. T-Micro’s 1430 Tulley Rd. Ste. 416 proprietary micro Au bump technology is fine San Jose, CA 95122 Teikoku Taping Systems size/pitch of 2.5um/5um and being utilized for Phone: +1 408-779-4440 5090 N 40th St. Suite 140 advanced sensors with millions of bumps. Our Fax: +1 408-779-4413 Phoenix, AZ 85018 cost‐competitive process infrastructure, using www.towajapan.co.jp Phone: +1 602-367-9916 a complete line of state‐of‐the‐art equipment, Contact: Naoki Hamada www.teikoku-taping.com provides worldwide customers with a cost‐ Email: [email protected] Contact: Joe Umpleby effective and short‐term TAT prototyping Booth 509 Email: [email protected] service for fundamental 3D‐IC R&D, technology Towa Corporation is the market leader in Booth 104 evaluation, “proof of concept” projects, providing leading edge molding solutions to the Teikoku Taping System has been a major prototype making for mass-production, and a semiconductor industry. Towa proudly offers the equipment supplier in the semiconductor industry base‐line process development for 3D-IC/Si latest compression mold solutions for advanced for more than 25 years. TTS specializes in interposer devices. applications such as wafer level molding, large designing, developing and manufacturing of back panel molding, stacked die, TSV, Molded Underfill end semiconductor equipment used for MEMS Tokyo Ohka Kogyo Co., Ltd. and LED’s. Towa’s compression mold systems dry film resist lamination, dicing, tape-and-die TOK America, Inc. have proven to be the most cost effective, attach film mounting, back grind tape lamination, 190 Topaz St. technologically advanced solutions for today’s and UV irradiation. Customers will be assured Milpitas, CA 95035 demanding applications. Towa also continues to because we are there to assist you throughout Phone: +1 408-934-8904 be the leader in transfer mold systems for your purchase, and support with processing set up Fax: +1 408-956-9995 MCM, BGA, automotive, and medical packaging and service after installation of TTS tools. Teikoku www.tok.co.jp/en/index.php applications. Towa has over 30 years of Taping System has three main focus areas: taping Contact: Yoshi Arai transformative technological leadership to support (“Haru”), de-taping (“Hagasu”) and handling Email: [email protected] all your packaging needs. (“Hakobu”). Booth 207 For over 60 years, TOK has supplied high purity Tresky GmbH ThreeBond International, Inc. chemicals and electronic materials across the Oranienburger Chaussee 31-33 6184 Schumacher Park Dr. globe. In 1971, TOK expanded its specialization 16548 Glienicke/Nordbahn West Chester, OH 45069 to also include process equipment production. Germany Phone: +1 408-638-7091 TOK has leveraged its microprocessing Phone: +49-33056-275 410 Fax: +1 513-779-7375 technology across various business fields: Fax: +49-33056-430 235 www.threebond.com Semiconductor, packaging, LCDs, 3D integration, www.tresky.de Contact: Kensuke Kitamura MEMS and image sensor solutions, and Contact: Daniel Schultze Email: [email protected] commercial products in new and emerging Email: [email protected] Booth 217 technologies. Current material and equipment Booth 516 Since founded in 1955 in Japan, Threebond has offerings enable fabrication of 3DIC and include Tresky GmbH is a manufacturer of advanced been offering the adhesive/sealant products photosensitive materials for insulation, passivation, Automated and Manual Die Attach and Flip globally with its cutting-edge technologies. RDL, bump, TSV, plating, encapsulation, and Chip Systems. Tresky’s modular bonding platform Threebond has developed networks across six other packaging related applications. allows modular setup for new processes by regions: Japan, North/central Americas, south adapting various options. Eutectic die bonding America, Europe, Asia, and China.. Threebond Toray International America with fast ramp rate heating plates, epoxy develops products mainly in the four sectors: 411 Borel Ave., Suite 520 dispensing and stamping, accommodation for Transportation Equipment, Electrical and San Mateo, CA 94402 up to 12” wafers and automatic tool change are Electronics, Industrial Materials & Public Works, Phone: +1 650-341-7152 just a few available options. For over 35 years, and Automotive Aftermarket. Threebond Fax: +1 650-341-0845 Tresky has been perfecting the art of creating high offers unique products such as UV-curing black www.toray.US/products/prod_003. precision assembly and die bonding systems for adhesive, 60°C x 1 minute curing elastic adhesive, html the semiconductor and microelectronics industry. moisture blocking adhesive, UV-activated dual Contact: Hiroyuki Niwa The fully automated bonding platforms T-6000-L curing epoxy, ultra low viscosity (2cP) UV-curing Email: [email protected] and T-8000 offering a high accurate placement in CA, high thermally conductive epoxy, etc. About Booths 407, 409 combination with a large working area. Tresky’s 1,600 products will provide solutions to the Toray Industries is a leading provider for Non- T-3000 series can generate forces up to 50kg, problems you are facing. Ask Threebond if you Conductive Film (NCF) for flip chip packages, using the True Vertical TechnologyTM and Beam need any specific adhesive or sealant. and photo-definable adhesive film for build-up Splitter Optics, can achieve 1.5μm alignment substrates and packages with cavity structure. resolution. Tohoku-MicroTec Co., Ltd. Toray’s unique polyimide and film processing T-Biz 203, 6-6-40 Aza-Aoba, technologies provide excellent reliability and Unisem Aramaki, Aoba-ku, performance which are already proven in the 2241 Calle de Luna Sendai, Miyagi 980-8579 Japan market. “Photoneece” is Toray’s photo-definable Santa Clara, CA 95054 Phone: +81-22-398-6264 polyimide coatings for front-end buffer layer and Phone: +1 408-734-3222 Fax: +81-22-398-6265 back-end re-distribution layer for WLP and TSV. Fax: +1 408-562-9971 www.t-microtec.com We also offer a newly developed “Photoneece” www.unisemgroup.com Contact: Mike Hasegawa LT-series, which enables low temperature Contact: Gil Chiu E-mail: [email protected] cure with low residual stress for minium wafer Email: [email protected] Booth 506 warpage. Toray Engineering Co., Ltd. provides Booth 105 Tohoku-MicroTec (T-Micro) is the leading state-of-the-art Flip Chip Bonding Equipment Unisem is a global provider of semiconductor 3D/2.5D foundry service professional. Our for semiconductor packaging (FC3000), Chip assembly and test services for many of the facility, “GINTI”, in Japan equips a new and on Wafer Bonding Equipment (FC3000W), world’s most successful electronics companies. complete 3D/2.5D process line of 200/300 mm Vacuum Encapsulation Equipment (VE500) and Unisem offers an integrated suite of packaging wafer. T-Micro provides worldwide customers various flexible substrates (TCP, interposer) and test services such as wafer bumping, wafer a wide variety of 3D-IC stacking service: full manufacturing equipment such as resist coater, probing, wafer grinding, a wide range of leadframe 200/300 mm wafer-to-wafer processing, chip‐ proximity exposure tool, etching and developing and substrate IC packaging, wafer level CSP and to‐wafer processing with VIA-last TSV by use lines. RF, analog, digital and mixed-signal test services. of current commercial/customized 2D chips, Our turnkey services include design, assembly, chip-to-chip special processing, large and thick test, failure analysis, and electrical and thermal Si-interposer processing, TSV/Micro-bump TEG characterization. With approximately 7,000

38 employees worldwide, Unisem has factory improve electrical properties of the copper layer, Zuken, Inc. locations in Ipoh, Malaysia; Chengdu, People’s and low-K dielectric cure to remove all moisture 1900 McCarthy Blvd. Republic of China and Batam, Indonesia. The from porous low-K material. Our manual and Suite 400 company is headquartered in Kuala Lumpur, automated vacuum cure ovens accommodate up Milpitas, CA 95035 Malaysia. to 300mm wafers and offer critical improvements Phone: +1 408-890-2831 in any cure process including complete removal www.zuken.com UnitySC of residual solvents, uniform temperature Email: [email protected] 611, rue Aristide Berges distribution, pressure control, ability to maintain Booth 118 ZA du Pre Millet dry inert atmosphere, and control of heating Zuken is a global provider of leading-edge 38330 Montbonnot Saint Martin, and cooling rates. In addition, YES ovens achieve software and consulting services for system- France particle reduction in most applications. YES level electrical and electronic design and Phone: +33-456-52-6800 equipment is engineered, manufactured and manufacturing. Founded in 1976, Zuken has Contact: Yann Guillou tested in Livermore, California USA. The answer the longest track record of technological Email: [email protected] is YES to quality, flexibility, superior products and innovation and financial stability in the electronic Booth 219 service. design automation (EDA) software industry for UnitySC is recognized worldwide as a key player advanced packaging, printed circuit board design, in inspection and metrology, combining advanced YOLE DEVELOPPEMENT and multi-domain co-design. The company’s technologies in automated optical inspection and Le Quartz – 75 cours Emile Zola extensive experience, technological expertise and 3D imaging with microscopy, temporal-mode 69100 Lyon-Villeurbanne, France agility, combine to create world-class software interferometry, and spectrometry, which enables Phone: +33-472-83-01-80 solutions. Zuken’s transparent working practices customers to deliver higher yields and faster Fax: +33-472-83-01-83 and integrity in all aspects of business produce time to market. UnitySC provides standard and www.yole.fr long-lasting and successful customer partnerships customized solutions adapted to specific industrial Contact: Camille Veyrier that make Zuken a reliable long-term business needs and constraints, enabling a new era in Email: [email protected] partner. Zuken is focused on being a long-term process control. Headquartered in Grenoble, Booth 404 innovation and growth partner. The security France, the company maintains offices in Taiwan Founded in 1998, Yole Développement has of choosing Zuken is further reinforced by the and is supported by a network of representatives grown to become a group of companies company’s people— the foundation of Zuken’s and distributors. Customers include the largest providing marketing, technology and strategy success. Coming from a wide range of industry foundries, integrated device manufacturers, consulting, media and corporate finance services. sectors, specializing in many different disciplines outsourced semiconductor assembly and test With a strong focus on emerging applications and advanced technologies, Zuken’s people service providers, and R&D centers. using silicon and/or micro manufacturing, relate to and understand each company’s unique the Yole has expanded to include more than requirements. XYZTEC 50 collaborators worldwide covering MEMS, 36 Balch Ave. Compound Semiconductors, LED, Image Zymet, Inc. Groveland, MA 01834 Sensors, Optoelectronics, Microfluidics & 7 Great Meadow Lane Phone: +1 978-880-2598 Medical, Advanced Packaging, Manufacturing, E. Hanover, NJ 07936 www.xyztec.com Nanomaterials, Power Electronics and Batteries Phone: +1 973-428-5245 Contact: Tom Haley & Energy Management. The “More than Fax: +1 973-428-5244 Email: [email protected] Moore” company Yole and its partners System www.zymet.com Booth 221 Plus Consulting, Blumorpho and KnowMade Contacts: Kelly Nostrame and Karl Loh XYZTEC, Inc. is the technology leader in bond support industrial companies, investors and R&D Email: [email protected] testing throughout the world. We are constantly organizations worldwide to help them understand Booth 321 innovating a technology that has been basically markets and follow technology trends to develop Adhesives and encapsulants for electronics and unchanged for many years. Our award winning their business. CONSULTING: Market data & optoelectronics assembly. Products include reworkable and non-reworkable underfill Condor Sigma includes a Rotating Measurement research, marketing analysis; Technology analysis; encapsulants, edgefill adhesives, and edgebond unit that allows up to 6 sensors to be available Reverse engineering & costing services; Strategy adhesives for high reliability board level assembly. with a mouse click. Our automation software consulting; Patent analysis. REPORTS: Collection Products also include electrically conductive and now includes a wire detection function that allows of technology & market reports; Manufacturing thermally conductive adhesives, ultralow stress complete hands off wire pull testing and our auto cost simulation tools; Component reverse adhesives, ACP’s and NCP’s, and UV curable grading capability makes shear-testing extremely engineering & costing analysis; Patent investigation encapsulants. fast and reliable. MEDIA: i-Micronews.com; @Micronews, weekly e-newsletter; Communication & webcasts Yield Engineering Systems services; Events: Yole Seminars, Market Briefing. 203A Lawrence Drive Livermore, CA 94551 Phone: +1 925-373-8353 www.yieldengineering.com Contact:Nicole Williams-Pruitt Email: nwilliams-pruitt@ ECTC SPONSORS yieldengineering.com Booth 116 With 67 years of history and experience options that can be customized to your Yield Engineering Systems (YES) provides a behind us, ECTC is recognized as the premier company’s interest. If you would like to enhance wide variety of processing equipment including semiconductor packaging conference and your presence at ECTC and increase your ovens for the cure of dielectric materials. YES offers an unparalleled opportunity to build impact with a sponsorship, please take a look manufactures quality equipment for the Fan-Out relationships with more than 1,000 individuals at our sponsorship brochure on the website Wafer Level Packaging, Semiconductor, MEMS, and organizations committed to driving www.ectc.net under “Sponsors.” Photovoltaic, FPD, Medical industries and more. innovation in semiconductor packaging. To sign-up for sponsorship or to get more Applications for our vacuum cure ovens include We have a limited number of sponsorship details, please contact Wolfgang Sauter at Polyimide/PBO cure, BCB bake for adhesive opportunities in a variety of packages to help get [email protected] wafer bonding, low temp polymer cure for your message out to attendees. These include or +1-802-922-3083. temperature sensitive devices, copper anneal to Gala, Program, and several other sponsorship

39 2017 Executive Committee Professional Development Course Chair Applied Reliability General Chair Kitty Pearsall Chair Henning Braunisch Boss Precision, Inc. Vikas Gupta Intel Corporation [email protected] Texas Instruments, Inc. [email protected] +1-512-845-3287 [email protected] +1-480-552-0844 Arrangements Chair +1-214-567-3160 Lisa Renzi Ragar Assistant Chair Vice-General Chair Renzi & Company, Inc. Deepak Goyal Sam Karikalan [email protected] Intel Corporation Broadcom Limited +1-703-863-2223 [email protected] [email protected] +1-480-554-5203 +1-949-926-7296 CPMT Representative C. P. Wong Babak Arfaei Program Chair Georgia Institute of Technology Ford Motor Company Mark Poliks [email protected] Sridhar Canumalla Binghamton University +1-404-894-8391 Microsoft Corporation [email protected] Tim Chaudhry +1-607-727-7104 2017 Program Committee Amkor Technology, Inc. Assistant Program Chair Advanced Packaging Tz-Cheng Chiu Christopher Bower Chair National Cheng Kung University X-Celeprint Inc. Young-Gon Kim Darvin R. Edwards [email protected] Integrated Device Technology, Inc. Edwards Enterprises +1-919-522-3230 [email protected] Dongming He Jr. Past General Chair ECTC +1-408-360-1545 Qualcomm Technologies, Inc. Alan Huffman Assistant Chair Toni Mattila Micross Advanced Interconnect Technology Luu Nguyen Aalto University [email protected] Texas Instruments Inc. Keith Newman +1-919-248-9216 [email protected] AMD Sr. Past General Chair ECTC +1-669-721-4786 Daniel Baldwin Donna M. Noctor Beth Keser Alcatel-Lucent Intel Corporation H.B. Fuller Company [email protected] Bora Baloglu S. B. Park Amkor Technology Binghamton University Sponsorship Chair Rozalia Beica Lakshmi N. Ramanathan Wolfgang Sauter Microsoft Corporation GLOBALFOUNDRIES Dow Electronic Materials wolfgang.sauter@globalfoundries,.com Jianwei Dong Richard Rao MicroSemi +1-802-922-3083 Dow Electronic Materials René Rongen Luke England Finance Chair NXP Semiconductors Patrick Thompson GLOBALFOUNDRIES Texas Instruments, Inc. Scott Savage Allyson Hartzell Medtronic Microelectronics Center [email protected] Veryst Engineering +1-214-567-0660 Jeffrey Suhling Beth Keser Auburn University Publications Chair Intel Corporation Dongji Xie Steve Bezuk John Knickerbocker NVIDIA Corporation Qualcomm Technologies, Inc. IBM Corporation [email protected] Steffen Kroehnert +1-858-218-5143 Assembly & Manufacturing Technology Nanium S.A. Chair Publicity Chair John H. Lau Wei Koh Eric Perfecto ASM Pacific Technology Pacrim Technology GLOBALFOUNDRIES Markus Leitgeb [email protected] [email protected] +1-714-417-9979 +1-845-894-4400 AT&S Mike Ma Assistant Chair Treasurer Amkor Technology Taiwan (ATT) Paul Tiner Tom Reynolds Texas Instruments T3 Group LLC Dean Malta [email protected] [email protected] Micross Advanced Interconnect Technology +1-469-471-3565 +1-850-897-7323 Deborah S. Patterson Sai Ankireddi Principal, Patterson Group Exhibits Chair Maxim Integrated Products, Inc. Joe Gisler Raj Pendse Garry Cunningham Vector Associates Qualcomm Technologies, Inc. NGC [email protected] Subhash L. Shinde Mark Gerber +1-480-288-6660 Notre Dame University Advanced Semiconductor Engineering Inc. USA Web Administrator Joseph W. Soucy Paul Houston Nancy Stoffel Draper Engent GE Global Research Kuo-Chung Yee Sa Huang [email protected] TSMC Medtronic Corporation +1-518-387-4529 Christophe Zinck Li Jiang 40 ASE Texas Instruments Vijay Khanna Xiaoxiong (Kevin) Gu Ramakrishna Kotlanka IBM Corporation IBM Corporation Analog Devices Chunho Kim Rockwell Hsu Kevin J. Lee Medtronic Corporation Cisco Systems, Inc. Qorvo Corporation Yang Liu Lih-Tyng Hwang Menglu Li IBM Corporation National Sun Yat-Sen University Qualcomm Technologies, Inc. Cheng-Hsiang (Sean) Liu Mahadevan K. Iyer Minhua Lu Siliconware Precision Industries Co. Ltd Texas Instruments, Inc. IBM Corporation Debendra Mallik Bruce Kim Bharat Penmecha City University of New York Intel Corporation Intel Corporation Timothy G. Lenihan Li Ming C. S. Premachandran TechSearch International ASM GLOBALFOUNDRIES Sebastian Liau Jae-Woong Nah Jintang Shang IBM Corporation ITRI Southeast University Valerie Oberson Lianjun Liu Nancy Stoffel IBM Corporation Freescale Semiconductor, Inc. GE Global Research Tom Poulin Nanju Na Aerie Engineering Xilinx Maaike M. Visser Taklo SINTEF ICT Shichun Qu Dan Oh Lumileds Altera Corporation Jimin Yao Intel Corporation Shawn Shi Andrea Paganini Medtronic Corporation GLOBALFOUNDRIES, Inc. Yue Zhang Oracle Tom Swirbel Luca Roselli Motorola, Inc. University of Perugia Sean Too Hideki Sasaki Interconnections Microsoft Renesas Electronics Corporation Chair Andy Tseng Li-Cheng Shen Katsuyuki Sakuma JSR Micro Quanta Research Institute IBM Corporation [email protected] Jan Vardaman Manos M. Tentzeris Georgia Institute of Technology +1-914-945-2080 Techsearch International Assistant Chair Shaw Fong Wong Nathan Lower Intel Corporation Emerging Technologies Chair Rockwell Collins, Inc. Jin Yang John Cunningham [email protected] Intel Corporation Consultant +1-319-295-6687 Tonglong Zhang [email protected] Thibault Buisson Nantong Fujitsu Microelectronics Ltd. +1-858-526-9121 Yole Développement Assistant Chair William Chen High-Speed, Wireless & Components Vaidyanathan Chelakara Advanced Semiconductor Engineering, Inc. Chair Acacia Communications, Inc. Kathy Cook P. Markondeya Raj [email protected] Tessera Georgia Institute of Technology +1-978-938-4896 x 883 [email protected] Isaac Robin Abothu David Danovitch +1-404 558 2615 Siemens Medical Solutions USA Inc. University of Sherbrooke Assistant Chair Jai Agrawal Rajen Dias Kemal Aygun Purdue University Amkor Technology, Inc. Intel Corporation Ankur Agrawal Bernd Ebersberger [email protected] Intel Corporation Intel Corporation +1-480-552-1740 Meriem Akin Takafumi Fukushima Amit P. Agrawal Leibniz Universitaet Hannover Tohoku University Keyssa Inc. Vasudeva P. Atluri Thomas Gregorich Wendem Beyene Renavitas Technologies SanDisk Rambus Inc. Mark Bachman Li Li Eric Beyne University of California, Irvine Cisco Systems, Inc. IMEC Karlheinz Bock Changqing Liu Prem Chahal Technische Universitat Dresden Loughborough University Michigan State University Benson Chan Wei-Chung Lo Zhaoqing Chen Binghamton University ITRI IBM Corporation Rabindra N. Das Craig Gaw MIT Lincoln Labs James Lu Rensselaer Polytechnic Institute NXP Semiconductor Steve Greathouse Apostolos Georgiadis Plexus Corporation Voya Markovich Microelectronic Advanced Hardware Consulting, Centre Tecnologic de Telecomunicacions de Florian Herrault LLC Catalunya (CTTC) HRL Laboratories, LLC Abhilash Goyal W. Hong YEO Lou Nicholls Oracle Amkor Technology, Inc. Georgia Institute of Technololgy 41 Gilles Poupon Hongbin Yu Alex Rosiewicz CEA-Leti Arizona State University A2E Partners Lei Shan Tieyu Zheng Henning Schroeder IBM Corporation Microsoft Corporation Fraunhofer IZM Ho-Young Son Andrew Shapiro SK Hynix Modeling & Simulation JPL Chuan Seng Tan Chair Masato Shishikura Nanyang Technological University Kuo-Ning Chiang Oclaro Japan Matthew Yao National Tsinghua University Hiren Thacker GE Energy Management [email protected] +886-3-574-2925 Masao Tokunari Dingyou Zhang IBM Corporation Qualcomm Technologies, Inc. Assistant Chair Jiantao Zheng Jean Trewhella Qualcomm Technologies, Inc. GLOBALFOUNDRIES Materials & Processing [email protected] Shogo Ura Chair +1-858-658-5738 Kyoto Institute of Technology Bing Dang IBM Corporation Xuejun Fan Stefan Weiss [email protected] Lamar University II-VI Laser Enterprise GmbH +1-914-945-1568 Przemyslaw Gromala Feng Yu Assistant Chair Robert Bosch GmbH Huawei Technologies Japan Mikel Miller Nancy Iwamote Thomas Zahner Draper Laboratory Honeywell OSRAM Opto Semiconductors GmbH [email protected] Pradeep Lall +1-617-258-2844 Ping Zhou Auburn University LDX Optronics, Inc. Tanja Braun Sheng Liu Fraunhofer IZM Wuhan University Yu-Hua Chen Interactive Presentations Yong Liu Unimicron Chair ON Semiconductor Michael Mayer Qianwen Chen Erdogan Madenci University of Waterloo IBM Corporation University of Arizona [email protected] Yung-Yu Hsu Tony Mak +1-519-888-4024 Apple Inc. Wentworth Institute of Technology Assistant Chair C. Robert Kao John Hunt National Taiwan University Erkan Oterkus University of Strathclyde Advanced Semiconductor Engineering, Inc. Dong Wook Kim [email protected] Gamal Refai-Ahmed Xilinx, Inc. +1 480-718-8011 Xilinx Chin C. Lee Swapan Bhattacharya University of California, Irvine Sandeep Sane Intel Corporation Engent Inc. Alvin Lee Rao Bonda Brewer Science Suresh K. Sitaraman Georgia Institute of Technology Amkor Technology Yi Li Mark Eblen Intel Corporation Wei Wang Qualcomm Technologies, Inc. Kyocera America, Inc. Kwang-Lung Lin Ibrahim Guven National Cheng Kung University G. Q. (Kouchi) Zhang Delft University of Technology (TUD) Virginia Commonwealth University Yan Liu Nam Pham Medtronic Inc. USA IBM Corporation Daniel D. Lu Opto-Electronics Mark Poliks Henkel Corporation Chair Takaaki Ishigure Binghamton University Diptarka Majumdar Superior Graphite Keio University Patrick Thompson [email protected] Texas Instruments, Inc. Joon-Seok Oh +81-45-566-1593 Samsung Electro-Mechanics Assistant Chair Professional Development Courses Praveen Pandojirao-S Gordon Elger Johnson & Johnson Chair Technische Hochschule Ingolstadt Kitty Pearsall Mark Poliks [email protected] Boss Precision, Inc. Binghamton University +49-841- 934-8284 [email protected] Dwayne Shirley Stephane Bernabe +1-512-845-3287 Ivan Shubin CEA Leti Assistant Chair Lejun Wang Fuad Doany Jeffrey Suhling Qualcomm Technologies, Inc. IBM Corporation Auburn University Frank Wei Soon Jang [email protected] Disco Japan ficonTEC USA +1-334-844-3332 Kimberly Yess Harry G. Kellzi Vijay Khanna Brewer Science Teledyne Microelectronic Technologies IBM Corporation Myung Jin Yim Masanobu Okayasu Lakshmi N. Ramanathan 42 Intel Corporation Oclaro Japan, Inc. Microsoft Corporation First Call for Papers

IEEE 68th Electronic Components and Technology Conference www.ectc.net To be held May 29 - June 1, 2018 at the Sheraton San Diego Hotel & Marina, San Diego, California, USA The Electronic Components and Technology Conference (ECTC) is the premier international electronics symposium that brings together the best in packaging, components and microelectronic systems science, technology and education in an environment of cooperation and technical exchange. ECTC is sponsored by the Components, Packaging and Manufacturing Technology (CPMT) Society of the IEEE. You are invited to submit abstracts that provide non commercial information on new developments, technology and knowledge in the areas including, but not limited to as given below under each technical program subcommittee name. Authors are encouraged to review the sessions of the previous ECTC programs to determine the committee selection for their abstracts.

Advanced Packaging: Interconnections: Fan-Out, 2.5 & 3D, TSV and Interposer, Heterogeneous Integration and SiP, Interconnections: Fan-Out and Fan-In, Wafer- and Panel-Level Interconnects, Embedded and Advanced Substrates, MEMS & Sensors, Automotive, Power 2.5D/3D, TSV Interconnect Structures for Heterogeneous Integration and SiP, Module, Wearable & IoT, Bio and Medical, RF, Microwave, Millimeter-Wave & Co-Designs and Process/Performance Trade-Off, Thermal/Mechanical/Electrical EMI, High Performance Computing and Data Center, Wafer Level & Panel Level Tests & Reliability, Embedded Systems; Si/Glass/Organic Interposers, PoP, Process, Advanced Flip-Chip, Advanced CSP and POP. WLCSP, Flip-Chip, Solder Bumping and Cu Pillar, TC Bonding, IMC Interconnect, Wirebonds, RDL, Conductive Adhesives, Flexible Substrates, Power Modules, Applied Reliability: Wearables, Interconnects for Bio-Medical, Automotive, Bio-Sensor, Energy Advanced Package Reliability (Including TSV/2.5D/3D Packaging, WCSP, Harvesting, and Harsh Environments. Fan-Out, Embedded Technologies), Challenges in SiP Reliability, Interconnect Reliability (Including Flip-Chip, Wire-Bond), LED, RFID, High Voltage Packaging Materials & Processing: and IoT Reliability, System Level Reliability Testing/Modeling, Reliability Test Wafer Level Packaging, Panel Processing & Materials, Next Generation Packaging Methods and Life Models, Physics of Failure, Failure Analysis Techniques Substrates, Flexible and Wearable Electronics, Carbon Electronics, Battery Materials, and Materials Characterization, Drop and Dynamic Mechanical Reliability, 3D Materials and Processing, Emerging Electronic Materials, Novel Conductive and Probabilistic Design for Reliability (PDfR), Automotive Reliability Requirements. Non-Conductive Adhesives, Solder Alloys, Photoresist, Dielectrics and Under-Fill, Molding Compounds, Thermal Interface Materials, Optoelectronic Materials. Assembly and Manufacturing Technology: Embedded/Hybrid Package Manufacturing Process, Wearable/IoT Package Thermal/Mechanical Simulation & Characterization: Assembly, Healthcare/Fitness Component Assembly, Warpage Control/ Thermal, Mechanical Simulation and Characterization Including: Component, Management in Board Level Assembly, Thin Die/Thin Mold/Thin Package Board and System Level Modeling for Microelectronics, e.g., 3D Interconnects (TSV, Stacked Die, etc.), 2.5D Packaging (Si, Glass, Flexible Interposer, etc.), Handling and Assembly, Large/Ultra Large Package (SiP, SIM, MCP) Integration Wafer-Level-Package (WLP), Ball-Grid-Array (BGA), Embedded Packages with and Processing, Panel Level Manufacturing for WLP, Dicing and Singulation. Active and Passive Components, System-in-Package (SiP), Power Electronic Emerging Technologies: Modules, LED Packaging, and MEMS; Fab/Thin Wafer Handling, Wire Bonding and Wearable and Medical Electronics, Flexible, Bendable, Stretchable, Disposable, or Assembly Manufacture Process; Reliability Modeling Related Fracture Mechanics, Dissolvable Packaging, Bio-Sensor Packaging, Implantable Device Packaging, New Fatigue, Electromigration, Warpage, Delamination/ Moisture, Drop Test, Material Materials and Methods for Packaging Microfluidics, MEMS and NEMS, Nano- Constitutive Relations and Characterization; Novel Modeling Including Multi- Battery. 3D Printing, Self-Alignment and Assembly, New Additive Packaging Scale and Multi-Physics Techniques and Solutions; Measurement Methodologies, Process Technologies and Materials. Novel Substrates, Materials and Approaches Characterization and Correlations. to Interconnects and Packaging, Packaging for Wireless, Photovoltaic, Optoelectronics: Redundancy, Repair, Security, Anti-Counterfeiting, Components for Internet Integrated Photonics Modules, Fiber Optical Interconnects, Advanced Optical of Things (IoT) and Smart Electronics, Heterogeneous Integration. Compact & Connectors, Optical Waveguide Circuits, Optical Printed Circuit Board, Mid-Board/ Autonomous Sensor Packaging, Wafer Level Integrated Silicon Photonics. On-Board Optical Modules, Silicon and III-V Photonics Packaging, Optical Chip-Scale High-Speed, Wireless & Components: and Heterogeneous Integration, Micro-Optical System Integration and Photonic Modules & Sub-Systems; High-Speed, RF to THz Devices & Passive System-in-Package, 3D Photonics Integration, Optoelectronic Assembly and Components, Mixed-Signal; Electrical Modeling and Design; Advanced Reliability, Materials and Manufacturing Technology, High-Efficiency LEDs and High Components: Materials, Structures, Fabrication and Characterization; Power and Power Lasers, Integrated Optical Sensors. Signal Integrity; High-Speed Data Transfer/Communications; Power Modules, Interactive Presentations: Power Management; Integrated Voltage Regulators (IVR); LTE, WLAN, 5G, Abstracts may be submitted related to any of the nine major program committee mm Wave and THz T/R Modules; Radars; Imagers; Wearable and Sensor topics listed above. Interactive presentations of technical papers are highly Technologies for Internet of Things (IoT); Flexible Electronics; 3D Printed RF encouraged at ECTC. They allow for significant interaction between the presenter Components and Modules; Automotive Sensors; RF-MEMS, RF-Opto, RFID and attendees, which is especially suited for material that benefits from more and Tagging; M2M Platforms; Proximity Sensors; Ambient Intelligence; Wireless explanation than is practical in oral presentations. Interactive presentation session Power; Wireless Sensor and Computing Nodes; Wearable and Biomedical papers are published and archived in equal merit with the other ECTC conference Electronics. papers.

You are invited to submit an abstract of no more than 750 words that describes the Professional Development Courses scope, content, and key points of your proposed paper via the website at www. In addition to abstracts for papers, proposals are solicited from individuals interested ectc.net. in teaching educational professional development courses (4 hours) on topics described in the Call for Papers. Using the format “Course Objectives/Course If you have any questions, contact: Outline/Who Should Attend,” 200-word proposals must be submitted via the Dr. Christopher Bower, 68th ECTC Program Chair website at www.ectc.net by October 9, 2017. X-Celeprint Inc. 3021 Cornwallis Road, Research Triangle Park, NC 27709, USA If you have any questions, contact: Phone: +1-919-522-3230 Kitty Pearsall E-mail: [email protected] 68th ECTC Professional Development Courses Chair Boss Precision, Inc. Abstracts must be received by October 9, 2017. All abstracts must be submitted 1806 W. Howard Lane, Austin, TX 78728, USA electronically at www.ectc.net. You must include the mailing address, business Phone: +1-512-845-3287 telephone number, and email address of presenting author(s) and affiliations of all E-mail: [email protected] authors with your submission.

43 CONFERENCE SPONSORS Gold Gala Sponsors

www.amkor.com www.cadence.com www.decatechnologies.com

www.dowelectronicmaterials.com www.lintec-usa.com/ www.nanium.com

www.pactech.com www.spts.com www.unity-sc.com/en/ Silver Gala Sponsors

www.appliedmaterials.com www.ibm.com/assembly www.micron.com

www.spil.com.tw www.suss.com www.veeco.com/technologiesandproducts/ precisionsurfaceprocessingsystems

www.zeiss.com/microscopy/int/solutions/ manufacturing-assembly.html

Special & Program Sponsors

www.aseglobal.com www.brewerscience.com www.lamresearch.com www.yieldengineering.com

44 CONFERENCE SPONSORS Wednesday Luncheon Sponsor Friday Luncheon Sponsor Badge Lanyard Sponsor

www.aseglobal.com www.statschippac.com www.hdmicrosystems.com Tote Bags Sponsor Student Reception Intel Student Paper Sponsor

www.emd-performance-materials.com www.ti.com www.intel.com Internet Sponsor Thumb Drive Sponsor

www.camtek.com www.spil.com.tw Refreshment Break Sponsors

www.agcem.com www.atotech.com www.fujifilmusa.com www.inemi.org

www.jsrmicro.com www.microsoft.com www.namics.co.jp/e/

www.qualcomm.com www.rudolphtech.com www.tok.co.jp/eng

Media Sponsors Official Media Sponsor

www.chipscalereview.com Additional Media Sponsors

www.i-micronews.com www.3dincites.infoneedle.com www.circuitassembly.com www.electronics-cooling.com

www.electronics www.magneticsmagazine.com www.memsjournal.com protectionmagazine.com

www.meptec.com www.semiconductor www.electroiq.com packagingnews.com 45 WALT DISNEY WORLD DOLPHIN RESORT, LAKE BUENA VISTA, FLORIDA, USA

68TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE

Sheraton San Diego Hotel & Marina San Diego, California, USA May 29 - June 1, 2018 ECTC will be 68 years old next year and we will be celebrating in San Diego, CA! The Sheraton San Diego Hotel & Marina is a tried and true venue for ECTC as ECTC has been using this property for quite some time! It touts panoramic views of the bay and the city skyline, yet is just 10 minutes from renowned attractions including the Gaslamp Quarter, Old Town, and Balboa Park. Dubbed by many as “the only area in the US with perfect weather,” San Diego is the oldest port on the West Coast and the sixth-largest city in the nation. Long known as a naval base, the military, along with tourism, still dominates the economy. In addition to rolling mountains, beautiful deserts, and seventy miles of coastline featuring some of the world’s best beaches, San Diego offers a wealth of attractions. Art lovers can choose from many fine museums or catch a Shakespearean play at the Old Globe Theater. With more championship golf courses, over 85, than any other US city, you won’t have a problem teeing off. The city also hosts the Major League Baseball’s Padres. And one last thing, don’t forget to take time to visit the world-renowned San Diego Zoo!

46 Conference At A Glance

MONDAY 3:00 p.m. – 3:20 p.m. 2:00 p.m. – 4:00 p.m. 2:00 p.m. – 4:00 p.m. May 29, 2017 Afternoon PDC Break Session 38: Interactive Session 40: Interactive 3:00 p.m. – 5:00 p.m. Southern Hemisphere Foyer and Presentations 2 Presentations 4 Northern Hemisphere E Foyer Northern Hemisphere Foyer Registration Northern Hemisphere Foyer Australia Foyer 5:00 p.m. – 6:00 p.m. 2:45 p.m. – 3:30 p.m. 2:45 p.m. – 3:30 p.m. TUESDAY ECTC Student Reception Refreshment Break May 30, 2017 Cabana Deck Northern Hemisphere A-C Refreshment Break 6:45 a.m. – 5:00 p.m. Backup: Asia 1 Northern Hemisphere A-C Registration 5:30 p.m. – 6:30 p.m. Australia Foyer 6:00 p.m. – 7:00 p.m. Technology Corner Reception 6:30 p.m. – 7:30 p.m. General Chair’s Speakers Northern Hemisphere A-C 67th ECTC Gala Reception Reception 6:45 a.m. – 8:15 a.m. Lake Terrace on Swan Property Crescent Terrace on Swan 6:30 p.m. – 7:30 p.m. Morning PDC Registration Only Property CPMT Women’s Panel & Backup: Northern Hemisphere D-E Backup: Northern Hemisphere D-E Reception 7:00 a.m. – 7:45 a.m. By invitation only Southern Hemisphere IV 8:00 p.m. – 9:30 p.m. PDC Instructors and Proctors Briefing & Breakfast CPMT Seminar 7:30 p.m. – 9:00 p.m. 7:30 p.m. – 9:00 p.m. Asia 1 Southern Hemisphere II & III ECTC Panel Session ECTC Plenary Session Southern Hemisphere II & III Southern Hemisphere II & III 7:00 a.m. – 5:00 p.m. FRIDAY Speaker Preparation WEDNESDAY THURSDAY June 2, 2017 Europe 2 May 31, 2017 June 1, 2017 7:00 a.m. – 5:00 p.m. 6:45 a.m. – 4:00 p.m. 7:00 a.m. – 5:00 p.m. Speaker Preparation 9:30 a.m. – 5:30 p.m. Conference Registration Speaker Preparation Europe 2 iNEMI Meeting Australia Foyer Europe 2 Oceanic 1 7:00 a.m. – 7:45 a.m. By invitation only 7:00 a.m. – 7:45 a.m. 7:00 a.m. – 7:45 a.m. Today’s Speakers Breakfast Today’s Speakers Breakfast Today’s Speakers Breakfast 8:00 a.m. – Noon Northern Hemisphere E 3-4 Northern Hemisphere E 3 & 4 Northern Hemisphere E 3-4 Morning PDCs See page 8 for locations 7:00 a.m. – 5:00 p.m. 7:30 a.m. – 4:00 p.m. 7:30 a.m. – Noon Speaker Preparation Conference Registration Conference Registration 8:00 a.m. – 5:00 p.m. Europe 2 Australia Foyer Australia Foyer CPMT Heterogeneous Integration Technology Roadmap Workshop 8:00 a.m. – 11:40 a.m. 8:00 a.m. – 11:40 a.m. 8:00 a.m. – 11:40 a.m. Europe 4 Sessions 1, 2, 3, 4, 5, 6 Sessions 13, 14, 15, 16, 17, 18 See pages 10–11 for Locations See pages 14–15 for Locations Sessions 25, 26, 27, 28, 29, 30 10:00 a.m. – 11:30 a.m. See pages 18–19 for Locations ECTC Special Session 9:00 a.m. – 11:00 a.m. 9:00 a.m. – 11:00 a.m. Southern Hemisphere I Session 37: Interactive Session 39: Interactive 8:30 a.m. – 10:30 a.m. Presentations 1 Presentations 3 Student Interactive Presentation Northern Hemisphere Foyer Northern Hemisphere Foyer 10:00 a.m. – 10:20 a.m. Session Morning PDC Break 9:00 a.m. – Noon 9:00 a.m. – Noon Northern Hemisphere Foyer Southern Hemisphere Foyer and Technology Corner Exhibits Technology Corner Exhibits Northern Hemisphere E Foyer Northern Hemisphere A-C Northern Hemisphere A-C 9:15 a.m. – 10:00 a.m. Refreshment Break Noon 9:15 a.m. – 10:00 a.m. 9:15 a.m. – 10:00 a.m. PDC Luncheon Southern Hemisphere Foyer Refreshment Break Refreshment Break Northern Hemisphere D-E Northern Hemisphere A-C Northern Hemisphere A-C Noon 1:00 p.m. – 5:00 p.m. Noon Noon ECTC Program Chair Luncheon Technology Corner Setup ECTC Luncheon CPMT Luncheon Northern Hemisphere D-E Northern Hemisphere A-C Northern Hemisphere D-E Northern Hemisphere D-E 1:30 p.m. – 5:10 p.m. 1:15 p.m. – 5:15 p.m. 1:30 p.m. – 6:30 p.m. 1:30 p.m. – 4:00 p.m. Sessions 31, 32, 33, 34, 35, 36 Afternoon PDCs Technology Corner Exhibits Technology Corner Exhibits See pages 20–21 for Locations See page 8 for locations Northern Hemisphere A-C Northern Hemisphere A-C

2:00 p.m. – 3:30 p.m. 1:30 p.m. – 5:10 p.m. 1:30 p.m. – 5:10 p.m. 2:45 p.m. – 3:30 p.m. ECTC Special Session Sessions 7, 8, 9, 10, 11, 12 Sessions 19, 20, 21, 22, 23, 24 Refreshment Break Southern Hemisphere I See pages 12–13 for Locations See pages 16–17 for Locations Southern Hemisphere Foyer 47 SPONSORED BY: