PCBNEW Wishlists, Blueprints, Design and Implementation Notes
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PCBNEW Wishlists, Blueprints, Design and Implementation Notes Brian Bidulock∗ c Copyright 2010, Optranex, Inc. September 6, 2010 Abstract Foreword This documents contains some of the design and implementation Overview notes that I have made along the way while making modifications This document provides the feature enhancements, blue prints on pcbnew. and wish lists for the pcbnew component of KiCad, the free1 Preface EDA tool. These enhancements, blueprints and wish lists de- rive from my desire to use KiCad for a series of high-speed optical License network add-in cards (frequencies ranging from 2.5 Gbps to 40 Copyright c 2010 Optranex, Inc. Gbps). These are medium density PCI Express add-in cards. All Rights Reserved. They contain upwards of 20,000 board features. My experiences with manually routing these cards, and attempting a plot-and-go Permission is granted to make and distribute verbatim copies of set of fabrication outputs, is what has driven this development. this document provided the copyright notice and this permission Purpose notice are preserved on all copies. My purpose is making these modifications has been twofold: Permission to use, copy, modify, and distribute this document • To make KiCad usable for designs up to 40 Gbps. That is, for any purpose and without fee is hereby granted, provided that to make KiCad superior for designs up to 40 Gbps. the above copyright notice appears in all copies and that both that • To make KiCad usable for modern techniques (such as back- copyright notice and this permission notice appear in supporting drilling). That is, to bring KiCad up to date. documentation, and that the name Optranex Incorporated not be used in advertising or publicity pertaining to distribution of • To make KiCad generate plot-and-go manufacturing outputs. the software without specific, written prior permission. Optranex That is, to make KiCad outputs directly usable for manufac- Incorporated makes no representations about the suitability turing processes. of this documentation for any purpose. It is provided \as is" • To make KiCad generate a wider range of manufacturing without express or implied warranty. and intermediate outputs (Gerber, DPF, Excellon-2, IDF, GenCAD, GenCAM, GenX, 258X). Optranex Incorporated disclaims all warranties with re- Most of these items affect only pcbnew (and to some degree the gard to this dcoumentation, including all implied war- module editor and gerbview) in the KiCad suite. ranties of merchantability and fitness. In no event shall Optranex Incorporated be liable for any special, indirect Scope or consequential damages or any damages whatsoever re- This document is not meant to be a textbook on manufacturing sulting from loss of use, data or profits, whether in an printed wiring assemblies. Where specific fabrication or manu- action of contract, negligence or other tortious action, facturing processes are described, read these passages with the arising out of or in connection with the use or perfor- understanding that, although I am an Electrical Engineer, that mance of this documentation. I am not an expert on fabrication or manufacturing processes. Notice The fabrication and manufacturing requirements listed are taken from fabricator and assembler customer DFM sheets, industry This document is based on KiCad, the open source CAD system. standards (where publicly available), research papers, and uni- Optranex Incorporated is making this documentation available versity level courses on PCB design and manufacturing. From as a reference point for the KiCad development project. While what I can see on google books, there are many good books writ- Optranex believes that these specifications are well-defined in this ten on the topic, by subject matter experts, and I refer you to release of the document, minor changes may be made prior to their guidance. The descriptions in this document were for the products conforming to the specifications being made available. purposes of documenting the reasoning behind a specific pcbnew feature, attribute, or parameter, rather than illuminating the pro- cess. For further information and detail, see References on page 155. Organization ∗[email protected] 1. As in speech. 1 2 B. Bidulock Contents 3.3.2 Blind Vias . 28 3.3.3 Buried Vias . 28 Abstract 1 3.3.4 Microvias . 29 3.3.5 Back-Drilled Vias . 30 Preface 1 3.3.6 Depth-Control-Drilled (DCD) Vias . 31 License . 1 3.3.7 Sub-Composite Vias (SCV) . 32 Notice . 1 3.3.8 Via-Through-Pad (VTP) . 33 3.3.9 Thermal Vias. 33 Foreword 1 3.3.10 Ground Plane Stitching. 33 Overview . 1 3.3.11 Isolation Vias. 33 Purpose . 1 3.4 Tracks . 34 Scope . 1 3.4.1 Etch Compensation . 34 Organization . 1 3.4.2 Teardrops . 35 List of Figures 5 3.4.3 Sub-Composite Vias . 37 3.4.4 Isolation Traces . 38 List of Tables 6 3.4.5 Arced Tracks . 38 3.4.6 Push/Pull Tracks . 39 1 Introduction 7 3.4.7 Neck-Downs . 39 1.1 Fundamentals . 7 3.5 Zones . 40 1.1.1 Manufacturing Principles . 7 3.5.1 Polygon Clipping . 40 1.1.2 Fabrication Principles . 7 3.5.2 Arced Outlines . 40 1.1.3 Assembly Principles . 7 3.5.3 Impedance Cutouts . 40 1.1.4 Test Principles . 8 3.5.4 Via Stitching . 41 3.5.5 Copper Islands . 41 2 Internal Changes 8 3.5.6 Isolation Zones . 41 2.1 Performance . 10 3.5.7 Module Zones . 41 2.1.1 Proximity Maps . 10 3.5.8 Zone Plotting . 41 2.1.2 Connect Maps . 10 3.6 Modules . 42 2.1.3 Dirty Classes . 11 3.6.1 Solder Dams . 42 DIRTY Class . 11 3.6.2 IPC Footprint Identification . 43 2.1.4 Connection Graphs . 11 3.6.3 IPC Component Types . 43 2.2 Fabrication Output . 12 3.6.4 Courtyards . 43 2.3 High-Speed Design . 12 3.6.5 Rework . 44 2.4 DRC . 12 3.6.6 Wave Soldering . 45 2.4.1 DRC Deficiencies . 12 3.6.7 Outlines . 47 2.4.2 DRC Enhancements . 13 3.6.8 Keep-Outs . 48 2.5 Ratsnests . 13 3.6.9 Rooms . 48 2.6 Layers . 13 3.6.10 Thermal Calculations . 48 2.6.1 Layer Identifiers . 13 3.6.11 Thermal Vias . 49 2.6.2 Layer Classes . 13 3.6.12 Press-Fit Fixtures . 49 2.6.3 Layer Handling . 15 3.6.13 Embedded Resistors . 49 2.7 Internal Units . 15 3.7 Nets . 50 2.7.1 Rectilinear Units . 15 3.8 Layer . 50 2.7.2 Angular Units . 15 3.8.1 Thieving . 50 2.8 Modules . 16 3.8.2 Venting . 52 3.8.3 Crosshatch . 53 3 New Features 17 3.9 Stack-Up . 54 3.1 General . 17 3.9.1 Dielectric . 54 3.1.1 Defaults . 17 3.9.2 Press Factor . 54 3.2 Pads . 17 3.10 Panels . 55 3.2.1 Pad Attributes . 18 3.10.1 Fiducial Marks . 55 3.2.2 BGA Pads . 18 3.10.2 Coupons . 55 3.2.3 Pad Removal . 18 3.10.3 Boards . 57 3.2.4 Complex Shapes . 20 3.10.4 Assembly Panels . 57 3.2.5 More Basic Pad Shapes . 20 3.10.5 Production Panels . 57 3.2.6 Plotting of Thermals . 21 3.2.7 Plotting of Moir´es . 21 4 Design for Excellence 58 3.2.8 Plotting of Drill Marks . 21 3.2.9 SMD vs. NSMD . 22 5 Layers 59 3.2.10 Non-Plate-Through-Holes (NPTH) . 25 5.1 Dielectric Layers . 59 3.2.11 Tooling Holes . 25 5.1.1 Process . 59 3.2.12 Hole Tolerance . 25 5.1.2 Materials . 59 3.2.13 Fiducial Marks . 25 5.1.3 DFX Rules . 59 3.2.14 Contacts . 26 5.1.4 Design . 59 3.3 Vias . 26 5.1.5 Imaging . 60 3.3.1 Through Vias . 27 5.1.6 Post-Processing . 60 B. Bidulock 3 5.2 Resistance Layers . 61 5.11.1 Process . 82 5.2.1 Process . 61 5.11.2 Materials . 82 5.2.2 Materials . 61 5.11.3 DFX Rules . 82 5.2.3 DFX Rules . 61 5.11.4 Design . 82 5.2.4 Design . 61 5.11.5 Imaging . 82 5.2.5 Imaging . 61 5.11.6 Post-Processing . 82 5.2.6 Post-Processing . 61 5.12 Legend Layers . 83 5.3 Copper Layers . 62 5.12.1 Process . 84 5.3.1 Process . 62 5.12.2 Materials . 84 5.3.2 Materials . 63 5.12.3 DFX Rules . 84 5.3.3 DFX Rules . 63 5.12.4 Design . 86 5.3.4 Design . ..