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A Transfer Function Model for Ternary Switching Logic Circuits

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A Transfer Function Model for Ternary Switching Logic Circuits A Transfer Function Model for Ternary Switching Logic Circuits Mitchell A. Thornton Southern Methodist University Dallas, Texas USA 75275–0122 Email: [email protected] Abstract an interconnection of symbols or gates whose function- ality is modeled by the operators within the algebraic Ternary switching functions are formulated as trans- structure. A common set of ternary logic network formations over vector spaces resulting in a character- elements are the MIN, MAX, and Literal Selection ization in the form of a transfer function. Ternary logic gates whose corresponding functionalities provide for constants are modeled as vectors, thus the transfer the specification of a functionally complete algebra functions are of the form of matrices that map vectors with constants. For conciseness we refer to the Literal representing logic network input values to correspond- Selection gate as a Ji gate where i denotes the polarity ing output vectors. Techniques for determination of the of the selected literal, i 2 f0; 1; 2g as defined in [2]. transfer matrix from a logic switching model or directly Here we use three-dimensional vectors to represent from a netlist are provided. The use of transfer matrices ternary logic values instead of the integers f0; 1; 2g for logic network simulation are then developed that and we model a ternary logic function or a ternary allow for multiple output responses to be obtained logic network by a characterizing transfer matrix. The through a single vector-matrix product calculation. transfer matrix transforms the logic network input vectors to corresponding output vectors. This linear algebraic model of a ternary logic network or function 1. Introduction is an alternative to the more commonly employed switching model. While we do not propose that the Design and analysis tasks require some means to rich set of results based on switching functions be specify logic network functionality that is compact and abandoned in favor of the linear algebraic model, useful for purposes such as simulation, implication, we do propose that this alternative model may be synthesis, and others. We introduce a linear algebraic advantageous for certain ternary logic synthesis and model analogous to the transfer function model used analysis tasks such as those described in [3], [4]. As in other areas of engineering. The transfer function an example, we examine the use of the linear algebra captures the behavior of the network and can also be approach when used for ternary logic simulation. We used to determine the network output response for a utilize a netlist as input where the term “netlist” is used given set of input stimuli [1]. The transfer function in the commonly accepted definition of representing model is formulated as a mapping of elements over a structural interconnections of logic gates. Modern vector spaces representing the function domain and EDA tools parse netlists into intermediate graphical range sets. Transfer functions are in the form of a representations representing a structural logic circuit matrix or linear transformation, thus, we use the terms and the term netlist does not refer to any specific “transfer function” and “transfer matrix” interchange- format. ably. The remainder of the paper is organized as follows. Ternary switching functions are traditionally mod- In Section 2, background and notation is introduced eled with an algebraic structure consisting of a discrete to support the derivations of the transfer matrices for set of logic constants f0; 1; 2g and an appropriate set of a logic network. Section 3 contains the definitions operators. Logic networks represent implementations and derivations of matrices that characterize a network using electronic or some other technology with a and also includes descriptions of how the matrices corresponding input/output characteristic modeled by can be obtained from a high-level switching function ternary switching functions. A ternary logic network is specification or through direct traversal of a logic Table 1. Ternary Logic Constants Integral Bra-Vector Row-Vector 0 h0j 1 0 0 1 h1j 0 1 0 2 h2j 0 0 1 network representation such as a netlist. Section 3 also contains examples that demonstrate of how the Figure 1. Hasse Diagrams of Ternary Vector Con- matrices are used for computation of system responses. stants Concluding remarks are provided in Section 4. h0j h1j 2. Background and Notation In addition to the vector constants , , and h2j, five other constants are defined and used, denoted as htj, ht01j, ht02j, ht12j, and h?j. htj represents the 2.1. Dirac Notation simultaneous presence of h0j, h1j, and h2j and is given by htj = h0j + h1j + h2j where the + operator denotes “Bra-ket” notation was originally devised as a con- vector space addition. Likewise, the constants ht j, cise representation of vectors and associated operations 12 ht j, and ht j represent the simultaneous presence of to aid in quantum mechanical system calculations [5]. 02 01 two logic values ht j = h0j+h1j, ht j = h0j+h2j, and Due to the conciseness of this notation, we employ 01 02 ht j = h1j+h2j. In contrast, h j represents the absence its use in this paper. Column vectors are referred to 12 ? of all logic values and is given as h j = 0 0 0 . as “kets” and the notation for column vector x is jxi. ? h j should not be confused with the logic-0 value, Likewise, a row vector y is referred to as “bra-y” and ? h0j = 1 0 0 . The collection of vector constants is written as hyj. The inner (or “dot”) product of two can be expressed as a Hasse diagram as shown in vectors x and y is written as hxjyi and the outer (or Figure 1 [2]. Two versions of the Hasse diagram are de- “Kronecker”) product as jxihyj. picted using bra- and the row-vector notation. The five additional constants can arise during calculations using 2.2. Ternary Logic Constants transfer function representations of logic networks. Ternary logic switching models commonly use an integral encoding f0; 1; 2g to represent logic values. 2.3. Network Elements In the model presented here, we represent ternary logic values as three-dimensional vectors, where each Any of a variety of two- and one-place operators logic value j is represented by a row vector whose can be defined and represented by logic gates within jth component is unity-valued and all other remaining a ternary logic network. For the algebraic construction components are zero-valued. Table 1 shows the corre- to enable representation of all possible functions, some spondence of the integral and vector logic values. The primitive set of operators is required such that all other choice of using row vectors as models for ternary logic possible operators can be expressed as a function of the values is arbitrary and column-vectors could have been primitives and constants [2]. In this work, we utilize chosen. As will become apparent in a later section, the the ternary MIN, MAX, and Ji operators as logic choice of row-vectors for ternary constants results in primitives. the logic network transfer function being expressed as a matrix that closely resembles the switching model 3. Transfer Functions truth table. We use the notation H to represent a Hilbert vector The transfer function is an expression that yields the space whose elements are three-dimensional row vec- output response of the corresponding network when tors. The 3n-dimensional Hilbert space is denoted as multiplied by an input stimulus. A particular input Hn and may be constructed through use of the outer stimulus is represented by a row vector of dimension product operation, denoted by the ⊗ operator, as shown 3n where n is the number of parallel network inputs. in Equation 1 where n is any natural number, n 2 N. Individual network input values are used to compute n the overall stimulus vector through the relationship in n O Equation 1. Lemma 3.1 describes a characteristic that H = H ⊗ H ⊗ ::: ⊗ H = H (1) i=1 is useful in the derivation of the transfer function. Lemma 3.1: Linear Independence: Consider a one or more logic network input vectors through a ternary logic network with n inputs. Two distinct single vector-matrix multiplication operation. Modern n network input assignments (hxij; hxjj) 2 H are Electronic Design Automation (EDA) tools generally linearly independent vectors when i 6= j. implement this operation through the use of discrete Proof: hxij and hxjj are represented as event simulation algorithms in conjunction with a hdndn−1 : : : d0j, where each di 2 f0; 1g represents description of the logic network. For the transfer a particular network input logic value. Using the matrix approach to be a practical alternative to EDA relation in Equation 1, the input vectors are expanded approaches, the transfer matrix T must be obtained in as hdnj ⊗ hdn−1j ⊗ ::: ⊗ hd0j. Expressed as a row an efficient manner. vector, hxj = 0 0 ::: 1 ::: 0 where The transfer matrix T can be derived in several the single unity-valued vector component exists in ways. We focus on two approaches here; derivation a different location for hxij and hxjj since i 6= j. of T when the switching function behavior is given, Therefore hxijxji = 0 and the norm of xi and xj and alternatively, when a low-level characterization of is L2(xi) = L2(xj) = 1, satisfying the definition the network is provided in the form of a logic network of linear independence. When i = j, hxijxji = 1 or netlist. and this only occurs when hxij = hxjj. Expressed mathematically, ( 3.1.1. Transfer Functions from Switching Models. 0; i 6= j For switching function specifications, common repre- xi · xj = hxijxji = (2) 1; i = j sentations include cube lists [6] or graphical represen- tations such as the Binary Decision Diagrams (BDD) [7] or their generalization as Multiple-valued Decision Lemma 3.2: Input-Output Response: The output re- Diagrams (MDD) [8].
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