A Transfer Function Model for Ternary Switching Logic Circuits

Mitchell A. Thornton Southern Methodist University Dallas, Texas USA 75275–0122 Email: [email protected]

Abstract an interconnection of symbols or gates whose function- ality is modeled by the operators within the algebraic Ternary switching functions are formulated as trans- structure. A common set of ternary logic network formations over vector spaces resulting in a character- elements are the MIN, MAX, and Literal Selection ization in the form of a transfer function. Ternary logic gates whose corresponding functionalities provide for constants are modeled as vectors, thus the transfer the specification of a functionally complete algebra functions are of the form of matrices that map vectors with constants. For conciseness we refer to the Literal representing logic network input values to correspond- Selection gate as a Ji gate where i denotes the polarity ing output vectors. Techniques for determination of the of the selected literal, i ∈ {0, 1, 2} as defined in [2]. transfer matrix from a logic switching model or directly Here we use three-dimensional vectors to represent from a netlist are provided. The use of transfer matrices ternary logic values instead of the integers {0, 1, 2} for logic network simulation are then developed that and we model a ternary logic function or a ternary allow for multiple output responses to be obtained logic network by a characterizing transfer matrix. The through a single vector-matrix product calculation. transfer matrix transforms the logic network input vectors to corresponding output vectors. This linear algebraic model of a ternary logic network or function 1. Introduction is an alternative to the more commonly employed switching model. While we do not propose that the Design and analysis tasks require some means to rich set of results based on switching functions be specify logic network functionality that is compact and abandoned in favor of the linear algebraic model, useful for purposes such as simulation, implication, we do propose that this alternative model may be synthesis, and others. We introduce a linear algebraic advantageous for certain ternary logic synthesis and model analogous to the transfer function model used analysis tasks such as those described in [3], [4]. As in other areas of engineering. The transfer function an example, we examine the use of the linear algebra captures the behavior of the network and can also be approach when used for ternary logic simulation. We used to determine the network output response for a utilize a netlist as input where the term “netlist” is used given set of input stimuli [1]. The transfer function in the commonly accepted definition of representing model is formulated as a mapping of elements over a structural interconnections of logic gates. Modern vector spaces representing the function domain and EDA tools parse netlists into intermediate graphical range sets. Transfer functions are in the form of a representations representing a structural logic circuit matrix or linear transformation, thus, we use the terms and the term netlist does not refer to any specific “transfer function” and “transfer matrix” interchange- format. ably. The remainder of the paper is organized as follows. Ternary switching functions are traditionally mod- In Section 2, background and notation is introduced eled with an algebraic structure consisting of a discrete to support the derivations of the transfer matrices for set of logic constants {0, 1, 2} and an appropriate set of a logic network. Section 3 contains the definitions operators. Logic networks represent implementations and derivations of matrices that characterize a network using electronic or some other technology with a and also includes descriptions of how the matrices corresponding input/output characteristic modeled by can be obtained from a high-level switching function ternary switching functions. A ternary logic network is specification or through direct traversal of a logic Table 1. Ternary Logic Constants

Integral Bra-Vector Row-Vector 0 h0|  1 0 0  1 h1|  0 1 0  2 h2|  0 0 1 

network representation such as a netlist. Section 3 also contains examples that demonstrate of how the Figure 1. Hasse Diagrams of Ternary Vector Con- matrices are used for computation of system responses. stants Concluding remarks are provided in Section 4. h0| h1| 2. Background and Notation In addition to the vector constants , , and h2|, five other constants are defined and used, denoted as ht|, ht01|, ht02|, ht12|, and h∅|. ht| represents the 2.1. Dirac Notation simultaneous presence of h0|, h1|, and h2| and is given by ht| = h0| + h1| + h2| where the + operator denotes “Bra-ket” notation was originally devised as a con- vector space addition. Likewise, the constants ht |, cise representation of vectors and associated operations 12 ht |, and ht | represent the simultaneous presence of to aid in quantum mechanical system calculations [5]. 02 01 two logic values ht | = h0|+h1|, ht | = h0|+h2|, and Due to the conciseness of this notation, we employ 01 02 ht | = h1|+h2|. In contrast, h | represents the absence its use in this paper. Column vectors are referred to 12 ∅ of all logic values and is given as h | =  0 0 0 . as “kets” and the notation for column vector x is |xi. ∅ h | should not be confused with the logic-0 value, Likewise, a row vector y is referred to as “bra-y” and ∅ h0| =  1 0 0 . The collection of vector constants is written as hy|. The inner (or “dot”) product of two can be expressed as a Hasse diagram as shown in vectors x and y is written as hx|yi and the outer (or Figure 1 [2]. Two versions of the Hasse diagram are de- “Kronecker”) product as |xihy|. picted using bra- and the row-vector notation. The five additional constants can arise during calculations using 2.2. Ternary Logic Constants transfer function representations of logic networks. Ternary logic switching models commonly use an integral encoding {0, 1, 2} to represent logic values. 2.3. Network Elements In the model presented here, we represent ternary logic values as three-dimensional vectors, where each Any of a variety of two- and one-place operators logic value j is represented by a row vector whose can be defined and represented by logic gates within jth component is unity-valued and all other remaining a ternary logic network. For the algebraic construction components are zero-valued. Table 1 shows the corre- to enable representation of all possible functions, some spondence of the integral and vector logic values. The primitive set of operators is required such that all other choice of using row vectors as models for ternary logic possible operators can be expressed as a function of the values is arbitrary and column-vectors could have been primitives and constants [2]. In this work, we utilize chosen. As will become apparent in a later section, the the ternary MIN, MAX, and Ji operators as logic choice of row-vectors for ternary constants results in primitives. the logic network transfer function being expressed as a matrix that closely resembles the switching model 3. Transfer Functions truth table. We use the notation H to represent a Hilbert vector The transfer function is an expression that yields the space whose elements are three-dimensional row vec- output response of the corresponding network when tors. The 3n-dimensional Hilbert space is denoted as multiplied by an input stimulus. A particular input Hn and may be constructed through use of the outer stimulus is represented by a row vector of dimension product operation, denoted by the ⊗ operator, as shown 3n where n is the number of parallel network inputs. in Equation 1 where n is any natural number, n ∈ N. Individual network input values are used to compute n the overall stimulus vector through the relationship in n O Equation 1. Lemma 3.1 describes a characteristic that H = H ⊗ H ⊗ ... ⊗ H = H (1) i=1 is useful in the derivation of the transfer function. Lemma 3.1: Linear Independence: Consider a one or more logic network input vectors through a ternary logic network with n inputs. Two distinct single vector-matrix multiplication operation. Modern n network input assignments (hxi|, hxj|) ∈ H are Electronic Design Automation (EDA) tools generally linearly independent vectors when i 6= j. implement this operation through the use of discrete Proof: hxi| and hxj| are represented as event simulation algorithms in conjunction with a hdndn−1 . . . d0|, where each di ∈ {0, 1} represents description of the logic network. For the transfer a particular network input logic value. Using the matrix approach to be a practical alternative to EDA relation in Equation 1, the input vectors are expanded approaches, the transfer matrix T must be obtained in as hdn| ⊗ hdn−1| ⊗ ... ⊗ hd0|. Expressed as a row an efficient manner.   vector, hx| = 0 0 ... 1 ... 0 where The transfer matrix T can be derived in several the single unity-valued vector component exists in ways. We focus on two approaches here; derivation a different location for hxi| and hxj| since i 6= j. of T when the switching function behavior is given, Therefore hxi|xji = 0 and the norm of xi and xj and alternatively, when a low-level characterization of is L2(xi) = L2(xj) = 1, satisfying the definition the network is provided in the form of a logic network of linear independence. When i = j, hxi|xji = 1 or netlist. and this only occurs when hxi| = hxj|. Expressed mathematically, ( 3.1.1. Transfer Functions from Switching Models. 0, i 6= j For switching function specifications, common repre- xi · xj = hxi|xji = (2) 1, i = j sentations include cube lists [6] or graphical represen- tations such as the Binary Decision Diagrams (BDD) [7] or their generalization as Multiple-valued Decision Lemma 3.2: Input-Output Response: The output re- Diagrams (MDD) [8]. These various descriptions allow sponse of a logic network due to a particular input specific corresponding input and output responses to be assignment hxi| is represented by hfi|. The output directly obtained. response vector is obtained as the product of hx | with i A direct approach for the calculation of T is to |x ihf |. i i form the outer product terms expressed in Equation Proof: The lemma statement is expressed as (hx |)(|x ihf |) = hx |x ihf |. 3 and sum them together. Unfortunately, this approach i i i i i i requires the formulation of an exponential number (3n) From Lemma 3.1, hx |x i = 1, thus i i matrices and then finding their sum. A better approach (hx |)(|x ihf |) = (1)hf | = hf |. i i i i i is to use the existing switching function representation Theorem 3.3: Transfer Function: The transfer func- as an implicit representation of the transfer matrix tion representing the input-output relationship of a T. This approach is viable and allows for system logic network f is of the form of a matrix T and is response calculations to be accomplished through the given by Equation 3. use of algorithms that implement the vector-matrix 3n product operation using the structure of the implicitly X T = |xiihfi| (3) represented transfer matrix T. i=1 Observation 3.4: Transfer Function/Truth Table Proof: By definition, the transfer function yields Isomorphism: A truth table specification of a ternary the logic network output response vector hfi| when switching function is isomorphic to the corresponding multiplied with the corresponding logic network input transfer function.  th stimulus hxi|. Multiplying T with the j logic net- To further illustrate Observation 3.4, consider a work stimulus vector hxj| yields switching function representation comprised of a single 3n ! 3n P P MIN operation, f = x · y. Using the direct approach hxj|T = hxj| |xiihfi| = hxj|xiihfi| i=1 i=1 for evaluating the transfer function of a MIN function Using Equation 2, transfer matrix, denoted as A, results in the following hxj|T = hfj| calculation. A = |00ih0| + |01ih0| + |02ih0| + |10ih0| 3.1. Transfer Matrix Derivation + |11ih1| + |12ih1| + |20ih0| + |21ih1| + |22ih2| The transfer matrix as derived in the previous section Expanding the outer product terms into 3 × 9 matri- allows for a means to derive the system response for ces and summing together yields  1 0 0   1 0 0     1 0 0     1 0 0    A =  0 1 0  .    0 1 0     1 0 0     0 1 0  0 0 1 Examination of the structure of TMIN reveals that each row vector is simply the vector representation of the MIN truth table output column. Thus, a truth table representation can be used as an implicit representation of the transfer matrix and algorithms can be formulated that implement the vector-matrix product operation to compute the output response. Since the transfer matrix representation is isomorphic to the truth table, decision Figure 2. Ternary Network Element Transfer Ma- diagram (DD) structures are sufficient to represent trices the transfer matrix such as those described in [8]. Furthermore, the matrix operations can be efficiently implemented using DDs as described in [9]. Thus, traversals. In the first traversal, the netlist is partitioned the complexity of transfer matrix representation is into a series of cascaded stages. The second traversal identical to that of using DDs. requires computation of the transfer matrix for each stage and the final step derives the overall transfer 3.1.2. Transfer Functions from Netlists. Many mod- matrix as the direct matrix product of each cascade ern EDA analysis tasks require the derivation of a net- stage transfer matrix. The partitioning step determines work response using only a low-level description such cuts through the netlist such that all elements in each as a netlist. Methods requiring a switching behavioral partition operate in parallel. Each partition is then model can prove problematic since the conversion of treated as a separate netlist whose inputs and outputs a netlist representation to a switching model represen- are combined using the outer product operation in tation can incur unacceptable complexity. Even when accordance with Equation 1 where individual three- state-of-the-art representations such decision diagrams dimensional vectors are combined into a single 3n- are used, parsing the netlist into such a structure can dimension vector. Because the partitions are chosen as require excessive amounts of memory. A commonly serial cascade stages, the output of the prior cascade cited example is a BDD representation of a fixed-point serves as the input to the subsequent stage, and the multiplication circuit. It has been proven that BDD overall transfer matrix is simply the direct product of representations of multiplier circuits grow exponen- the partition matrices. tially with operand wordsize regardless of the variable This technique can be implemented through use of orderings. a library of transfer matrices for the atomic logic Another commonly encountered analysis task re- network elements such as the MIN, MAX, and Ji quires analysis of an internal partition or subcircuit gates. Additional atomic transfer matrices are needed within a netlist. Extraction of the switching model for in the library that correspond to the single line (pass- an internal subcircuit can also be difficult in some through), fanout, and fanin structures since they will cases. For these reasons, there is a need to devise appear as parallel elements in some of the network an efficient means of determining netlist responses partitions. Figure 2 contains the transfer matrices for to various stimuli and motivates us to determine a a library composed of these elements. The transfer means to efficiently extract the corresponding transfer matrix for the fanin gate FI has ∅ components for the function directly from a netlist representation while cases where the two inputs are different logic values. avoiding the intermediate step of first extracting a Example 3.5: Transfer Matrix from Netlist: Con- switching model, and then determining the transfer sider the logic network in Figure 3 with input stimulus matrix. of hx1| = h1| and hx2| = h2|. The uppermost diagram The transfer matrix can be determined directly from shows the partitioned cascaded stages denoted by φ1, a netlist representation of a logic network through two φ2, and φ3. Each partition is comprised of a set of network stimulus vector. Theorem 3.6: Network Response: The output re- sponse hfj| of a logic network characterized by transfer matrix T can be calculated by multiplying the input stimulus vector hxj| with T as expressed in Equation 4. hfj| = hxj|T (4) Proof: Multiplying Equation 3 with input stimulus hxj| 3n ! P hxj|T = hxj| |xiihfi| i=1 3n P = hxj|xii|fii Figure 3. Partitioned Ternary Logic Network i=1 From Lemma 3.1, the inner product hxj|xii = 0 for the 3n − 1 cases in Equation 4 where i 6= j. parallel network elements and can be characterized Furthermore, hxj|xii = 1 for the single case in by individual transfer matrices Tφ1 , Tφ2 , and Tφ3 . Equation 4 where i = j. When i = j, hfi| = hfj|, The logic network diagram in the center of Figure 3 hence hxj|T = hfj|. depicts a specific input stimulus written as individual Corollary 3.7: Multiple system Response: The sys- vectors. From Equation 1, the network input values tem response due to multiple logic network input vec- can be combined into a single vector as shown on tors can be calculated through a single multiplication the bottom-most diagram. The corresponding network operation by forming the input stimulus vector using output response is shown on the right side of the the logic value ht| and using the transfer matrix T. network diagrams, both as individual vectors and as Proof: Three different input stimuli can be ex- a combined vector formed as the outer product of the pressed in a single combined logic network input individual vectors. vector, hxcomb| by specifying one of the network inputs The output of φ1 is produced by a MIN gate, as ht| resulting in that particular input having logic values h0|, h1|, and h2| simultaneously. By definition therefore Tφ1 = A. Stage φ2 is comprised of a single fanout network element and has a transfer matrix of the logic value ht|, the combined input vector can be expanded as hx | = hx | + hx | + hx | where Tφ2 = FO. Stage φ3 is comprised of two network comb 0 1 2 elements; a J1 literal selection gate and a single each hxi| represents a logic input vector with one input pass through conductor. Just as the input vectors are assigned logic value i. Multiplying the input vector combined into a single vector using the outer product, hxcomb| with T results in the logic network response so is the overall transfer matrix T = J ⊗ I. hf0| + hf1| + hf2| where hfi| denotes the network  φ3  1  1 0 0 1 0 0 response for input stimulus hxi|. This result can be

Tφ3 = J1 ⊗ I =  0 0 1  ⊗  0 1 0  generalized by setting more than one input to value ht|. 1 0 0 0 0 1 Furthermore, it is desired to restrict one of the inputs  1 0 0 0 0 0 0 0 0  to simultaneously be a subset of logic values {0, 1, 2},  0 1 0 0 0 0 0 0 0  a new value akin to ht| can be defined and used.    0 0 1 0 0 0 0 0 0  Example 3.8: Calculating Single Network    0 0 0 0 0 0 1 0 0  Response: The logic network depicted in Figure   =  0 0 0 0 0 0 0 1 0  3 is partitioned into three stages and the overall    0 0 0 0 0 0 0 0 1  transfer matrix, T, is computed as T = Tφ3 Tφ2 Tφ1 .    1 0 0 0 0 0 0 0 0  T = Tφ3 Tφ2 Tφ1 = (A)(FO)(J1 ⊗ I)      0 1 0 0 0 0 0 0 0  1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0  1 0 0 0 0 0 0 0 0     1 0 0 0 0 0 0 0 0      1 0 0 0 0 0 0 0 0    3.2. Switching Domain Response =  0 0 0 0 0 0 0 1 0     0 0 0 0 0 0 0 1 0    As implied in Theorem 3.3, the transfer matrix can  1 0 0 0 0 0 0 0 0    be used to compute the output response of the char-  0 0 0 0 0 0 0 1 0  acterized logic network through multiplication with a 0 0 1 0 0 0 0 0 0 To determine the logic network response hf12| for three times. Instead of computing the total system an input stimulus of hx1x2| = h12|, the network inputs response, this technique can be used to find partial are expressed as a single vector, h12| = h1| ⊗ h2| and system responses through the use of input stimuli is multiplied with the transfer matrix T in accordance vectors with a subset of inputs assigned the values ht|, with Theorem 3.6. ht01|, ht02|, or ht12|. hf12| = h12|T T  0   1 0 0 0 0 0 0 0 0  4. Conclusion  0   1 0 0 0 0 0 0 0 0       0   1 0 0 0 0 0 0 0 0  A model of a ternary switching function as a      0   1 0 0 0 0 0 0 0 0  transformation over vector spaces is presented. The     =  0   0 0 0 0 0 0 0 1 0  characteristic transfer matrix for a particular switching      1   0 0 0 0 0 0 0 1 0  function is introduced and methods for obtaining it      0   1 0 0 0 0 0 0 0 0  from either a switching function specification or a      0   0 0 0 0 0 0 0 1 0  netlist are provided. Inclusion of additional constants 0 0 0 1 0 0 0 0 0 0 that cover more than one logic value are described and =  0 0 0 0 0 0 0 1 0  used to obtain multiple system responses through a =  0 0 1  ⊗  0 1 0  single calculation with the transfer matrix. = h2| ⊗ h1| = h21|  Here, we arbitrarily choose to perform outer product References operations from the topmost signal to the bottommost when forming the transfer matrices for partitions and [1] C. T. Chen, Linear System Theory and Design. Holt, to perform the direct matrix multiplication operations Rinehart and Winston, 1984. using the transfer matrix closest to the network inputs [2] D. M. Miller and M. A. Thornton, Multiple Valued as the leftmost operand. The network response to Logic: Concepts and Representations. Morgan & multiple input stimuli can be computed with a single Claypool Publishers, 2007. evaluation of the transfer matrix through use of the ht| value where ht| = h1|+h1|+h2| as proven in Corollary [3] M. A. Thornton and J. Dworak, “Ternary logic net- 3.7. work justification using transfer matrices,” Proceed- ings. IEEE International Symposium on Multiple-Valued Example 3.9: Calculating Multiple Network Re- Logic, 2013. sponses: The total network response due to all possible network input values hftot| is calculated as [4] M. A. Thornton and T. W. Manikas, “Spectral response of ternary logic netlists,” Proceedings. IEEE Interna- hftot| = htt|T T tional Symposium on Multiple-Valued Logic, 2013.  1   1 0 0 0 0 0 0 0 0   1   1 0 0 0 0 0 0 0 0  [5] P. A. M. Dirac, “A new notation for quantum mechanics,”      1   1 0 0 0 0 0 0 0 0  Proc. of the Cambridge Philosophical Society, vol. 54,     p. 416, 1939.  1   1 0 0 0 0 0 0 0 0      =  1   0 0 0 0 0 0 0 1 0      [6] T. Sasao, Switching Theory for Logic Synthesis. Kluwer  1   0 0 0 0 0 0 0 1 0  Academic Publishers, 1999.      1   1 0 0 0 0 0 0 0 0       1   0 0 0 0 0 0 0 1 0  [7] R. E. Bryant, “Graph-Based algorithms for boolean 1 0 0 1 0 0 0 0 0 0 function manipulation,” IEEE Trans. Comput., vol. C- 35, no. 8, pp. 677 –691, Aug. 1986. =  5 0 1 0 0 0 0 3 0    = 5 1 0 0 0 0 0 0 0 0 [8] D. M. Miller and R. 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