Intel® Trusted Execution Technology (Intel® TXT)

Intel® Trusted Execution Technology (Intel® TXT) Software Development Guide Measured Launched Environment Developer’s Guide May 2017 Revision 014 Document: 315168-014 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. 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Copyright © 2006-2017 Intel Corporation 2 315168-014 Contents 1 Overview ...................................................................................................... 10 1.1 Measurement and Intel® Trusted Execution Technology (Intel® TXT) ........... 10 1.2 Dynamic Root of Trust ......................................................................... 11 1.2.1 Launch Sequence ................................................................... 11 1.3 Storing the Measurement ..................................................................... 12 1.4 Controlled Take-down .......................................................................... 12 1.5 SMX and VMX Interaction ..................................................................... 12 1.6 Authenticated Code Module ................................................................... 12 1.7 Chipset Support .................................................................................. 13 1.8 TPM Usage ......................................................................................... 14 1.9 Hash Algorithm Support ....................................................................... 14 1.10 PCR Usage ......................................................................................... 15 1.10.1 Legacy Usage ........................................................................ 16 1.10.2 Details and Authorities Usage ................................................... 16 1.11 DMA Protection ................................................................................... 17 1.11.1 DMA Protected Range (DPR) .................................................... 18 1.11.2 Protected Memory Regions (PMRs) ............................................ 18 1.12 Intel® TXT Shutdown ........................................................................... 18 1.12.1 Reset Conditions .................................................................... 18 2 Measured Launched Environment ..................................................................... 20 2.1 MLE Architecture Overview ................................................................... 20 2.2 MLE Launch ........................................................................................ 23 2.2.1 Intel® TXT Detection and Processor Preparation .......................... 23 2.2.2 Detection of Previous Errors ..................................................... 24 2.2.3 Loading the SINIT AC Module ................................................... 25 2.2.4 Loading the MLE and Processor Rendezvous ............................... 30 2.2.5 Performing a Measured Launch ................................................. 33 2.3 MLE Initialization ................................................................................. 35 2.4 MLE Operation .................................................................................... 40 2.4.1 Address Space Correctness ...................................................... 41 2.4.2 Address Space Integrity .......................................................... 41 2.4.3 Physical RAM Regions ............................................................. 41 2.4.4 Intel® Trusted Execution Technology Chipset Regions .................. 41 2.4.5 Device Assignment ................................................................. 42 2.4.6 Protecting Secrets .................................................................. 42 2.4.7 Model Specific Register Handling .............................................. 42 2.4.8 Interrupts and Exceptions ........................................................ 43 2.4.9 ACPI Power Management Support ............................................. 43 2.4.10 Processor Capacity Addition (aka CPU Hotplug) ........................... 46 2.5 MLE Teardown .................................................................................... 46 2.6 Other Considerations ........................................................................... 49 2.6.1 Saving MSR State across a Measured Launch ............................. 49 3 Verifying Measured Launched Environments ....................................................... 51 3.1 Overview ........................................................................................... 51 3.1.1 Versions of LCP Components .................................................... 52 3.2 LCP Components. General provisions, V2 ................................................ 52 315168-014 3 3.2.1 LCP Policy ............................................................................. 53 3.2.2 LCP Policy Data ...................................................................... 55 3.2.3 LCP Policy Element ................................................................. 57 3.2.4 Signed Policies ....................................................................... 57 3.2.5 Supported Cryptographic Algorithms ......................................... 57 3.2.6 Policy Engine Logic ................................................................. 58 3.2.7 Platform Owner Index ............................................................. 60 3.3 LCP Components. V3 Deltas .................................................................. 60 3.3.1 TPM NV RAM .......................................................................... 60 3.3.2 LCP Policy 2 ........................................................................... 61 3.3.3 LCP Policy Data ...................................................................... 62 3.3.4 LCP Policy Elements ................................................................ 62 3.3.5 List Signatures ....................................................................... 62 3.3.6 PCR Extend Policy .................................................................. 62 3.3.7 V3 Policy Engine Logic. ............................................................ 63 3.3.8 Measuring the Enforced Policy .................................................. 64 3.3.9 Effective TPM NV info Hash ...................................................... 67 3.4 Combined Policy Engine Processing Logic ................................................ 68 3.4.1 Overall Topological Changes .................................................... 68 3.4.2 Processing of Policy Data Files .................................................. 68 3.4.3 TPM 1.2 mode ....................................................................... 69 3.4.4 TPM 2.0 Mode ........................................................................ 69 3.5 Revocation ......................................................................................... 71 3.5.1 SINIT Revocation ................................................................... 71 4 Development and Deployment Considerations .................................................... 73 4.1 Launch Control Policy Creation .............................................................. 73 4.2 Launch Errors and Remediation ............................................................. 73 4.3 Determining Trust ............................................................................... 74 4.3.1 Migration of SEALed Data ........................................................ 74 4.4 Deployment

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