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IBM System P5 590 and 595 Technical Overview and Introduction September 2006

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IBM System P5 590 and 595 Technical Overview and Introduction September 2006 Front cover IBM System p5 590 and 595 Technical Overview and Introduction Finer system granularity using Micro-Partitioning technology to help lower TCO Support for versions of AIX 5L, Linux, and i5/OS operating systems Enterprise class features for applications that require a robust environment Carlo Costantini Charlie Cler Jim Wood ibm.com/redbooks Redpaper International Technical Support Organization IBM System p5 590 and 595 Technical Overview and Introduction September 2006 Note: Before using this information and the product it supports, read the information in “Notices” on page vii. Second Edition (September 2006) This edition applies to the IBM System p5 590 and 595, and AIX 5L Version 5.3, product number 5765-G03. © Copyright International Business Machines Corporation 2005, 2006. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . vii Trademarks . viii Preface . ix The team that wrote this Redpaper . ix Become a published author . .x Comments welcome. .x Chapter 1. General description . 1 1.1 Model abstract for 9119-590 and 9119-595 . 2 1.2 System frames . 3 1.3 Installation planning . 4 1.3.1 System specifications . 4 1.3.2 Physical package . 5 1.3.3 Service clearances . 5 1.4 Power and cooling. 6 1.5 Minimum and optional features . 7 1.5.1 Processor features . 9 1.5.2 Memory features . 10 1.5.3 USB diskette drive . 11 1.5.4 Hardware Management Console models . 11 1.6 External disk subsystems . 12 1.6.1 IBM TotalStorage EXP24 . 12 1.6.2 IBM TotalStorage DS4000 series . 12 1.6.3 IBM TotalStorage DS6000 and DS8000 series. 12 1.7 Statement of Direction. 13 Chapter 2. Architecture and technical overview . 15 2.1 System design. 16 2.1.1 Central Electronics Complex. 16 2.1.2 CEC backplane . 17 2.1.3 Processor books . 18 2.1.4 The POWER5+ processor . 18 2.1.5 Multi-chip module and system interconnect . 20 2.1.6 Simultaneous multithreading. 22 2.1.7 Dynamic power management . 23 2.1.8 Available processor speeds . 23 2.2 System flash memory configuration . 24 2.2.1 Vital product data and system smart chips . 24 2.3 Light strip. 25 2.4 Memory subsystem . 27 2.4.1 Memory cards . 28 2.4.2 Memory configuration and placement. 29 2.4.3 Memory throughput. 31 2.5 System buses . 32 2.5.1 GX+ and RIO-2 buses. 32 2.6 Internal I/O subsystem . 33 2.6.1 I/O drawer . 33 2.6.2 I/O drawer attachment . 34 © Copyright IBM Corp. 2005, 2006. All rights reserved. iii 2.6.3 Single loop (full-drawer) cabling . 35 2.6.4 Dual looped (half-drawer) cabling . 36 2.6.5 Disks and boot devices . 36 2.6.6 Media options . 37 2.6.7 PCI-X slots and adapters . 37 2.6.8 LAN adapters . 38 2.6.9 SCSI adapters. 38 2.6.10 iSCSI. 38 2.6.11 Fibre Channel adapters . 40 2.6.12 Graphic accelerators. 41 2.6.13 Asynchronous PCI-X adapters . 41 2.6.14 PCI-X Cryptographic Coprocessor . 41 2.6.15 Internal storage . 42 2.7 Logical partitioning . 42 2.7.1 Dynamic logical partitioning . 42 2.8 Virtualization . 43 2.8.1 POWER Hypervisor . 43 2.9 Advanced POWER Virtualization feature . 45 2.9.1 Micro-Partitioning technology . 46 2.9.2 Logical, virtual, and physical processor mapping . 47 2.9.3 Virtual I/O Server . 49 2.9.4 Partition Load Manager. 52 2.9.5 Operating system support for Advanced POWER Virtualization. ..
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