USOO8051 118B2

(12) United States Patent (10) Patent No.: US 8,051,118 B2 Lundvall et al. (45) Date of Patent: *Nov. 1, 2011

(54) COMPOSITION OF DECIMAL FLOATING 23.8% A l 3. E",rOne et al. PONT DATA 5,220,523 A 6/1993 Yoshida et al. 5,268,855 A 12, 1993 M tal. (75) Inventors: Shawn D. Lundvall, Midlothian, VA 5,384,723 A 1/1995 R. (US); Eric M. Schwarz, Gardiner, NY 5,481,489 A 1/1996 Yanagida et al. 5,696,709 A 12/1997 Smith, Sr...... 364,745 W.Roaldappingers Falls, M. SythsNY (US); Phil C. YehYeh, 5,696,7115,729,228 A 12/19973/1998 MakineniFranaszek et al. Poughkeepsie, NY (US) 5,825,678 A 10/1998 Smith ...... 364,748 5,982,307 A 11/1999 Adachi (73) Assignee: International Business Machines 6,098,192 A 8, 2000 Glover Corporation, Armonk, NY (US) 6,369,725 B1 4/2002 Busaba s s 6,437,715 B1 8/2002 Cowlishaw (*) Notice: Subject to any disclaimer, the term of this 6,525,679 B1 2, 2003 Cowlishaw patent is extended or adjusted under 35 (Continued) U.S.C. 154(b)(b) bybV 1069 days.yS FOREIGN PATENT DOCUMENTS This patent is Subject to a terminal dis- JP 9062863. A 3, 1997 Ca10. (Continued) (21) Appl. No.: 11/740,711 OTHER PUBLICATIONS (22) Filed: Apr. 26, 2007 “Intel(R) 64 and IA-32 Architectures Software Developer's Manual.” vol. 1: Basic Architecture, 253665-022US, Nov. 2006. (65) Prior Publication Data (Continued) US 2008/O270496 A1 Oct. 30, 2008 Primary Examiner — Tan V Mai (51) Int. Cl. (74) Attorney, Agent, or Firm — Dennis Jung G06F 5/00 (2006.01) (52) U.S. Cl...... 708/204 (57) ABSTRACT (58) Field of Classification Search ...... 708/204 A decimal floating point finite number in a decimal floating See application file for complete search history. point format is composed from the number in a different (56) Ref Cited format. A decimal floating pointformat includes fields to hold eerees e information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal float U.S. PATENT DOCUMENTS ing point data, including infinities and NaNs (not a number), 3,934,462 A 1/1976 Rende 4,075,679 A 2/1978 Christopher et al. are also composed. Decimal floating point data are also 4.429,370 A 1, 1984 Blau et al. decomposed from the decimal floating point format to a dif 4,442.498 A 4, 1984 Rosen ferent format. 4,589,087 A 5/1986 Auslander et al. 4,799,181 A 1/1989 Tague et al. 28 Claims, 14 Drawing Sheets

DFPDATA IMPORT OVERWEW 700

OBTANDATA INHUMAN READABEFORMAT 702 SIGNEDPACKEDCONVERT HUMAN DECIMAL READABLE FOR FORMATSNS T AND SIGN, AND TO SIGNED BINARY INTEGER FOR exPONENT

- rs w ------

s 706 COMBINE ExpoNENTTHESIGNIFICAND TO CREATE WITH THE BASEDBA THE DECIMAL FLOATING PON DATM

r - a - - r s - w w ------s - r a my w w ...... US 8,051,118 B2 Page 2

U.S. PATENT DOCUMENTS “DRAFT Standard for Floating-Point Arithmetic P754,” Draft 1.3.0, 6,681.237 B1 1/2004 Fossum et al. Feb. 23, 2007. 6,745,220 B1 6, 2004 Hars “z/Architecture—Principles of Operation.” Sixth Edition, SA22 6,842,124 B2 1/2005 Penna 7832-05, Apr. 2007. 6,898,615 B2 5/2005 Miyasaka et al. “z/Architecture—Preliminary Decimal-Floating-Point Architec 7,389,499 B2 * 6/2008 Donovan et al...... T17,143 ture.” SA23-2232-00, Nov. 2006. 7.467,174 B2 12/2008 Wang et al. “IEEE Standard for Binary Floating-Point Arithmetic.” IEEE Std 7,698.352 B2 * 4/2010 Carlough et al...... TO8.204 T54-1985. 7,707,233 B2 * 4/2010 Cornea-Hasegan ...... TO8.204 “IEEE Standard for Radix-Independent Floating-Point Arithmetic.” 2002fO184282 A1 12/2002 Yuval et al. IEEE Std 854-1987. 2003,0005189 A1 1/2003 Wilson et al. “Densely Packed Decimal Encoding.” Mike Cowlishaw, IEEE Pro 2006/0047739 A1 3, 2006 Schulte et al. ceedings—Computers and Digital Techniques, ISSN 1350-2387. 2006/0265443 A1 11/2006 Cornea-Hasegan vol. 149, No. 3, pp. 102-104, IEEE, May 2002 (Abstract Only). 2007/0050436 A1* 3/2007 Chen et al...... TO8.204 "A Summary of Densely Packed Decimal Encoding.” www.2. 2007/0061388 A1* 3/2007 Carlough et al...... TO8.204 hursley.ibm.com/decimal/DPDecimal.html. 4 pages. 2008/0270495 A1 10/2008 Lundvallet al. Office Action for U.S. Appl. No. 1 1/840,345 dated Dec. 3, 2010. 2008/0270497 A1 10/2008 Lundvallet al. Office Action for U.S. Appl. No. 1 1/840,323 dated Nov. 4, 2010. 2008/0270498 A1 10/2008 Lundvallet al. Office Action for U.S. Appl. No. 1 1/840,359 dated Dec. 2, 2010. 2008/0270499 A1 10/2008 Lundvallet al. Office Action for U.S. Appl. No. 1 1/740,701 dated Oct. 21, 2010. 2008/02705OO A1 10/2008 Lundvallet al. Notice of Allowance for U.S. Appl. No. 1 1/740,683 dated Oct. 4. 2008/0270506 A1 10/2008 Lundvallet al. 2010. 2008/0270.507 A1 10/2008 Lundvallet al. 2008/0270.509 A1 10/2008 Lundvallet al. Cowlishaw, Mike, "A Summary of Densely Packed Decimal Encod 2008/0270756 A1 10/2008 Lundvallet al. ing.” IEE Proceedings—Computers and Digital Techniques, ISSN 1350-2387, Vo. 149, No. 3, pp. 102-104, May 2002, revised Feb. 13, FOREIGN PATENT DOCUMENTS 2007. JP 9069781 A 3, 1997 Carter, et al., “Efficient Floating Point to Clipped Integer Conver WO WO 01 08001 A1 2, 2001 sion.” IBM Technical Disclosure, May 1992, pp. 364-365. Office Action for U.S. Appl. No. 1 1/227,515 (U.S. Patent No. 7,698.352 B2) dated May 28, 2009. OTHER PUBLICATIONS U.S. Appl. No. 1 1/227,481. Non Final Office Action Mailed Jun. 26, “Intel(R) 64 and IA-32 Architectures Software Developer's Manual.” 2009. vol. 2A: Instruction Set Reference, A-M, 253666-022US, Nov. 2006. U.S. Appl. No. 1 1/227,481 Final Office Action mailed Jan. 25, 2010. U.S. Appl. No. 1 1/227,481 Non Final Office Action mailed Apr. 5, “Intel(R) Itanium(R Architecture Software Developer's Manual.” vol. 2010. 1: Application Architecture, Revision 2.2, Jan. 2006, Document No. U.S. Appl. No. 1 1/227,481 Final Office Action mailed Jul 22, 2010. 245317-005. U.S. Appl. No. 1 1/227,515 Non Final Office Action mailed May 28, “Intel(R) Itanium(R Architecture Software Developer's Manual.” vol. 2009. 2: System Architecture, Revision 2.2, Jan. 2006, Document No. U.S. Appl. No. 1 1/227,515 Notice of Allowance mailed Nov. 25, 245318-005. 2010. Intel(R) Itanium(R Architecture Software Developer's Manual, vol. 3: U.S. Appl. No. 1 1/225,515 Issue Notification mailed Mar. 24, 2010. Instruction Set Reference, Revision 2.2, Jan. 2006, Document No. 245,319-005. * cited by examiner U.S. Patent Nov. 1, 2011 Sheet 1 of 14 US 8,051,118 B2

106 108 110 100 S COMBINATION TENCODED TRALING SIGNIFICAND O 1 12 31 fig. 1A

106 108 110 102

S COMBINATION ENCODED TRALING SIGNIFICAND O 1 14 63 fig. 1B

106 108 f10 104

s COMBINATION ENCODED TRALING SIGNIFICAND O 1 18 127 fig. 1C 150 106 108 (7110 (% (% ENCODED TRAILNG

SIGN COMBINATION FIELD SIGNIFICAND SIGN MDSN of TWOEFMOSTBS QF : REMAININGBITS OF REMAININGDIGITS OF BIASED EXP. BIASED EXP. SIGNIFICAND fig. 1D U.S. Patent Nov. 1, 2011 Sheet 2 of 14 US 8,051,118 B2

BITS B T BIASED 12345 TYPE EXPONENT LMD OOOOO FINITE NUMBER OO RBE OOOO1 FINITE NUMBER OO RBE OOOO FINITE NUMBER OO RBE FINITE NUMBER OO RBE OO1 OO FINITE NUMBER OO RBE FINITE NUMBER OO RBE FINITE NUMBER OO RBE FINITE NUMBER OO RBE O 1 OOO FINITE NUMBER O1 RBE FINITE NUMBER O1 RBE

FINITE NUMBER 1 RBE

o1011 m FINITE NUMBERO1 RBE 3 of 100 m FINITE NUMBERO1 RBE 4 01101 m FINITE NUMBERo1 IRBE 5 O1110 m FINITE NUMBERO1 RBE 6 O1111 m FINITE NUMBERO1 RBE 7 10000 m FINITE NUMBER 10 RBE 1000 m FINITE NUMBER 10 RBE

1 O1 O1

O RBE

O RBE 1 1 0 1 O 1 IRBE

1 RBE O RBE 11 1 01 r INFINTY T - QNoN? - SNaN? T - fig. 2A U.S. Patent Nov. 1, 2011 Sheet 3 of 14 US 8,051,118 B2

EXPLANATION: NOT APPLICABLE CONCATENATION ALL BITS IN THE COMBINATION FIELD TO THE RIGHT OF BIT 5 OF THE FORMAT CONSTITUTE THE RESERVED FELD FOR INFINITY. ALL BITS IN THE COMBINATION FIELD TO THE RIGHT OF BIT 6 OF THE FORMAT CONSTITUTE THE RESERVED FIELD FOR NoN. LEFTMOST DIGIT OF THE SIGNIFICAND. BIT 6 S A PART OF THE REMAINING BIASED EXPONENT. REMAINING BIASED EXPONENT. T. INCLUDES ALL BITS IN THE COMBINATION FIELD TO THE RIGHT OF BIT 5 OF THE FORMAT. BIT 6 S A RESERVED BIT FOR INFINITY. fig. 2B

U.S. Patent Nov. 1, 2011 Sheet 6 of 14 US 8,051,118 B2

500 502 504

data class MAGNITUDE

SUBNORMAL O < x < N min

EXPLANATION: 510 THE COEFFIECINT IS ZERO AND THE 5:59ENT IS ANY REPRESENTABLE LU fig. 5

600 6O2 604 6O6 610 DATA CLASS ES5

612 INFINITY + 11110 xxx... xxx QUIET NaN + m oxx. xxx 614 fig. 6 U.S. Patent Nov. 1, 2011 Sheet 7 of 14 US 8,051,118 B2

DFP DATA IMPORT OVERVIEW 700 OBTAN DATA IN HUMAN READABLE FORMAT 702

CONVERT HUMAN READABLE FORMAT TO SIGNED PACKED DECIMAL FOR SIGNIFICAND AND SIGN, AND TO SIGNED BINARY INTEGER FOR EXPONENT

------n 704 convert PACKED DECIMAll To A DECIMAL FLOATING POINT INTEGER 705 CONVERT SIGNED BINARY INTEGER TO UNISIGNED BINARY INTEGER FOR BIASED EXPONENT s 706 : COMBINE THE SIGNIFICAND WITH THE BIASED EXPONENT TO CREATE THE DECIMAL FLOATING POINT DATUM

v up wa w MP as to tag up up a s to s up a n us a y nu i s m is as a - U.S. Patent Nov. 1, 2011 Sheet 8 of 14 US 8,051,118 B2

DFP COMPOSITION BOO LOAD A NUMBER OF MOST SIGNIFICANT DIGITS IN REGISTER PAIR AB 802 LOAD REMAINING LEAST SIGNIFICANT DIGITS IN REGISTER PAIR CD 804 LOAD BIASED EXPONENT IN GENERAL REGISTER E B O6 CONVERT CONTENTS OF REGISTER PAR AB TO FLOATING POINT REGISTER PAIR O1 808 CONVERT DECIMAL VALUE IN CD TO OFP FORMAT IN FPR PAR 23 8 10 SHIFT SIGNIFICAND OF FPR PAR O1

ORIGINAL SIGNIFICAND IN N 816 PACKED DECIMAL FORMAT POSITIVE B12 p SUBTRACT FPR PAR Y O1 FROM FPR PAIR 23; STORE INTO FPR O1 31 4. ADD FPR PAIR O TO FPR PAIR 23; STORE INTO FPR O1

318 COMBINE REGISTERE WITH FPR PAR O1; STORE INTO FPR O1 fig. 8 (END U.S. Patent Nov. 1, 2011 Sheet 9 of 14 US 8,051,118 B2

900 906 CONVERT FROM UNSIGNED PACKED //////// R. R. O 16 24 28 J1 902 f 9. 9 904

OBTANDATA AND COMPRESS ) 1000 OBTAIN DATA IN WORKING FORMAT 10O2

CONVERT WORKING FORMAT TO OFP FORMAT

fig. 10A

OBTANDATA AND EXPAND

1050 OBTAIN DATA IN DFP FORMAT

1052 CONVERT DFP FORMAT TO WORKING FORMAT

fig. 10B U.S. Patent Nov. 1, 2011 Sheet 10 of 14 US 8,051,118 B2

1100 1106 CONVERT FROM SIGNED PACKED //////// R. R. O 16 24 28 51 1102 fi9. 11 1104 1200

sHFT scNFICAND LEFTS0 is 12O2 OP codERxB, D, R, //// 8 J 12 16 20 JS2 36 4. O 4. 7 1202a 1204 120g 1212

1300 1303 ADD OP code R. //// R. R. O 162O 24 28 31 1302 1304 fig. 13 1306 1400 1402 3' os 1408 SUBTRACT OP code R//// R. R. O 16 20 24 28 J1 fig. 14 1500 15O2 1506 1503 INSERT BIASED EXPONENT OP CODER//// R. R. O 16 J2O 24 28 S1 1504 fig. 15 U.S. Patent Nov. 1, 2011 Sheet 11 of 14 US 8,051,118 B2

DFP DATA EXPORT OVERVIEW

OBTAN DATA IN DFP FORMAT

1602 CONVERT OFP FORMAT TO PACKED DECIMAL FOR SIGNIFICAND AND SIGN, AND TO BINARY INTEGER FOR BASED EXPONENT

CONVERT PACKED DECIMAL AND BINARY INTEGER TO HUMAN READABLE FORMAT fig.16 €9

DFP DECOMPOSITON 1700 EXTRACT BIASED EXPONENT TO GENERAL REGISTERE 1702 CONVERT LOWER 31 DIGITS AND SIGN OF THE SIGNIFICAND INTO PACKED DECIMAL: STORE INTO REGISTER CD 1704 SHIFT SIGNIFICAND OF FPR PAR O TO RIGHT 1706 CONVERT REMAINING DIGITS INTO REGISTER AB f708 STORE 3 DIGITS OF AB AND 31 DIGITS PLUS SIGN OF CD 1710 STORE GENERAL REGISTER E fig. 17 €9 U.S. Patent Nov. 1, 2011 Sheet 12 of 14 US 8,051,118 B2

1800 1804 1806 EXTRACT BIASED EXPONENT

////////R,R, O 16 24, 28 S1 1802 fig. 18 1900 1904. 1906 1908 CONVERT TO SIGNED PACKED OP code //// M.R.R. O 16 2O 24 28 31 1902 fig. 19 2000

OP CODERx B. D. R. //// O 8 47

2106

OP code 7/////// R. R. O 16 2102 fig. 21

U.S. Patent Nov. 1, 2011 Sheet 13 of 14 US 8,051,118 B2

2300 23O2 2304 2306

NATIVE MEMORY CPU 2312 INPUT/ 2310 EMULATOR OUTPUT REGISTERS CODE DEVICES

fig. 23 2308

INSTRUCTION GUEST FETCHING ROUTINE INSTRUCTIONS

INSTRUCTION TRANSLATION ROUTINE

EMULATION CONTROL ROUTINE U.S. Patent Nov. 1, 2011 Sheet 14 of 14 US 8,051,118 B2

COMPUTER PROGRAM PRODUCT 2500

PROGRAM CODE LOGIC

COMPUTER USABLE MEDIUM 2502

fig. 25 US 8,051,118 B2 1. 2 COMPOSITION OF DECIMAL FLOATING the decimal floating point format. Each decimal floating point POINT DATA format includes fields to hold information on the sign, the exponent, and the significandofa decimal floating point finite CROSS-REFERENCE TO RELATED number. APPLICATIONS In one example, to convert a decimal floating point finite number in human-readable format into a decimal floating This application contains subject matter which is related to point format, the human-readable data is first converted into the subject matter of the following application, which is an intermediate data type, and then from the intermediate data assigned to the same assignee as this application. The below type to a decimal floating point format. The intermediate data listed application is hereby incorporated herein by reference 10 type is to be able to support the conversion without loss of in its entirety: accuracy. One example of an intermediate data type that “COMPOSITION OF DECIMAL FLOATING POINT meets this criteria is signed packed decimal for the sign and DATA, AND METHODS THEREFOR. Lundvallet al., U.S. the significand, and signed binary integer for the exponent. Ser. No. 1 1/840,323, filed herewith. 15 Thus, in this example, the sign and the significand of the human-readable input are converted to signed packed deci TECHNICAL FIELD mal and the exponent of the human-readable input is con This invention relates, in general, to employing decimal Verted to a signed binary integer, then from signed packed floating point data in processing within a processing environ decimal and signed binary integer to a decimal floating point ment, and in particular, to composing decimal floating point format. data in a decimal floating point format from data that are not Therefore, a need exists for a capability that provides data represented in a decimal floating point format. Moreover, conversion from an intermediate data type, like signed packed aspects of the invention relate to decomposing decimal float decimal and signed binary integer, to a decimal floating point ing point data. format. Further, a need exists for a capability that provides 25 data conversion from the decimal floating point format to an BACKGROUND OF THE INVENTION intermediate data type. The shortcomings of the prior art are overcome and addi Floating point is used to represent real numbers on com tional advantages are provided through the provision of an puters. There are different types offloating point arithmetic, article of manufacture that includes at least one computer including binary floating point and decimal floating point, as 30 usable medium having computer readable program code examples. Floating point numbers are discussed in IEEE Std logic to compose a decimal floating point datum. The com 854-1987, IEEE Standard for Radix-Independent Floating puter readable program code logic when executing perform Point Arithmetic; and in IEEE Std 754-1985, IEEE Standard ing, for instance, the following: obtaining a significand of a nary Floating-Point Arithmetic, which are hereby incorpo datum in a first format and an exponent of the datum in a rated herein by reference in their entirety. 35 second format converting the significandin the first format to Binary floating point numbers are represented in computer the significandin a decimal floating point format; converting hardware as base two (binary) fractions. While binary floating the exponent in the second format to a biased exponent; and point has been very valuable over the years, there are some combining the significand in the decimal floating point for limitations with binary floating point operations. For mat and the biased exponent to create the datum in the deci instance, binary floating point cannot represent some decimal 40 mal floating point format. fractions, such as 0.1; and the scaling of binary floating point Methods and systems relating to one or more aspects of the requires rounding. Due to the limitations of binary floating present invention are also described and claimed herein. point, decimal floating point has evolved for use in computa Additional features and advantages are realized through tional processing in computers and other processing environ the techniques of the present invention. Other embodiments mentS. 45 and aspects of the invention are described in detail herein and Decimal floating point is easier to comprehend, since deci are considered a part of the claimed invention. mal data is the most common of all numeric data. A decimal floating point finite number includes a sign bit, an exponent BRIEF DESCRIPTION OF THE DRAWINGS and a significand. The sign bit is Zero for plus and one for minus. The exponent, a signed value, is represented as an 50 One or more aspects of the present invention are particu unsigned binary value by adding a bias, resulting in a biased larly pointed out and distinctly claimed as examples in the exponent. The significand includes a string of decimal digits, claims at the conclusion of the specification. The foregoing where each digit is an integral value between Zero and one less and other objects, features, and advantages of the invention than the radix (i.e., 10 is the radix for decimal). The number of are apparent from the following detailed description taken in digit positions in the significandis called the precision of the 55 conjunction with the accompanying drawings in which: floating point number. FIG. 1A depicts one embodiment of a short data format of a decimal floating point datum, in accordance with an aspect SUMMARY OF THE INVENTION of the present invention; FIG. 1B depicts one embodiment of a long data format of Typically, data that is input to a processing environment is 60 a decimal floating point datum, in accordance with an aspect in a format other than a decimal floating point format. For of the present invention; instance, a human-readable format of numerical data that is, FIG. 1C depicts one embodiment of an extended data for for instance, in decimal character strings, may be input to the mat of a decimal floating point datum, in accordance with an processing environment. Thus, if decimal floating point data aspect of the present invention; is to be used in processing, the data is first converted from the 65 FIG. 1D pictorially depicts an encoding of a decimal float human-readable format to an intermediate format, and then ing point datum, in accordance with an aspect of the present the data in the intermediate format is used to compose data in invention; US 8,051,118 B2 3 4 FIGS. 2A-2B depict one example of the encoding and FIG. 23 depicts another embodiment of a processing envi layout of the combination field of FIGS. 1A-1C, in accor ronment to incorporate and use one or more aspects of the dance with an aspect of the present invention; present invention; FIG.3 depicts examples of values of finite numbers in the FIG.24 depicts further details of the memory of FIG. 23, in various formats of FIGS. 1A-1C, in accordance with an 5 accordance with an aspect of the present invention; and aspect of the present invention; FIG. 25 depicts one example of a computer program prod FIG. 4 depicts one example of various properties of the uct to incorporate one or more aspects of the present inven three decimal floating point formats of FIGS. 1A-1C, in tion. accordance with an aspect of the present invention; FIG. 5 depicts one embodiment of value ranges for finite 10 DETAILED DESCRIPTION OF THE INVENTION number data classes of decimal floating point data, in accor dance with an aspect of the present invention; In accordance with an aspect of the present invention, a FIG. 6 depicts one example of the encoding of not a number capability is provided for composing decimal floating point (NaNs) and infinity data classes of decimal floating point (DFP) data. For instance, a datum in a format other than a data, in accordance with an aspect of the present invention; 15 decimal floating point format is converted to a decimal float FIG.7 depicts one embodiment of an overview of the logic ing point format. This conversion converts the exponent and associated with importing a decimal floating point datum significand separately, in one example. The capability from a non-decimal floating point format, in accordance with employs, in one embodiment, a plurality of instructions or an aspect of the present invention; logic that facilitate the conversion and composition. FIG. 8 depicts further details of one embodiment of the As a further aspect of the present invention, a capability is logic associated with composing a decimal floating point provided for decomposing the decimal floating point data. datum, in accordance with an aspect of the present invention; For instance, a decimal floating point datum is converted to a FIG.9 depicts one example of a format of a Convert signed format other than a decimal floating point format. This capa Packed instruction used in accordance with an aspect of the bility also employs, in one embodiment, a plurality of instruc present invention; 25 tions or logic that facilitate the conversion and decomposi FIG. 10A depicts one embodiment of the logic associated tion. with a compress function used in accordance with an aspect of A decimal floating point finite number includes three com the present invention; ponents: a sign bit, an exponent, and a significand. The mag FIG. 10B depicts one embodiment of the logic associated nitude (an unsigned value) of the number is the product of the with an expand function used in accordance with an aspect of 30 significand and the radix (10 for DFP) raised to the power of the present invention; the exponent. The number is positive or negative depending FIG.11 depicts one example of a formatofa Convert From on whether the sign bit is Zero or one, respectively. Signed Packed instruction used in accordance with an aspect The significand has an implied radix point, and its position of the present invention; depends on which interpretation of the floating point datum is FIG. 12 depicts one embodiment of a format of a Shift 35 being applied. This interpretation is called a view. There are Significand Left instruction used in accordance with an multiple views that can be applied to a floating point format, aspect of the present invention; and each view is an interpretation of the meaning of the fields FIG. 13 depicts one example of a format of an Add instruc in a floating point datum, and an implied radix point. tion used in accordance with an aspect of the present inven Examples of the multiple views include a fraction view, a left tion; 40 units view and a right units view. With the fraction view, the FIG. 14 depicts one example of a format of a Subtract radix point is implied to be to the left of the leftmost digit of instruction used in accordance with an aspect of the present the significand. With the left units view, the leftmost digit of invention; the significand is assumed to be the units digit and the radix FIG. 15 depicts one example of a format of an Insert Biased point is implied to be immediately to the right of this digit. Exponent instruction used in accordance with an aspect of the 45 With the right units view, the rightmost digit of the significand present invention; is assumed to be the units digit and the radix point is implied FIG. 16 depicts one embodiment of an overview of the to be immediately to the right of the entire significand. logic associated with exporting a decimal floating point Although all three views can be applied to a floating point datum, in accordance with an aspect of the present invention; format, in the examples described herein, the right units view FIG. 17 depicts further details of one embodiment of the 50 is applied to DFP. unless otherwise noted. Thus, for the sig logic associated with decomposing a decimal floating point nificand, the implied radix point is immediately to the right of datum, in accordance with an aspect of the present invention; the significand. FIG. 18 depicts one example of a format of an Extract The use of different views has an affect on the definition of Biased Exponent instruction used in accordance with an unbiased exponent and the bias. The value of the floating aspect of the present invention; 55 point number is defined to be the product of the significand FIG. 19 depicts one example of a format of a Convert To times the base raised to the power of the unbiased exponent. Signed Packed instruction used in accordance with an aspect Since different views place the assumed radix point at differ of the present invention; ent positions in the significand, to keep the value the same, the FIG. 20 depicts one example of a format of a Shift Signifi unbiased exponent is to change by a corresponding amount, cand Right instruction used in accordance with an aspect of 60 and the bias to convert between the biased exponent and the the present invention; unbiased exponent is to change. This results in different expo FIG. 21 depicts one example of a format of a Convert nent and bias terms including: fraction view exponent, left signed Packed instruction used in accordance with an aspect units view (LUV) exponent, right units view (RUV) expo of the present invention; nent, fraction view bias, left units view bias and right units FIG. 22 depicts one embodiment of a processing environ 65 view bias. ment to incorporate and use one or more aspects of the present The representation of decimal floating point finite numbers invention; allows leading Zeros and trailing Zeros in the significand. This US 8,051,118 B2 5 6 allows some numbers to have multiple representations. Each below table. When the delivered value is exact, the preferred representation has a different combination of significand and quantum depends on the operation. When the delivered value exponent. For example, 1000000x10 and 10x10' are two is inexact, the preferred quantum is the Smallest quantum, different representations of the same number. This number unless otherwise stated. representation carries information about both the numerical 5 In the absence of an overflow or underflow interruption, if value and the quantum of a decimal floating point finite num the delivered value is a finite number, the cohort member with ber. The set of different representations of a decimal floating the quantum closest to the preferred quantum is selected. point number using the same sign is called a cohort. Each of In the case of an overflow or underflow interruption, the these multiple representations is called a cohort member. A cohort member with the quantum closest to the scaled pre plus Zero and a minus Zero have the same value, but are in 10 ferred quantum is selected. The scaled preferred quantum is different cohorts. obtained by Scaling the preferred quantum using the same For a DFP finite number, the magnitude of a value of one in scale factor that was used to obtain the delivered value. the rightmost digit position of the significand is called the Examples of preferred quantum for various operations are quantum. Each cohort member of a cohort uses a different depicted below.

Operations Delivered Value Preferred Quanta ADD Exact The Smaller quantum of the two source operands Inexact The Smallest quantum CONVERT FROM FIXED Exact One Inexact The Smallest quantum CONVERT FROM SIGNED One PACKED CONVERT FROM One UNSIGNED PACKED DIVIDE Exact The quantum of the dividend divided by the quantum of the divisor nexact The Smallest quantum NSERT BIASED The quantum corresponds to the requested EXPONENT biased exponent LOAD AND TEST The quantum of the source operand LOAD FPINTEGER X80 The larger value of one and the quantum of he source operan nexact One LOAD LENGTHENED Exac The quantum of the source operand nexact The Smallest quantum LOAD ROUNDED Exac The quantum of the source operand nexact The Smallest quantum PERFORM FLOATING Exac The largest quantum POINT OPERATION nexact The Smallest quantum (DPQC = 0) PERFORM FLOATING Exac One POINT OPERATION nexact The Smallest quantum (DPQC = 1) MULTIPLY Exac The product of the quanta of the two source operands nexact The Smallest quantum QUANTIZE Exac The requested quantum nexact The requested quantum REROUND Exac The larger value of the quantum that corresponds to the requested significance and the quantum of the source operand nexact The quantum that corresponds to the requested significance SHIFT SIGNIFICAND LEFT The quantum of the source operand SHIFT SIGNIFICAND The quantum of the source operand RIGHT SUBTRACT Exact The Smaller quantum of the two source operands Inexact The Smallest quantum Explanation: —For these operations, the concept of exact result or inexact result does not apply, If the delivered value cannot be represented with the preferred quantum, it is represented with the quantum closest to the preferred quantum, DPQCDFP preferred quantum control. quantum to represent the same value. The quantum of a cohort 60 Decimal floating point numbers may be represented in any member is the same, regardless of whether the left units view of three data formats: short, long, or extended. As examples, or right units view is taken. the short format includes 32 bits, the long format 64 bits, and For operations that produce a DFP result, a quantum, called the extended format 128 bits. the preferred quantum, is defined to select a cohort memberto 65 NaNs (Not a Number) and other symbols, such as infinity, represent the delivered value, if it is a finite number. The may also be represented in any of the three data formats. A preferred quanta for these operations are depicted in the NaN is a value or symbol that is usually produced as a result US 8,051,118 B2 7 8 ofan operation on invalid operands. There are quiet NaNs and Encoding. Mike Cowlishaw, Jul. 16, 2005, signaling NaNs. A quiet NaN, in most instances, does not www2.hursley.ibm.com/decimal/DPDecimal.html, and raise any additional exceptions as it propagates through “Densely Packed Decimal Encoding.” Mike Cowlishaw, operations, such as decimal floating point operations. On the IEEE Proceedings—Computers and Digital Tech other hand, a signaling NaN does raise additional exceptions. niques, ISSN 1350-2387, Vol. 149, No. 3, pp. 102-104, The contents of each data format represent encoded infor IEEE, May 2002, each of which is hereby incorporated mation. Special codes are assigned to NaNs and infinities. herein by reference in its entirety. Examples of the formats are described with reference to Each of the three data formats has different values of finite FIGS. 1A-1C. For instance, FIG. 1A depicts one example of numbers. Examples of these values in the various formats are a short data format representation 100 of a decimal floating 10 point datum: FIG. 1B depicts one example of a long data shown in FIG.3. As depicted, values are provided for both the format representation 102 of a decimal floating point datum; left units view 300 and right units view 302 for each format, and FIG. 1C depicts one embodiment of an extended data including the short format304, long format306 and extended format representation 104 of a decimal floating point datum. format 308. Each data format is of a different length, but has the same 15 As described above, in one example, a decimal floating fields. The fields include, for instance, the following: point number includes a sign, an exponent, and a significand. A sign field (S) 106 represents the sign bit of the decimal The sign is encoded, for instance, as a one bit binary value and floating point datum. In one example, it is bit 0 in each is represented in sign field 106. The significand is encoded, format, and is set to Zero for plus and one for minus; for instance, as an unsigned decimal integer in two distinct A combination field 108: For finite numbers, this field parts: the leftmost digit (LMD) of the significand is encoded includes the biased exponent and the leftmost digit of the as part of combination field 108; and the remaining digits of significand; for NaNs and infinities, this field includes the significand are encoded in encoded trailing significand codes to identify them. 110. Similarly, the exponent is represented in two parts, as an When bits 1-5 of the format are in the range of 00000 example. However, prior to encoding the exponent, the expo 11101, the operand is a finite number. The two leftmost 25 nent is converted to an unsigned binary value, called the bits of the biased exponent and the leftmost digit of the biased exponent, by adding a bias value, which is a constant significand are encoded in bits 1-5 of the format. Bit 6 for each format. The two leftmost bits of the biased exponent, through the end of the combination field includes the rest as well as the remaining 6, 8, or 12 bits (depending on the of the biased exponent. format) are also encoded in combination field 108. This When bits 1-5 of the format field are 11110, the operand is 30 encoding is pictorially depicted in FIG. 1D. an infinity. All bits in the combination field to the right of As shown in FIG. 1D, an encoding 150 of a decimal float bit 5 of the format constitute the reserved field for infin ing point number includes a sign 152 in sign field 106; the ity. A nonzero value in the reserved field is accepted in a leftmost digit of the significand 154, the two leftmost bits of source infinity; the reserved field is set to Zero in a the biased exponent 156 and the remaining bits of the biased resultant infinity. 35 exponent 158 in combination field 108; and the remaining When bits 1-5 of the format are 11111, the operand is a digits of the significand 160 in encoded trailing significand NaNand bit 6, called the SNaN bit, further distinguishes 110. QNaN from SNaN. If bit 6 is zero, then it is QNaN: Each of the three data formats for decimal floating point otherwise, it is SNaN. All bits in the combination field to numbers has properties associated therewith. These proper the right of bit 6 of the format constitute the reserved 40 ties are summarized in FIG. 4. As depicted, properties 400 field for NaN. A nonzero value in the reserved field is include for each format 402 the following, as examples: for accepted in a source NaN; the reserved field is set to zero mat length 404, combination length 406, encoded trailing in a resultant NaN. significand length 408, precision 410, maximum left units FIGS. 2A-2B summarize the encoding and layout of the view (LUV) exponent (E.) 412, minimum left units view combination field. In the figures, the biased exponent of 45 exponent (E.) 414, left units view bias 416, maximum right a finite number is the concatenation of two parts: (1) two units view (RUV) exponent (Q) 418, minimum right units leftmost bits are derived from bits 1-5 of the format, and view exponent (Q) 420, right units view bias 422, maxi (2) the remaining bits in the combination field. For mum biased exponent 424, largest (in magnitude) normal example, if the combination field of the DFP short for number (N) 426, Smallest (in magnitude) normal number mat includes 10101010101binary, it represents a biased 50 (N) 428, and Smallest (in magnitude) Subnormal number exponent of 10010101binary and a leftmost significand (D) 430. digit of 5. In addition to the above, decimal floating point data is An encoded trailing significand 110 (FIGS. 1A-1C): This categorized into six classes of data, including Zero, Subnor field includes an encoded decimal number, which rep mal number, normal number, infinity, signaling NaN and resents digits in the trailing significand. The trailing 55 quiet NaN data classes. The value of a decimal floating point significand includes all significand digits, except the finite number, including Zero, Subnormal number, and normal leftmost digit. For infinities, nonzero trailing significand number, is a quantization of the real number based on the data digits are accepted in a source infinity; all trailing sig format. The value ranges for finite number data classes are nificand digits in a resultant infinity are set to Zeros, depicted in FIG. 5, and the codes for NaNs and infinity are unless otherwise stated. For NaNs, this field includes 60 depicted in FIG. 6. diagnostic information called the payload. For instance, FIG.5 shows a sign 502 and a magnitude 504 In one example, the trailing significand digits in a DFP data for each data class 500, including Zero data class 506, Sub format are encoded by representing three decimal digits normal data class 508, and normal data class 510. As shown, with a 10-bit declet. The digits in the trailing significand a Subnormal number has a value Smaller than N(Smallest are encoded using densely packed decimal encoding. 65 normal number) and greater than Zero in magnitude. A normal Examples of densely packed decimal encoding are number is a nonzero finite number whose magnitude is described in “A Summary of Densely Packed Decimal between N, and N (largest normal number) inclusively. US 8,051,118 B2 10 Similarly, FIG. 6 shows, in one embodiment, a sign 602, an the Z/Architecture(R) offered by International Business encoding of bits 1-5 of the combination field 604, and an Machines Corporation, include functions to convert to encoding of the remaining bits of the combination field 606 of packed decimal and binary integer. Z/Architecture R is a reg the data format for each data class 600, including infinity data istered trademark of International Business Machines Corpo class 610, quiet NaN data class 612, and signaling NaN data ration, Armonk, N.Y. class 614. Referring to STEP 704, at least a portion of the significand As part of a decimal floating point operation, in which the in the intermediate form is then converted to a decimal float Source operands are finite numbers, a precise intermediate ing point value, and the exponent in the intermediate form is value is first produced, which is the value that would have converted to a biased exponent in unsigned binary integer, been computed if both the precision and exponent range were 10 unbounded. Then, a rounded intermediate value is produced. STEP 705. The converted values are then used in composing That is, except when otherwise specified, the precise inter the decimal floating point datum, STEP 706. mediate value is rounded to the precision of the target format, Further details regarding converting from packed decimal but with unbounded exponent range. This process is called and binary integer to a DFP format and for composing a target precision constrained rounding, and the value selected 15 floating point datum are described with reference to FIG.8. In by this type of rounding is called the precision rounded value. particular, one embodiment of the logic associated with con For IEEE targets, when the IEEE underflow interruption is Verting the significand from a packed decimal value and the disabled and the tininess condition exists, the precise inter biased exponent from a binary integer to a decimal floating mediate value is rounded to fit in the destination format. That point format is described. is, with both precision and exponent range of the target for As one example, the technique is described with reference mat. This process is called denormalization rounding and the to an example in which a 35 digit (34 digit significand and 1 value selected by this type of rounding is called the denor digit sign) signed significand (stored as packed decimal) and malized value. its associated Scaling factor (stored as a 64-bit binary integer) In other examples, a Source operand is taken and modified are converted to an extended decimal floating point format. to fit in a subset of the destination format. This process is 25 This example addresses the problem in which 35 digits in called functionally constrained rounding and the value packed decimal require more than 128 bits. selected by this type of rounding is called the functionally Initially, a value is loaded into a general register pair AB, rounded value. STEP 800. The register pair is selected from a plurality (e.g., In any particular instance, only one of the three rounding 16) of available general registers. In one embodiment, the first processes is performed and the value selected (precision 30 register of the pair that is selected is an even register and the rounded value, denormalized value, or functionally rounded next register of the pair is the odd register immediately suc value) is generically referred to as the rounded intermediate ceeding the even register. In this example, sixty-four bits are value. loaded into each general register of the general register pair, In the absence of overflow and underflow interruptions, the with the upper (most significant) 12 bits of the binary coded rounded intermediate value is used as the delivered value. For 35 decimal packed number (3 digits out of 35) right aligned in overflow and underflow interruptions, the rounded interme the register pair and the left 116 bits zeroed. diate value is divided by a scale factor to produce a scaled Additionally, a general register pair CD, which is also value, which is used as the delivered value. selected from the plurality of available registers, is loaded As described above, a decimal floating point datum is with the lower 128bits (least significant 31 digits and sign) of highly encoded in that more information is packed into less 40 the packed decimal, STEP 802. It is assumed that the signed space. For instance, for a decimal floating point finite number, digit is the rightmost digit. the combination field includes a portion of the significand, as Further, a general register, Register E. Selected from the well as the exponent. Since the decimal floating point data is plurality of available registers is loaded with the associated highly encoded, composition of decimal floating point data is biased exponent, which in this example is a 64-bit binary not trivial. 45 integer, STEP 804. Thus, the sign, significand and biased One embodiment of an overview of the logic associated exponent are loaded in general registers, as indicated above. with importing a decimal floating point data from a non Next, the contents of general register pair AB are converted decimal floating point format is described with reference to into a decimal floating point number, which is a portion of the FIG. 7. In this particular example, the non-decimal floating significand of the decimal floating point datum being com point format is a human readable format. 50 posed, STEP 806. The converted decimal floating point num Referring to FIG. 7, in one embodiment, a human readable ber is stored in a selected floating point register pair. Such as data value. Such as a decimal numerical value, is obtained by floating point register pair 01. In one example, the conversion a processor of a processing environment, STEP 700. In one is performed using a Convert signed Packed instruction, example, the value is input by a user. The inputted value is which is described below. converted from its human readable form to an intermediate 55 Additionally, the packed decimal in the general register form, Such as packed decimal and signed binary integer, pair CD is converted into a decimal floating point format and STEP 702. the result is stored in a selected floating point register pair, There are two packed decimal formats, in one example: such as floating point register pair 23, STEP 808. In one signed packed and unsigned packed. In the signed packed example, this conversion is performed using a Convert From decimal format, each byte includes, for instance, two decimal 60 Signed Packed instruction, as described in further detail digits (D), except for the rightmost byte, which includes a below. sign (S) to the right of a decimal digit. Thereafter, the significand of the floating point register pair In the unsigned packed decimal format, each byte includes, 01 is shifted 31 digits to the left to align it for operations with for instance, two decimal digits (D) and there is no sign. floating point register pair 23, STEP 810. The shifting is Techniques to convert from human-readable format to 65 performed by a Shift Significand Left instruction, in one packed decimal and binary integer are known in the art. Many example. The shift does not affect the exponent or sign of the processing environments, including an environment based on decimal floating point data. US 8,051,118 B2 11 12 Subsequently, a determination is made as to whether the Z/Architecture(R) offered by International Business Machines original significand in the packed decimal format is positive, Corporation, Armonk, N.Y. Z/Architecture(R) is a registered INQUIRY 812. If the original significand in the packed deci trademark of International Business Machines Corporation, mal format is positive, then the contents of floating point Armonk, N.Y. Other names used herein may be registered register pair 01 are added to the contents of floating point trademarks, trademarks or product names of International register pair 23, and the result is stored into floating point Business Machines Corporation or other companies. One register pair 01, STEP 814. In one example, this add is per embodiment of the Z/Architecture(R) is described in “Z/Archi formed using an Add instruction, which is described in further tecture Principles of Operation.” IBM Publication No. SA22 detail below. 10 7832-05, 6th Edition, April 2007, which is hereby incorpo However, if the original significand in the packed decimal rated herein by reference in its entirety and which shows one format is negative, INQUIRY 812, then the contents offloat example of the various instructions. Further details regarding ing point register pair 01 are subtracted from the contents of the instructions, as well as additional details relating to deci floating point register pair 23, and the result is stored in mal floating point, and in particular, to a decimal floating floating point register pair 01, STEP 816. A Subtract instruc 15 architecture offered by International Business Machines Cor tion is used, in one example, to perform the Subtraction. poration, are described in an IBM publication entitled “Pre Subsequent to performing either the add or subtract, the liminary Decimal-Floating-Point Architecture.” IBM Publi contents of register E are combined with the contents of cation No. SA23-2232-00, November 2006, which is hereby floating point register pair 01, and placed back into floating incorporated herein by reference in its entirety. Each of the point register pair 01, STEP 818. In one example, an Insert instructions is also described in further detail herein. Biased Exponent instruction is used to perform this combi One instruction used to convert the packed decimal value to nation. This results in a composed DFP data representation of a decimal floating point value (see, e.g., STEP 806, FIG. 8) is the 35 digit significand in packed decimal and its associated the Convert signed Packed instruction 900, which is Scaling factor in binary integer. However, in other examples, 25 the composition can be from other types of non-decimal described with reference to FIG. 9. In one example, instruc floating point formats. tion 900 is a 32-bit instruction in format RRE (register and In the previous examples, the intermediate form includes a register operation having an extended opcode) as that format signed significand in the signed packed decimal format. Two is defined in the IBM(R) Z/Architecture Principles of Opera examples are now given where the intermediate form includes 30 tion. It includes, for instance: an unsigned significand in the unsigned packed decimal for An operation code 902 (e.g., bits 0-15) designating the mat along with a separate bit for the sign. In these examples, Convert signed Packed instruction. In this example, the significandand the sign are converted separately. As in the there are two possible operation codes: one for a 64-bit previous examples, the intermediate form also includes a 35 unsigned packed decimal source in general register, long 64-bit biased exponent in the binary integer format. In both DFP result; and another for a 128-bit unsigned packed examples, the unsigned significand in the intermediate form decimal source in general registers, extended DFP is first converted to a positive integer in the DFP format. As in result. the previous examples, the Insert Biased Exponent instruc A register field 904 (e.g., R., bits 24-27) designating a tion is then used to combine the 64-bit biased exponent in the 40 intermediate form with the integer in the DFP format. Also, in floating point register or a floating point register pair, the both examples, if the result is to be negative, the sign bit is set contents of which are a first operand used by the instruc to one. This could be done in many ways, such as a logical OR tion. and may be performed before or after the Insert Biased Expo A register field 906 (e.g., R., bits 28-31) designating a nent instruction. 45 general register or general register pair, the contents of For the first example, the unsigned significand in the inter which are a second operand used by the instruction. The mediate form is a 34-digit Value in the unsigned packed second operand is an unsigned BCD number. decimal format and it is converted to a positive integer in the The preferred quantum is one, and the delivered value is DFP extended format using the Convert signed Packed, Shift represented with the preferred quantum. Significand Left, and Add instructions. The Convert From 50 The result placed at the first operand location is canonical. Signed Packed and Subtract instructions are not needed. A finite number is canonical when all declets are canonical For the second example, the unsigned significand in the declets. An infinity is canonical when the reserved field is intermediate form is a 16-digit value in the unsigned packed Zero and all digits in the trailing significandare Zeros. A NaN decimal format and it is converted to a positive integer in the 55 is canonical when the reserved field is zero and all declets are DFP long format by a single execution of the Convert signed canonical declets. Packed instruction. The Convert From Signed Packed, Shift Significand Left, Add, and Subtract instructions are not To further explain, the trailing significand digits in a DFP needed. data format are encoded by representing three decimal digits with a 10-bit declet. Of the 1024 possible declets, 1000 In the above logic for composing a decimal floating point 60 datum, a number of instructions are employed. These instruc canonical declets are produced in resultant DFP operands, tions can be implemented in many architectures and may be and 24 noncanonical declets are not produced as DFP results. emulated. As examples, the instructions are executed inhard Both canonical and noncanonical declets are accepted in ware by a processor; by Software executing on a processor source DFP operands. having a native instruction set; or by emulation of a non 65 The following table shows the 24 noncanonical declets, the native instruction set that includes the instruction. In one decimal value to which each maps, and the corresponding particular example, the instructions are implemented in the canonical declet to which this decimal value maps. US 8,051,118 B2 13 14 In one embodiment, compress involves the following four steps: Map To Noncanonical Decimal Canonical Declets (Hex) Value Declets (Hex) 16E 26E 36E 888 O6E 16F 26F 36F 889 O6F 17E 27E 37E 898 O7F G includes two subfunctions G1 and G2. Subfunction G1 17F 27F 37F 899 O7F uses the type field (T), the leftmost two bits of the biased 1EE 2EE 3EE 988 OEE exponent (E1), and the leftmost digit of the significand (D1) 1EF 2EF 3EF 989 OEF 10 1FE 2FE 3FE 998 OFE to form part of the combination field (a). In particular, the 3 1FF 2FF 3FF 999 OFF fields (T, E1 and D1) are used to obtain an encoding of the combination field. Examples of the encoding are shown in When an invalid digit code is detected in the second oper FIGS. 2A-2B. Thus, if for instance, T represents a finite and, a decimal operand data exception is recognized. 15 number, E1 is 2 and D1 is 5, the encoding (from FIG. 2A) is When the opcode of the Convert signed Packed instruction 10101. indicates a 128 bit unsigned packed decimal source, the R Subfunction G2 converts the remaining digits of the sig field designates a valid floating point register pair. Also, the nificand (D2) to the encoded trailing significand field (c). R field designates an even-odd pair of general registers, with Each 3-digit BCD number in D2 is converted to a 10-bit the even numbered register being specified. Densely Packed Decimal (DPD) value. One example of a During execution of the Convert signed Packed instruction, technique to convert to a DPD value is described in “A Sum the second operand in the unsigned packed decimal format is mary of Densely Packed Decimal Encoding. Mike Cowl converted to the DFP format with a positive sign, and the ishaw, Jul. 16, 2005, www2.hursley.ibm.com/decimal/DP result is placed at the first operand location. Decimal.html, and “Densely Packed Decimal Encoding.” In one embodiment, to convert from an unsigned packed 25 Mike Cowlishaw, IEEE Proceedings—Computers and Digi decimal number to a decimal floating point format, a hard tal Techniques, ISSN 1350-2387, Vol. 149, No. 3, pp. 102 ware internal working format of the unsigned packed decimal 104, IEEE, May 2002. Details are also provided below. number is created and that working format is used to create The digits in the trailing significand of a decimal floating point datum are encoded using densely packed decimal the DFP format. This is described in further detail with ref 30 erence to FIG. 10A. (DPD) encoding. Translation operates on three Binary Coded Referring to FIG.10A, initially a value in unsigned packed Decimal (BCD) digits at a time converting the 12 bits into 10 bits with a technique that can be applied or reversed using decimal format in the second operand of the instruction is simple Boolean operations. In the following examples, a converted to a working format, STEP 1000, as described 3-digit BCD number is represented as (abcd)(efgh)(ijkm), a below. 35 10-bit DPD number is represented as (pgr)(stu)(v)(wxy), and The working format (W) of a DFP data includes four pri the boolean operations, & (AND), (OR), and (NOT) are mary fields, for instance: (W=SITIED), where is concat used. enation and: The conversion from a 3-digit BCD number to a 10-bit Primary Fields DPD can be performed through the following Boolean opera S: Sign 40 tions. T: Type (SNaN, QNaN, Infinity, Finite Number) E: Biased exponent D: Significand Digits Secondary Fields Two of the primary fields are further broken down into 45 secondary fields: E1: leftmost two bits of the biased exponent E2: remaining bits of the biased exponent v=aeli D1: leftmost digit of the significand D2: remaining digits of the significand 50 Thus: Alternatively, the following table can be used to perform the conversion. The most significant bit of the three BCD digits (left column) is used to select a specific 10-bit encoding During execution of the instruction, the data in the (right column) of the DPD. unsigned packed decimal format of the second operand is 55 converted to the working format, as indicated above. That is, the sign, which in this case is set to positive, of the data in unsigned packed decimal format is indicated at S. The type, aei prastu V wxy which in this case is a finite number, is indicated at T. The OOO bcd fgh Ojkm biased exponent, which in one example, is obtained from a 60 OO1 bcd fgh 100m table, is indicated at E; and the significand digits are indicated O10 bcdjkh 101m. at D. Again, E includes E1 and E2; and D includes D1 and D2. O11 bcd 10h 111m The working format is used to produce the data in a DFP 100 jkd fgh 1 10m 101 fgd 01h 111m format. In particular, the working format is converted to a 110 jkdOOh 111m DFP format, STEP 1002. As one example, a compress func 65 111 00d 11h 111m tion (G) is used to convert the working format (W) to the DFP format (p). This can be shown symbolically as p=G(W). US 8,051,118 B2 15 16 As described above, the BCD to DPD encoding provides a A register field 1204 (e.g., R., bits 8-11) designating a value for the encoded trailing significand field. Thus, the floating point register or a floating point register pair, the compress function provides the sign and encoded trailing contents of which area third operand used by the instruc significand field (i.e., DFP format) of the packed decimal tion. number in register pair AB. It also provides the combination 5 An index field 1206 (e.g., X, bits 12-15) designating a field. general register having, for instance, a 64-bit number. This compress function is also used by the Convert From A base field 1208 (e.g., B, bits 16-19) designating agen Signed Packed instruction, which is employed in converting eral register having, for instance, a 64-bit number. the decimal value in signed packed decimal format in the A displacement value 1210 having, for instance, a 12-bit register pair CD to a DFP format (see, e.g., STEP808, FIG. 10 number. The contents of the general registers specified 8), as described below. in fields 1206 and 1208, if any, are added to the contents One example of a format of the Convert From Signed of displacement value 1210 to form a second operand Packed instruction 1100 is described with reference to FIG. address. The second operand address is not used to 11. In one example, instruction 1100 is a 32 bit instruction in 15 address data; instead, its rightmost six bits indicate the format RRE (register and register operation having an number of digits to be shifted. The remainder of the extended opcode) as that format is defined in the IBM(R) address is ignored. Z/Architecture Principles of Operation. It includes, for A register field 1212 (e.g., R., bits 32-35) designating instance: another floating point register or floating point register An operation code 1102 (e.g., bits 0-15) designating the pair used by the instruction, the contents of which are a Convert From Signed Packed instruction. In this first operand used by the instruction. example, there are two possible operation codes: one for In operation of this instruction, the significand of the third a 64-bit signed packed decimal source, long DFP result; operand is shifted left the number of digits specified by the and another for a 128-bit signed packed decimal source, second operand address, and the result is placed at the first extended DFP result. 25 operand location. A register field 1104 (e.g., R., bits 24-27) designating a Digits shifted out of the leftmost digit are lost. Zeros are floating point register or a floating point register pair, the Supplied to the vacated positions on the right. The sign of the contents of which are a first operand used by the instruc result is the same as the sign of the third operand. tion. For a finite number, all digits in the significand participate A register field 1106 (e.g., R., bits 28-31) designating a 30 in the shift and the result is a finite number with the same general register or general register pair, the contents of biased exponent as the third operand and the shifted signifi which are a second operand used by the instruction. The cand. For an infinity, all digits in the trailing significand second operand is a signed packed decimal number. participate in the shift, and the result is an infinity with the The preferred quantum is one, and the delivered value is shifted trailing significand and a zero in the reserved field of represented with the preferred quantum. 35 the format. For a QNaN or SNaN, all digits in the trailing The result placed at the first operand location is canonical. significand participate in the shift and the result is a QNaN or When an invalid digit or sign code is detected in the second SNAN, respectively, with the shifted trailing significand and operand, a decimal operand data exception is recognized. a Zero in the reserved field of the format. When the opcode of the Convert From Signed Packed 40 The preferred quantum is the quantum of the third operand. instruction indicates conversion of a 128-bit source, the R If the delivered value is a finite number, it is represented with field designates a valid floating point register pair. Also, the the preferred quantum. R field designates an even-odd pair of general registers, with The result placed at the first operand location is canonical, the even numbered register being specified. except for infinity. When the result is an infinity, if all digits in During execution of the Convert From Signed Packed 45 the trailing significand of the result are Zeros, then the result instruction, the signed packed decimal number in the second is canonical; otherwise, the result is an infinity that has the operand is converted to a DFP number, and the result is placed reserved field set to Zero, canonical declets in the encoded at the first operand location. trailing significand field, and some nonzero digits in the trail This conversion also creates a working format of the signed ing significand. packed decimal number, and from that working format pro 50 This operation is performed for any second operand, including an infinity, QNaN, or SNaN, without causing an duces a DFP representation of the signed packed decimal IEEE exception. number, as described herein with reference to FIG. 10A. When the opcode of the Shift Significand Left instruction Another instruction used during the composition of a DFP indicates an extended DFP operation, the R and R fields datum is a Shift Significand Left instruction (see, e.g., STEP 55 designate valid floating point register pairs. 810, FIG. 8). One example of a format of the Shift Significand To perform the Shift, in one example, an expand function is Left instruction 1200 is described with reference to FIG. 12. used to convert the data to be shifted in a DFP format to a In one example, instruction 1200 is a 48-bit instruction in working format. The shift is performed on the working for format RXF (register and index storage operation having an mat, and then the compress function is performed to convert extended opcode field and an additional register field) as that 60 the working format into the DFP format. The compress func format is defined in the IBM(R) Z/Architecture Principles of tion is described above; however, one example of an expand Operation. It includes, for instance: function is described below with reference to FIG. 10B. An operation code 1202a (e.g., bits 0-7), 1202b (e.g., bits Referring to FIG. 10B, initially, a DFP datum in DFP 40-47) designating the Shift Significand Left instruc format is obtained, STEP 1050. In this particular example, the tion. In this example, there are two possible operation 65 datum is the third operand of the Shift Significand Left codes: one for long decimal floating point operand, and instruction. The datum, which is in a DFP format and has a another for an extended decimal floating point operand. trailing significand in the densely packed decimal format, is US 8,051,118 B2 17 18 converted to a working format, which includes a trailing Another instruction that may be employed in the compo significand in the packed decimal format, STEP 1052, as sition of a DFP entity is the Add instruction. One example of described below. a format of an Add instruction 1300 is described with refer An expand function (F) converts the DPF format (p) to the ence to FIG. 13. In one example, instruction 1300 is a 32-bit working format (W). This can be shown symbolically as instruction in format RRR (non-destructive 3 register opera W=F(p). Expansion involves, for instance, eight steps, as tion) as that format is defined in the IBM(R) Z/Architecture follows: Principles of Operation. It includes, for instance: An operation code 1302 (e.g., bits 0-15) designating the 10 Add instruction. In this example, there are two possible operation codes: one for a long DFP format, and the other for an extended DFP format. A register field 1304 (e.g., R., bits 16-19) designating a floating point register or a floating point register pair, the 15 contents of which are a third operand. F includes four subfunctions F1, F2, F3, and F4. Subfunc A register field 1306 (e.g., R., bits 24-27) designating a tions F1, F2, and F3 use the combination field (a) to form the floating point register or a floating point register pair, the type field (T), the leftmost two bits of the biased exponent contents of which are a first operand. (E1), and the leftmost digit of the significand (D1). Subfunc A register field 1308 (e.g., R., bits 28-31) designating a tion F4 converts the contents of the encoded trailing signifi floating point register or a floating point register pair, the cand field (c) to the remaining digits of the significand (D2). contents of which are a second operand. Each 10-bit DPD value in (c) is converted to a 3-digit BCD number, as described below and in “A Summary of Densely During execution of the Add instruction, the third operand Packed Decimal Encoding. Mike Cowlishaw, Jul. 16, 2005, 25 is added to the second operand, and the Sum is placed at the www2.hursley.ibm.com/decimal/DPDecimal.html, and first operand location. “Densely Packed Decimal Encoding.” Mike Cowlishaw, The second and third operands in the DFP format are IEEE Proceedings Computers and Digital Techniques, converted to the working format using the expand function. ISSN 1350-2387, Vol. 149, No. 3, pp. 102-104, IEEE, May The Add operation is performed on data in the working for 2002. 30 mat. The result in the working format is converted to the DFP The conversion from a 10-bit DPD to a 3-digit BCD num ber can be performed through the following Boolean opera format using the compress function. tions. If both operands are finite numbers, they are added alge braically, forming an intermediate sum. The intermediate 35 Sum, if nonzero, is rounded to the operand according to the current DFP rounding mode (described below). The sum is then placed at the result location. The sign of the sum is determined by the rules of algebra. This also applies to a result of Zero: 40 hu If the result of rounding a nonzero intermediate Sum is Zero, the sign of the Zero result is the sign of the inter mediate Sum. If the Sum of two operands with opposite signs is exactly my 45 Zero, the sign of the result is plus in all rounding modes Alternatively, the following table can be used to perform except round toward -oo, in which mode the sign is the conversion. A combination of five bits in the DPD encod minus. ing (leftmost column) are used to specify conversion to the The sign of the sum X plus X is the sign of X, even when X 3-digit BCD encoding. Dashes (-) in the table are don't cares, is Zero. and can be either one or Zero. 50 If one operand is an infinity and the other is a finite number, the result is an infinity with the sign of the source infinity. If both operands are infinities of the same sign, the result is an WXWSt abcd efgh ikm infinity with the same sign. If the two operands are infinities 0---- Opqr Ostu Owxy 55 of opposite signs, an IEEE invalid operation condition is 100-- Opqr Ostu 10Oy recognized. 101-- Opqr 1OOu Osty 110-- 10Or Ostu Opdy When the delivered value is exact, the preferred quantum is 11100 10Or 1OOu Opdy the smaller quantum of the two source operands. When the 11101 10Or Opdu 10Oy delivered value is inexact, the preferred quantum is the Small 11110 Opqr 1OOu 10Oy 60 11111 10Or 1OOu 10Oy est quantum. The result placed at the first operand location is canonical. After converting the DFP format to the working format, the When the opcode of the Add instruction indicates an shift is performed by shifting the digits of the significand in extended DFP, the R fields designate valid floating point the working format (packed decimal), and then compress is 65 register pairs. performed to convert the working format back to the DFP One example of the results for the Add instruction are format. summarized in the below table. US 8,051,118 B2 19 20

Second operand Results for ADD (b + c) when Third Operand (c) is (b) is -Ox -Nn -Dn -O +O +Dn +Nn --ca QNaN SNaN T(-o), Xi: T(c), Xi: cc.1 T(dNaN), cc3 T(c), -Nn T(-o), R(b+c), R(b+c), T(b), T(b), R(b+c), R(b+c), T(+o), T(c), Xi: CC CC CC cc1 cc1 cc1 CCS cc.2 cc3 T(c), -Dn T(-o), R(b+c), R(b+c), R(b), R(b), R(b+c), R(b+c), T(+o), T(c), Xi: CC CC CC cc1 cc1 CCS cc.2 cc.2 cc3 T(c), -O T(-o), T(c), R(c), T(-0), Rezd, R(c), T(c), T(+o), T(c), Xi: CC CC CC ccO ccO cc.2 cc.2 cc.2 cc3 T(c), +O T(-o), T(c), R(c), Rezd, T(+0), R(c), T(c), T(+o), T(c), Xi: CC CC CC ccO ccO cc.2 cc.2 cc.2 cc3 T(c), +Dn T(-o), R(b+c), R(b+c), R(b), R(b), R(b+c), R(b+c), T(+o), T(c), Xi: CC CC CCS cc.2 cc.2 cc.2 cc.2 cc.2 cc3 T(c), +Nn T(-o), R(b+c), R(b+c), T(b), T(b), R(b+c), R(b+c), T(+o), T(c), Xi: CC CCS cc.2 cc.2 cc.2 cc.2 cc.2 cc.2 cc3 T(c),

QNaN T(b), T(b), T(b), T(b), T(b), T(b), T(b), T(b), T(b), Xi: cc3 cc3 cc3 cc3 cc3 cc3 cc3 cc3 cc3 T(c),

SNaN X: Xi: Xi: Xi: Xi: Xi: Xi: Xi: Xi: Xi: T(b), T(b), T(b), T(b), T(b), T(b), T(b), T(b), T(b), T(b), cc3 cc3 cc3 cc3 cc3 cc3 Explanation: *The SNaN is converted to the corresponding QNaN before it is placed at the target operand location. ccn Condition code is set to n, ccrs Condition code is set according to the resultant sum, dNaN Default quiet NaN. A quiet NaN with a positive sign, zeros in the reserved field, and zeros in the trailing significand. NnNormal number, R(w) Rounding is performed on the value v. The result is canonical. RezdExact zero-difference result, Dn Subnormal number, T(x) The canonical resultx is placed at the target operand location, Xi: IEEE invalid operation exception. The results shown are produced only when FCP 0.0, is zero.

As examples, for CCRS, above, if the value of the result (r) 1. A permissible set does not include infinity. Infinity is is zero, then a condition code of Zero is set. Similarly, if r is handled as a special case. less than Zero, a condition code of 1 is set, and if r is greater 2. For target precision constrained rounding, the permis than Zero, a condition code of two is set. 45 sible set is considered to have an unbounded exponent The Add instruction refers to rounding mode. Thus, further range. details regarding DFP rounding and rounding mode are 3. For denormalization rounding, the permissible set is described below. limited to the values representable inaparticular format. Rounding takes an input value, and, using the effective If a member of the permissible set is equal in value to the rounding method, selects a value from the permissible set. 50 input value, then that member is selected; otherwise, two The input value, considered to be infinitely precise, may bean adjacent candidates with the same sign as the input value are operand of an instruction or the numeric output from an chosen from the permissible set. One candidate, called TZ arithmetic operation. The effective rounding method may be (toward Zero), is the member of the permissible set nearest to the current rounding method specified in a rounding mode 55 and Smaller in magnitude than the input value; the other field of a control register; or, for some instructions, an explicit candidate, called AZ (away from Zero), is the member of the rounding method is specified by a modifier field. permissible set nearest to and larger in magnitude than the For target precision constrained rounding and denormal input value. Which of the two candidates is selected depends ization rounding, the input is the precise intermediate value. on the rounding method. For functionally constrained rounding, the input is a source 60 The following are example rounding methods: operand. Round to nearest with ties to even: The candidate nearest to Rounding selects a value from the permissible set. A per the input value is selected. In case of a tie, the candidate missible set is a set of values, and not representations; thus, Selected is the one whose Voting digit has an even value. for DFP, the selection of a member from the cohort is consid Round toward 0: The candidate that is smaller in magni ered to be performed after rounding. A permissible set differs 65 tude is selected. from the values representable in a particular format in the Round toward +oo: The candidate that is algebraically following way: greater is selected. US 8,051,118 B2 21 22 Round toward -oo: The candidate that is algebraically less format. The result in the working format is converted to the is selected. DFP format using the compress function. Round to nearest with ties away from 0: The candidate When the delivered value is exact, the preferred quantum is nearest to the input value is selected. In case of a tie, the the smaller quantum of the two source operands. When the candidate selected is the one that is larger in magnitude. delivered value is inexact, the preferred quantum is the Small Round to nearest with ties toward 0: The candidate nearest est quantum. to the input value is selected. In case of a tie, the candi The result placed at the first operand location is canonical. date selected is the one that is Smaller in magnitude. When the opcode of the Subtract instruction indicates an Round away from 0: The candidate that is greater in mag extended DFP, the R fields designate valid floating point nitude is selected. 10 register pairs. Round to prepare for shorter precision: The candidate Yet another instruction used by the composition process is Selected is Smaller in magnitude, unless its voting digit an Insert Biased Exponent instruction. One example of a has a value of either 0 or 5; in that case, the candidate that format of an Insert Biased Exponent instruction 1500 is is greater in magnitude is selected. described with reference to FIG. 15. In one example, instruc Three rounding methods depend on a condition called a 15 tion 1500 is a 32-bit instruction in format RRF (register and “tie.” This condition exists when the two candidates are equi register operand having an extended opcode field and an distant from the input value. additional R or M field) as that format is defined in the IBM(R) Two rounding methods depend on the value of the Voting Z/Architecture Principles of Operation. It includes, for digit of each candidate. (Each “digit' is an integral value instance: between Zero and one less than the radix.) Thus, a DFP digit An operation code 1502 (e.g., bits 0-15) designating the is a value between Zero and nine. The Voting digit is the units Insert Biased Exponent instruction. In this example, digit of the significand when considered in the common there are two possible operation codes: one for a long rounding point view. DFP operand; and another for an extended DFP operand. Without changing the value of a floating point number, the A register field 1504 (e.g., R., bits 16-19) designating a significand may be viewed with the implied radix point in 25 floating point register or a floating point register pair, the different positions, provided a corresponding adjustment is contents of which are a third operand. made to the exponent. In the common rounding point view, an A register field 1506 (e.g., R., bits 24-27) designating a implied radix point (called the common rounding point) and floating point register or a floating point register pair, the an associated exponent are selected for the input value and the contents of which are a first operand. two candidates, TZ and AZ. The common rounding point is 30 A register field 1508 (e.g., R., bits 28-31) designating a selected to satisfy the following requirements: general register, the contents of which are a second 1. The input value and the two candidates all have the same operand. The second operand is a 64-bit signed binary exponent. integer. 2. The significand of TZ is equal to the significand of the During execution of the Insert Biased Exponent instruc input value truncated at the rounding point. 35 tion, a DFP operand is produced by combining the requested 3. The significand of AZ is one greater in magnitude than biased exponent with the sign bit and the significand of the the significand of TZ. DFP third operand, and the result is placed in the first operand Another instruction that may be employed in the compo location. sition of a DFP entity is a Subtract instruction. One example The Insert Biased Exponent instruction also uses the of a format of a Subtract instruction 1400 is described with 40 expand function, as well as the compress function, described reference to FIG. 14. In one example, instruction 1400 is a above. For instance, the expand function is used to convert the 32-bit instruction in format RRR as that format is defined in DFP format (of, e.g., the third operand) to the working for the IBM(R) Z/Architecture Principles of Operation. It includes, mat. The insert is then performed using the working format, for instance: and then the compress function is used to convert the working An operation code 1402 (e.g., bits 0-15) designating the 45 format back to the DFP format. In particular, as an example, Subtract instruction. In this example, there are two pos the working format includes a sign, a type, a biased exponent sible operation codes: one for long DFP. and one for and significand digits. The source biased exponent is exam extended DFP. ined to set the type of the working format and replace the A register field 1404 (e.g., R., bits 16-19) designating a biased exponent. The sign, the type, the new biased exponent floating point register or a floating point register pair, the 50 and the new significandare used by the compress function to contents of which are a third operand. create the result in the DFP format. A register field 1406 (e.g., R., bits 24-27) designating a The value of the requested biased exponent is a 64 bit floating point register or a floating point register pair, the signed binary integer and is located in the general register contents of which are a first operand. designated by R2. A register field 1408 (e.g., R., bits 28-31) designating a 55 When the value of the requested biased exponent is in the floating point register or a floating point register pair, the range between Zero and the maximum biased exponent, inclu contents of which are a second operand. sively, for the target format, the result is a finite number. The During execution of the Subtract instruction, the third biased exponent of the result is set to the value of the operand is subtracted from the second operand, and the dif requested biased exponent; the significand of the result is set ference is placed at the first operand location. The execution 60 to the significand of the third operand. If the third operand is of Subtract is identical to that of Add, except that the third an infinity or NaN, the significand of the third operand operand, if numerical, participates in the operation with its includes the digits of the trailing significand of the third sign bit inverted. When the third operand is a NaN, it partici operand padded with a Zero digit on the left. pates in the operation with its sign bit unchanged. When the value of the requested biased exponent is -1, the The second and third operands in the DFP format are 65 result is an infinity. The reserved field of the result is set to converted to the working format using the expand function. Zero; the trailing significand of the result is set to the trailing The Subtract operation is performed on data in the working significand of the third operand. US 8,051,118 B2 23 24 When the value of the requested biased exponent is equal to Further details regarding converting the significand of a -2, less than -3, or greater than the maximum biased expo DFP datum to packed decimal and the biased exponent of a nent for the target format, the result is a QNaN; when the DFP datum to binary integer are described with reference to value of the requested biased exponent is -3, the result is an FIG. 17. In particular, one embodiment of the logic associated SNaN. When a NaN is produced as the result, the reserved 5 with converting the significand and the biased exponent to a field of the result is set to Zero, and the trailing significand of signed packed decimal number and a binary integer, respec the result is set to the trailing significand of the third operand. tively, is described. The sign of the result is the same as the sign of the third Initially, the biased exponent is extracted and placed in a operand. general register, such as general register E. STEP 1700. This The preferred quantum is the quantum that corresponds to 10 extracted biased exponent is a 64-bit signed binary integer. In the requested biased exponent. If the delivered value is a finite one example, this extract function is performed using an number, it is represented with the preferred quantum. Extract Biased Exponent instruction, as described below. The result placed at the first operand location is canonical, Additionally, the lower 31 digits and sign of the significand except for infinity. When the result is an infinity, if all digits in 15 are converted into packed decimal and the result is stored into the trailing significand of the third operand are Zeros, then the a general register pair CD, STEP 1702. In one example, a result is a canonical infinity; otherwise, the result is an infinity Convert To Signed Packed instruction is used for this conver that has the reserved field set to zero, canonical declets in the Sion. encoded trailing significandfield, and some nonzero digits in Further, the significand stored in floating pair register 01 is the trailing significand. shifted 31 digits to the right, using a Shift Significand Right This operand is performed for any requested biased expo instruction, as an example, STEP 1704. nent and any third operand without causing an IEEE excep The remaining digits are converted using a Convert signed tion. Packed instruction and stored in general register pair AB, When the opcode of the Insert Biased Exponent instruction STEP 1706. The three digits of the contents of register pair indicates the extended DFP, the R and R fields designate 25 AB and the 31 digits plus the sign of register pair CD are valid floating point register pairs. stored in storage, STEP1708. In one example, the three digits One example of a summary of the results for this instruc of general register pair AB and the 31 digits plus sign of tion are depicted in the below table. general register CD are concatenated in storage. Additionally, the contents of general register E are stored in storage, STEP 30 1710. Results' for INSERT BIASED In the previous example, the intermediate form includes a EXPONENT when third operand (c) is signed significand in the signed packed decimal format. Two Value (b) in second examples are now given where the intermediate form includes operand F ce QNaN SNaN an unsigned significand in the unsigned packed decimal for 35 b > MBE T(QNaN) T(QNaN) T(QNaN) T(QNaN) mat along with a separate bit for the sign. In these examples, MBE se be O T(F) T(F2) T(F2) T(F2) the significand and the sign of a decimal floating point num b = -1 N(o) N(o) N(o) N(o) ber are converted separately. As in the previous example, the b = -2 T(QNaN) T(QNaN) T(QNaN) T(QNaN) intermediate form also includes a 64-bit biased exponent in b = -3 T(SNaN) T(SNaN) T(SNaN) T(SNaN) B s-4 T(QNaN) T(QNaN) T(QNaN) T(QNaN) the binary integerformat. In both examples, the significandin 40 the decimal floating point format is first converted to an Explanation: unsigned packed decimal number. The sign of the result is the same as the sign of the third operand. 'The leftmost digit of the significandis zero, As in the previous example, the Extract Biased Exponent FAll infinite numbers, including zeros, instruction is then used to extract the 64-bit biased exponent MBE Maximum biased exponent for the target format, from the DFP format and place it in the intermediate form. N(oo) The result is a canonical infinity if all digits in the trailing significand of the third 45 operand are zeros; otherwise, the resultant infinity has the reserved field set to zero, canoni Also, in both examples, the sign bit in the intermediate form cal declets in the encoded trailing-significandfield, and some nonzero digits in the trailing is set to indicate the sign of the original number in the DFP significand. format. T(x) The canonical resultx is placed at the target operand location, In the first example, the 34-digit significand of a decimal Described in detail above is a capability for composing a floating point number in the DFP extended format is con decimal floating point datum. In accordance with another 50 Verted to an unsigned packed decimal number using the Con aspect of the present invention, a capability is provided for vert signed Packed and Shift Significand Right instructions. decomposing a decimal floating point datum. The Convert To Signed Packed instruction is not needed. One embodiment of an overview of the logic associated In the second example, the 16-digit significand of a deci with exporting a decimal floating point datum is described mal floating point number in the DFPlong format is converted with reference to FIG. 16. In this particular example, the 55 to an unsigned packed decimal number by a single execution exported datum is a non-decimal floating point format. Such of the Convert signed Packed instruction. The Convert To as a human readable format. Signed Packed and Shift Significand Right instructions are Referring to FIG. 16, in one embodiment, a decimal float not needed. ing point datum in a DFP format is obtained by a processor of In other examples, the decomposition can be to other types a processing environment, STEP 1600. The data is converted 60 of non-decimal floating point formats. from its decimal floating point format to an intermediate In the above logic for decomposing a decimal floating point form, such as packed decimal for the significand and binary datum, a number of instructions are employed. These instruc integerfor the biased exponent, STEP 1602. The intermediate tions can be implemented in many architectures and may be result is then converted to a human readable format, such as a emulated. As examples, the instructions are executed inhard decimal numerical value, STEP 1604. Techniques to convert 65 ware by a processor, by Software executed on a processor from packed decimal and binary integer to human-readable having a native instruction set; or by emulation of a non format are known in the art. native instruction set that includes the instruction. In one US 8,051,118 B2 25 26 particular example, the instructions are implemented in the An operation code 1902 (e.g., bits 0-15) designating the Z/Architecture(R) offered by International Business Machines Convert To Signed Packed instruction. In this example, Corporation, Armonk, N.Y. there are two possible operation codes: one for a 64-bit One instruction used by the decomposition process is an signed packed decimal result, long DFP source; and Extract Biased Exponent instruction. One example of a for another for a 128-bit signed packed decimal result, mat of an Extract Biased Exponent instruction 1800 is extended DFPSource. described with reference to FIG. 18. In one example, instruc A field 1904 (e.g., M., bits 20-23) used during processing tion 1800 is a 32-bit instruction in format RRE (register and of this instruction, as described below. register operation having an extended opcode field) as that A register field 1906 (e.g., R., bits 24-27) designating a format is defined in the IBM(R) Z/Architecture Principles of 10 general register or a general register pair, the contents of Operation. It includes, for instance: which are a first operand used by the instruction. An operation code 1802 (e.g., bits 0-15) designating the A register field 1908 (e.g., R., bits 28-31) designating a Extract Biased Exponent instruction. In this example, floating point register or a floating point register pair, the there are two possible operation codes: one for a long contents of which are a second operand used by the DFP source, 64-bit binary integer result; and another for 15 instruction. a 64-bit binary integer result, extended DFP source. During execution of the Convert To Signed Packed instruc A register field 1804 (e.g., R., bits 24-27) designating a tion, the expand function described above is used. In particu general register, the contents of which are a first oper lar, the expand function converts the source operands in the and. DFP format to the working format and the conversion is A register field 1806 (e.g., R., bits 28-31) designating a performed on this working format. floating point register or a floating point register pair, the When the opcode of the Convert To Signed Packed instruc contents of which are a second operand. tion indicates a long DFP operand, the rightmost 15 signifi During execution of the Extract Biased Exponent instruc cand digits and the signed bit of the DFP second operand are tion, the biased exponent of the DFP second operand is placed converted to a 64-bit result (154-bit decimal digits and a 4-bit at the first operand location. In particular, when the second 25 sign) in the signed packed decimal format. operand is a finite number, the biased exponent of the second When the opcode indicates an extended DFP operand, the operand is placed into the first operand location. When the rightmost 31 digits in the trailing significand and the sign bit second operand is an infinity, QNaN, or SNaN, a special code of the second operand are converted to a 128-bit result (31 is placed into the first operand location. 4-bit decimal digits and a 4-bit sign). The Extract Biased Exponent instruction uses the expand 30 The sign of the result is the sign of the second operand. function described above during execution. For instance, the Bit 3 of the Mafield (M3) is the + sign code selection bit. expand function is used to convert the DFP format (of, e.g., When M3 is zero, the plus sign is encoded as 1100; when the the second operand) to the working format, and then the bit is one, the plus sign is encoded as 1111. Bits 0-2 are extraction is performed using the working format. In particu ignored. lar, as an example, the type of the working format is examined 35 The result is a signed packed decimal number that is placed and the extract function is performed according to the type. If in the general register or general register pair designed by R. it is a finite number, the bias exponent is extracted as a binary For an extended DFP source instruction, the R field des integer result. If it is an infinity or NaN, the extract returns a ignates a valid floating point register pair. Also, the R field special code depending on the type (a.k.a., data class). designates an even/odd pair of general registers in which the This operation is performed for any second operand with 40 even number register is designated. out causing an IEEE exception. Another instruction used during the decomposition of a When the opcode of the Extract Biased Exponent instruc DFP entity is a Shift Significand Right instruction (see, e.g., tion indicates the extended DFP operand, the R field desig STEP 1704, FIG. 17). One example of a format of the Shift nates a valid floating point register pair. Significand Right instruction 2000 is described with refer The result is a 64-bit signed binary integer that is placed in 45 ence to FIG. 20. In one example, instruction 2000 is a 48-bit the general register designated by R. One example of a instruction in format RXF (register and index storage opera summary of the results for this instruction are depicted in the tion having an extended opcode field and an additional reg below table. ister field) as that format is defined in the IBM(R) Z/Architec ture Principles of Operation. It includes, for instance: 50 An operation code 2002a (e.g., bits 0-7), 2002b (e.g., bits 40-47) designating the Shift Significand Right instruc Second-operand data class First-operand value tion. In this example, there are two possible operation codes: one for long decimal floating point operand, and Finite number e Infinity -1 another for an extended decimal floating point operand. QNaN -2 55 A register field 2004 (e.g., R., bits 8-11) designating a SNaN -3 floating point register or a floating point register pair, the Explanation: contents of which area third operand used by the instruc e Biased exponent tion. An index field 2006 (e.g., X, bits 12-15) designating a Another instruction used is the Convert To Signed Packed 60 general register having, for instance, a 64-bit number. instruction. One example of a format of the Convert To A base field 2008 (e.g., B, bits 16-19) designating agen Signed Packed instruction 1900 is described with reference to eral register having, for instance, a 64-bit number. FIG. 19. In one example, instruction 1900 is a 32 bit instruc A displacement value 2010 having, for instance, a 12-bit tion in format RRF (register and register operation having an number. extended opcode and an addition R or M field) as that format 65 The contents of the general registers specified in fields is defined in the IBM(R) Z/Architecture Principles of Opera 2006 and 2008, if any, are added to the contents of tion. It includes, for instance: displacement value 2010 to form a second operand US 8,051,118 B2 27 28 address. The second operand address is not used to During execution of the convert to unsigned packed address data; instead, its rightmost six bits indicate the instruction, the expand function is used in which the DFP number of digits to be shifted. The remainder of the format is converted to a working format and the working address is ignored. format is used during execution of the instruction. A register field 2012 (e.g., R., bits 32-35) designating 5 When the opcode of the Convert signed Packed instruction another floating point register or floating point register indicates a long DFP source, 16 significand digits of the pair used by the instruction, the contents of which are a second operand are converted to a 64-bit result (16 4-bit first operand used by the instruction. decimal digits). (If the second operand is an infinity or NaN, During operation, the significand of the third operand is the 15 digits in the trailing significandare padded with a Zero shifted right the number of digits specified by the second 10 digit on the left to form 16 significand digits.) operand address, and the result is placed at the first operand When the opcode indicates an extended DFP source, the location. rightmost 32 digits in the trailing significand of the second To perform the Shift, in one example, an expand function is operand are converted to a 128-bit result (32 4-bit decimal used to convert the format of the DFP value being shifted to a digits). working format. The shift is performed on the working for 15 The result is an unsigned packed decimal number that is mat, and then the compress function is performed to convert placed in the general register or general register pair desig the working format into the DFP format. nated by R. Digits shifted out of the rightmost digit are lost. Zeros are This operation is performed for any second operand, supplied to the vacated positions on the left. The sign of the including an infinity QNaN, or SNaN, without causing an result is the same as the sign of the third operand. IEEE exception. For a finite number, all digits in the significand participate When the operand indicates an extended DFP operand, the in the shift and the result is a finite number with the same R field designates a valid floating point register pair. Also, biased exponent as the third operand and the shifted signifi the R field designates an even/odd pair of general registers in cand. For an infinity, all digits in the trailing significand which the even number register is designated. participate in the shift, and the result is an infinity with the 25 In one embodiment, each instruction is executed by a pro shifted trailing significand and a zero in the reserved field of cessor of a processing environment. One embodiment of a the format. For a QNaN or SNaN, all digits in the trailing processing environment to incorporate and use one or more significand participate in the shift and the result is a QNaN or aspects of the present invention is described with reference to SNaN, respectively, with the shifted trailing significandanda FIG.22. Processing environment 2200 includes, for instance, Zero in the reserved field of the format. 30 a Z/Architecture R processor 2202 (e.g., a central processing The preferred quantum is the quantum of the third operand. unit (CPU)), a memory 2204 (e.g., main memory), and one or If the delivered value is a finite number, it is represented with more input/output (I/O) devices 2206 coupled to one another the preferred quantum. via, for example, one or more buses 2208 and/or other con The result placed at the first operand location is canonical, nections. except for infinity. When the result is an infinity, if all digits in 35 In the example shown, Z/Architecture(R) processor 2202 is a the trailing significand of the result are Zeros, then the result part of a System ZTM server, offered by International Business is canonical; otherwise, the result is an infinity that has the Machines Corporation (IBM(R), Armonk, N.Y. System ZTMm reserved field set to Zero, canonical declets in the encoded servers implement IBM's Z/Architecture(R), which specifies trailing significand field, and some nonzero digits in the trail the logical structure and functional operation of the computer. ing significand. 40 The System ZTM server executes an operating system, such as This operation is performed for any second operand, Z/OSR), also offered by International Business Machines Cor including an infinity, QNaN, or SNaN, without causing an poration. IBM(R), Z/Architecture(R) and Z/OS(R) are registered IEEE exception. trademarks of International Business Machines Corporation, When the opcode of the Shift Significand Right instruction Armonk, N.Y., USA. Other names used herein may be regis indicates an extended DFP operation, the R and R fields 45 tered trademarks, trademarks or product names of Interna designate valid floating point register pairs. tional Business Machines Corporation or other companies. Another instruction used to convert the DFP value to a In another embodiment, the instruction and/or the logic of BCD value (see, e.g., STEP 1706, FIG. 17) is the Convert the instruction can be executed in a processing environment signed Packed instruction 2100, which is described with ref that is based on one architecture (which may be referred to as erence to FIG. 21. In one example, instruction 2100 is a 32-bit 50 a “native' architecture), but emulates another architecture instruction in format RRE (register and register operation (which may be referred to as a "guest' architecture). In such having an extended opcode) as that format is defined in the an environment, for example, the instructions and/or logic IBM(R) Z/Architecture Principles of Operation. It includes, for thereof, which is specified in the Z/Architecture(R) and instance: designed to execute on a Z/Architecture R machine, is emu An operation code 2102 (e.g., bits 0-15) designating the 55 lated to execute on an architecture other than the Z/Architec Convert signed Packed instruction. In this example, ture R. One example of this processing environment is there are two possible operation codes: one for a 64-bit described with reference to FIGS. 23-24. unsigned packed decimal result, long DFPSource; and Referring to FIG. 23, one embodiment of a processing another for a 128-bit unsigned packed decimal result, environment to incorporate and use one or more aspects of the extended DFPSource. 60 present invention is described. Processing environment 2300 A register field 2104 (e.g., R., bits 24-27) designating a includes, for instance, a native central processing unit 2302, a general register or a general registerpair, the contents of memory 2304 (e.g., main memory) and one or more input/ which are a first operand used by the instruction. output (I/O) devices 2306 coupled to one another via, for A register field 2106 (e.g., R., bits 28-31) designating a example, one or more buses 2308 and/or other connections. floating point register or floating point register pair, the 65 As examples, processing environment 2300 may include a contents of which are a second operand used by the Power PC(R) processor, a pSeries(R server, or an xSeries(R) instruction. server offered by International Business Machines Corpora US 8,051,118 B2 29 30 tion, Armonk, N.Y.; an HP Superdome with Intel(R) Itanium(R) native instructions 2409, and emulation code 2312 may reside 2 processors offered by Hewlett-Packard Company, Palo in the same memory or may be dispersed among different Alto, Calif.; and/or other machines based on architectures memory devices. offered by IBM(R), Hewlett-Packard, Intel(R), Sun Microsys In one example, a guest instruction 2402 that is obtained, tems or others. Power PC(R), pSeries(R) and xSeries(R) are reg translated and executed is one of the instructions described istered trademarks of International Business Machines Cor herein. The instruction, which is a Z/Architecture R instruc poration, Armonk, N.Y., U.S.A. Intel(R) and Itanium(R, 2 are tion in this example, is fetched from memory, translated and registered trademarks of Intel Corporation, Santa Clara, represented as a sequence of native instructions 2409 (e.g., Calif. Power PCR, pSeries(R, xSeries(R, Intel(R), etc.) which are 10 executed. Native central processing unit 2302 includes one or more In another embodiment, one or more of the instructions are native registers 2310. Such as one or more general purpose executed in another architecture environment including, for registers and/or one or more special purpose registers, used example, an architecture as described in the “INTEL(R) 64 and during processing within the environment. These registers IA-32 Architectures Software Developer's Manual Volume include information that represent the state of the environ 15 1 Order Number 253665-022US, November 2006; ment at any particular point in time. “INTEL(R) 64 and IA-32 Architectures Software Developer's Moreover, native central processing unit 2302 executes Manual Volume 2A. Order Number 253666-022US, instructions and code that are stored in memory 2304. In one November 2006; the “INTEL(R) Itanium(R Architecture Soft particular example, the central processing unit executes emu ware Developer's Manual Volume 1.” Doc. No. 245317-005, lator code 2312 stored in memory 2304. This code enables the January 2006; the “INTEL(R) Itanium(R Architecture Soft processing environment configured in one architecture to ware Developer's Manual Volume 2. Doc. No. 245318-005, emulate another architecture. For instance, emulator code January 2006; and/or the “INTEL(R) Itanium(R Architecture 2312 allows machines based on architectures other than the Software Developer's Manual Volume 3.” Doc. No. 245319 Z/Architecture(R), such as Power PC(R) processors, pSeries(R) 005, January 2006; each of which is hereby incorporated servers, xSeries(R servers, HP Superdome(R) servers, or others 25 herein by reference in its entirety. to emulate the Z/Architecture(R) and to execute software and In yet a further embodiment, a data processing system instructions developed based on the Z/Architecture(R). Suitable for storing and/or executing program code is usable Further details relating to emulator code 2312 are that includes at least one processor coupled directly or indi described with reference to FIG. 24. Guest instructions 2402 rectly to memory elements through a system bus. The 30 memory elements include, for instance, local memory comprise Software instructions (e.g., machine instructions) employed during actual execution of the program code, bulk that were developed to be executed in an architecture other storage, and cache memory which provide temporary storage than that of native CPU2302. For example, guest instructions of at least some program code in order to reduce the number 2402 may have been designed to execute on Z/Architecture(R) of times code must be retrieved from bulk storage during processor 2202, but are instead being emulated on native CPU 35 execution. 2302 (which may be for example an Intel(R) Itanium(R, 2 pro Input/Output or I/O devices (including, but not limited to, cessor). In one example, emulator code 2312 includes an keyboards, displays, pointing devices, DASD, tape, CDs, instruction fetching routine 2400 to obtain one or more guest DVDs, thumb drives and other memory media, etc.) can be instructions 2402 from memory 2304, and to optionally pro coupled to the system either directly or through intervening vide local buffering for the instruction obtained. It also 40 I/O controllers. Network adapters may also be coupled to the includes an instruction translation routine 2404 to determine system to enable the data processing system to become the type of guest instruction that has been obtained and to coupled to other data processing systems or remote printers or translate the guest instruction into one or more corresponding storage devices through intervening private or public net native instructions 2409. This translation includes, for works. Modems, cable modems, and Ethernet cards are just a instance, identifying the function to be performed by the 45 few of the available types of network adapters. guest instruction and choosing the native instructions to per One or more aspects of the present invention can be form that function. included in an article of manufacture (e.g., one or more com Further, emulator 2312 includes an emulation control rou puter program products) having, for instance, computer tine 2406 to cause the native instructions to be executed. usable media. The media has therein, for instance, computer Emulation control routine 2406 may cause native CPU 23.02 50 readable program code means or logic (e.g., instructions, to execute a routine of native instructions that emulate one or code, commands, etc.) to provide and facilitate the capabili more previously obtained guest instructions and, at the con ties of the present invention. The article of manufacture can be clusion of Such execution, to return control to the instruction included as a part of a system (e.g., computer system) or sold fetch routine to emulate the obtaining of the next guest separately. instruction or group of guest instructions. Execution of the 55 One example of an article of manufacture or a computer native instructions 2409 may include loading data into a reg program product incorporating one or more aspects of the ister from memory 2304; storing data back to memory from a present invention is described with reference to FIG. 25. A register, or performing some type of arithmetic or logical computer program product 2500 includes, for instance, one or operation, as determined by the translation routine. more computerusable media 2502 to store computer readable Each routine is, for instance, implemented in Software, 60 program code means or logic 2504 thereon to provide and which is stored in memory and executed by the native central facilitate one or more aspects of the present invention. The processing unit 2302. In other examples, one or more of the medium can be an electronic, magnetic, optical, electromag routines or operations are implemented in firmware, hard netic, infrared, or semiconductor system (or apparatus or ware, software or some combination thereof. The registers of device) or a propagation medium. Examples of a computer the emulated guest processor may be emulated using the 65 readable medium include a semiconductor or Solid State registers 2310 of the native CPU or by using locations in memory, magnetic tape, a removable computer diskette, a memory 2304. In embodiments, the guest instructions 2402. random access memory (RAM), a read-only memory (ROM), US 8,051,118 B2 31 32 a rigid magnetic disk and an optical disk. Examples of optical program of instructions executable by the machine to perform disks include compact disk-read only memory (CD-ROM), the capabilities of the present invention can be provided. compact disk-read/write (CD-R/W) and DVD. The flow diagrams depicted herein are just examples. A sequence of program instructions or a logical assembly There may be many variations to these diagrams or the steps of one or more interrelated modules defined by one or more (or operations) described therein without departing from the computer readable program code means or logic direct the spirit of the invention. For instance, the steps may be per performance of one or more aspects of the present invention. formed in a differing order, or steps may be added, deleted, or Although one or more examples have been provided modified. All of these variations are considered a part of the herein, these are only examples. Many variations are possible claimed invention. 10 Although embodiments have been depicted and described without departing from the spirit of the present invention. For in detail herein, it will be apparent to those skilled in the instance, processing environments other than the examples relevant art that various modifications, additions, Substitu provided herein may include and/or benefit from one or more tions and the like can be made without departing from the aspects of the present invention. As an example, a processor spirit of the invention, these are, therefore, considered to be can be other than an IBM System ZTM processor and can 15 within the scope of the invention as defined in the claims. execute an operating system other than Z/OSR). Further, the environment need not be based on the Z/Architecture(R), but What is claimed is: instead can be based on other architectures offered by, for 1. A computer program product for composing a decimal instance, IBM(R), Intel(R), Sun Microsystems, as well as others. floating point datum, said computer program product com Yet further, the environment can include multiple processors, prising: be partitioned, and/or be coupled to other systems, as a non-transitory computer readable medium readable by a examples. processor and storing instructions for execution by the Additionally, one or more of the instructions can include process for performing a method comprising: other registers or entities other than registers to designate obtaining a significandofa datum in a first format and an information. Further, although examples of registers are 25 exponent of the datum in a second format; described above, each of the registers may include more, less converting the significand in the first format to the sig or different information. Further, each may include additional nificand in a decimal floating point format; data not necessarily needed in one or more aspects of the converting the exponent in the second format to a biased present invention. Specific location within the registers for exponent; and the information is implementation and/or architecture depen 30 combining the significand in the decimal floating point dent. Yet further, different data and/or positioning within the format and the biased exponent to create the datum in registers and/or entities are possible. the decimal floating point format. Still further, one or more aspects of the present invention 2. The computer program product of claim 1, wherein the can be usable with other floating point Systems, including first format comprises a packed decimal format, the second variations on the decimal floating point described herein. 35 format comprises a signed binary integer and the biased expo Further, the formats of decimal floating point numbers, as nent comprises an unsigned binary integer format. well as properties and any other characteristics, including but 3. The computer program product of claim 1, wherein the not limited to, the contents of the data formats may be differ method further comprises providing a sign for the datum. ent than described herein. A decimal floating point number 4. The computer program product of claim 1, wherein an can be defined as having more, less or different components 40 encoding of the datum in decimal floating point format com than described herein; definitions can vary; and/or there can prises including a sign of the datum in a sign field, a leftmost be more, less or different formats. digit of the significand, two leftmost bits of the biased expo Moreover, one or more aspects of the present invention also nent and the remaining bits of the biased exponent in a com apply to implementations using BID (Binary Encoded Deci bination field, and the remaining digits of the significandinan mal Floating Point data) encoding, as well as other encoding. 45 encoded trailing significand field. In an embodiment wherein the significand is Binary 5. The computer program product of claim 4, wherein the Encoded Decimal (BID) format rather than DPD, the BID sign field is bit 0 of the decimal floating point format, the significand is decoded to a decimal value, such as packed combination field is bits 1-11, bits 1-13 orbits 1-17 depend decimal, for example, such that each decimal digit is repre ing on a length of the data format, and the encoded trailing sented by a distinct 4 bit value. The decimal value is operated 50 significand is bits 12-31, bits 14-63 or bits 18-127 depending on according to the function required and the result is re on the length of the data format. encoded into the BID format, thereby the BID significand is 6. The computer program product of claim 1, wherein operated on as a decimal number rather than a binary number. converting the significand comprises: In one example, the function required is a shift operation on loading a number of most significant digits of the signifi the significand. The shift operation is performed on the deci 55 cand in a first register pair; mal number such that the value of the decimal number is loading the remaining least significant digits of the signifi shifted by a predetermined number of decimal digit positions. cand in a second register pair; The shifted value is then encoded into BID format and saved converting contents of the first registerpair into the decimal as a result operand. floating point format, and storing the converted contents As used herein, the term “obtaining as in, for instance, 60 in a first floating point register pair; “obtaining an instruction' includes, but is not limited to, converting contents of the second register pair into the fetching, receiving, having, providing, being provided, creat decimal floating point format, and storing the converted ing, developing, etc. contents in a second floating point register pair; The capabilities of one or more aspects of the present shifting the contents of the first floating point register pair invention can be implemented in Software, firmware, hard 65 a selected number of digits to the left to align it for ware, or Some combination thereof. At least one program operations with the second floating point register pair, storage device readable by a machine embodying at least one determining a sign of the significand; US 8,051,118 B2 33 34 Subtracting contents of the first floating point register pair the remaining bits of the biased exponent in a combination from the contents of the second floating point register field, and the remaining digits of the significandinan encoded pair and storing the result in the first floating point reg trailing significand field. ister pair, in response to the determining indicating a 19. The computer system of claim 18, wherein the sign negative sign; and field is bit 0 of the decimal floating point format, the combi nation field is bits 1-11, bits 1-13 orbits 1-17 depending on a adding contents of the first floating point register pair and length of the data format, and the encoded trailing significand the second floating point register pair and storing the is bits 12-31, bits 14-63 or bits 18-127 depending on the result in the first floating point register pair, in response length of the data format. to the determining indicating a positive sign. 20. The computer system of claim 15, wherein converting 7. The computer program product of claim 6, wherein the 10 the significand comprises: combining comprises combining the biased exponent with loading a number of most significant digits of the signifi the result stored in the first floating point register pair to create cand in a first register pair; the datum in decimal floating point format. loading the remaining least significant digits of the signifi 8. The computer program product of claim 7, wherein the cand in a second register pair; combining comprises employing an insert biased exponent 15 converting contents of the first registerpair into the decimal instruction to perform the combining. floating point format, and storing the converted contents 9. The computer program product of claim 6, wherein the in a first floating point register pair; converting contents of the first register pair comprises using a converting contents of the second register pair into the decimal floating point format, and storing the converted convert from 7 packed instruction to perform the converting. contents in a second floating point register pair; 10. The computer program product of claim 6, wherein the shifting the contents of the first floating point register pair converting contents of the second register pair comprises a selected number of digits to the left to align it for employing a convert from signed packed instruction to per operations with the second floating point register pair, form the converting. determining a sign of the significand; 11. The computer program product of claim 6, wherein the 25 Subtracting contents of the first floating point register pair shifting comprises employing a shift left instruction to per from the contents of the second floating point register form the shifting. pair and storing the result in the first floating point reg 12. The computer program product of claim 6, wherein the ister pair, in response to the determining indicating a Subtracting comprises employing a Subtract instruction to negative sign; and perform the Subtracting. 30 adding contents of the first floating point register pair and 13. The computer program product of claim 6, wherein the the second floating point register pair and storing the adding comprises employing an add instruction to perform result in the first floating point register pair, in response the adding. to the determining indicating a positive sign. 14. The computer program product of claim 1, wherein the 21. The computer system of claim 20, wherein the com combining comprises employing an insert biased instruction 35 bining comprises combining the biased exponent with the to combine the significand with the biased exponent to create result stored in the first floating point registerpair to create the the datum in the decimal floating point format. datum in decimal floating point format. 15. A computer system to compose a decimal floating point 22. The computer system of claim 21, wherein the com datum, said computer system comprising: bining comprises employing an insert biased exponent a memory; and 40 instruction to perform the combining. a processor in communications with the memory, wherein 23. The computer system of claim 20, wherein the convert the computer system is configured to perform a method, ing contents of the first register pair comprises using a convert the method comprising: from unsigned packed instruction to perform the converting. obtaining a significandofa datum in a first format and an 24. The computer system of claim 20, wherein the convert exponent of the datum in a second format; 45 ing contents of the second register pair comprises employing converting the significand in the first format to the sig a convert from signed packed instruction to perform the con nificand in a decimal floating point format; Verting. converting the exponent in the second format to a biased 25. The computer system of claim 20, wherein the shifting exponent; and comprises employing a shift left instruction to perform the combining the significand in the decimal floating point 50 shifting. format and the biased exponent to create the datum in 26. The computer system of claim 20, wherein the subtract the decimal floating point format. ing comprises employing a subtract instruction to perform the 16. The computer system of claim 15, wherein the first Subtracting. format comprises a packed decimal format, the second format 27. The computer system of claim 20, wherein the adding comprises a signed binary integer and the biased exponent 55 comprises employing an add instruction to perform the add comprises an unsigned binary integer format. ing. 17. The computer system of claim 15, wherein the method 28. The computer system of claim 15, wherein the com further comprises providing a sign for the datum. bining comprises employing an insert biased instruction to 18. The computer system of claim 15, wherein an encoding combine the significand with the biased exponent to create the of the datum in decimal floating point format comprises 60 including a sign of the datum in a sign field, a leftmost digit of datum in the decimal floating point format. the significand, two leftmost bits of the biased exponent and k k k k k