United States Patent (19) 11 Patent Number: 4,912,345 Steele et al. 45 Date of Patent: Mar. 27, 1990 (54) PROGRAMMABLE SUMMING FUNCTIONS Assistant Examiner-Margaret Rose Wambach FOR PROGRAMMABLE LOGIC DEVICES Attorney, Agent, or Firm-Richard K. Robinson; 75 Inventors: Randy C. Steele; Safoin A. Raad, both Kenneth C. Hill of Scottsdale, Ariz. 57 ABSTRACT 73 Assignee: SGS-Thomson Microelectronics, Inc., A programmable logic device includes a programmable Carrollton, Tex. logic array and an output logic macrocell. The output logic macrocell includes a user configurable summing 21 Appl. No.: 291,711 function that has a first logic gate connected to receive 22 Filed: Dec. 29, 1988 a first plurality of product terms, a second logic gate connected to receive a second plurality of product 51 Int. Cl."...... H03K 19/173; H03K 19/094 terms and a third logic gate connected to receive the 52 U.S. C...... 307/465; 307/468; combination of the first plurality of product terms and a 307/471 controls signal, a fourth logic gate connected to receive 58 Field of Search ...... 307/443, 448, 451, 471, the combination of the second plurality of Product 307/465, 468-469 Terms and the control signal and a logic circuit con (56) References Cited nected to receive the output signals from the first, sec ond, third and fourth logic gates and to provide a first U.S. PATENT DOCUMENTS logical combination when the control signal is at a first 4,558,236 12/1985 Burrows ...... 307/.465 logic state and a second logical combination when the 4,609,838 9/1986 Huang ...... 307/471 controls signal is at a second logic state. 4,612,459 9/1986 Pollachek ...... 307/471 Primary Examiner-Stanley D. Miller 11 Claims, 5 Drawing Sheets

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52 64 46 4,912,345 1. 2 receive a plurality of product terms, the third and PROGRAMMABLE SUMMING FUNCTIONS FOR fourth logic gates are additionally NOR gates and the PROGRAMMABLE LOGIC DEVICES logic circuit is an exclusive Field Effect Transistor OR circuit. In this embodiment when the control signal is at BACKGROUND OF THE ENVENTION 5 a logic 1 an OR summing function is performed and This invention relates to programmable logic devices when the control signal is at a logic 0 an exclusive OR and in particular to programmable logic devices con summing function is performed. taining a summing function and still more particular to These and other advantages and features will be more programmable logic devices in which the summing apparent from a reading of the specification in combina function may be user configurable. O tion with the figures in which: Programmable logic devices are user configurable integrated circuits. These devices contain a set of un BRIEF DESCRIPTION OF THE FIGURES dedicated inputs, a set of undedicated outputs and a FIG. 1 is a schematic diagram of a programmable programmable array which permits the logic connec logic device according to the invention; tion of these inputs to a given output. The most com 15 FIG. 2 is a schematic diagram of an output logic mon implementation of this logic connection is a sum of macrocell of FIG. 1; products using an OR summing function, that is, with FIG. 3 is a schematic diagram of a user configurable inputs A,B,C, and D, an output takes the form of OUTs (A'B)--(CD) where the terms (AB) and summing function circuit of FIG. 2; (CD) are called product terms. These product terms 20 FIG. 4 is a schematic diagram of an alternate embodi are generated from the programmable array and may ment of the user configurable summing function of FIG. include any of the inputs, or their complements, in each 2; and AND function. The logical representation of the sum FIG. 5 is a schematic diagram of a further alternate of-products with an OR summing function is exempli embodiment of the user configurable summing function fied by a device called AMPAL20R4 manufactured by 25 of FIG. 2. Advanced Micro Devices of Sunnyvale, CA and illus DETALED DESCRIPTION OF THE trated on page 4-130 of the "Programmable Logic Handbook/Data Book” which was copyrighted in 1986 EMBODIMENTS by Advanced Micro Devices, Inc. In FIG. 1, to which reference should now be made, A less common, but very powerful, approach to the 30 there is shown a programmable logic device 10. The summing function is the exclusive OR (XOR) imple programmable logic device includes the input circuits mentation. The logical representation of this configura 25 which includes a terminal, an input macrocell (IMC) tion is illustrated on page 4-170 of the above referenced and a driver amplifier 26. The input macrocell 27 typi handbook. The XOR sum can implement certain logical cally includes an input latch for latching the input data. functions, such as counters, comparators, parity genera 35 The input date is then used to address the memory array tors-checkers, more efficiently than the standard OR 28, which in the embodiment of FIG. 1 is an electrically sum function. erasable CMOS programmable array or EECMOS. The memory array 28 is arranged, for illustration SUMMARY OF THE INVENTION purposes only, into sub arrays 30-39 with each sub A programmable logic device includes a programma array having an output circuit 40 that includes an output ble logic array and an output logic macrocell. The out logic macrocell 41 and a plurality of sense amplifiers 42 put logic macrocell includes a user configurable sum which are connected to the rows of each sub-array. ming function that has a first logic gate connected to The sense amplifiers 42 are connected to sense the receive a first plurality of product terms, a second logic product terms whose logic states are dependent upon gate connected to receive a second plurality of product 45 the input states and the connecting switches between terms and a third logic gate connected to receive the the row lines 50 and the product terms. The output combination of the first plurality of product terms and a circuit 40 also includes an output logic macrocell of control signal. A fourth logic gate is connected to re which a schematic diagram is provided in FIG. 2 to ceive the combination of the second plurality of prod which reference should now be made. uct terms and the control signal and a logic circuit is 50 connected to receive the output signals from the first, In FIG. 2 sense amplifier outputs are brought into OR second, third and fourth logic gates and to provide a gates 43,44, or 60. The output of OR gates 44 and 60 are first output signal when the control signal is at a first combined by OR gate 45 and applied to the user con logic state and a second output signal when the control figurable summing function 46 via conductor 52 and the signal is at a second logic state. 55 output of OR gate 43 is applied to the user configurable In one embodiment the first and second logic gates summing function 46 via conductor 51. Depending are OR gates and the third and fourth logic gates are upon the configuration that will be discussed in con NAND gates, the logic circuit is a CMOS exclusive OR junction with FIGS. 3 and 4, the output of the user gate and consequently when the control signal is a logic configurable summing function is applied either directly 0 the output signal is the OR combination of the logical 60 to the combining mux or to an output latch 47 which in OR of the first plurality of product terms with the logi the embodiment of FIG. 2 is a D type flip flop but may cal OR of the second plurality of product terms. When be an RS flip flop, J-K flip flop or a toggle flip flop the control signal is at a logic 1 then the output signal is depending upon the configuration. The output is buff the exclusive OR combination of the logical OR of the ered by the exclusive OR gate 51 and an inverter 50 to first plurality of products terms with the logical OR of 65 provide the output of the combined product terms on the second plurality of product terms. pin 14/23. The combined product terms may be multi In an alternate embodiment the first and second logic plexed back into the memory array via the feedback gates are NOR gates with each NOR gate connected to multiplexer 61 and line driver 63. 4,912,345 3 4 FIG. 3 to which reference should now be made, is a a first logic gate connected to receive a first plurality schematic diagram of the user configurable summing of input signals; function 46 and includes NAND gates 54 and 55. a second logic gate connected to receive a second NAND gate 54 is connected to conductor 51 and to plurality of input signals; receive a control signal noted as Config. NAND gate 55 a first NAND gate connected to receive the output of is connected to conductor 52 and connected to receive the first logic gate and a control signal; the control signal, Config. The outputs of NAND gates a second NAND gate connected to receive the out 54 and 55 are connected to a CMOS exclusive NOR put of the second logic gate and the control signal; circuit 56 which performs either a NOR or an exclusive and NOR on the signals which are present on conductors 51 O a logic circuit connected to receive outputs from the and 52. Config. determines which of these functions is first and second logic gates and the first and second provided. When Config. is at a logical 0 an OR sum NAND gates, to provide an output signal for a first ming function is performed by the user configurable logical combination when the control signal is at a summing function 46 as shown in FIG. 3 and when first logic state and a second logical combination Config. is at a logic 1 then the user configurable sum 15 when the control signal is at a second logic state. ming function 46 of FIG. 3 produces an exclusive OR 2. The programmable summing function for a pro summing function. The output of the exclusive NOR grammable logic device according to claim 1 wherein circuit 56 is applied to an inverter 57 which is connected the first and second logic gates each comprise an OR to conductor 53. gate. 20 3. The programmable summing function for pro An alternate embodiment to the embodiment of FIG. grammable logic devices according to claim 2 wherein 3 is the embodiment of FIG. 4 which is the DeMorgan the first logic state is a logic one and the first logical reduction of the embodiment of FIG. 3 and requires combination is an OR combination of a summation of that the OR gates 42 and 45 of FIG. 2 be converted to the first plurality of input signals and a summation of the NOR gates. For schematic purposes this is illustrated by 25 second plurality of input signals. inverters 59 and 58 which are connected to conductors 4. The programmable summing function for pro 51 and 52 respectively. The outputs of the inverters are grammable logic devices according to claim 2 wherein applied to NOR gates 54 and 55. NOR gate 54 performs the first logic state is a logic 0 and the first logical com a logical NOR of the control signal, Config. and the bination is an exclusive OR combination of a summation logical NOR from NOR gate 43 where as NOR gate 55 30 of the first plurality of input signals and a summation of performs a logic NOR combination on the Config. sig the second plurality of input signals. nal and the logical NOR output from NOR gate 45. 5. A programmable summing function for a program Exclusive OR circuit 56 performs either an OR or nable logic device comprising: exclusive OR of the outputs of inverters 58 and 59 for a first NOR gate connected to receive a first plurality output onto conductor 53. Config, determines which of 35 of input signals; these functions is provided. When Config. is at a logical a second NOR gate connected to receive a second 1 an OR summing function is performed by the user plurality of input signals; configurable summing function 46 is shown in FIG. 4 a third NOR gate connected to receive the output of and when Config is at a logic 0 then the user configura the first logic NOR gate and a control signal; ble summing function 46 of FIG. 4 produces an exclu 40 a fourth NOR gate connected to receive the output of sive OR summing function. the second logic gate and the control signal; and A further alternate embodiment of FIG. 3 is the em a logic circuit connected to receive outputs from the bodiment of FIG. 5. In this embodiment, conductors 51 first, second, third, and fourth NOR gates and to and 52 are applied to OR gate 64 directly, while these provide an output signal of a first logical combina same conductors are applied to exclusive OR gate 65 45 tion when the control signal is at a first logic state through switching transistors 67 and 55 respectively. and a second logical combination when the control The outputs of OR gate 64 and exclusive OR gate 65 are signal is at a second logic state. multiplexed onto conductor 53 through mix 68. Switch 6. The programmable summing function for pro ing transistors 66 and 67 and mux 68 are all controlled grammable logic devices according to claim 5 wherein by the Config. signal. When Config. is at a logical 0 then 50 the first logic state is logic 1 and the first logical combi switching transistors 66 and 67 are off and the mux nation is an exclusive OR combination of a summation connects the output of OR gate 64 to conductor 53. In of the first plurality of input signals and a summation of this state the user configurable summing function per the second plurality of input signals. forms the logical OR of the signals present on conduc 7. A programmable summing function for a program tors 51 and 52. When Config. is at a logical 1 then 55 mable logic device comprising; switching transistor 66 and 67 are on, and the mux 68 a first logic gate means for providing a first summa connects the output of exclusive OR gate 65 to conduc tion of a first plurality of input signals; tor 53. In this state the user configurable summing func a second logic gate means for providing a second tion 46 performs the logical exclusive OR of the signals summation of a second plurality of input signals; present on conductors 51 and 52. The embodiment of 60 a first NAND gate for logically combining the first FIG. 5 is advantageous in applications where the propa summation with a control signal and to provide a gation delay of the OR function needs to minimized. third summation; When Config, is at a logic Oswitching transistors 66 and a second NAND gate for logically combining the 67 are off and the load and delay of the exclusive OR second summation and the control signals and to gate 65 is not applied to conductors 51 and 52. 65 provide a fourth summation; and Accordingly I claim the following: a logic circuit means for combining in a first logic 1. A programmable summing function for a program manner the first, second, third and fourth summa mable logic device comprising: tion when the control signal is at a first logic state 4,912,345 5 6 and in a second logic manner when the control a first logic gate means for providing a first summa- . signal is at a second logic state. tion of a first plurality of input signals; 8. The programmable summing function for pro a second logic gate means for providing a second summation of a second plurality of input signals; grammable logic devices according to claim 7 wherein a fist NOR gate for logically combining the first sum the first logic gate means and second logic gate means mation with a control signal and to provide a third each comprise an OR gate. summation; 9. The programmable summing function for pro a second NOR gate for logically combining the sec grammable logic devices according to claim 7 wherein ond summation and the control signals and to pro the first logical combination is an OR combination. 10 vide a fourth summation; and 10. The programmable summing function for pro a logic circuit means for combining in a first logic grammable logic devices according to claim 7 wherein manner the first, second, third and fourth summa the logical combination is an exclusive OR combina tion when the control signal is at a first logic state tion. and a second logical combination when the control 11. A programmable summing function for a pro 15 signal is at a second logic state. grammable logic device comprising; is k h is

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