Multi-Objective Optimization of Unidirectional Non-Isolated Dc/Dcconverters

MULTI-OBJECTIVE OPTIMIZATION OF UNIDIRECTIONAL NON-ISOLATED DC/DCCONVERTERS

Andrija Stupar

A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Edward S. Rogers Department of Electrical and Computer Engineering University of Toronto

Multi-Objective Optimization of Unidirectional Non-Isolated DC/DC Converters

Andrija Stupar

Doctor of Philosophy

Graduate Department of Edward S. Rogers Department of Electrical and Computer

Engineering

University of Toronto

2017

Engineers have to fulﬁll multiple requirements and strive towards often competing goals while designing power electronic systems. This can be an analytically complex and computationally intensive task since the relationship between the parameters of a system’s design space is not always obvious. Furthermore, a number of possible solutions to a particular problem may exist.

To ﬁnd an optimal system, many different possible designs must be evaluated.

Literature on power electronics optimization focuses on the modeling and design of particular converters, with little thought given to the mathematical formulation of the optimization problem. Therefore, converter optimization has generally been a slow process, with exhaustive search, the execution time of which is exponential in the number of design variables, the prevalent approach.

In this thesis, geometric programming (GP), a type of convex optimization, the execution time of which is polynomial in the number of design variables, is proposed and demonstrated as an efficient and comprehensive framework for the multi-objective optimization of non-isolated unidirectional DC/DC converters. A GP model of multilevel flying capacitor step-down converters is developed and experimentally verified on a 15-to-3.3 V, 9.9 W discrete prototype, with sets of loss-volume Pareto optimal designs generated in under one minute. It is also demonstrated how the GP model can be used to determine the sensitivity of the optimized designs to the design parameters. Furthermore, a general procedure for deriving GP models is presented and demonstrated on the example of inductors for higher power applications.

ii Finally, using the example of the seven-switch ﬂying capacitor converter, it is shown how in cases where a converter-level GP model is not possible, component-level GP models can be coupled with a circuit simulator to perform efﬁciency optimization quickly. This hybrid approach is used to design a wide input and output voltage range, 2 A output current converter

IC.

The results show that GP is of great value to both researchers and practicing engineers.

The methods demonstrated for deriving GP models of power converters are extendable to other converter topologies, allowing for the creation of a rigorous mathematical framework for the optimization of power electronics that guarantees globally optimum designs generated quickly.

iii When sorrows come, they come not single spies

But in battalions.

— King Claudius in Shakespeare’s Hamlet (Act IV, Scene 5)

For at the moment of the ﬁnal division, the ﬁnal miniaturization of matter, suddenly the whole cosmos opened up.

— Thomas Mann, Der Zauberberg

iv To Tanja, for sticking with me to the end

Acknowledgements

This doctoral degree has been a long, and often turbulent, eight years in the making and now that it is ﬁnally over there is a long list of people to thank, some of whom will be invariably missed in these few brief paragraphs - to them I wholeheartedly apologize in advance. I began work towards a PhD degree at the Swiss Federal Institute of Technology (ETH) in Zurich,

Switzerland, in February 2009, where I spent slightly more than four years as a full-time student and employee at the Power Electronic Systems Laboratory (PES), and a subsequent two as an “external” PhD student while working to develop a spin-off company, Gecko-Simulations AG, that my colleagues from PES and I had co-founded in 2012. Although my work at PES/ETH has found its way into many refereed publications, conference and workshop presentations, and

Gecko-Simulations products, little of it is present directly in the text of this thesis. However, the work I did at PES has greatly informed this thesis, and has been a basis for the work presented therein without which, I feel, this thesis would not be possible, and would certainly not have the form that it does. PES at ETH was and continues to be at the forefront of research into the optimization of power converters, and I was privileged not only to have taken part of that work myself, but also to have been able to absorb the knowledge and skills generated by my colleagues and supervisors there, both during and before my time. I was able to learn the state-of-the-art when it comes to optimizing power electronics, and how to improve it – which is what, as I hope the reader will in the end conclude, this thesis is about. I would therefore like to thank ﬁrst and foremost my former supervisor at ETH Zurich and the Director of PES,

Prof. Dr. Johann W. Kolar for giving me the opportunity to work and learn in a challenging and world-class academic environment, for all that I have learned under his supervision, and for accommodating the various arrangements over the years. I would also like to thank the post- docs under whose supervision I worked at PES: Dr. Uwe Drofenik, under whom I got started

v and who provided some important words of encouragement; Dr. Dominik Bortis, who was of immense practical help in the early years; Dr. Florian Krismer, who was always ready to offer help and advice; and ﬁnally, Dr. Thomas Friedli, who was probably simultaneously the kindest, most committed and most knowledgeable person I have had the pleasure of working with. I would also like to thank my fellow PhD students whom I collaborated most closely with at PES and at Gecko-Simulations AG, Dr. Ivana Kovaˇcevi´c-Badstübner, Dr. Andreas Müsing, and Dr.

Jonas Mühlethaler, from whom I learned and with whom I built a lot. They provided great pro- fessional and personal support during my time at ETH Zurich. I would also like to thank other colleagues from PES I have the opportunity to work with and know: Dr. Uwe Badstübner, who was especially helpful, Daniel Christen, Dr. David Boillat, Dr. Arda Tüysüz, Prof. Dr. Jürgen

Biela, Dr. Toke Andersen, Dr. Matthias Kasper, Dr. Johann Miniböck, Dr. Cristoph Marxgut, Dr.

Yannick Lobsiger, Dr. Hirofumi Uemura, Florian Vancu, Dr. Benjamin Wrzecionko, Dr. Thiago

Soeiro, Dr. Christof Zwyssig, Dr. Thomas Baumgartner, staff members Monica Kohn-Müller and

Peter Seitz, and others.

Unfortunately it was not possible for my to bring my degree to completion at ETH Zürich, and a solution was found in my “transferring back”, in 2015, to my alma mater, the Univer- sity of Toronto, to which I transferred my course credits and research from ETH. Therefore most importantly, I would like to thank most of all, my PhD co-supervisors at the University of

Toronto, Prof. Aleksandar Prodi´c and Asst. Prof. Joshua A. Taylor, for rescuing my academic career when it seemed at its lowest – and breaking – point and for giving me another chance.

Moreover, I owe my start in power electronics research to Prof. Prodi´c, who invited my to work at his lab as an undergraduate student back in the summer of 2004. It was in his lab and under his supervision that I completed my Master’s degree in 2008. My return to the Laboratory for

Power Management and Integrated Switch-Mode Power Supplies in the Energy Systems Group at the Faculty of Applied Science and Engineering of the University of Toronto was thus a home- coming - made successful not only by Prof. Prodi´c’s support and steady supply of challenging research projects, but also by support, guidance, and key insights provided by Prof. Taylor, whose insistence on using convex optimization re-oriented my research into a much more fruitful direction. I would like to stress that although greatly informed by my previous work, the major results of thesis and its major contribution – the use of geometric programming for the

vi multi-objective optimization of power converters – have been developed only and fully during my time at the University of Toronto. I would once more like to thank my two co-supervisors

Profs. Taylor and Prodi´c for all the support and guidance they have provided over the past two years, without which the – I believe – signiﬁcant results of this thesis would not be possible.

I would also like to thank my colleagues in Prof. Prodi´c’s lab for all I’ve learned from them and for the support they have provided. Speciﬁcally I’d like to thank Timothy McRae and

Nenad Vukadinovi´c for their help with developing posynomial models of ML-FC converters, as well as for their help in all sorts of work-related matters and their friendship, and Tom

Moiannou with whom I worked on the 7SFC converter project. I would also like to thank Dr.

S.M. Ahsanuzzaman, Samuel Carvalho, Michael Halamicek, and others.

Furthermore I would like to thank, from the University of Toronto, Assoc. Prof. Stark Draper, whose course on convex optimization I wish I had taken at least four years earlier, and where the use of geometric programming for power electronics got started as a course project, and Prof.

Jason Anderson for being members of my PhD qualifying exam committee; Prof. Reza Iravani for being a member of my PhD thesis proposal and then departmental defense committee;

Prof. Peter Lehn for being a member of my qualifying exam, thesis proposal, and ﬁnal defense committees; Assoc. Prof. Zeb Tate for being a member of my qualifying exam, departmental and

final defense committees; Prof. Costas Sarris for being the chair of my departmental defense committee; and Prof. Steven Thorpe for being the chair of my final defense committee. I would also like to thank Prof. Predrag Pejović from the Faculty of Electrical Engineering (ETF) of the

University of Belgrade, Serbia, for being a member of my ﬁnal defense commitee as the external examiner, and for previously offering important words of advice during a difﬁcult time.

Finally, on a personal note, I would like to thank the people close to me, my family and friends, for their support and understanding during what was often a difficult journey. I would like to thank my parents, Dušan Stupar and Dr. Vesna Bataković-Stupar, for all that they have given me in life, and without whom I would not be the person that I am. I would like to thank my sister Ksenija Stupar for her love and support. Finally I want to thank my girlfriend of nine years, Tatjana Skoˇcajić, for her love, support, encouragement, and almost never-ending patience over the years. I dedicate this thesis to them, and to the memory of my recently departed late uncle, the distinguished scholar Dr. Dušan T. Bataković.

vii CONTENTS

Acknowledgements v

Table of Contents viii

List of Tables xi

List of Figures xii

List of Abbreviations xv

1 Introduction 1

1.1 Design Goals in Power Electronics ...... 2

1.2 Design Variables - The Converter Design Space ...... 5

1.3 Thesis Objectives, Scope, and Structure ...... 7

2 Prior Art in the Field of Converter Optimization 9

3 Convex Optimization and Geometric Programming 12

3.1 Convex Optimization ...... 13

3.2 Geometric Programming ...... 14

3.3 Trade-Off and Sensitivity Analysis ...... 16

3.4 Multi-Objective Geometric Programs ...... 17

3.5 Software ...... 18

4 Multi-Objective η−ρ Optimization of ML-FC Converters by Geometric Programming 20

viii 4.1 ML-FC Converter Design ...... 22

4.2 Posynomial Loss and Volume Models ...... 24

4.2.1 Power MOSFETs ...... 26

4.2.2 Inductors ...... 31

4.2.3 Capacitors ...... 35

4.3 GP Formulation ...... 36

4.4 Experimental Veriﬁcation ...... 38

4.5 Optimization Results ...... 41

4.5.1 Design Space A ...... 43

4.5.2 Design Space B ...... 47

4.5.3 Discrete Design Variables ...... 47

4.5.4 Sensitivity Analysis ...... 52

4.5.5 Trade-Off Analysis ...... 55

4.6 Adding a Cooling System to the GP Formulation ...... 59

5 Approximation of Power Electronics Models Using Multivariate Posynomial Func-

tions 60

5.1 Types of Posynomial Functions ...... 60

5.1.1 Max-Monomials and Max-Afﬁne Functions ...... 61

5.1.2 Posynomials and Softmax-Afﬁne Functions ...... 61

5.2 Fitting Procedure ...... 62

5.3 Fitting Example - Higher Power Inductors ...... 64

5.3.1 Inductor Type and Application ...... 65

5.3.2 Simulation and Fitting ...... 66

5.3.3 Optimization Results ...... 67

6 7SFC Converter IC η Optimization by a Circuit Simulation-Coupled Geometric Pro-

gram 70

6.1 7SFC Converter Operation ...... 72

6.1.1 Nishijima mode ...... 72

6.1.2 Meynard mode ...... 72

ix 6.1.3 Two-phase interleaved buck mode ...... 75

6.2 Hybrid Optimization Procedure ...... 75

6.2.1 Posynomial Component-Level Loss Models ...... 75

6.2.2 Converter-Level Modeling ...... 77

6.2.3 Simulation-coupled GP ...... 79

6.3 Optimization Results ...... 81

6.4 Veriﬁcation ...... 86

6.5 Improved Optimization Procedure ...... 90

7 Conclusions and Future Work 92

7.1 Future Work ...... 93

7.1.1 Magnetic Components ...... 93

7.1.2 AC/DC Converters and EMI Filters ...... 94

7.1.3 Generalized Geometric Programming ...... 95

7.2 Final Remarks ...... 95

Appendices 96

Bibliography 133

x LIST OF TABLES

4.1 Regions of Operation of ML-FC Converters According to Duty Ratio ...... 24

4.2 The Value of the Flying Capacitor Current Coefﬁcient X According to Regions of

Operation ...... 24

4.3 ML-FC Converter Application, Operating Point and Design Space Constants . . . . 39

4.4 Free Design Variables for ML-FC Converter Optimization - Design Space Bounds . 39

4.5 Characteristic Values of Power MOSFETs Used for ML-FC Converter Optimization 39

4.6 Coefﬁcients of Inductor and Capacitor Volume and Loss Models ...... 39

4.7 Run Times for Different Convex Optimization Solvers and Problems in MATLAB . 41

4.8 Optimized ML-FC Converter Designs for Design Space A ...... 46

4.9 Achievable Efﬁciency for a Fixed Volume Budget of 300 mm3 ...... 47

4.10 Achievable Power Density for a Fixed Loss Budget of 0.7 W (93.4% Efﬁciency) . . 47

4.11 Allowable LN Values for the Discrete Optimization Problem ...... 48

5.1 Converter Application and Operating Point ...... 66

5.2 Range of Inductor Design Variables Simulated ...... 67

5.3 Posynomial Models Derived From Simulation ...... 68

5.4 Fitting Errors To Simulation Results ...... 68

6.1 Characteristic Values of Employed 0.18 µm Process ...... 83

6.2 Constant Parameters in the 7SFC Optimization Process ...... 83

6.3 Optimization Results for Different Operating Conditions (Switch Areas in mm2). 86

6.4 Comparison of Switch Characteristics ...... 89

6.5 Effect of Interconnection Resistance ...... 91

xi LIST OF FIGURES

1.1 PCBs of two generations of Apple iPad devices, with the power supplies shaded

in green and with some of the power electronic components identiﬁed...... 3

1.2 An example of a design space and Pareto front of a buck converter...... 6

1.3 Changing the Pareto front by expanding or reconﬁguring the design space. . . . .7

3.1 A convex function in three dimensions...... 13

4.1 Circuit diagrams of the (a) buck (2-level), (b) 3-level and (c) 4-level ML-FC DC-

DC converters...... 21

4.2 Principal switching waveforms of the 2-, 3- and 4-level ﬂying capacitor converters. 25

4.3 Prototype of the 4-level converter used for measurement of losses...... 41

4.4 Comparison of the efﬁciency calculated by the posynomial loss models to exper-

imental efﬁciency measurements. Gate drive losses are not included...... 42

4.5 Loss-Volume Pareto fronts for N-level ML-FC converters resulting from Design

Space A...... 43

4.6 Comparison of losses and volumes, broken down by components, between the

three N-level converters for different values of γ, at 100% load, for Design Space

A...... 45

4.7 Loss-Volume Pareto fronts for N-level ML-FC converters resulting from Design

Space B...... 48

4.8 Comparison of losses and volumes, broken down by components, between the

three N-level converters for different values of γ, at 100% load, for Design Space

B...... 49

xii 4.9 Loss-Volume Pareto fronts for N-level ML-FC converters resulting from the dis-

crete (MIGP) version of the optimization problem, for Design Space A...... 51

4.10 Loss-Volume Pareto fronts for N-level ML-FC converters resulting from the round-

ing off of results of the continuous (GP) version of the optimization problem, for

Design Space A...... 52

4.11 Comparison of the Pareto fronts for Design Space A produced by the continuous

GP, the rounded-off continuous GP, and the MIGP...... 53

4.12 Local sensitivity of the optimum to the MOSFET thermal constraint across the

entire range of design goals γ...... 54

4.13 Local sensitivity of the optimum to the lower bound of fripple across the entire range of design goals γ...... 54

4.14 Trade-off curves showing the impact of the upper bound of the allowed semi-

conductor area on the (a) the most efﬁcient possible and the (b) most compact

possible design in Design Space A...... 56

4.15 Trade-off curves showing the impact of the lower bound of the allowed inductor

ripple current on the (a) the most efﬁcient possible and the (b) most compact

possible design in Design Space A...... 57

4.16 Trade-off curves showing the impact of the upper bound of the allowed inductor

ripple current on the (a) the most efﬁcient possible and the (b) most compact

possible design in Design Space A...... 57

4.17 Trade-off curves showing the impact of the lower bound of the inductor current

ripple frequency on the (a) the most efﬁcient possible and the (b) most compact

possible design in Design Space A...... 58

4.18 Trade-off curves showing the impact of the upper bound of the allowed inductor

current ripple frequency on the (a) the most efﬁcient possible and the (b) most

compact possible design in Design Space A...... 58

5.1 The procedure for ﬁtting multidimensional data to multivariate posynomial func-

tions...... 63

5.2 The type of inductor considered in the ﬁtting example...... 65

xiii 5.3 Losses and volumes of the inductor designs simulated to derive the posynomial

models in Table 5.3, and losses and volumes of the set of Pareto-optimal solutions

- the Pareto front - calculated by solving (5.6) using those models for 20 different

values of γ between 0 and 1...... 69

6.1 The Seven-switch ﬂying capacitor (7SFC) step-down converter...... 70

6.2 Operation of the 7SFC in Nishijima (two-phase interleaved high step-down buck)

mode: (a) switching sequence, with the path of current conduction shown in

each state (b) inductor voltage and current waveforms...... 73

6.3 Operation of the 7SFC in Meynard (single-phase three-level ﬂying capacitor buck)

mode: (a) switching sequence, with the path of current conduction shown in

each state (b) inductor voltage and current waveforms...... 74

6.4 Operation of the 7SFC in two-phase interleaved buck mode: (a) switching se-

quence, with the path of current conduction shown in each state (b) inductor

voltage and current waveforms...... 76

6.5 A generalized hypothetical reference efﬁciency curve for particular operation

condition of the 7SFC converter, showing desired efﬁciency at operating points

deﬁned as a percentage of Iout...... 79 6.6 The hybrid simulation-geometric programming efﬁciency optimization procedure. 82

6.7 Efﬁciency calculated from Cadence simulations for designs #3, #8, and #9 from

Table 6.3, in different modes of operation at three different operating conditions.

Reference efﬁciency curves for each of the operating conditions are also included. 87

6.8 The breakdown of the total area of 3.5 mm2 by MOSFET resulting from (a) the

original optimization procedure and (b) the improved optimization procedure

for the selected optimized design, #8...... 88

6.9 The (a) layout of the seven MOSFETs in Cadence for the selected optimized

design, #8, and (b) the fabricated 7SFC converter power stage IC...... 88

6.10 A comparison of GeckoCIRCUITS simulations and Cadence simulations of the

laid out 7SFC design in operating condition 8...... 90

xiv LIST OF ABBREVIATIONS

AC Alternating current

BNB Branch and bound

CSPI Cooling system performance index

DC Direct current

EMI Electro-magnetic interference

GP Geometric program

GGP Generalized geometric program

IC Integrated circuit

ISMA Implicit softmax-afﬁne

MA Max-afﬁne

MIGP Mixed-integer geometric program

ML-FC Multi-level ﬂying capacitor

MOSFET Metal-oxide-semiconductor ﬁeld-effect transistor

NiZn Nickel-zinc ferrite

PoL Point-of-load

PCB Printed circuit board

RAM Random-access memory

RMS Root mean square

SMA Softmax-afﬁne

SMD Surface-mounted device

SMPS Switch-mode power supply

SPICE Simulation Program with Integrated Circuit Emphasis

xv SSD Solid-state drive

7SFC Seven-switch ﬂying capacitor

η Efﬁciency

ρ Power density

xvi CHAPTER

ONE

INTRODUCTION

Power electronic or switching converters are ubiquitous components of many electronic and electrical devices of the present day [1, 2]. They process power in the microwatt to milliwatt range in Internet-of-Things devices [3]; in the watts range in electrical stimulators for medical applications [4]; in the tens to hundreds of watts range in portable electronic devices, computers and other household electronics [2]; in the hundreds of watts to kilowatt range in motor drives and in other applications in electric vehicles [2,5]; and in the kilowatt to megawatt range in the electrical power generation and distribution system [6]. The proliferation of power converters in these and numerous other applications has enabled engineers to improve greatly the performance of power supplies while simultaneously reducing their size [7].

Power converters have thus become indispensable and have now, in many cases, become the main bottleneck for the further improvement of the electronic and electrical devices of which they form a part. The days in which an electronic device could be made more efﬁcient or more compact simply by substituting a power converter for a previously used linear regulator for instance, are, for the most part, long gone. For example, in modern portable electronics, such as smartphones and tablets, the power supplies, which are predominantly or exclusively switching converters, often take up more space than either the central processing unit and the various types of memory combined. They can also be the components deﬁning a minimum physical dimension of a device, and make up in some cases the bulk of the overall weight [8].

1 2 1.1. DESIGN GOALS IN POWER ELECTRONICS

To illustrate this point, consider Fig. 1.11, where the bare printed circuit boards (PCBs) [9, 10] of two generations of Apple iPad tablets are shown. The power supplies are shaded in green.

The ﬁrst generation iPad is shown in Fig. 1.1a. Considering the area taken up by components on the PCB, it can be seen that the power supplies take up about 70% of the total. The PCB of the iPad Air, released approximately three years later, is shown in Fig. 1.1b. Here it can be seen that the power supplies take up only about 30% of the area on the PCB. Both devices have the same screen size, but the iPad Air is thinner, signiﬁcantly lighter, and offers better performance.

The signiﬁcant difference in the size of the two PCBs is mostly made up by the difference in the space taken up by the power supplies. This is a clear example of how the design of power supplies drives the miniaturization of portable electronics.

Similar concerns are present in the design of higher power converters. For example, the

Google & IEEE Little Box Challenge [11] was a competition to design a 2 kW inverter with a power density of at least 50 W/in3 (approx. 3 kW/dm3), while maintaining an overall power conversion efficiency of at least 95%. It is thought that reducing the size of inverters by more than an order of magnitude from what is currently typical would significantly drive further adoption of solar photo-voltaic panels, battery powered vehicles, and improve the efficiency and reach of the power grid. The winning inverter design [12] achieved a power density of 143

W/in3 and was the size of stack of Post-It notes.

1.1 Design Goals in Power Electronics

Size is not the only design goal for power converters. Another primal concern is efﬁciency, often denoted η. All converters incur losses during operation. A converter is rated for a given output power Pout. Due to the losses, the input power Pin drawn from the converter’s power source (e.g. a battery, the power grid, or the output of another power converter) is always higher than

Pout. Efﬁciency is therefore deﬁned as P η = out (1.1) Pin

1Please note that this ﬁgure is based on data from [9,10] and from a visual identiﬁcation of the components, not from any data from Apple or any of its suppliers. CHAPTER 1. INTRODUCTION 3

Magnetic Power Components

Power Management IC Considered PCB Area (a) iPad PCB, photo from [9]

Magnetic Power Components

Power Management IC

(b) iPad Air PCB, photo from [10]

Figure 1.1: PCBs of two generations of Apple iPad devices, with the power supplies shaded in green and with some of the power electronic components identiﬁed.

and is a dimensionless quantity. (1.1) is also often multiplied by 100 and expressed as a percentage. An equivalent quantity, measured in watts (W), is the total converter loss:

Ploss,tot = Pin − Pout. (1.2)

It is difficult to overstate the need for maximizing efficiency, that is, minimizing losses. Every complex battery-powered device contains one or multiple converters between its batteries and its various parts. Battery chargers are also switching converters. In the power grid, switching converters are present in multiple roles, and are especially heavily used with renewable energy sources such as wind and solar. Therefore higher efficiency improves everything from the 4 1.1. DESIGN GOALS IN POWER ELECTRONICS battery life of smartphones and notebook computers, through the range of electric cars, to the consumption of energy and the efforts to curb climate change.

Losses create waste heat which needs to be dissipated. Components of converters have maximum safe operating temperatures that mustn’t be exceed. Also, there are many cases in which they need to be kept even cooler: a phone cannot be too hot to hold or carry in a pocket; a server room should minimize its need for air conditioning. Increasing efﬁciency therefore helps meet these thermal constraints. Since the amount of heat a converter can dissipate is generally proportional to its size, increasing efﬁciency also helps drive the further miniaturization of devices.

The size of a converter is often quantiﬁed via its power density, usually denoted ρ, and

3 3 commonly reported in W/in or kW/L (kW/dm ). It is calculated by dividing Pout by the total converter volume V oltot: P ρ = out . (1.3) V oltot

Ideally, power electronics engineers strive to increase η and ρ, i.e. decrease Ploss,tot and V oltot, simultaneously. As shall be seen in the next Section however, these two design goals are often in conﬂict with one another.

Other commonly discussed design goals are weight, reliability, and cost. In many cases, a reduction of volume is followed by a reduction of weight. This is especially true in mobile electronics, where often no cooling system, active or passive, exists. For higher power designs, this may not necessarily be true, as active cooling systems (i.e. heat sinks with fans) added to dissipate the waste heat from high ρ designs might add extra weight to reduce volume. Weight is therefore sometimes considered separately, especially for e.g. very mass-sensitive airborne applications [13].

Reliability is, on its own, an extensive and immersive topic. While loss and volume models of power electronic components are well-established, dependable reliability modeling of power electronic systems is still an ongoing ﬁeld of research [14–16]. Furthermore, the parametriza- tion of commonly used reliability models requires information about component structure and their failure rate which is often not published by the manufacturers. This makes it difﬁcult to evaluate reliability in depth in an academic setting. On the other hand, reliability is almost CHAPTER 1. INTRODUCTION 5 always implicitly taken into account when designing converters, since manufacturers state safe and recommended operating conditions for all components.

Cost is an immensely important practical design goal. Depending on the application, minimizing cost may be more important than minimizing losses or volume. Cost however varies greatly based on the specific logistics of a manufacturing process – the unit price given by a sup- plier for an order of 40 and an order of 4000 transistors is usually not the same. Manufacturers of power supplies typically do not release a detailed breakdown of their cost structure. This makes obtaining reliable cost figures in the academic setting of a university laboratory difficult.

It is easy to state the cost a laboratory prototype, but deriving wider conclusions from that is difﬁcult and could indeed be misleading. For all of the reasons stated above, this thesis focuses on η and ρ, i.e. losses and volume.

1.2 Design Variables - The Converter Design Space

The buck converter, shown in Fig. 1.2, is the simplest and most widely used step-down converter topology. It consists of two semiconductor devices (two power transistors, or one power transistor and one diode), one inductor, and one capacitor. Even for such a simple topology, the engineer designing the power supply has several choices to make. The input voltage Vin, output voltage Vout, and output current Iout are given. There are then several design variables which need to be selected. One is the frequency fsw with which the transistor(s) are turned on and off. The semiconductor components must be chosen from a wide variety of choices: there are different underlying implementation technologies, and for each, the size and performance of the components can be related to their semiconductor area Asw. The semiconductors may require a cooling system – in any case, the converter must meet thermal constraints. The output voltage ripple ∆vout is typically a given requirement, but the inductor current ripple ∆iL is a free design variable. These two values determine the inductance L and C of the converter, which then must be implemented by choosing appropriate components. This in turn presents more choices of different components implemented using different technologies. For low power applications, this entails selecting pre-fabricated components that come in discrete package sizes. For high power applications, a custom inductor design is possible from a selection of magnetic cores and 6 1.2. DESIGN VARIABLES - THE CONVERTER DESIGN SPACE

Magnetics

Pareto Front Iout ρ L + S Design D C V Vin out Space t - 1 / fsw η

Asw

Capacitors Semiconductors Cooling Figure 1.2: An example of a design space and Pareto front of a buck converter. wires. Electrical, thermal, magnetic and mechanical models of the different components are required.

Each combination of design variables creates a possible converter design, and all of these designs constitute the design space of a particular design task. The engineer’s task is to select from this space the design which best satisﬁes the desired design goals. It has been shown [17] that, for a particular design space, there is an inherent trade-off between η and ρ. At some point in the design space, it is no longer possible to decrease the volume without increasing the losses, and vice-versa. The designs for which it is not possible to increase η without decreasing ρ and vice-versa constitute the Pareto-optimal set of the design space. These designs are visualized as a Pareto front on a two-dimensional plot of η vs ρ (Fig. 1.2).

Due to the aforementioned ever-increasing pressure to improve converter designs, ideally, every converter design should be a member of the Pareto set of its design space. Moreover, computing the entire Pareto front in each case would be advantageous, as it would allow the evaluation of all available η-ρ tradeoffs and the selection of a design most appropriate to the application at hand. Therefore, the design of switching converters is an optimization problem.

To further potentially improve both η and ρ, the Pareto front must be “pushed outwards”

(Fig. 1.3). This can potentially be done by enlarging the design space by adding new types of components. For example, a new, more efﬁcient semiconductor technology, or a new inductor CHAPTER 1. INTRODUCTION 7

ρ expand

reconfigure

η Figure 1.3: Changing the Pareto front by expanding or reconfiguring the design space. core material. The design space can also be reconfigured by the choice of a different converter topology. Many more complicated step-down topologies exist. Even with the same topology, a different control method or modulation scheme can reconfigure the design space by changing the voltage and current stresses across the components. Each of those brings a different set of trade-offs to the table and is more suited to a particular set of applications. The Pareto fronts of different design spaces can both overlap and intersect. The topology selection problem, i.e. deciding which of the available converter topologies is the best for the task at hand, is best solved by evaluating Pareto-optimal designs, as this provides the fairest possible comparison.

1.3 Thesis Objectives, Scope, and Structure

The goal of this thesis is to develop a method for the efficient and accurate multi-objective optimization of switching converters that is mathematically rigorous, repeatable and transferable between different converter design problems. This can best be done by “fitting” the converter optimization problem mathematically to a known class of optimization problems. Doing so would allow all of the existing knowledge pertinent to that problem – such as existing method- ologies for finding solutions, mathematical proofs regarding the characteristics of optima, and so on – to be directly applied to power electronics. Convex optimization is such a thoroughly- studied mathematical and engineering field [18], which has been used in electrical engineering for solving circuit-sizing problems [19, 20], sizing a hybrid-electric powertrain [21] and designing analog-to-digital converters [22]. It has hitherto, however, been almost unapplied to problems in power electronics. 8 1.3. THESIS OBJECTIVES, SCOPE, AND STRUCTURE

This thesis was completed at the Laboratory for Power Management and Integrated Switch-

Mode Power Supplies (SMPS) at the University of Toronto, which mostly (but not exclusively) performs research on low-power DC/DC converters. This is reﬂected therefore on the two converter design studies which were used to develop the optimization method. This thesis thusly deals with DC/DC converters, converting a DC voltage to another DC voltage. There is no study of the impact of the requirements of the power grid (such as electro-magnetic interference (EMI) constraints) on the optimization problem. All of the converters considered are non-isolated, which means that no transformer modeling is performed. They are also unidirectional, meaning that energy transfer in only one direction is considered for the modeling.

Both optimization examples involve step-down converters, but the presented methods can be applied to all step-up non-isolated unidirectional DC/DC converters, as the modeling procedure would be identical.

This is not to say that the methods which will be presented cannot be applied to other types of converters (AC/DC or DC/AC converters), isolated DC/DC topologies, or higher power levels.

The work presented in this thesis is informed by previous research performed at the Power Elec- tronics Systems Laboratory at the Swiss Federal Institute of Technology in Zurich (ETH Zürich), where the author began his PhD studies and worked on the optimization of kilowatt-range

AC/DC and isolated DC/DC converters, reliability testing, and thermal and magnetic modeling.

The steps which would needed to be taken to apply the methods that will be presented here to such design problems are discussed in the ﬁnal Chapter.

Chapter 2 examines the current state-of-the-art in the ﬁeld of converter optimization. Chap- ter 3 gives an overview of convex optimization and the only class of convex optimization problem that is suitable for wide use in power electronics. In Chapter 4 the developed multi- objective optimization method is presented through the optimization of low-power multilevel

ﬂying capacitor (ML-FC) converters. A more general method for modeling power electronic components within the developed optimization framework is presented in Chapter 5, using the example of inductors for higher power applications. Chapter 6 extends the method, by the use of circuit simulation, to a case in which applying convex optimization on the converter level is not possible. Chapter 7 presents conclusions and ideas for future work. CHAPTER

TWO

PRIOR ART IN THE FIELD OF CONVERTER OPTIMIZATION

There is abundant literature concerning the single- and multi-objective optimization of switching converters, for both discrete [17, 23–42] and integrated (on-chip) [43–58] converters of varying power levels, types, and applications. Most such papers on optimization focus on a particular converter or system, and on the development of models for components and systems and their experimental veriﬁcation. This is of paramount importance and such publications provide essential information and insight, since optimization procedures cannot produce valid converter designs without being grounded in physically realistic models. However, less attention is paid to the general mathematical and functional framework within which optimization itself as a process is performed. Usually, when power electronics optimization publications provide some detail as regards to the actual implementation of the optimization procedure, as in [31, 36, 39, 41, 42] for high-power converters made of discrete components, or in [43, 44, 47, 49–56, 58] for low-power integrated converters, the derived model of the converter system is evaluated for all possible combinations of the design parameters, and the optimal design (or set of Pareto-optimal designs if there are multiple design objectives) is found at the end of such an exhaustive search.

Although this type exhaustive search or parameter sweep is guaranteed to ﬁnd a globally optimal set of designs, it is a very time-consuming process. Optimization studies which use exhaustive search are therefore limited by computation time to demonstrating the achievable limits of a particular system, and no great insight into how the process of optimization itself

9 10 should be executed in general is gained. In some cases [29,30,35], this approach is modiﬁed so that instead of exhaustive search, at least part of the optimization problem is solved by passing the non-linear objective function to a generic non-linear solver available in mathematical software packages such as MATLAB or Mathematica. Still, no analysis is performed to determine whether the form of the model is well-suited to the optimization algorithm used nor what the optimization algorithm actually is. Furthermore, in order to speed up execution, both of these approaches usually necessitate breaking up the optimization procedure into “inner and outer loops” (see e.g. [30]) to reduce the number of design parameter combinations, casting some doubt on whether the resulting designs are truly globally optimal.

There are some notable exceptions to this prevailing approach. The first is [59], where an attempt is made to derive a mathematical formalism for converter optimization and a set of appropriate algorithms. The drawbacks with the proposed approach are that first, the power converter is treated as a general non-linear system, which causes problems with algorithm convergence, and second, that advances in the modeling of power electronic components have made the approach dated and re-evaluation of the proposed algorithms necessary. Similarly, in [48, 57] the integrated converter is modeled as a set of constrained non-linear equations, and the optimization problem is solved as a generic non-linear programming problem. In [46], the optimization task is formulated as a mixed-integer non-linear program, a class of problems difficult to solve, and several heuristics are compared.

The treatment of the overall model of a power electronic converter as a non-linear system whose characteristics are not suited for many traditional optimization algorithms is a common theme in the literature. Therefore, many recent approaches employ non-linear techniques such as genetic or evolutionary algorithms [24, 26, 34, 37, 45]. Such algorithms are able to ﬁnd optima in non-linear problems and are extremely ﬂexible with regards to the type of underlying model employed. However, their usage is not mathematically rigorous, and they possess many tunable parameters which greatly impact their performance. Finding the correct set of algorithm parameters for a particular problem is not trivial, and is most often done through trial and error, without a clear conclusion whether a particular set of parameters is generally applicable to other instances of the same problem, or to similar problems.

A promising approach to mathematically formulating the problem of converter optimization CHAPTER 2. PRIOR ART IN THE FIELD OF CONVERTER OPTIMIZATION 11 in order to make it suitable for fast optimization was, however, presented in [60]1, where the optimization of DC-DC buck and boost converters for efﬁciency is done by modeling the converters as a geometric program (GP), a well known class of convex optimization problem [61].

The GP model presented in [60] is designed for only a single design objective (efficiency), con- siders three simple converter topologies (the boost and the buck converters with a diode, and the synchronous rectifier buck), and both the switch, and especially, inductor loss models are over-simplified. No thermal modeling is performed, nor are any thermal constraints, which cannot be ignored in real-world designs, introduced into the problem formulation. Although [60] represents a breakthrough in the mathematical conceptualization of converter optimization, the approach presented therein is limited by the very simplified modeling. As such, it seems to have unfortunately gone unnoticed by the wider power electronics community.

The goal of this thesis therefore is to apply the advantages of convex optimization to power electronics by formulating the problem of multi-objective efﬁciency (loss) and power density

(volume) optimization of non-isolated unidirectional DC-DC converters as a geometric program which models all the converter components accurately and comprehensively. GPs are presented in more detail in the following Chapter.

1The author would like to note that he was unfortunately unaware of the existence of [60] when he published his ﬁrst papers (in 2016) on using GPs to optimize converters and components. These papers therefore erroneously claim that no-one had framed converter optimization as GP prior to the author and his co-authors on those papers. The author hereby apologizes to the authors of [60] and recognizes their important contribution. CHAPTER

THREE

CONVEX OPTIMIZATION AND GEOMETRIC PROGRAMMING

This Chapter provides a short summary of basic concepts in convex optimization that are cov- ered in more depth in books such as [18]. The overview of geometric programming is summarized from [61]. The reader is directed to these publications for a more detailed and mathematically rigorous treatment of these subjects.

Most often, a mathematical optimization problem is formulated as a minimization problem:

minimize fo(x) (3.1)

subject to fi(x) ≤ bi, i = 1, ..., m

hj(x) = ci, j = 1, ..., p

where fo(x) is the objective function to be minimized. This is well suited for use in power electronics, as the converter optimization problem can always be expressed in terms of quantities to be minimized (e.g. losses, volume, weight, cost). fi(x) is the set of inequality constraints and hj(x) the set of equality constraints to be satisﬁed by the minimum solution. Therefore (3.1) is more properly called a constrained minimization problem. A simple power electronics example would be minimizing total converter volume while not exceeding a set amount of watts of losses. The solution of (3.1) is the vector x = (x1, ..., xn) which gives the minimum value of fo(x) which also satisﬁes the constraints. In power converter optimization, x is the set of free design variables, such as switching frequency, semiconductor area, inductor core size and so

12 CHAPTER 3. CONVEX OPTIMIZATION AND GEOMETRIC PROGRAMMING 13 on. It should be noted that for constrained minimization problems, it may be possible that no solution that meets the constraints exists.

3.1 Convex Optimization

If fo(x), fi(x), and hj(x) are convex functions, then (3.1) is a convex optimization problem.A

n function f : R → R is convex if it satisﬁes the relationship

f(θx + (1 − θ)y) ≤ θf(x) + (1 − θ)f(y) (3.2)

n for all x, y ∈ R and all θ ∈ R where 0 ≤ θ ≤ 1. All linear functions are convex, as are all quadratic functions (i.e. a paraboloid in three dimensions as in Fig. 3.1). Therefore linear programs, least-squares problems, and quadratic programs are all types of convex optimization problems. There are two main advantages of convex optimization problems. The ﬁrst is that

Figure 3.1: A convex function in three dimensions. in all convex functions, a local minimum is also a global minimum. Therefore if a solution to a convex problem exists, it is guaranteed to be globally optimum. The second is that convex optimization problems are solved using interior-point methods, which are very robust in practice and almost always produce the solution in a number of steps and mathematical operations that does not exceed a polynomial function of the dimensions of the problem. In other words, if an 14 3.2. GEOMETRIC PROGRAMMING optimization problem is convex, it is highly likely that a global optimum can be found quickly.

3.2 Geometric Programming

Models of power electronic components are multivariate polynomial or power functions: they most often include the multiplication of different design variables together, sometimes raised to different powers. For example, calculating a part of the switching losses of a power MOSFET involves multiplying the switching frequency, a design variable, by the output capacitance, which is a function of the semiconductor area, another design variable. The only class of convex optimization problem which allows the use of such a form is geometric programming.A geometric program (GP) has the form:

ko11 ko12 ko1n kon1 konn minimize fo(x) = ao1x1 x2 ...xn + ... + aonx1 ...xn (3.3)

ki11 ki1n kin1 kinn subject to fi(x) = ai1x1 ...xn + ... + ainx1 ...xn ≤ 1, i = 1, ..., m

kj1 kj2 kjn hj(x) = ajx1 x2 ...xn = 1, j = 1, ..., p

where the exponents kj can be any real number. However, in the above form of (3.3), fo(x), fi(x), and hj(x) are in fact not convex functions. The GP is put into a convex form by the means of a logarithmic transformation, where each design variable xl is replaced by its natural logarithm so that

yl = log(xl) (3.4)

yl xl = e and then the GP of (3.3) becomes

y minimize log(fo(e )) (3.5)

y subject to log(fi(e )) ≤ 0, i = 1, ..., m

y log(hj(e )) = 0, j = 1, ..., p CHAPTER 3. CONVEX OPTIMIZATION AND GEOMETRIC PROGRAMMING 15

where y is the vector of all yl. By expanding an equality constraint function,

y log(hj(e )) = log(aj) + kj1 log(x1) + kj2 log(x2) + ... + kjn log(xn) (3.6) it can be seen that the original exponential function has been transformed into a linear, and therefore convex, function. However, it follows then that in order for (3.6) to be a valid expression, the design variables xl must be positive non-zero real numbers, as must be the coefﬁcients

(aj > 0). In geometric programming literature, functions hj(x) satisfying these conditions are called simply “monomials”. However, monomials as deﬁned in classical algebra do not satisfy these conditions. Therefore to avoid confusion, such functions will be referred to as

GP-monomials in this thesis.

Likewise, if the same conditions, aol > 0, ail > 0, and xl > 0 are imposed on the functions fo(x) and fi(x), it can be seen that they are sums of GP-monomials and thus termed posynomials (“positive polynomials”). Under the logarithmic transformation of (3.5), posynomials become the log-sum-exp function:

n y X kily+log(ail) log(fi(e )) = log e (3.7) l=1 which is known to be convex [18].

It follows from the above that a GP-monomial multiplied or divided by another GP-monomial results in another GP-monomial. It is also trivial to see that all GP-monomials are posynomials.

The rules for posynomials are

1. A posynomial added to a posynomial is a posynomial;

2. A posynomial multiplied by a posynomial is a posynomial;

3. A posynomial divided by a GP-monomial is a posynomial;

4. A posynomial subtracted from a posynomial is NOT a posynomial;

5. A posynomial divided by a posynomial is NOT a posynomial. 16 3.3. TRADE-OFF AND SENSITIVITY ANALYSIS

3.3 Trade-Off and Sensitivity Analysis

The sensitivity of an optimized design to the values of the design variables, that is, knowing how much the optimum design would be affected by the tightening (or loosening) of a constraint, is often of great interest. For example, the maximum allowable switching frequency of a converter might need to be reduced due to noise concerns. To perform such an analysis, the perturbed version of the GP of (3.3) can be examined:

minimize fo(x) (3.8)

subject to fi(x) ≤ ui, i = 1, ..., m

hj(x) = vj, j = 1, ..., p

where ui and vj are values that replace the 1 in the inequality and equality constraints, respectively. If ui > 1, then the inequality constraint is deemed loosened compared to the original problem, and likewise tightened if ui < 1. By varying ui, and re-solving the GP for each value of ui considered, an optimal trade-off curve of the optimal value of fo(x) vs. ui can be plotted, showing how the optimum changes with respect to the tightening or loosening of the constraint.

A steep trade-off curve indicates that the value of the optimum is highly sensitive to a change in the constraint, and conversely a flat trade-off curve signifies that changing the constraint has no effect on the final outcome. If two values of ui or vj are varied simultaneously, the result is a trade-off surface.

The slope of a trade-off curve at a particular point represents the local sensitivity of the optimum to small changes in the constraint around that point. Furthermore, in optimization theory, there is something called the dual formulation of the problem, in which, through the usage of Lagrange multipliers, a dual variable is associated with each constraint of the original, or primal problem. The details shall be omitted here for brevity, but it sufﬁces to know that the optimum value of the dual variable is equal to the upper bound of the local sensitivity of the optimal objective to constraint perturbations as in (3.8) [18]. Since modern GP solvers are constructed so that they solve the primal and the dual problem concurrently [61], the optimum dual variables, and so the sensitivities, are available “for free” as a result of the GP optimization. CHAPTER 3. CONVEX OPTIMIZATION AND GEOMETRIC PROGRAMMING 17

Every time a GP is solved therefore, the local sensitivities to each constraint are automatically made available. For example, if the optimum dual variable associated with a constraint is equal to 1.73, this means that if this constraint is loosened by 10%, the minimum achievable value of the objective function will decrease by no more than 17.3%.

Note that these sensitivities are local, and that therefore when it comes to the design variables x, non-zero sensitivities will appear only in cases where the selected value of the design variable causes a constraint fi(x) to be close to its bound. This does not give the global sensitivity to a design variable or a constraint – for that, the trade-off curve approach must be used.

The local sensitivities, being immediately available, can however convey which of the bounds on the design space is limiting the optimum design. They can also be used to judge the effect of component tolerances (e.g. a design very sensitive to the bounds on inductor ripple current will require an inductor with a very small tolerance compared to the nominal inductance, or otherwise the real-world design will not perform as expected) or model accuracy (e.g. an optimum highly sensitive to thermal constraints suggests that special care should be paid to the thermal models used). This shows how geometric programming can be used not only to arrive at optimal converter designs, but also for a more thorough exploration and understanding of a given design space.

3.4 Multi-Objective Geometric Programs

As noted in Chapter 1, the design of switching converters is often a multi-objective problem.

For two objectives, this can be represented by two separate objective functions to be minimized,

n fo1(x) and fo2(x). Since the GP of (3.3) requires an objective posynomial function fo : R → R, a single objective function must be created from the two using a weighting factor γ. This gives

minimize γfo1(x) + (1 − γ)fo2(x) (3.9)

subject to fi(x) ≤ 1, i = 1, ..., m

hj(x) = 1, j = 1, ..., p 18 3.5. SOFTWARE

where 0 ≤ γ ≤ 1. The component objective functions foi(x) are normalized:

foi(x) foi(x) = (3.10) NFi

by normalization factor NFi that ensures that 0 ≤ foi(x) ≤ 1. The choice of NFi depends on the particular problem; an example is given in Chapter 4. Normalization allows γ to be a meaningful quantity, since the component functions become unit-less and appropriately scaled to the same range of values. It can thus be seen that γ = 1 corresponds to only minimizing fo1(x), while ignoring fo2(x), and that γ = 0 does the reverse. The value γ = 0.5 can be said to produce a “half-way compromise” between the two objectives. Solving (3.9) for a sufﬁciently large number of values of γ will reproduce the Pareto front of the design space of the problem.

(3.9) can be extended for an arbitrary number of objectives K by introducing more weighting factors, so that K X fo(x) = γifoi(x) (3.11) i=1

PK where γi ∈ [0, 1] ∀ i and i=1 γi = 1. Solving the GP for a sufﬁcient number of combinations of values of γi would then reconstruct the Pareto surface of the design space.

3.5 Software

Software for convex optimization generally consists of two parts: an interface, or toolbox, which allows the user to deﬁne convex optimization problems, and a solver, to which the toolbox interfaces and which is actually used to ﬁnd the solution. It is possible to call the solvers directly, however the toolboxes provide a much more user-friendly way of formulating convex problems without having to worry about the details of the solver implementation.

GGPLAB [62] is a geometric programming toolbox for MATLAB which includes a dedicated solver, GGPOSY. It is recommended for small GPs and is distributed under the GNU General

Public License (GPL). YALMIP [63] is a more capable, general convex optimization toolbox for MATLAB, which can solve GPs using, among others, MATLAB’s built-in FMINCON solver, but can also interface with GGPOSY. YALMIP is also distributed freely and can also be used in

Octave, the free open-source alternative to MATLAB. When running under Octave however, the CHAPTER 3. CONVEX OPTIMIZATION AND GEOMETRIC PROGRAMMING 19 choice of solvers is much more limited and GGPOSY is not available. The most well known

MATLAB toolbox for convex optimization is probably CVX [64]. CVX is also freely distributed, but cannot run in Octave, nor can it use MATLAB’s built-in solvers. CVX comes bundled with two free open-source solvers also distributed under the GPL: SDPT3 and SeDuMi. CVX can also use two commercial solvers: Gurobi and MOSEK [65]. These solvers require an additional, paid, license, but are free to use by academic institutions. A Python version of CVX called

CVXOPT is available for use outside of MATLAB.

All three toolboxes allow GPs to be entered in their standard form, (3.3). In fact, they are more ﬂexible: it is not necessary to normalize all constraint functions to be less than or equal to 1. It is also allowed to enter inequality constraints as “greater than” relations instead of only

“less than” relations. Furthermore, following the rules of the previous Section,

1. An equality constraint can have GP-monomials on both sides, or a constant on either side;

2. A less-than inequality constraint can have a posynomial on the left side and a GP-monomial

or a constant on the right side; and

3. A greater-than inequality constraint can have a GP-monomial or a constant on the left

side and a posynomial on the right side.

Therefore for the remainder of this thesis, GPs shall be formulated using these conventions.

The toolboxes automatically convert the GP into standard form, and then into the logarithmic form of (3.5). This highlights another advantage of the convex optimization framework in practice: the power electronics engineer does not need to know or worry about how the solvers work. All that is necessary is to be able to model and formulate a problem mathematically as a GP. This can be difﬁcult, but essentially does not require any deeper understanding of convex optimization theory beyond what is presented in this Chapter. Once a GP formulation is achieved, solving the problem is relatively straightforward. CHAPTER

FOUR

MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY

GEOMETRIC PROGRAMMING

Multilevel ﬂying capacitor (ML-FC) converters, shown in Fig. 4.1, have been widely adopted in high power applications, processing hundreds of kilowatts [66–68], and have also been proposed for medium-power applications of several hundred watts [69, 70]. More recently these converters have been analyzed as solutions to much lower power applications, processing tens of watts [71–78]. In this Chapter, to illustrate the use of geometric programming, a multi- objective optimization of a conventional buck, 3-level ML-FC, and 4-level ML-FC converter between volume (power density) and losses (efﬁciency) will be demonstrated for a low-power application, over a large range of several design variables. The loss-volume Pareto fronts for all three converters will be generated and compared.

Note that this Chapter is concerned with the selection of the components for Pareto-optimal low-power ML-FC converter designs. Using ML-FC converters in low-power applications also presents signiﬁcant practical challenges for the converter control. These are discussed in more detail, with proposed solutions, in [74, 76, 78].

20 CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 21

c1(t) SW1

c1(t) SW1 c2(t) SW2 L2 L3 iL2 Iout iL3 Iout Vin vsw Vin Cfly vsw + SW SW c1(t) 2 C2 Vout iCfly c2(t) 3 - + C3 Vout - c (t) SW4 (a) (b) 1

c1(t) SW1

c2(t) SW2

c3(t) SW3 L4 iL4 Iout Cfly1 Cfly2 vsw Vin

iCfly1 iCfly2 c3(t) SW4

c2(t) SW5 C4 Vout -

c1(t) SW6 (c)

Figure 4.1: Circuit diagrams of the (a) buck (2-level), (b) 3-level and (c) 4-level ML-FC DC-DC converters. 22 4.1. ML-FC CONVERTER DESIGN

4.1 ML-FC Converter Design

The number of levels in a multi-level ﬂying capacitor (ML-FC) converter is denoted by N.A conventional buck converter (Fig. 4.1a)) can be thought of as a “2-level” ML-FC converter

(N = 2). Circuit schematics of the 3-level (N = 3) and 4-level (N = 4) ML-FC converters are shown in Fig. 4.1b) and c) respectively. A principal beneﬁt of multi-level converters is the fact that the voltage stress across the power switches and the voltage swing of the switching node voltage, labeled vsw in Fig. 4.1, are reduced N −1 times compared to the conventional buck. An

N-level converter thus contains N − 2 ﬂying capacitors Cfly. This allows for the use of lower voltage-rated switches with increasing levels. These advantages can be leveraged to reduce semiconductor losses and the required inductance [75]. Geometric programming will be used to precisely quantify these advantages over a range of Pareto-optimal trade-offs between the volume (power density) and the losses (efﬁciency) for converters with N = 2, 3, 4.

The switching waveforms of ML-FC converters for N = 2, 3, 4, including the switching node voltage vsw, the inductor current iL,N , and the ﬂying capacitor current iC,fly are shown in Fig. 4.2. Following the analysis in [74–76], it can be seen that the inductor current ripple frequency fripple is related to the switching frequency fsw by

fripple = (N − 1)fsw (4.1) and by deﬁning the duty ratio D for every value of N as

V D = in (4.2) Vout

where Vin and Vout are the DC values of the input and output voltage of the converter, respectively. The peak-to-peak inductor current ripple ∆iL,N,pp is

R(N − 1)Vin ∆iL,N,pp = (4.3) frippleLN

where LN is the inductance of the output inductor of the N-level converter. R is the inductor CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 23 ripple coefﬁcient deﬁned by

i i − 1 R = − D D − (4.4) N − 1 N − 1 where i is the index of the region of operation of the converter deﬁned by D, so that

i − 1 i < D ≤ (4.5) N − 1 N − 1

as shown in Table 4.1. Furthermore, the RMS current of each flying capacitor Cfly, IC,fly,RMS is s 2 √ 1 ∆iL,N,pp IC,fly,RMS = Iout 2X 1 + (4.6) 3 2Iout where Iout = IL,N is the DC converter output and inductor current. X is the flying capacitor current coefficient which also depends on i as defined by the rule

if i = 1 then X = D, (4.7)

else if i = N − 1, then X = 1 − D, 1 else X = N − 1 as shown in Table 4.2. X also therefore impacts the ﬂying capacitor peak-to-peak voltage ripple

∆vC,fly,pp as given by IoutX(N − 1) ∆vC,fly,pp = (4.8) Cflyfripple

Finally, the output capacitor peak-to-peak voltage ripple ∆vout,pp and RMS current ∆iC,N,RMS are deﬁned by ∆iL,N,pp ∆vout,pp = (4.9) 8CN fripple

∆iL,N,pp IC,N,RMS = √ (4.10) 2 3 where CN is the output capacitance of the N-level converter. Rearranging for LN , CN , and 24 4.2. POSYNOMIAL LOSS AND VOLUME MODELS

Table 4.1: Regions of Operation of ML-FC Converters According to Duty Ratio N i = 1 i = 2 i = 3 2 D ≤ 1 - - 3 D ≤ 0.5 0.5 < D ≤ 1 - 4 D ≤ 1/3 1/3 < D ≤ 2/3 2/3 < D ≤ 1

Table 4.2: The Value of the Flying Capacitor Current Coefﬁcient X According to Regions of Operation N i = 1 i = 2 i = 3 2 X = D - - 3 X = D X = 1 − D - 4 X = D X = 1/3 X = 1 − D

Cfly, the following design rules for the passive components are derived:

R(N − 1)Vin LN = (4.11) ∆iL,N,ppfripple ∆iL,N,pp CN = 8∆vout,ppfripple IoutX(N − 1) Cfly = fripple∆vC,fly,pp

from which it is evident that it is advantageous to consider ∆iL,N,pp and fripple as the design variables, since ∆vout,pp and ﬂying capacitor ripple ∆vC,fly,pp are typically constant design constraints to be satisﬁed.

4.2 Posynomial Loss and Volume Models

The terms in a posynomial cannot have negative coefﬁcients (cf. Chapter 3). Therefore, in order to remove the negative signs from the equations in Section 4.1, it is evident that only one converter can be optimized at a time, thus making N (and by extension the factor (N − 1)) a constant, and for only one DC operating point at a time, thus making Vin, Vout, Iout, and by extension D, i, R, and X constants. In other words, one GP can be used to optimize one N- level converter at one operating point. By doing so, (4.3) - (4.11) can be treated as posynomial functions of fripple and ∆iL,N,pp. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 25

1 / f sw2 N = 2

c1 t

Vin

vsw

iL2 ΔiL2,pp

N = 3 c1

1 / fsw3 c2

Vin 2 vsw

i L3 ΔiL3,pp

iCfly

N = 4 c1

1 / fsw4

Vin vsw 3

iL4 ΔiL4,pp

iCfly1

iCfly2

fripple Figure 4.2: Principal switching waveforms of the 2-, 3- and 4-level ﬂying capacitor converters. 26 4.2. POSYNOMIAL LOSS AND VOLUME MODELS

4.2.1 Power MOSFETs

The switches add a third design variable, the total semiconductor area per switch Asw. It is assumed that all switches are sized equally. As the ML-FC converters to be optimized are targeting a low-power application such as a mobile device, and are to be implemented using discrete MOSFET, inductor, and capacitor components, Asw is taken to represent the entire package area of the power MOSFETs, not just the semiconductor die area. Furthermore in such an application, there is no room for active cooling or heat sinks of any kind, and therefore posynomial modeling of any type of cooling system is omitted here. For higher power systems, a heat sink based cooling system is generally necessary, or at least must be considered during the optimization. The addition of a cooling system to the posynomial model is presented in

Section 4.6.

The MOSFET loss models are based on [1, 31, 75], and [79]. The reference switch area

Asw,ref , the reference MOSFET output capacitance for that area at the required blocking voltage

Coss,ref , the reference on-state MOSFET resistance for that area at the required conduction current RDS,on,ref , the on-state resistance temperature-dependance coefﬁcient α, the reference total gate charge for that area Qg,ref , the reference MOSFET body diode reverse recovery charge for that area Qrr,ref , and the reference junction-to-ambient thermal resistance for that area

RT h,j−a,ref characterize a particular semiconductor device selected for a particular N-level ML- FC, and are therefore constant for a given value of N. The switching loss of one switch is

1 P = f t V I + t V I + C V 2 (4.12) sw 2 sw on DS,on DS,on off DS,off DS,off oss DS,blocking

where turn-on time ton and turn-off time toff depend on the gate charge Qg, the off-state blocking voltages at turn-on and after turn-off, VDS,on and VDS,off , respectively, and the on- state currents after turn-on and before turn-off, IDS,on and IDS,off , respectively, as well as on the MOSFET transconductance and parasitic inductances [79]. As the last two quantities are especially difﬁcult to derive from switch data sheets, the best approach is to simulate the ML-

FC converters at the desired operating point using manufacturer-supplied SPICE models of the selected switches, as well as the gate drivers if possible, in order to determine the approximate ton and toff at Asw,ref . If it is further assumed that the gate drivers will scale up with Asw, CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 27

thereby eliminating the dependence on Qg which increases with Asw, ton and toff can be treated as constants. VDS,blocking is the blocking voltage of the MOSFETs during the off-state which charges the MOSFET output capacitance Coss. It is the same for both high-side and low-side switches, and is also equal to VDS,on and VDS,off of the high-side switches:

V V = V = V = in (4.13) DS,blocking DS,on,HS DS,off,HS N − 1

For the low-side switches however, the body diode conducts during the dead-time between the high-side and low-side switching transitions, and therefore the blocking voltage just before the turn-on and just after the turn-off of a low-side switch is equal to the MOSFET body diode forward voltage VF ,

VDS,on,LS = VDS,off,LS = VF (4.14)

Furthermore, since a low-side switch turns on as a high-side switch turns off and vice-versa,

IDS,on of the low-side switches is equal to IDS,off of the high side switches, and vice-versa, so that 1 I = I = I − ∆i (4.15) DS,on,HS DS,off,LS out 2 L,N,pp 1 I = I = I + ∆i (4.16) DS,off,HS DS,on,LS out 2 L,N,pp

Each N-level converter has a total of (N − 1) low-side and (N − 1) high-side switches. Given that the output capacitance Coss scales with Asw,

Coss,ref Coss = Asw (4.17) Asw,ref

and substituting in (4.1), the total high-side switching losses Psw,tot,HS and low-side switching losses Psw,tot,LS of an ML-FC converter are

Psw,tot,HS = (N − 1)Psw,HS (4.18) 1 V 1 V = f (t + t )I in + (t − t )∆i in 2 ripple on,HS off,HS out N − 1 2 off,HS on,HS L,N,pp N − 1 2 1 Coss,ref Vin + frippleAsw 2 Asw,ref N − 1 28 4.2. POSYNOMIAL LOSS AND VOLUME MODELS

1 1 P = (N − 1)P = f (t + t )I V + (t − t )∆i V sw,tot,LS sw,LS 2 ripple on,LS off,LS out F 2 on,LS off,LS L,N,pp F (4.19) 2 1 Coss,ref Vin + frippleAsw 2 Asw,ref N − 1

It was conﬁrmed through SPICE simulations that toff,HS > ton,HS while ton,LS > toff,LS, therefore making the constant coefﬁcients (toff,HS − ton,HS) and (ton,LS − toff,LS) positive. This makes sense since IDS,off,HS > IDS,on,HS, while on the other hand IDS,on,LS > IDS,off,LS.

To simplify the modeling, it is assumed that (toff,HS − ton,HS) = (ton,LS − toff,LS) and that

(ton,HS + toff,HS) = (ton,LS + toff,LS). This over-estimates the losses somewhat, since in re- ality the turn-on and turn-off times for the low-side switches are lower than the times for the high-side switches. Combining (4.18) and (4.19) then gives the total switching loss:

1 V 1 V P = f (t + t )I in + V + (t − t )∆i in + V sw,tot ripple 2 on off out N − 1 F 4 off on L,N,pp N − 1 F (4.20) 2 Coss,ref Vin + Asw Asw,ref N − 1

which is a posynomial function of the design variables fripple, ∆iL,N,pp, and Asw. It was found through SPICE simulations of the ML-FC converters that the reverse recovery losses of the low- side MOSFET body diode are not negligible and must be included in the total loss calculation.

The reverse recovery loss for one switch is

Prr = QrrVDSfsw (4.21) since the body diode reverse recovery charge scales with area as

Qrr,ref Qrr = Asw (4.22) Asw,ref and since there are N − 1 low-side switches per N-level converter, and substituting in (4.1) and CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 29

(4.13), the total reverse recovery losses are

Qrr,ref Vin Prr,tot = (N − 1)Prr = Asw fripple (4.23) Asw,ref N − 1

which is a GP-monomial function of fripple and Asw. The gate driving losses for a single switch are

Pg = QgVGSfsw (4.24)

where the gate-source voltage VGS applied to the MOSFET is taken to be a constant, and the total gate charge Qg scales up with area as

Qg,ref Qg = Asw (4.25) Asw,ref

After substituting (4.1) and (4.13) the total gate driving losses are

Qg,ref Pg,tot = 2(N − 1)Pg = 2Asw frippleVGS (4.26) Asw,ref which is a GP-monomial function in the same manner as (4.23). The conduction loss of a single switch is

2 Pcond = Isw,RMS RDS,on (4.27)

where the MOSFET RMS current Isw,RMS and the on-state resistance which scales inversely with area Asw are

s 2 √ 1 ∆iL,N,pp Isw,RMS,HS = Iout D 1 + (4.28) 3 2Iout s 2 √ 1 ∆iL,N,pp Isw,RMS,LS = Iout 1 − D 1 + 3 2Iout

RDS,on,ref Asw,ref RDS,on = (1 + α(Tj − Tamb)) (4.29) Asw

Isw,RMS,HS and Isw,RMS,LS are the RMS currents of the high-side and low-side switches, respectively, Tj the junction temperature of the MOSFET and Tamb the ambient temperature. To remove the minus sign and put (4.29) into posynomial form, the change in junction tempera- 30 4.2. POSYNOMIAL LOSS AND VOLUME MODELS

ture with respect to the ambient ∆Tj,

∆Tj = Tj − Tamb (4.30)

is introduced and substituted in. Note that (4.29) presents a problem: RDS,on, and by extension the losses Pcond, depend on ∆Tj, but the calculated change in junction temperature ∆Tj,calc depends on the losses:

∆Tj,calc = (Psw,tot + Prr,tot + Pcond,tot)RT h,j−a (4.31) which introduces a circular dependency into the problem. To break this circular dependency,

∆Tj is introduced as an additional design variable to the GP formulation, and named the assumed junction temperature rise. This then necessitates the introduction of the ﬁrst constraint to the problem, namely that the assumed temperature and the calculated temperature must be the same. However, introducing an equality constraint is not possible, since equality constraints in the GP (3.3) can include only GP-monomials, and (4.31) is a posynomial. Since it is clear from (4.29) that losses, and therefore ∆Tj,calc, increase with an increase in the assumed temperature ∆Tj, it sufﬁces to introduce an inequality constraint

∆Tj,calc ≤ 1.1∆Tj (4.32) where the assumed temperature is allowed to be within 10% of the calculated temperature.

With the addition of the extra design variable ∆Tj and the constraint (4.32), the circular dependency is resolved automatically by the solver. The ability to inherently take into account such circular dependencies is another signiﬁcant advantage of using convex optimization for converter design. The total conduction losses for an N-level converter are then

2 2 Pcond,tot = (N − 1)(Isw,RMS,HS + Isw,RMS,LS )RDS,on (4.33)

2 1 2 RDS,on,ref Asw,ref = (N − 1)(Iout + ∆iL,N,pp ) (1 + α∆Tj) 12 Asw

which is a posynomial expression of three design variables: Asw, ∆iL,N,pp, and ∆Tj. Finally, CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 31 the switches must satisfy a thermal constraint: the junction temperature should be less than a set maximum temperature Tj,max. Knowing that the junction-to-ambient thermal resistance

RT h,j−a scales inversely with area as

Asw,ref RT h,j−a = RT h,j−a,ref (4.34) Asw and substituting into (4.31) yields the inequality constraint

Asw,ref (Psw,tot + Prr,tot + Pcond,tot)RT h,j−a,ref ≤ ∆Tj,max (4.35) Asw

where ∆Tj,max is the maximum allowed junction temperature change relative to the ambient.

Hence (4.35) is a posynomial function of all four design variables (Asw, fripple, ∆iL,N,pp, ∆Tj) as can be seen from (4.20), (4.23), and (4.33). Looking also at (4.26), it is clear that the total semiconductor losses of an N-level converter,

PS,tot = Psw,tot + Prr,tot + Pg,tot + Pcond,tot (4.36) is also a posynomial function of all four variables. The expression for calculating the volume of the switches simply takes the GP-monomial form

V olS,tot = 2(N − 1)hswAswg (4.37)

where hsw is the height of the switch package and is a constant for a given device and g is a constant coefﬁcient used to account for the volume of the gate drivers.

4.2.2 Inductors

Generally, the volume of a passive component, i.e an inductor or capacitor, is related to its required energy storage capacity and its rated current or voltage. In practice, component volumes are discretized into standard package sizes. Since this discretization would result in a non-convex problem, continuous curves were ﬁt to families of components using a least-squares 32 4.2. POSYNOMIAL LOSS AND VOLUME MODELS method. The volume of a family of inductor components can be represented by [80]

2 V olL = kL,1LN Ipk (4.38)

where the kL,1 is a ﬁtted volume coefﬁcient, which must be positive as the required volume will increase with the required energy storage capacity, and Ipk is the peak current for which the inductor should be rated, which in the ML-FC case is equal to

1 I = I + ∆i (4.39) pk out 2 L,N,pp

Substituting this into the expression for LN from (4.11) and also (4.39) into (4.38) gives

2 Iout Iout ∆iL,N,pp V olL,N = kL,1R(N − 1)Vin + + (4.40) fripple∆iL,N,pp fripple 4fripple

which is a posynomial in fripple and ∆iL,N,pp. Inductor loss models are not convex by nature.

Using variants of the Steinmetz equation, the volumetric core losses Pc,v in inductors to which triangular current waveforms are applied are given by [81–83]

α β Pv,c = ki(2fripple) (∆B) (4.41)

where ki, α, and β are the Steinmetz coefﬁcients, and ∆B is the peak-to-peak ﬂux density inside the inductor core. Knowing that ∆B is proportional to ∆iL,N,pp, from (4.41) it can be deduced that core losses in one inductor Pcore can be approximated by

a b PLN,core = kL,2fripple ∆iL,N,pp (4.42)

where kL,2, a, and b play a role similar to that of Steinmetz coefﬁcients. Inductor winding losses are more complex and consist of losses due to DC and AC resistance, and must take into account skin and proximity effects. AC losses due to htot harmonics of the inductor current can CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 33 be written as [29, 31]

htot 2 X ∆iL,N,pp,h P = R F (hf ) (4.43) AC L,DC 3 R,AC ripple h=1 where ∆iL,N,pp,h is the peak-to-peak magnitude of the hth harmonic of the inductor current, and RL,DC the DC winding resistance. FR,AC (hfripple) is a function used to determine the AC winding resistance which, besides on the hth harmonic of fripple, depends on the winding cross- section and the layout of the winding around the core. It can be evaluated using Bessel [83] or hyperbolic sine functions [84], which are not convex, but can be approximated with posynomials [85]. However, the application of (4.43) requires detailed knowledge of the inductor geometry, which is typically not known for the discrete low-power inductor components that need to be modeled for the target application. It therefore sufﬁces to approximate (4.43) with

c PLN,AC = kL,3fripple∆iL,N,pp (4.44)

where kL,3 is a constant and where real-valued exponent c captures some of the inherent non- linearity of (4.43). Finally the DC winding losses of an inductor

2 PDC = RL,DC Iout (4.45) can be approximated by the expression

2 d PLN,DC = kL,4Iout ∆iL,N,pp (4.46)

d where ∆iL,N,pp , being related to size of the inductor (4.40), is introduced to account for the effect of the size and conﬁguration of a particular inductor on the winding geometry. It can therefore be seen that (4.42), (4.44), and (4.46), the components of the posynomial model for inductor losses, are inspired by well-known physical models for inductor losses. Manufacturers of low-power inductor components often provide online simulation tools, such as Würth’s RED-

EXPERT [86], which contain loss models based on experimental measurements. The structure of these models is not published. However if such online tools are used to simulate a family of 34 4.2. POSYNOMIAL LOSS AND VOLUME MODELS inductor components over the range of currents, voltages, and frequencies to be considered for the optimization, the total inductor loss in the form

PL,N = PLN,core + PLN,AC + PLN,DC (4.47)

a b c 2 d = kL,2fripple ∆iL,N,pp + kL,3fripple∆iL,N,pp + kL,4Iout ∆iL,N,pp can be ﬁtted to the simulation results with a good degree of accuracy. Note that even though for the purpose of explaining the derivation of (4.47), the equations (4.42), (4.44), and (4.46) were presented as separate components, the total loss equation (4.47) should be ﬁtted to the simulation results directly as a single expression, in order to capture the various effects [83] that the different types of losses have on each other.

The thermal constraint applied to the switches should also be applied to the inductor. As the heat dissipation is a function of the losses and the inductor geometry [83], one could assume that an expression of the form e PL,N TL,N = f (4.48) V olL,N could be used to approximate the upper limit on the inductor temperature TL,N . Such an expression, however, would not be usable in a GP, since a posynomial divided by a posynomial as in (4.48) is not itself a posynomial [61]. Since tools such as REDEXPERT also provide a projected temperature rise as part of the simulation results, care must be taken to select for the optimization components which do not exceed a maximum desired TL,N , and so the selection of the appropriate fripple and ∆iL,N,pp (and thus component for LN ) can be enforced by requiring the losses calculated by (4.47) to be less than the maximum simulated inductor loss PL,max over the considered family of inductor components. This adds the third inequality constraint

PL,N ≤ PL,max (4.49) to the GP formulation of the optimization problem. A more general posynomial formulation of inductor loss, volume, and thermal models, applicable to higher power applications, is discussed in Chapter 5. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 35

4.2.3 Capacitors

The volume of a family of capacitor components can be, analogously as with inductors, be represented by [80]

2 V olC = kC,1CVC + kC,2CVC + kC,3 (4.50) where kC,1, kC,2, and kC,3 are least-squares fitted coefficients which must be positive for (4.50) to achieve posynomial form, and VC is the voltage the capacitor component with capacitance C should be rated for. Assuming that the same family of components is used for both the flying and output capacitors, and substituing into (4.50) the expressions for Cfly and CN from (4.11), the following expressions for the output capacitor volume V olC,N and the total volume of the

ﬂying capacitors V olC,fly are given by:

(N − 2)VinXIout Vin V olC,fly = kC,1 + kC,2 + (N − 2)kC,3 (4.51) fripple∆vC,fly,pp N − 1

2 ∆iL,N,pp V olC,N = (kC,1Vout + kC,2Vout) + kC,3 (4.52) 8∆vout,ppfripple

For ceramic capacitors commonly used in low-power applications, only the losses due to ESR need to be considered, which are given by

2 IRMS,C tan δ PC = (4.53) 2πfrippleC

where IRMS,C is the RMS current through the capacitor and a constant upper value of the loss factor tan δ can be used. Substituting (4.11), (4.6), and (4.10) into (4.54) gives the output capacitor loss PC,N and the total ﬂying capacitor losses PC,fly as shown below.

2 (N − 2)Iout tan δ∆vC,fly,pp (N − 2) tan δ∆vC,fly,pp∆iL,N,pp PC,fly = + (4.54) π(N − 1) 12π(N − 1)Iout

8∆v tan δ∆i P = out,pp L,N,pp (4.55) C,N 24π

Since in practice the capacitors take up much less space in low-power converters than the inductors, thermal modeling may be omitted as long as care is taken to select properly rated 36 4.3. GP FORMULATION components.

4.3 GP Formulation

The total volume and losses are

V oltotal = zv(V olS,tot + V olL,N + V olC,fly + V olC,N ) (4.56)

Ptotal = PS,tot + PL,N + PC,fly + PC,N

where the constant coefﬁcient zv accounts for the volume of the PCB and interconnections. The ﬁnal constraints for the GP problem are the upper and lower bounds on the design variables.

As noted in Section 3.4, the expressions from (4.56) must be normalized in order to formulate the optimization problem as a multi-objective GP. This means that the total losses Ptotal should be divided by the maximum possible losses Ptot,max over the design space. Due to the inverse relationship between volume and losses [17], this can be done by ﬁrst solving for the minimum volume V oltot,min within the same design space. Solving the GP

minimize V oltotal (4.57)

subject to ∆Tj,calc ≤ ∆Tj,max

∆Tj,calc ≤ 1.1∆Tj

PL,N ≤ PL,max

fripple,min ≤ fripple ≤ fripple,max

∆iL,N,pp,min ≤ ∆iL,N,pp ≤ ∆iL,N,pp,max

Asw,min ≤ Asw ≤ Asw,max

∆Tj,min ≤ ∆Tj ≤ ∆Tj,max

gives the converter design with V oltot,min and therefore also Ptot,max. Similarly, the total losses

V oltotal should be normalized by the maximum possible volume V oltot,max over the design CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 37

space. As above, V oltot,max can be obtained by solving the GP

minimize Ptotal (4.58)

subject to ∆Tj,calc ≤ ∆Tj,max

∆Tj,calc ≤ 1.1∆Tj

PL,N ≤ PL,max

fripple,min ≤ fripple ≤ fripple,max

∆iL,N,pp,min ≤ ∆iL,N,pp ≤ ∆iL,N,pp,max

Asw,min ≤ Asw ≤ Asw,max

∆Tj,min ≤ ∆Tj ≤ ∆Tj,max

which gives the converter design with the minimum losses Ptot,min and the maximum volume

V oltot,max. Finally, the multi-objective optimization problem, at a single operating point, for a single choice of N, can be expressed as the GP

P V ol minimize γ total + (1 − γ) total (4.59) Ptot,max V oltot,max

subject to ∆Tj,calc ≤ ∆Tj,max

∆Tj,calc ≤ 1.1∆Tj

PL,N ≤ PL,max

fripple,min ≤ fripple ≤ fripple,max

∆iL,N,pp,min ≤ ∆iL,N,pp ≤ ∆iL,N,pp,max

Asw,min ≤ Asw ≤ Asw,max

∆Tj,min ≤ ∆Tj ≤ ∆Tj,max

A solution for one value of γ represents one Pareto-optimal converter design, i.e. one point on the loss-volume Pareto front of the converter design space. Since the solutions for γ = 0 and

γ = 1 are already solved for in (4.57) and (4.58) respectively, reconstructing the Pareto front at a granularity of ∆γ = 0.05 requires solving (4.59) an additional 19 times for values of γ 38 4.4. EXPERIMENTAL VERIFICATION between 0.05 and 0.95. Calculating the set of Pareto-optimal designs for one value of N thus requires solving 21 GPs, and for all three values of N considered in this Chapter a total of 63

GPs.

It follows from the deﬁnition of (4.59) that setting γ = 0 will yield the minimum volume

(maximum ρ) design and that γ = 1 will yield the minimum loss (maximum η) design, with

γ = 0.5 yielding a “halfway compromise design” between these two points.

4.4 Experimental Veriﬁcation

The targeted application, deﬁned as the operating point at 100% load, and the design spec- iﬁcation to be met by the optimized converters are given in Table 4.3. The ranges of the design variables considered for this design, i.e. the bounds fripple,min, fripple,max, ∆iL,N,pp,min,

∆iL,N,pp,max, Asw,min, Asw,min, ∆Tj,min, and ∆Tj,max from (4.57) - (4.59), are given in Table 4.4.

A 25 V MOSFET (CSD16411Q3) was selected for the 2-level converter, and a 20 V MOS-

FET (CSD15571Q2) for the 3-level converter. For the 4-level, two different 12 V MOSFETs

(CSD13202Q2 and CSD13306W, marked A and B in Table 4.5, respectively) were selected for comparison. All of the MOSFETs are manufactured by Texas Instruments. As mentioned in

Section 4.2, ton and toff were determined using SPICE simulations and are shown with the other characteristic values derived from the device data sheets in Table 4.5.

A family of Würth NiZn SMD inductor devices appropriate to the targeted application was selected, and losses were simulated in REDEXPERT for the operating point conditions given in

Table 4.3 over the range of design variables given in Table 4.4. A family of TDK SMD ceramic capacitors was used, and an upper limit for tan δ was derived from the data sheets. This value and the passive component ﬁtting coefﬁcients discussed in the previous Section are given in

Table 4.6. The ﬁts given are for losses in Watts and volume in cubic metres. A maximum inductor loss PL,max of 0.3 W is taken to ensure that the temperature of the inductors never exceeds 65°C.

The losses were measured over a range of load currents on a series of prototypes with different switching frequencies and inductance values. All prototypes, for every value of N, CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 39

Table 4.3: ML-FC Converter Application, Operating Point and Design Space Constants

Input voltage Vin 15 V

Output voltage Vout 3.3 V

Output current Iout 3 A

Output ripple ∆vout,pp 0.022Vout

Input ripple ∆vC,fly,pp 0.04Vin

Ambient temperature Tamb 25°C

Max. junction temp. Tj,max 50°C

∆Tj,max = Tj,max − Tamb 25°C

PCB volume factor zv 1.2

Table 4.4: Free Design Variables for ML-FC Converter Optimization - Design Space Bounds Design variable Min. value Max. value

Ripple frequency fripple 500 kHz 2.5 MHz

Current ripple ∆iL,pp 0.1Iout 0.5Iout

Switch area Asw Asw,ref 15Asw,ref

Assumed temp. rise ∆Tj 1°C 25°C

Table 4.5: Characteristic Values of Power MOSFETs Used for ML-FC Converter Optimization Rated voltage 25 V 20 V 12 V (A) 12 V (B) 2 Asw,ref [mm ] 10.9 4.0 4.0 1.5

Coss,ref [pF] 300 200 500 320

Qg,ref [nC] 5 4.25 9.1 14.5

Qrr,ref [nC] 11.7 10.7 13.0 14.8

RDS,on,ref [mΩ] 12 21 9.5 11.0 α [1000/°C] 3.64 4.0 3.08 2.67

RT h,j−a,ref [°C/W] 165 235 210 230

VGS [V] 8 8 8 8 h [mm] 1.0 0.75 0.75 0.62 g 0.5 0.5 0.5 0.5

ton [ns] 2.744 2.193 1.555 3.34

toff [ns] 3.136 2.247 2.725 4.66

VF [V] 0.8 0.8 0.7 0.8

Table 4.6: Coefﬁcients of Inductor and Capacitor Volume and Loss Models

kC1 kC2 kC3 tanδ kL1 kL2 kL3 kL4 a b c d 5.4982 × 10−7 1.74473 × 10−6 2.7854 × 10−10 0.02 0.005508 0.02401 6.381 × 10−10 0.002242 0.1302 0.06675 0.2853 2.774 40 4.4. EXPERIMENTAL VERIFICATION were constructed using the 25 V switches from Table 4.5. One of the 4-level prototypes is shown in Fig. 4.3. The comparisons of the measured and the calculated efficiency over the entire load current range for six different combinations of LN and fripple, two for each value of N, are shown in Fig. 4.4. Since the gate drivers of the laboratory prototypes were supplied from a separate power supply, the gate driver losses are not included in the measurements nor in the calculations the measurements are compared to in Fig. 4.4. It can be seen that generally the agreement between the posynomial loss models and the measurements is very good. The observed discrepancies can be explained by two main factors. First, a careful examination of the results given by the REDEXPERT inductor simulation tool will reveal that the loss model employed by it does not, at the time of writing, include the effect of the DC bias current through the inductor on the core losses. This, however, has been shown to be significant [87], and that the presence of a DC bias can in certain cases double the core loss [83]. This is the likely explanation for the measured efficiency being consistently lower than the calculated one for

N = 2 in Fig. 4.4a and Fig. 4.4b. Second, the MOSFET data sheets do not give a curve for

Qrr as they do with the other characteristic quantities, but only a single value at a single operating point – most importantly, a single VDS. Therefore, the reverse recovery losses are likely overestimated at higher values of N, where VDS is lower than given in the data sheet Qrr speciﬁcation. This is the likely cause of the measured efﬁciency being somewhat larger than the calculated one at certain currents for N = 3 and N = 4 as in Fig. 4.4c. This also probably partly explains the lower difference between the measurements and the calculations for N = 3 and

N = 4 compared to N = 2. It should also be noted that there are some losses which were not modeled in Section 4.2, such as the parasitic capacitance of the PCB layers, the effect of which is typically not great but can be non-negligible [31], the PCB trace resistances, and so on, which are difﬁcult to predict ahead of time since they depend greatly on the physical construction of the prototype. Nevertheless, the average absolute error of the calculated efﬁciencies relative to the measurements is only 2.5%, demonstrating that posynomials can be used to accurately model power electronic converters. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 41

Vout

Vin

L4 SW1-6 Cfly1-2 Figure 4.3: Prototype of the 4-level converter used for measurement of losses.

4.5 Optimization Results

The multi-objective optimization problem (4.59) was solved in CVX using the MOSEK solver, and also in YALMIP using the GGPOSY solver, as these were found to be the fastest. All solutions were generated on a laptop computer with a dual-core (quad-thread) Intel Core i5-6200U processor with a nominal speed of 2.4 GHz, 8 GB of RAM, an SSD, and running Windows 10.

The execution times vary slightly from run to run, and according to the load of the computer’s processor and memory at a given moment. Typical running times at low background processor load are given in Table 4.7. It can be seen that the optimization problems are solved extremely quickly, showing that the GP is a very efﬁcient formulation of the converter optimization problem. The MATLAB code is given in Appendix A.

Table 4.3 to Table 4.6 deﬁne the considered design space of the ML-FC converters. For the purpose of the comparison of the effects of the different choice of 12 V MOSFET given in

Section 4.4, Design Space A refers to the design space with the 12 V switch marked A in Table

4.5, while Design Space B refers to the design space with the 12 V switch marked B in the same table. The two design spaces are otherwise identical.

Table 4.7: Run Times for Different Convex Optimization Solvers and Problems in MATLAB Solver Problem type Total running time (s) CVX + SDPT3 Continuous (incl. sensitivity analysis) 320.0 CVX + MOSEK Continuous (incl. sensitivity analysis) 49.0 YALMIP + GGPOSY Continuous (incl. sensitivity analysis) 24.4 YALMIP + BNB, FMINCON Discrete 394.1 CVX + MOSEK Trade-off analysis 182.9 42 4.5. OPTIMIZATION RESULTS

100 95 90 85 80 75 70

Efficiency Efficiency (%) 65 60 55 50 0.5 1 1.5 2 2.5 3 Load current (A)

N = 2, calculated N = 2, measured N = 3, calculated N = 3, measured

(a) fripple = 1.5 MHz, LN = 2.2 µH

100 95 90 85 80 75 70

Efficiency Efficiency (%) 65 60 55 50 0.5 1 1.5 2 2.5 3 Load current (A)

N = 2, calculated N = 2, measured N = 4, calculated N = 4, measured

(b) fripple = 1.5 MHz; LN = 1.2 µH for N = 2 and LN = 0.47 µH for N = 4

100 95 90 85 80 75 70

Efficiency Efficiency (%) 65 60 55 50 0.5 1 1.5 2 2.5 3 Load current (A)

N = 3, calculated N = 3, measured N = 4, calculated N = 4, measured

Figure 4.4: Comparison of the efﬁciency calculated by the posynomial loss models to experimental efﬁciency measurements. Gate drive losses are not included. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 43

1200

1000

800 ) 3

600 Volume Volume (mm 400

200

0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 Losses (W)

N = 2 N = 3 N = 4

Figure 4.5: Loss-Volume Pareto fronts for N-level ML-FC converters resulting from Design Space A.

4.5.1 Design Space A

Fig. 4.5 shows the Pareto fronts of the three N-level converters at 100% load resulting from the optimization for Design Space A. Compared to the conventional buck (N = 2), the curves of the 3- and 4- level converter are pushed down and to the left on the graph, indicating that these designs are better from both an efficiency and volume perspective. In other words, for this particular design space, by utilizing ML-FC topologies, it is not only possible to achieve a more compact or more efficient converter than a conventional buck, but it is possible to reduce both size and losses simultaneously. It can be seen that the benefit gained from increasing N from 2 to 3 is significantly greater than the benefit gained from increasing N from 3 to 4, i.e. each additional level yields a smaller benefit than the previous.

A breakdown of the volume and losses by component for the three converters is given in

Fig. 4.6a and Fig. 4.6b, respectively, for three design goals: γ = 0.0 (most compact design), γ

= 1.0 (most efﬁcient design) and γ = 0.5 (halfway compromise). The volume of the inductor

(shown in yellow) is of particular interest as it approximately occupies between 45% and 97% of the total volume over the different number of levels and γ. As the number of levels increases, the volume of the inductor decreases. This result conﬁrms the argument made in [67,70,75,88].

With increasing number of levels the most volume-optimized design is both smaller and more efficient than the conventional buck. Furthermore, a significant reduction of volume oc- 44 4.5. OPTIMIZATION RESULTS curs at each additional level for both the halfway-compromise and most efficiency-optimized designs. Although the 3- and 4-level converters have lower losses than the 2-level at both the halfway-compromise and most efficiency-optimized designs, they are penalized by increasing conduction, gate driving, and flying capacitor losses. Consequently, the 4-level has slightly higher overall losses than the 3-level. While this is clear also from Fig. 4.5 for the most efficiency-optimized design since the two Pareto curves merge and then just intersect, the result for the halfway-compromise design is surprising. While the Pareto curve of the 4-level is, other than at the left-most extreme, consistently below that of the 3-level, the losses of the halfway-compromise (γ = 0.5) 4-level design are slightly higher than that of the 3-level. The explanation is that the 4-level design achieves a smaller most efficiency-optimized result (γ =

1) thereby lowering the Pareto curve compared to the 3-level, causing its midpoint (γ = 0.5) to be a at a different point on the graph compared to the midpoint of the 3-level curve.

A more intuitive way therefore to compare the performance of different N-level converters is to see the minimum losses i.e. maximum efficiency achievable for a given volume budget for different N, and conversely, the minimum volume i.e. maximum power density achievable for different N for a given loss budget. This data can be read from Fig. 4.5 and is summarized in Table 4.9 and Table 4.10. Within Design Space A, for a given maximum allowable volume, it is possible to design a more efficient converter by increasing N, and conversely, for a given minimum allowed efficiency, it is possible to design a more compact converter by increasing N.

The optimized designs themselves are shown in Table 4.8. It can be seen that a dramatic decrease in semiconductor junction temperature is achieved with increasing N. For N = 2, the design is either always thermally limited (i.e. the semiconductors heat up to the maximum allowed temperature), close to it, or undergoing significant warming. With increasing levels, this is only true for the more compact designs at N = 3. The components which contribute most to the thermal limitation are the MOSFETs, as the inductors are well under their maximum loss limit of 0.3 W across all designs. The optimization procedure gives some, at first glance, counter-intuitive results: for example, the most compact designs at N = 2 use more semiconductor area Asw than the most efficient designs with a much larger total volume. The explanation becomes clear by looking at the other results: since the volume of the converters is dominated by the size of the inductor, for the most compact design it is minimized by select- CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 45

1200

1000 ) 3 800

Flying capacitor volume 600 Output capacitor volume Inductor volume 400

Total Total (mmVolume Switch and gate driver volume

200

0 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 γ = 0.0 γ = 0.5 γ = 1.0

(a) Volumes

1.6

1.4

1.2 Flying capacitor loss 1 Output capacitor loss

0.8 Inductor loss Gate driving loss 0.6 Reverse recovery loss Total Total Losses (W) Switching loss 0.4 Conduction loss 0.2

0 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 γ = 0.0 γ = 0.5 γ = 1.0

(b) Losses

Figure 4.6: Comparison of losses and volumes, broken down by components, between the three N-level converters for different values of γ, at 100% load, for Design Space A. 46 4.5. OPTIMIZATION RESULTS

Table 4.8: Optimized ML-FC Converter Designs for Design Space A γ 0.0 0.5 1.0 N 2 3 4 2 3 4 2 3 4 2 Asw [mm ] 18.7 4.0 4.0 10.9 5.55 4.0 10.9 7.05 5.3

Asw/Asw,ref 1.72 1.0 1.0 1.0 1.39 1.0 1.0 1.76 1.33

fripple [MHz] 1.816 2.5 2.5 0.645 0.698 0.816 0.5 0.5 0.5

LN [µH] 0.945 0.493 0.299 2.67 2.05 1.04 17.2 12.3 1.96

CN [µF] 1.42 1.03 1.03 4.0 3.19 2.08 1.03 1.03 1.03

Cfly [µF] 0 0.88 1.32 0 3.15 4.05 0 4.4 6.6 Volume [mm3] 156 68.1 61.3 287 211 126 1165 847 535 Losses [W] 1.448 0.937 1.042 0.512 0.529 0.525 0.367 0.360 0.369

∆Tj [°C] 25 25 12.9 18.3 9.5 8.2 15.6 5.8 4.9

ing the maximum possible ∆iL,pp. This however increases the switching losses, necessitating a higher Asw to meet the thermal constraint. The optimization results show that in this design space, when seeking minimum volume, it makes sense to pay the penalty of a higher Asw in order to achieve a smaller volume of LN . Insights such as these underline the usefulness of a fast optimization method, as results which would otherwise be arrived through a lengthy trial-and-error procedure are produced on the ﬁrst run.

Furthermore, these results underscore the usefulness of the GP formulation in comparing different converter topologies. Unlike in [75], where different N-level converters are compared while keeping fripple ﬁxed, or in [70, 88], where switching and conduction losses are kept constant by design and the volume of the passive components is the only metric used for comparison, the method presented in this thesis allows different topologies to be compared over the entire design space, over a broad range of design parameters. This ensures a meaningful like-for-like comparison as always the optimum design of one converter with respect to a design goal is compared to the optimum design of another converter at the same design goal.

As the information presented in this subsection, giving optimized designs at one operating point and for one set of components, is generated in under one minute on a mid-rage personal computer, it is evident that a large number of optimized designs for a range of operating points and a large number of different component sets can be generated quickly in a few hours. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 47

Table 4.10: Achievable Power Density for Table 4.9: Achievable Efficiency for a Fixed a Fixed Loss Budget of 0.7 W (93.4% Effi- Volume Budget of 300 mm3 ciency) N Total Losses Efficiency N Total Volume Power Density 2 0.5 W 95.2% 2 195 mm3 50.8 W/cm3 3 0.40 W 96.1% 3 100 mm3 99.0 W/cm3 4(A) 0.38 W 96.3% 4(A) 82 mm3 120.7 W/cm3 4(B) 0.47 W 95.5% 4(B) 90 mm3 110.0 W/cm3

4.5.2 Design Space B

The 12 V switch marked B in Table 4.5, seems to be an attractive alternative to A, used in the previous subsection. It has a signiﬁcantly smaller package area Asw,ref , a smaller output capacitance Coss,ref , but on the other hand slightly higher RDS,on,ref and Qrr,ref with a signiﬁcantly higher Qg,ref . It is therefore interesting to see how the Pareto front for N = 4 looks if it is substituted into the design. The volume and loss breakdown by component is given in Fig. 4.8.

The results of the optimization in that case are given in Fig. 4.7. While, as expected, Design

Space B produces a smaller volume-optimized design (γ = 0) at N = 4 then Design Space A, for γ ≥ 0.5 the 4-level design is now no longer more efﬁcient than the 3-level or the conventional buck, as evidenced by the intersection of the Pareto fronts in Fig. 4.7. This contrasts the neat progression of Pareto fronts successively closer to the origin produced by Design Space A, and suggests that optimization results obtained in one design space cannot be generalized to another. This underscores the need to optimize the converters anew for each new design space

(even for the same application) and thus highlights again the advantage of a procedure that facilitates doing so quickly. The results in Fig. 4.8b quickly identify the main culprit for the low efﬁciency of switch B: the gate driving losses.

4.5.3 Discrete Design Variables

The previous results assume that design variables are continuous – that any Asw can be selected within the given range, and that inductances and capacitances can be any real number. This is what is in optimization terminology called the continuous relaxation of the original problem. In actual low-power discrete power supply implementations, switches, inductors and capacitors 48 4.5. OPTIMIZATION RESULTS

1200

1000

800 ) 3

600 Volume Volume (mm 400

200

0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 Losses (W)

N = 2 N = 3 N = 4

Figure 4.7: Loss-Volume Pareto fronts for N-level ML-FC converters resulting from Design Space B.

come in discrete sizes. Therefore, for a realistic design, the GP formulation must be modiﬁed to account for discrete design variables. First, the switch area Asw can be replaced by the number of switches Nsw, Asw Nsw = (4.60) Asw,ref so that each occurrence of Asw in (4.59) is replaced by NswAsw,ref . Adding the constraint that

Nsw must be an integer, i.e. Nsw ∈ Z, turns (4.59) into a Mixed-Integer Geometric Program (MIGP) [61].

Table 4.11: Allowable LN Values for the Discrete Optimization Problem L (µH) 0.72 1.0 1.2 1.5 1.8 2.2 3.3 4.7 6.8 10 18

Second, LN should be constrained to a discrete set of values representing available components as in Table 4.11. Introducing this constraint into the MIGP is more complicated. The ﬁrst step is to introduce LN as a design variable in place of ∆iL,N,pp, by substituting the expression relating the two from (4.11) into (4.59) for each occurrence of ∆iL,N,pp. Then for each possible value Lp of LN a binary decision variable dp, which can take either the value of 0 or 1, must be introduced. A constraint must be added stating the only one of the decision variables may be CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 49

1200

1000 ) 3 800

Flying capacitor volume 600 Output capacitor volume Inductor volume 400

Total Total (mmVolume Switch and gate driver volume

200

0 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 γ = 0.0 γ = 0.5 γ = 1.0 (a) Volumes

1.6

1.4

1.2 Flying capacitor loss 1 Output capacitor loss

0.8 Inductor loss Gate driving loss 0.6 Reverse recovery loss Total Total Losses (W) Switching loss 0.4 Conduction loss 0.2

0 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 N = 2 N = 3 N = 4 γ = 0.0 γ = 0.5 γ = 1.0

(b) Losses

Figure 4.8: Comparison of losses and volumes, broken down by components, between the three N-level converters for different values of γ, at 100% load, for Design Space B. 50 4.5. OPTIMIZATION RESULTS equal to 1 for the solution to be valid:

s X dp = 1 (4.61) p=1 where s is the total number of different discrete LN values. Then the constraint relating LN to dp s X LN = dpLp (4.62) p=1 ensures that LN can only take one of the values Lp. Since this introduces an additional integer variable into the MIGP for every discrete value a passive component can take, the capacitors CN and Cfly can be left as continuous values, since it has been shown in the previous subsections that their effect on the total volume and losses is small. This gives the ﬁnal MIGP formulation

P V ol minimize γ total + (1 − γ) total (4.63) Ptot,max V oltot,max

subject to ∆Tj,calc ≤ ∆Tj,max

∆Tj,calc ≤ 1.1∆Tj

PL,N ≤ PL,max

fripple,min ≤ fripple ≤ fripple,max s X LN = (dpLp) p=1 s X dp = 1 p=1

Nsw,min ≤ Nsw ≤ Nsw,max

∆Tj,min ≤ ∆Tj ≤ ∆Tj,max

dp ∈ [0, 1], dp ∈ Z

Nsw ∈ Z

where the normalization factors Ptot,max and V oltot,max are still determined by solving the original continuous GP. MIGPs are more difﬁcult to handle than standard continuous GPs, and are typically solved using branch and bound (BNB) algorithms [61]. MIGPs are non-convex and CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 51

1400

1200

1000 ) 3 800

600 Volume Volume (mm

400

200

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Losses (W)

N = 2 N = 3 N = 4

Figure 4.9: Loss-Volume Pareto fronts for N-level ML-FC converters resulting from the discrete (MIGP) version of the optimization problem, for Design Space A.

NP-hard, and consequently cannot be solved optimally and efﬁciently when there are a large number of discrete variables. YALMIP contains a BNB solver which is used in conjunction with

Matlab’s FMINCON solver to produce a solution for the MIGP. The time it takes to solve the 6 normalization GPs and the 63 MIGPs is over 10 times longer than the time it takes to solve the continuous GPs (cf. Table 4.7). Results for Design Space A are given in Fig. 4.9.

To compensate for the slow performance of the MIGP solver, a heuristic for discrete design can be introduced: simply rounding off the results given by the continuous relaxation GP from the previous subsections (it was shown in [77] that re-solving for the continuous variables after the discrete ones are rounded-off gives no beneﬁt). Nsw can be calculated from Asw using

(4.60) and rounded off to the nearest integer, and LN can be rounded off to the closest value in Table 4.11. The Pareto fronts resulting from this rounding approach for Design Space A are given in Fig. 4.10.

A comparison of the results given by the three aforementioned approaches is given in

Fig. 4.11. As can be seen, the rounded-off solutions closely approximate the original continuous solutions in every case. This is also true for the MIGP solutions for N = 2. For N = 3 and N = 4, as seen in Fig. 4.11b and Fig. 4.11c, the MIGP solutions deviate greatly from the ideal, continuous Pareto front. This is explained by the fact that in this case, the YALMIP BNB solver was exceeding its maximum number of allowed iterations. By raising this maximum, 52 4.5. OPTIMIZATION RESULTS

1400

1200

1000 ) 3 800

600 Volume Volume (mm

400

200

0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Losses (W)

N = 2 N = 3 N = 4

Figure 4.10: Loss-Volume Pareto fronts for N-level ML-FC converters resulting from the rounding off of results of the continuous (GP) version of the optimization problem, for Design Space A. the MIGP solutions would likely more closely approximate the continuous ones, but this would also increase the running time. In any case, the rounding off heuristic produces better solutions much more quickly, rendering the MIGP formulation (4.63) unnecessary.

4.5.4 Sensitivity Analysis

As noted in Section 3.3, the local sensitivities to all constraints are available as soon as the

GP is solved. The sensitivity to the thermal constraint ∆Tj,calc ≤ ∆Tj,max at different values of the design goal γ is shown in Fig. 4.12. From the graph it can be read, for example, that the sensitivity to the thermal constraint for N = 2, γ = 0 is equal to 0.62. This means that if the thermal constraint is loosened (a higher Tj,max is allowed) by 10%, the minimum achievable volume will decrease by no more than 6.2%. Conversely if the thermal constraint is tightened by the same percentage (a lower Tj,max is allowed), the minimum volume will increase by no more than 6.2% [61]. Looking at the graph, it can be seen for which design goals – i.e., for which portion of the Pareto front – the optimum designs in the Pareto set are thermally limited.

It can also be concluded that for N = 3 and N = 4, the thermal limitation is not an issue over the entire range of design goals, as the sensitivity for each γ is zero. Fig. 4.13 shows likewise the local sensitivity to fripple,min, the lower bound of the ripple frequency. It can be seen that CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 53

1400

1200

1000 ) 3 800

600 Volume (mm

400

200

0 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 Losses (W)

Continuous Rounded Mixed Integer

(a) N = 2

1200

1000

800 ) 3

600 Volume Volume (mm 400

200

0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Losses (W)

Continuous Rounded Mixed Integer

(b) N = 3

1200

1000

800 ) 3

600 Volume Volume (mm 400

200

0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Losses (W)

Continuous Rounded Mixed Integer

Figure 4.11: Comparison of the Pareto fronts for Design Space A produced by the continuous GP, the rounded-off continuous GP, and the MIGP. 54 4.5. OPTIMIZATION RESULTS

0.6

0.5

0.4

0.3

Local Local sensitivity 0.2

0.1

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Design goal γ

N = 2 N = 3 N = 4

Figure 4.12: Local sensitivity of the optimum to the MOSFET thermal constraint across the entire range of design goals γ.

0.7

0.6

0.5

0.4

0.3 Local Local sensitivity 0.2

0.1

0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Design goal γ

N = 2 N = 3 N = 4

Figure 4.13: Local sensitivity of the optimum to the lower bound of fripple across the entire range of design goals γ. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 55 the sensitivity is zero until γ = 0.6, when it begins to rise sharply for all N. This indicates the portion of the Pareto front on which the optimal designs are selecting a fripple close to fripple,min. The graph makes sense intuitively, as this is the portion of the Pareto front closer to the most efﬁcient design, which always converges to fripple,min (see Table 4.8). Once the sensitivity line acquires a constant slope, this means that all designs are always converging on the use of fripple,min. This happens past γ = 0.65 for N = 2 and N = 3, and past γ = 0.7 for

N = 4. It can also be seen that the conventional buck is more sensitive to fripple,min than the multi-level converters. For example, at γ = 1, a 20% increase in fripple,min would increase the minimum attainable losses for N = 2 by no more than 13%, while for N = 3 and N = 4 the losses would increase by more than 9.6% and 9.2% respectively for the same case.

4.5.5 Trade-Off Analysis

To examine the global sensitivies of the optimum converter designs to the design variable bounds, trade-off analysis was performed (see Section 3.3). The upper bound Asw,max on the semiconductor area was varied from the minimum value to the maximum value of Asw, with the GP re-solved at each step for γ = 0 and γ = 1. The trade-off curves showing the impact of the upper bound of Asw on the most efﬁcient and most compact design possible are shown in Fig. 4.14, for Design Space A. As it can be seen from Fig. 4.14a, varying the bound has no effect on the maximum possible efﬁciency at N = 2. This is due to the fact that the γ = 1 design for the conventional buck uses the minimum available Asw in any case (cf. Table 4.8).

For the other two values of N, the minimum loss achievable drops until Nsw,max > 2, from which point on it is ﬂat. On the other extreme of the Pareto set, as can be seen from Fig. 4.14b, varying Asw,max has no effect on the minimum possible volume for N = 3 and N = 4, but sur- prisingly at N = 2 it drops until Nsw,max > 2. This was explained in the previous subsection – restricting the MOSFET area requires the reduction of ∆iL,N,pp to meet the thermal constraint, requiring a larger inductor and causing a larger overall volume. It can be concluded from both cases that for Design Space A, Asw,max could have been set at a much lower value than the one initially selected in Table 4.4.

This same procedure was repeated for the other two design variables, but at both the lower 56 4.5. OPTIMIZATION RESULTS

0.45 350

0.44 300 0.43 ) 0.42 3 250 0.41

0.4 200

0.39

Minimum Loss (W) 150 0.38 MinimumVolume (mm 0.37 100 0.36

0.35 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Maximum allowed switch area (number of switches) Maximum allowed switch area (number of switches)

N = 2 N = 3 N = 4 N = 2 N = 3 N = 4

(a) γ = 1 (b) γ = 0

Figure 4.14: Trade-off curves showing the impact of the upper bound of the allowed semiconductor area on the (a) the most efﬁcient possible and the (b) most compact possible design in Design Space A.

and upper bounds. First ∆iL,N,pp,min was swept from the minimum to the maximum value in

Table 4.4, then ∆iL,N,pp,max was swept from the minimum to the maximum value, and then the same was done for fripple,min and fripple,max. The run time of the entire procedure is given in Table 4.7. It was found that, as expected, the varying of ∆iL,N,pp,min has no effect on the minimum volume design (Fig. 4.15b), and that varying ∆iL,N,pp,max has no effect on the minimum loss design (Fig. 4.16a). These curves are therefore ﬂat. The trade-off curves for the converse cases are shown in Fig. 4.15a and Fig. 4.15b. It can be seen that the maximum achievable efﬁciency is highly sensitive to ∆iL,N,pp,min, while the minimum achievable volume is highly sensitive to ∆iL,N,pp,max. This is expected due to the inverse relationship of the losses and volume of the inductor. The sensitivity is approximately equal for all N-level designs.

More interesting are the trade-off curves for the ripple frequency. Varying fripple,max has no effect on the minimum loss design (Fig. 4.18a), as these designs naturally tend toward the lowest possible frequency (cf. Table 4.8). Fig. 4.18b shows the effect of increasing the upper bound of the ripple frequency on the minimum volume design. One would expect this to enable smaller and smaller designs, and this is indeed the case for N = 3 and N = 4.

However, for N = 2, increasing fripple,max past approximately 1.7 MHz has no effect. This is because the design is thermally limited beyond those frequencies. While the trade-off curve of the conventional buck thus ﬂattens out, the others continue to decrease, showing that a multi-level design has a higher potential for exploiting a higher ripple frequency for minimizing CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 57

0.45 170

0.44 150 0.43 ) 0.42 3 130 0.41

0.4 110

0.39

Minimum Loss (W) 90 0.38 Minimum Volume (mm 0.37 70 0.36

0.35 50 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0.3 0.5 0.7 0.9 1.1 1.3 1.5 Minimum allowed inductor ripple current (A) Minimum allowed inductor ripple current (A)

N = 2 N = 3 N = 4 N = 2 N = 3 N = 4

(a) γ = 1 (b) γ = 0

Figure 4.15: Trade-off curves showing the impact of the lower bound of the allowed inductor ripple current on the (a) the most efﬁcient possible and the (b) most compact possible design in Design Space A.

0.45 350

0.44 300 0.43 ) 0.42 3 250 0.41

0.4 200

0.39

Minimum Loss (W) 150 0.38 Minimum Volume (mm 0.37 100 0.36

0.35 50 0.3 0.5 0.7 0.9 1.1 1.3 1.5 0.3 0.5 0.7 0.9 1.1 1.3 1.5 Maximum allowed inductor ripple current (A) Maximum allowed inductor ripple current (A)

N = 2 N = 3 N = 4 N = 2 N = 3 N = 4

(a) γ = 1 (b) γ = 0

Figure 4.16: Trade-off curves showing the impact of the upper bound of the allowed inductor ripple current on the (a) the most efﬁcient possible and the (b) most compact possible design in Design Space A. 58 4.5. OPTIMIZATION RESULTS

3 180

160 2.5 ) 3 140 2

120 1.5 100

Minimum Loss (W) 1 80 MinimumVolume (mm

0.5 60

0 40 500 1000 1500 2000 2500 500 1000 1500 2000 2500 Minimum allowed inductor ripple frequency (kHz) Minimum allowed inductor ripple frequency (kHz)

N = 2 N = 3 N = 4 N = 2 N = 3 N = 4

(a) γ = 1 (b) γ = 0

Figure 4.17: Trade-off curves showing the impact of the lower bound of the inductor current ripple frequency on the (a) the most efﬁcient possible and the (b) most compact possible design in Design Space A.

0.45 400

0.44 350 0.43 ) 0.42 3 300

0.41 250 0.4 200 0.39 Minimum Loss (W) 0.38 150 MinimumVolume (mm 0.37 100 0.36

0.35 50 500 1000 1500 2000 2500 500 1000 1500 2000 2500 Maximum allowed inductor ripple frequency (kHz) Maximum allowed inductor ripple frequency (kHz)

N = 2 N = 3 N = 4 N = 2 N = 3 N = 4

(a) γ = 1 (b) γ = 0

Figure 4.18: Trade-off curves showing the impact of the upper bound of the allowed inductor current ripple frequency on the (a) the most efﬁcient possible and the (b) most compact possible design in Design Space A.

volume. This is mirrored in Fig. 4.17b, which shows the effect of varying fripple,min on the minimum volume design. One would expect these curves to be ﬂat, as they are for the 3- and

4-level converters. However, due the thermal limitation of the conventional buck, the trade-off curve for N = 2 rises sharply past 2 MHz, as the volume of the converter must increase to accommodate the losses resulting from the higher switching frequency. Finally, in Fig. 4.17a, the effect of varying the lower bound of the frequency on the minimum loss design is shown.

The conventional buck is highly sensitive, with losses increasing exponentially with frequency.

The multi-level designs are also sensitive, but much less, with losses increasing linearly with frequency. This highlights another beneﬁt of multi-level converters. CHAPTER 4. MULTI-OBJECTIVE η − ρ OPTIMIZATION OF ML-FC CONVERTERS BY GEOMETRIC PROGRAMMING 59

4.6 Adding a Cooling System to the GP Formulation

As noted earlier, modeling of a cooling system (such as a heat sink) was not dealt with in Sec- tion 4.2 due to the space constraints of the low-power application selected as the optimization example. However even in low or lower power applications, for example in automotive or industrial settings, a cooling system may be required. A cooling system of any kind can in general be characterized using the cooling system performance index (CSPI), proposed in [89,90], which relates the thermal resistance of the cooling system to the ambient, Rth,CS−a, and its total volume, V olCS: 1 CSPI = . (4.64) Rth,CS−aV olCS

Note that this assumes the use of a cooling system the CSPI of which is known or assumed.

Heat sink manufacturers will, for example, typically provide the thermal resistance of a heat sink as a function of the air ﬂow through its channels in its datasheet. Cooling systems come in various forms, and the design and optimization of a cooling system can in itself be a complex task. The use of geometric programming to design or optimize the cooling system itself is not considered in this thesis. Potentially, a heat sink based cooling system could be modeled by using the method of Chapter 5 to derive posynomial approximations of the analytical heat sink

(including fan) model of [91] or [92].

The addition of a cooling system to the previously developed GP formulation requires only a modiﬁcation of (4.34), where the junction-to-ambient thermal resistance RT h,j−a was taken from the ﬁgure given in MOSFET datasheets, which assumes no cooling system. In this case, the junction-to-case thermal resistance RT h,j−c, also available in the datasheet, should be taken instead. As in (4.34), RT h,j−c can be expressed a function of the reference thermal resistance

RT h,j−c,ref of the reference area Asw,ref . The total RT h,j−a is then the sum of RT h,j−c and

Rth,CS−a, so substituting in (4.64), (4.34) is replaced with:

Asw,ref 1 RT h,j−a = RT h,j−c,ref + (4.65) Asw (CSPI)V olCS

where the CSPI is a constant. This therefore adds a ﬁfth design variable, V olCS, to the GP formulation of Section 4.3. CHAPTER

FIVE

APPROXIMATION OF POWER ELECTRONICS MODELS USING

MULTIVARIATE POSYNOMIAL FUNCTIONS

In the previous Chapter, posynomial models of converter components were derived intuitively.

It was seen that standard MOSFET loss models can be put into posynomial form by careful algebraic manipulation. The volume model for MOSFETs and the loss model for capacitors were already in posynomial form. Since the volume of families of pre-defined inductor and capacitor components is commonly modeled using polynomial fitting, it suffices to take care that the produced fits are posynomial. A modification of this approach, informed by knowledge of inductor loss modeling, was developed to fit losses of pre-defined inductor components to a posynomial function that mimics physical loss models. The purpose of this Chapter is to provide a more generalized method for deriving posynomial models of converter components, for use in cases when such algebraic manipulation of existing models is not possible, and when the manner in which physical models should be approximated by posynomials is not obvious and difficult to derive intuitively. In such situations, posynomial functions must be fitted to data generated by non-posynomial analytical models, simulations, and measurements.

5.1 Types of Posynomial Functions

As seen in Section 3.2, posynomial functions are turned into convex form via a logarithmic transformation. One way to think of data for ﬁtting once it has been transformed into the

60 CHAPTER 5. APPROXIMATION OF POWER ELECTRONICS MODELS USING MULTIVARIATE POSYNOMIAL FUNCTIONS 61 logarithmic domain is in terms of piecewise-linear functions [93].

5.1.1 Max-Monomials and Max-Afﬁne Functions

A way of constructing a convex piecewise-linear function is through the use of a max-afﬁne

(MA) function with l terms:

al log(hm(x)) = max[log(e ) + kl1log(x1) + ... + klnlog(xn)] (5.1) 1...l which when returned to the original domain of the data x corresponds to a max-monomial function:

al kl1 kln hm(x) = max[e x1 ...xn ] (5.2) 1...l where the result is the maximum value returned by evaluating each of the l GP-monomial terms for the given value of x.

5.1.2 Posynomials and Softmax-Afﬁne Functions

In [94], an extension of the MA function, the soft-max afﬁne (SMA) function, is deﬁned as

m X log(f(x)) = log( eal+kllog(x)) (5.3) l=1 which when transformed back into the original domain of x becomes a posynomial function of the form in (3.3): m n X al Y kli f(x) = e xi (5.4) l=1 i=1 An advantage of the MA and SMA is that the coefﬁcient of each posynomial term is given as a

a a power of e so that the actual coefficient is e l . Since e l ≥ 0 for any al that is a real number, this relaxes the constraints on al from (3.3) and gives more flexibility to the fitting procedure and choice of fitting algorithm. It has been shown in [94] that the SMA function can be fitted well to a wide range of multidimensional data. It is therefore the natural choice for posynomial modeling of converter components, which can be a multidimensional problem due to the large number of design variables that can be present. 62 5.2. FITTING PROCEDURE

5.2 Fitting Procedure

The procedure for fitting SMA functions to multidimensional data, shown in Fig. 5.1, is adapted from those outlined in [93] and [94]. Although the affine, MA, and SMA functions are themselves convex, the problem of fitting data to them is generally not, and is in general a non-linear least-squares problem. Standard non-linear least-squares solvers and algorithms are available in most scientific or technical software packages such as MATLAB.

It has been found that attempting a direct fit of multidimensional data to an SMA function often gives unsatisfactory results. The reason lies in the difficulty of guessing an initial set of exponents kl of (5.4) close enough to the actual least squares solution. Setting the initial kl values either to all zero, all one, or a randomly generated set, will often cause the least-squares solvers to converge on a non-optimal fit. Also, the optimal number of terms l in (5.2) or (5.4) that produce an optimal fit is difficult to ascertain ahead of time. Therefore a gradual approach from affine to MA to SMA functions must be employed:

1. The data x that is to be ﬁt into an SMA function of form (5.4) must ﬁrst be partitioned. In

[93,94], partitioning is done at random, by choosing a random number of well-distributed

data points and forming the partitions around them, and by adding into each partition

the points closest by some geometrical measure to the randomly chosen points. If a set of

partitions results in an unsatisfactory ﬁt, a new set of partitions in chosen by selecting a

new set of points at random. To accelerate this procedure, it is however better to partition

the data according to some visible or logical division of the values of x. An example is

given in Section 5.3.

2. A local least squares ﬁt to an afﬁne (i.e. monomial) function of the form of (3.6) must then

be performed in each partition. This results in as many afﬁne ﬁts as there are partitions.

Since each partition contains only a subsection of the data, a good ﬁt to an afﬁne function

should be obtained in each. If this is not the case, it means that the data should be

re-partitioned.

3. The local afﬁne ﬁts from each partition must then be gathered into an initial MA function.

The number of terms l is therefore equal to the number of partitions. The coefﬁcients [Replace the following names and titles with those of the actual contributors: Dorena Paschke, PhD1; David Alexander, PhD2; Jeff Hay, RN, BSN, MHA3, and Pilar Pinilla, MD4 1[Add affiliation for first contributor], 2[Add affiliation for second contributor], 3[Add affiliation for third contriutor], 4[Add affiliation for fourth contributor]

CHAPTER 5. APPROXIMATION OF POWER ELECTRONICS MODELS USING MULTIVARIATE POSYNOMIAL FUNCTIONS 63

ANALYTICAL SIMULATIONS MEASUREMENTS EQUATIONS

DATA

CREATE DATA PARTITIONS . . . . .

P1 P2 P3 . . . . . Pp-2 Pp-1 Pp

FIT FIT FIT FIT FIT FIT MONOMIAL MONOMIAL MONOMIAL . . . . . MONOMIAL MONOMIAL MONOMIAL ap-2 ap-1 h1(x) = h2(x) = h3(x) = hp-2(x) = e hp-1(x) = e hp(x) = a1 k11 k1n a2 k21 k2n a3 k31 k3n kp-2 kp-2 kp-1 kp-1 ap kp1 kpn e x1 …xn e x1 …xn e x1 …xn x1 …xn x1 …xn e x1 …xn . . . . . COMBINE TO FORM INITIAL MAX-MONOMIAL

FIT MAX-MONOMIAL al kl1 kln hm(x) = max(l=1…p)[e x1 …xn ]

USE RESULT TO FORM INITIAL POSYNOMIAL

FIT POSYNOMIAL a1 k11 k1n ap kp1 kpn p(x) = e x1 …xn + … + e x1 …xn

Figure 5.1: The procedure for ﬁtting multidimensional data to multivariate posynomial functions.

• List objectives here • Result 1 • Conclusion 1 • Objective 1 • Result 2 • Conclusion 2 • Objective 2 • Result 3 • Conclusion 3 • Objective 3 64 5.3. FITTING EXAMPLE - HIGHER POWER INDUCTORS

calculated from the local ﬁts are used as an initial guess for the values of al and kl of the MA function. A global least-squares ﬁt to an MA function of the form (5.1) is then

performed over all the data x.

4. Finally, the values of al and kl resulting from the MA fit must then be used as an initial guess for the same values of the SMA fit. With the results of the MA fit as initial values,

an SMA ﬁt to a function of the form (5.3) can then be ﬁnally performed globally over all

of the data x. The number of terms is equal to the number of terms of the MA function,

i.e. the number of partitions.

The above procedure enables a good fit of multidimensional data to an SMA function to be made. Proper partitioning determines the number of terms in the SMA function, while the exponents and coefficients are first determined on localized, more tractable problems and then improved iteratively with each step.

5.3 Fitting Example - Higher Power Inductors

Inductors account for a major part of the volume and losses of power electronic converters [17, 29–31, 75], as was seen on the example of ML-FC converters in Section 4.5. Special care must be paid to their design when optimizing converters for efﬁciency and power density. In fact, the magnetic component optimization sub-problem is often the most complex and challenging part of converter optimization [29, 30, 95]. Meaningful optimization of magnetic components depends on accurate calculation of their losses under diverse operating conditions.

The accurate calculation of core losses is especially challenging, and the entire problem is very complex [83] as the effects of all electric and magnetic operating conditions (including DC pre- magnetization) must be taken into account together with core and winding temperature, and the thermal cross-coupling between the core and the windings.

A diverse literature on inductor optimization exists. Similar to the literature on overall converter optimization, it focuses either on analytically-derived models, such as in [17, 30, 31,

96, 97], measurement-based simulation models [83, 95], and ﬁnite-element simulation models

[98, 99]. [98], [99] and [97] are notable for their use of genetic algorithms for optimization, CHAPTER 5. APPROXIMATION OF POWER ELECTRONICS MODELS USING MULTIVARIATE POSYNOMIAL FUNCTIONS 65

(a) Inductor waveforms in buck- and DC-DC (b) The free design variables when building an boost-type converters inductor from EE cores.

Figure 5.2: The type of inductor considered in the ﬁtting example. while the remainder utilize mostly exhaustive search.

5.3.1 Inductor Type and Application

Analytical inductor loss models, especially for the core loss, are limited and valid only over a given operating range. There are many cross-coupling effects between winding and core losses [83]. Therefore, the only accurate way to calculate losses is via simulation, as was done for low-power inductive components in Section 4.2. In this Chapter, the optimization of higher power inductors is considered, where the inductor component is not pre-deﬁned and pre-packaged but custom-built from a selection of cores and wires.

The design variables in this case are shown in Fig. 5.2b, using the example of an inductor built from EE cores: the number of cores to use nc, the air gap lg, the number of turns N, and the wire thickness (most conveniently expressed as a winding window ﬁll factor FF ).

The electrical operating point of the inductor inﬂuences both the losses PL and the sizing of the component, which inﬂuences the volume V olL. The relevant quantities are illustrated in Fig. 5.2a, where the familiar inductor waveforms for buck- and DC-DC boost-type converters are given as an example. Therefore, the applied voltage ∆VL, average DC current IL, current ripple ∆IL, and frequency f must be taken into account. The temperature of the component must also be considered. Since the temperature depends on the losses, the independent variable is therefore the ambient temperature Tamb. 66 5.3. FITTING EXAMPLE - HIGHER POWER INDUCTORS

Table 5.1: Converter Application and Operating Point

Input voltage Vin 48 V Output voltage Vout 12 V Output current Iout 7 - 12 A Ambient temperature Tamb 25°C Core and material EPCOS E55, N87

Furthermore, it is important to know whether an inductor design has saturated at a given operating point, i.e. if the core ﬂux density has gone over the maximum allowed for that core material. It is therefore of interest to derive functions of the following form:

PL = f1(∆VL,IL, ∆IL, f, nc, lg,N,FF ) (5.5)

V olL = f2(∆VL,IL, ∆IL, f, nc, lg,N,FF )

Tcore = f3(∆VL,IL, ∆IL, f, nc, lg,N,FF )

Twinding = f4(∆VL,IL, ∆IL, f, nc, lg,N,FF )

Sat = f5(∆VL,IL, ∆IL, f, nc, lg,N,FF )

where fi are SMA posynomial functions in the form of those shown in (5.4). The ﬁnal quantity Sat should be greater than 1 if the inductor is in saturation and therefore an unusable design.

5.3.2 Simulation and Fitting

To generate the data for posynomial ﬁtting, an inductor for a DC-DC buck converter operating as shown in Table 5.1 was simulated over a range of switching frequencies, output currents, inductor current ripples, and physical inductor design parameters as shown in Table 5.2. These simulations were performed using GeckoMAGNETICS1 [100], which is based on the comprehensive inductor model developed in [83]. This gave a total of 1289 data points. For each combination of operating point and design variable quantities, i.e. at each data point, the total losses, volume, core temperature, winding temperature, and saturation condition were recorded.

Using MATLAB, the data was partitioned into two sets based on the frequency of the current

1The calculation core of GeckoMAGNETICS was largely written by the author of this thesis during his time at ETH Zürich and Gecko-Simulations AG, from 2012 to 2015. CHAPTER 5. APPROXIMATION OF POWER ELECTRONICS MODELS USING MULTIVARIATE POSYNOMIAL FUNCTIONS 67

Table 5.2: Range of Inductor Design Variables Simulated Design variable Min. value Max. value Switching frequency f 18 kHz 48 kHz

Current ripple, peak to peak ∆iL 0.1IL 0.4IL Air gap lg 0.25 mm 1.0 mm Number of stacked cores nc 1 4 Fill factor FF 0.1 0.7 waveform, with lower frequencies in one partition and higher in the other. An SMA posynomial function was then ﬁt to the results using the procedure outlined in Fig. 5.1. The loss ﬁt gave an average error of 10.4% compared to the simulation results - which is within the error of

GeckoMAGNETICS simulations when compared to experimental results in certain cases [83,

101]. Volume, temperature, and saturation data was ﬁtted with even lower errors compared to simulation, as shown in Table 5.4. The derived posynomial expressions for total losses, boxed volume, core and winding temperature, and the saturation condition in this example, where

∆VL and Tamb are omitted as they are constant, and the integer variable nc is replaced by the real-valued resulting inductance L in order to achieve a better ﬁt, are given in Table 5.3.

5.3.3 Optimization Results

The multi-objective optimization of inductors for losses (efﬁciency) and volume (power density) can therefore be formulated as a geometric program in the following way:

P V ol minimize γ L + (1 − γ) L (5.6) PL,max V olL,max

subject to Tcore ≤ Tmax

Twinding ≤ Tmax

Sat ≤ 1.01

where Tmax is the maximum allowable temperature of the inductor. As in Section 4.3, the normalization factor PL,max - the maximum possible losses in the given design space - is derived by minimizing (5.6) for the volume only (i.e. γ = 0) and then calculating the losses of that minimum-volume design. Similarly, the normalization factor V olL,max - the maximum possible 68 5.3. FITTING EXAMPLE - HIGHER POWER INDUCTORS

Table 5.3: Posynomial Models Derived From Simulation

PL[W ] = −6.0631 1.1813 0.0718 −1.0063 2.3202 0.2450 1.0821 −0.0343 e L N (1000lg) ∆IL IL f FF −6.4292 −0.5766 1.1049 0.2825 0.4946 1.2980 −0.6408 −0.4949 +e L N (1000lg) ∆IL IL f FF

V ol[m3] = −4.6094 −5.1598 1.3502 −0.5282 −4.8747 −1.4170 −4.5997 1.2685 e L N (1000lg) ∆IL IL f FF 3.8203 1.1614 −1.9220 0.7552 0.2451 0.1116 0.2422 0.0446 +e L N (1000lg) ∆IL IL f FF

◦ Tcore[ C] = 0.5648 −0.7187 0.5152 −0.5337 −0.1637 −0.0107 −0.5213 0.0413 e L N (1000lg) ∆IL IL f FF −0.0172 0.6982 −0.2495 1.2176 0.0256 1.4824 0.6125 −0.1169 +e L N (1000lg) ∆IL IL f FF

◦ Twind[ C] = 0.6156 0.4714 −0.0047 −0.0695 0.6719 0.6318 0.4644 0.0202 e L N (1000lg) ∆IL IL f FF −4.2458 −2.1699 2.0525 0.3287 −1.1485 0.3329 −1.8299 −0.4741 +e L N (1000lg) ∆IL IL f FF

Sat = −0.3650 0.3952 −1.3325 −0.1931 −0.3167 −0.4861 −1.4066 −0.3525 e L N (1000lg) ∆IL IL f FF +1

Table 5.4: Fitting Errors To Simulation Results Quantity Average Error R2

Total losses PL 10.4% 0.9131 Boxed volume V olL 1.7% 0.9972 Core temperature Tcore 3.5% 0.9540 Winding temperature Twind 6.5% 0.8040 Saturation condition 5 × 10−9% 1.0 CHAPTER 5. APPROXIMATION OF POWER ELECTRONICS MODELS USING MULTIVARIATE POSYNOMIAL FUNCTIONS 69

0.0005

0.0004 ) 3

0.0003

0.0002 Boxed Volume (m Volume Boxed

0.0001

0 0 1 2 3 4 5 6 7 8 Losses (W)

Simulated inductors GP-calculated Pareto front Figure 5.3: Losses and volumes of the inductor designs simulated to derive the posynomial models in Table 5.3, and losses and volumes of the set of Pareto-optimal solutions - the Pareto front - calculated by solving (5.6) using those models for 20 different values of γ between 0 and 1. volume in the given design space - is derived by minimizing (5.6) for the losses only (i.e. γ = 1) and then calculating the volume of that minimum-loss design. Then, by solving (5.6) repeatedly with different values of γ between 0 and 1, the set of Pareto-optimal solutions with respect to losses and volume in the given design space can be calculated.

The posynomial models shown in Table 5.3 were used with (5.6) to derive a loss-volume

Pareto front in the design space of Table 5.2. The GP was solved in MATLAB using CVX. The

Pareto front resulting from the GP solutions is shown in Fig. 5.3, along with all of the inductor designs simulated to initially derive the models. The calculated Pareto front bounds the simulated designs as expected, showing the validity of the posynomial models and the GP formulation of the optimization problem. CHAPTER

SIX

7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT

SIMULATION-COUPLED GEOMETRIC PROGRAM

SW SW 1 V 3 L1 + Cfly -

Cfly

SW2

SW7 + Vin L2 C R Vout -

SW4 SW5 SW6

Figure 6.1: The Seven-switch ﬂying capacitor (7SFC) step-down converter.

The Seven-switch ﬂying capacitor (7SFC) step-down converter, introduced in [102, 103], and shown in Fig. 6.1, is a versatile point-of-load (PoL) topology concieved to operate over a wide range load currents and voltage conversion ratios. The 7SFC has the potential to achieve superior efﬁciency compared to conventional PoL solutions. This is because its seven switches allow it to operate in three distinct modes, as three different previously known converter topologies, thereby combining the advantages of all three over a wide range of conversion ratios and loads. It can operate as the high-step down two-phase interleaved buck, or Nishijima converter [104, 105], which is advantageous at medium and heavy loads at high input to output

70 CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 71 voltage step-down ratios. The Nishijima converter however suffers from poor efﬁciency at light loads. To circumvent this, the 7SFC converter can also operate as a Meynard 3-level ML-FC converter, already discussed in Chapter 4. The Nishijima topology is limited by design to conversion ratios M(D) < 0.25. The Meynard mode as implemented in the 7SFC is limited to conversion ratios M(D) < 0.5, in order to keep the design simpler and more compact [103].

Therefore for conversion ratios M(D) ≥ 0.5, the 7SFC converter can operate as the well-known conventional two-phase buck [106, 107].

This versatility allows the 7SFC to theoretically always operate at high efficiency, by selecting the operating mode which will produce the peak efficiency at the current operating point. If the 7SFC power stage is to be implemented as an “off-the-shelf” integrated circuit (IC) suitable for a broad range of a PoL applications, fulfilling this high-efficiency promise is a significant challenge. The seven switches, which do not all experience equal voltage and current stresses, neither within one mode of operation nor across different modes, must be sized so that the efficiency remains high over the entire operating range. This requires the evaluation of many possible switch sizings at different operating points quickly. Therefore an automated optimization procedure is required, which is the focus of this Chapter.

Unfortunately, the 7SFC converter, due to its complexity, cannot be modeled using geometric programming on the converter level. The method developed for ML-FC converter in Chapter

4 cannot be applied directly. It can, however, be modeled as a geometric program on the component level, and this component-level model can be combined with a simulation model of the converter running in a fast power electronic circuit simulator to produce optimized power stage designs quickly.

The detailed description of the 7SFC converter IC prototype designed with the help of this optimization procedure is given in [108]. 72 6.1. 7SFC CONVERTER OPERATION

6.1 7SFC Converter Operation

The three modes of operation are reviewed here only brieﬂy. For a more detailed description and analysis, the reader is referred to [102,103,108]. The conversion ratio M(D) is deﬁned as

V M(D) = out (6.1) Vin

where Vin and Vout are the DC input and output voltage of the converter, respectively.

6.1.1 Nishijima mode

The manner of operation of the 7SFC in Nishijima mode is depicted in Fig. 6.2(a). The conversion ratio in this mode is D M(D) = (6.2) 2 where D is the duty ratio as shown in Fig. 6.2(b). In Nishijima mode, the maximum achievable value of D is 0.5, and therefore the maximum conversion ratio is 0.25. MOSFET SW3 is con- stantly in the on-state in this conﬁguration. The voltage VCfly across the ﬂying capacitor Cfly is V V = in (6.3) Cfly 2 which is also the maximum blocking voltage experienced by the switches. In this mode, transistors SW2, SW5, SW6, and SW7 experience soft switching transitions for both turn-on and turn-off.

Aside from the maximum value of M(D), another limitation of the Nishijima converter is that it cannot perform phase shedding to improve efﬁciency at light loads. The solution to both of these limitations is the Meynard mode of operation.

6.1.2 Meynard mode

The manner of operation of the 7SFC in Meynard mode is depicted in Fig. 6.3(a). The conversion ratio in this mode is

M(D) = D (6.4) CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 73

(a) State 1: 0 < t < DTs

VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + V Vin L2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

States 2 and 4:

DTs < t < Ts/2 Ts/2 + DTs < t < Ts

VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + Vin VL2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

State 3: Ts/2 < t < Ts/2 + DTs

VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + Vin VL2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

(b) State 1 State 2 State 3 State 4 Vin - VCfly - Vout VL1(t) t

- Vout

iL1(t) t

VCfly - Vout VL2(t) t

- Vout - Vout

iL2(t) t

0 DTs Ts/2Ts/2 + DTs Ts Figure 6.2: Operation of the 7SFC in Nishijima (two-phase interleaved high step-down buck) mode: (a) switching sequence, with the path of current conduction shown in each state (b) inductor voltage and current waveforms. 74 6.1. 7SFC CONVERTER OPERATION

States 2 and 4: (a) State 1: DTs < t < Ts/2 0 < t < DTs Ts/2 + DTs < t < Ts

VCfly L1 VCfly L1 SW1 + - SW3 SW1 + - SW3

Cfly + - Cfly + - VL1 iL1(t) VL1 iL1(t) SW2 SW2 SW7 SW7 + + V Vin L2 - C R Vout Vin VL2 - C R Vout + - + -

L2 L2 SW4 SW5 SW4 SW5 SW6 iL2(t) SW6 iL2(t)

State 3: Ts/2 < t < Ts/2 + DTs

VCfly L1 State 1 State 2 State 3 State 4 SW1 + - SW3 (b) Vin - VCfly - Vout VCfly - Vout Cfly + - VL1(t) VL1 iL1(t) SW2 t SW 7 - V - V + out out V Vin L2 - C R Vout iL1(t) + -

L2 t SW4 SW5 SW6 iL2(t)

Vin - VCfly - Vout VCfly - Vout VL2(t) t

- Vout - Vout

iL2(t) t

0 DTs Ts/2Ts/2 + DTs Ts Figure 6.3: Operation of the 7SFC in Meynard (single-phase three-level ﬂying capacitor buck) mode: (a) switching sequence, with the path of current conduction shown in each state (b) inductor voltage and current waveforms.

where D is likewise the duty ratio as shown in Fig. 6.3(b). The ﬂying capacitor voltage, and so the blocking voltage of the switches, is the same as in Nishijima mode as given by (6.3). In this mode transistors SW5 and SW7 are always on, putting inductors L1 and L2 in parallel, thereby effectively making one phase out of two. Similar to the previous mode of operation, only two of the switches are hard-switched, with SW2, SW3, and SW6 undergoing soft turn-on and turn-off transitions.

The switching sequence shown in Fig. 6.3 is valid for M(D) < 0.5. By the use of a different switching sequence [102], this mode of converter operation would enable the use of conversion ratios higher than 0.5. However, the corresponding gate driving implementation would not be usable for the Nishijima mode, necessitating some sort of active driving scheme [108]. This is avoided due to the complexity it would add to an on-chip implementation. Instead the two- phase interleaved buck mode is used for conversion ratios higher than 0.5. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 75

6.1.3 Two-phase interleaved buck mode

In this mode MOSFETs SW1, SW2, and SW4 are always kept in the on-state as shown in Fig. 6.4(a). The conversion ratio is the same as the in the Meynard mode as given by (6.4), however now the ﬂying capacitor voltage, and thus the blocking voltage of the switches, is equal to the input voltage, i.e. VCfly = Vin as can be seen through Fig. 6.4(b). For this reason, the input voltage in two-phase interleaved buck mode is limited to the range

1 V ≤ V (6.5) in 2 in,max

where Vin,max is the maximum input voltage the converter can operate at in the Nishijima and the Meynard modes. This is done to save semiconductor area, since it allows all of the switches

1 to be rated only for 2 Vin,max. The limitation this trade-off creates is that the 7SFC cannot 1 operate at M(D) > 0.5 when Vin > 2 Vin,max. In this mode, SW3 and SW6 have soft-switching transitions utilizing the body diode of these MOSFETs.

6.2 Hybrid Optimization Procedure

To implement the 7SFC converter power stage as an IC, each of the seven switches SWi must be sized appropriately, i.e. implemented on the chip with an appropriate area Asw,i. The seven switch areas Asw,1 through Asw,7 are therefore the design variables of the optimization problem. The ﬁrst constraint on the problem is that the combined area of the switches must be less than or equal to the total area Asw,tot available for the implementation of the power stage on the chip, 7 X Asw,i ≤ Asw,tot (6.6) i=1

6.2.1 Posynomial Component-Level Loss Models

The same component-level posynomial loss models for MOSFETs that were presented in Section

4.2 are used here. The switching loss of one switch is

1 P = f t V I + t V I + C A V 2 (6.7) sw,i 2 sw on DS,i DS,i,on off DS,i DS,i,off oss,ref sw,i DS,i 76 6.2. HYBRID OPTIMIZATION PROCEDURE

States 1 and 3:

(a) 0 < t < (D - 0.5)Ts

Ts/2 < t < Ts/2 + (D - 0.5)Ts VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + V Vin L2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

State 2:

(D - 0.5)Ts < t < Ts/2

VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + Vin VL2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

State 4:

Ts/2 + (D - 0.5)Ts < t < Ts

VCfly L1 SW1 + - SW3

Cfly + - VL1 iL1(t) SW2

SW7 + Vin VL2 - C R Vout + -

L2 SW4 SW5 SW6 iL2(t)

(b) State 1 State 2 State 3 State 4 Vin - Vout VL1(t) t

- Vout

iL1(t) t

Vin - Vout Vin - Vout VL2(t) t

- Vout

iL2(t) t

0 (D - 0.5)Ts Ts/2DTs Ts

Figure 6.4: Operation of the 7SFC in two-phase interleaved buck mode: (a) switching sequence, with the path of current conduction shown in each state (b) inductor voltage and current waveforms. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 77

where fsw is the switching frequency, VDS,i the blocking voltage of the switch, and IDS,i,on and

IDS,i,off the turn-on and turn-off current of the switch, respectively. Coss,ref is the MOSFET output capacitance per unit area, which can be derived for a given semiconductor manufacturing process using simulations in the Cadence chip design and layout tool. The conduction loss of a single switch is

2 RDS,on,ref Pcond,i = Isw,i,RMS (6.8) Asw,i where Isw,i,RMS is the RMS current through the switch. RDS,on,ref is the MOSFET on-state resistance per unit area, which can also be derived from Cadence simulations. To simplify the modeling, a constant junction temperature is assumed. Finally, the gate driving loss per switch is

Pgate,i = Cg,ref Asw,iVgfsw (6.9)

where Vg is the applied gate voltage, which can be treated as constant, and Cg,ref is the gate capacitance per unit area, which can again be derived from Cadence simulations. The passive components of the converter are not included in the optimization process. The capacitor losses, typically being small in low-power applications [77], are ignored. For the inductors, a ﬁxed inductance value is assumed and components with a known equivalent resistance RL,i are selected. The losses of one inductor are then

2 PL,j = IL,RMS,j RL,i (6.10)

where IL,RMS,j is the current through Lj. The thermal modeling of the MOSFETs done in Section 4.2 is avoided for two reasons. First, the IC manufacturer did not provide enough information to calculate the thermal resistance of the chip die per unit area. Second, the ﬁnal package, and therefore its thermal resistance, in which the manufactured IC would be placed was not known at the time of optimization.

6.2.2 Converter-Level Modeling

Expressions (6.7) – (6.9) are posynomials in Asw,i at the level of an individual MOSFET, for a given operating point where all the voltages and currents can be taken as constant. However, 78 6.2. HYBRID OPTIMIZATION PROCEDURE

at the converter level, this is not the case. Consider for example the RMS current of SW2 in Nishijima mode, which is given by [102]

2 " 2# 2 1 2 1 ∆isw,2,sr Isw,2,RMS = − D Isw,2,srα 1 + (6.11) 2 3 2Isw,2,srα 2 " 2# 1 2 1 ∆isw,2,sr + − D Isw,2,srβ 1 + 2 3 2Isw,2,srβ " # I 2 1∆i 2 + D2 out 1 + sr,γ 2 3 Iout

where Iout is the average output current of the converter. Isw,2,srα and Isw,2,srβ are the average currents of SW2 during State 2 and State 4, respectively (cf. Fig. 6.2). It sufﬁces to examine one of them:

I RDS,on,ref + RDS,on,ref + I RDS,on,ref L1,srα Asw,7 Asw,5 out Asw,6 Isw,2,srα = (6.12) R 1 + 1 + 1 + 1 + 1 DS,on,ref Asw,2 Asw,3 Asw,5 Asw,6 Asw,7

Observe that (6.11) is not a posynomial expression. Both the numerator and denominator of (6.12) are posynomial in Asw,i, but a posynomial divided by a posynomial is not itself a posynomial [61]. The equations for Isw,2,srβ and the ripple currents ∆isw,2,sr and ∆isr,γ have the same structure. The expressions for the remaining RMS currents Isw,i,RMS are similar to (6.11), with some also containing negative coefﬁcients [102]. The same holds for the on and off currents IDS,i,on and IDS,i,off . The reason for this is that in the 7SFC, unlike in most conventional power converters, the current is able to take multiple paths, via different sets of switches, from the input to the output within a single switching state. This can be seen clearly for all three modes respectively in Fig. 6.2, Fig. 6.3, and Fig. 6.4. Therefore, the RMS current through one switch depends on the on-state resistances, and therefore the areas, of other switches. This makes a posynomial converter-level model impossible.

Notwithstanding the desire to frame the optimization problem as a GP, working with equations of the form of (6.11) and (6.12) is cumbersome. This motivates modeling the 7SFC in a fast circuit simulator. One such simulator is GeckoCIRCUITS [109], which, besides being very efﬁcient, has a scripting interface1 via which it can be integrated with other software packages,

1Developed by the author during his time at ETH Zürich and Gecko-Simulations AG. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 79

80 (%)

70 Efficiency Efficiency 60 Peak efficiency point Efficiency constraint points 50

20 40 60 80 100

Output Load (% of Iout) Figure 6.5: A generalized hypothetical reference efficiency curve for particular operation condition of the 7SFC converter, showing desired efficiency at operating points defined as a percentage of Iout. such as MATLAB. The 7SFC converter model in GeckoCIRCUITS reaches steady-state in a few seconds, and the relevant currents and voltages can be extracted easily. The control portion of the model can be coded in such a way as to easily facilitate switching between the three converter modes before and during simulation.

6.2.3 Simulation-coupled GP

The overall optimization procedure for sizing the switches of the 7SFC needs to combine a

GP with a simulation model. The converter can be optimized for each operating condition: a combination of a particular operating mode deﬁned by a Vin, Vout, and a maximum output current Iout. Furthermore, a particular operating point at which converter losses should be minimized must be selected for the optimization. This can be done by examining reference efﬁciency curves, usually supplied by manufacturers or potential users of power converter ICs.

These curves specify the desired efficiency under a particular operating point over the range of the output current up to Iout. A generalized reference efficiency curve is given in Fig. 6.5. Such curves typically have a peak efficiency point. This point should be selected as the operating point at which to optimize the converter, since this guarantees maximum efficiency. In the example of Fig. 6.5, the peak efficiency point is at 80% of Iout. The rest of the efficiency curve should be added as a set of constraints to the optimization problem. Points at 20%, 40%, 60%,

80%, and 100% of Iout, as marked on Fig. 6.5, are taken from the efﬁciency curve to get the maximum allowable losses Ptot,max,20% through Ptot,max,100% across the load current range. 80 6.2. HYBRID OPTIMIZATION PROCEDURE

The total losses at Y % of Iout are therefore

7 2 X X Ptot,Y % = (Psw,i,Y % + Pcond,i,Y % + Pgate,i,Y %) + PL,j,Y % (6.13) i=1 j=1

Losses at the peak efﬁciency point are denoted Ptot,pkeff . Furthermore, there is a minimum size

Amin that each switch can be implemented with. This limit arises from the electromigration constraints of the underlying implementation technology, which dictate a minimum amount of metal per switch. If the switch is too small, this requirement is difﬁcult or impossible to meet.

This gives the GP

minimize Ptot,pkeff (6.14)

subject to Ptot,20% ≤ Ptot,max,20%

Ptot,40% ≤ Ptot,max,40%

Ptot,60% ≤ Ptot,max,60%

Ptot,80% ≤ Ptot,max,80%

Ptot,100% ≤ Ptot,max,100% 7 X Asw,i ≤ Asw,tot i=1

Asw,i ≥ Amin, i = 1 to 7

where the only variables are the seven areas Asw,i, and all of the other terms from (4.12) - (4.47) are constants.

The overall efﬁciency optimization procedure, implemented in MATLAB, is shown in Fig. 6.6.

First, an operating condition is selected. From the reference efficiency curve, the optimization operating (peak efficiency) point and the constraint points are derived. For the first simulation run, all switches are sized equally, so that each takes up one seventh of the available area. This allows an initial set of on-resistances to be calculated. With this data the GeckoCIRCUITS simulation model of the 7SFC is initialized. The converter is simulated at all six operating points

(the peak efﬁciency point and the constraint points) to steady-state. From each simulation, the required voltages and currents (VDS,i, IDS,i,on, IDS,i,off , Isw,i,RMS, and IL,RMS,j) are ex- CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 81 tracted, and then entered into (6.14) which is then solved using CVX. Since the solution of

(6.14) then produces areas Asw,i and therefore on-resistances different from what was initially assumed, these new on-resistances must be sent again to the GeckoCIRCUITS converter model and the simulations repeated. The procedure therefore iterates back and forth between the simulation and the GP until the on-resistances fed into the simulation and those resulting from the optimization after the simulation converge to the same value. The resulting optimized design is simulated over the entire output current range in all three modes. This produces three efﬁciency curves that can be used to evaluate the design. Then the entire procedure can be repeated again for a different operating condition. The MATLAB code is given in Appendix B.

6.3 Optimization Results

The selected implementation technology was a high-voltage 0.18 µm process. Table 6.1 gives the characteristic values of the devices in this process, which were extracted from Cadence simulations. The on- and off-times were determined using Cadence simulations. They were measured for a nominal Vg of 5 V. The power consumed by hard-switched devices during their transitions was measured, and the duration of elevated consumption recorded. This yielded a value that was typically around 2 ns. It is important to note that the ton and toff are not strictly pegged to a percentage of the rise or fall time. This is because the RDS,on of these devices varies very little after a certain value of Vg. Hence what is most important is the time required to gain sufﬁcient clearance over the device threshold voltage. Increasing or reducing Vg will reduce or increase these times, respectively.

The total chip area available for implementing the seven MOSFETs was 3.5 mm2. Each switch must take up at least 10% of this area. The selected switching frequency, inductances and capacitances are given in Table 6.2. Their selection is discussed in more detail in [108].

The maximum output current (100% load) was 2 A in all cases. Twelve different operating conditions, i.e. twelve different values of M(D), were envisioned for the converter IC. A reference efﬁciency curve was derived for each based on the stated performance of currently available commercial power management ICs. The 7SFC was optimized for each operating condition – the resulting switch areas are given in Table 6.3. The GPs were modeled using the CVX con- 82 6.3. OPTIMIZATION RESULTS

Define design space constants:

Coss,ref, RDS,on,ref, Cg,ref, Amin, Asw,tot

Define operating constants:

fsw, L1, L2, RL1, RL2, ton, toff, Cfly, C

Select operating condition and reference efficiency curve:

Iout,pkeff, Vin, Vout, Iout + Pout,Y%

MATLAB

Assume initial Asw,i RDS,on,i

Simulate in GeckoCIRCUITS to steady-state New RDS,on,i

Extract voltages and currents

VDS,i, IDS,i,on, IDS,i,off Isw,i,RMS, IL,i,RMS

Solve GP in CVX Repeat for another operating condition operating another for Repeat

Asw1, Asw2, Asw3 Asw4, Asw5, Asw6, Asw7 No Assumed RDS,on,i = Resulting RDS,on,i ? Yes

Simulate over entire range of Iout in all three modes

Store efficiency curves and sizings for comparison Asw3 Asw4 Asw2

Asw1 Asw5 Asw7 Asw6

Select final design:

Asw1, Asw2, Asw3, Asw4, Asw5, Asw6, Asw7 Figure 6.6: The hybrid simulation-geometric programming efﬁciency optimization procedure. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 83

Table 6.1: Characteristic Values of Employed 0.18 µm Process

2 Coss,ref 284 pF/mm 2 RDS,on,ref 27.58 mΩ-mm 2 Cg,ref 698.3 pF/mm

ton 2 ns

toff 2 ns

Table 6.2: Constant Parameters in the 7SFC Optimization Process

2 Asw,tot 3.5 mm 2 Amin 0.35 mm

L1 = L2 1 µH

RL,1 = RL,2 30 mΩ

Cfly 40 µF C 200 µF

Vg 5 V

fsw 800 kHz

Iout 2 A vex optimization package for MATLAB [64], and solved using MOSEK. The overall procedure in each case converged within two to three iterations between the GP in CVX and the circuit simulation in GeckoCIRCUITS. Each of the twelve optimizations took about 70 seconds on a high-end desktop machine with 16 GB of RAM, an Intel quad-core i7-4790K processor operating at 4 GHz, a 256 GB solid-state drive, and running Windows 7.

As can be seen from Table 6.3, the optimal sizing of the switches differs greatly based on mode and M(D). Some patterns can be discerned from the results. It is clear from Section 6.2 that increasing the area of a switch decreases its conduction loss, but increases its switching loss. In 2-phase interleaved buck mode (operating conditions 1 and 6), SW2, which is always on but conducts only a part of the load current during only one of the four converter states, is always held at Amin. Clearly, due to the sparse utilization of this switch in this mode, it does not make sense to increase its area (which would decrease its conduction loss) at the expense of the other switches. On the other hand, SW1 and SW4, which are also always on but conduct the full current in every converter state, are always the two largest resulting switches. This make sense, since increasing them lowers their on-resistance and thus their conduction loss, while creating no switching loss penalty as these MOSFETs do not switch in this mode of operation. SW3 and 84 6.3. OPTIMIZATION RESULTS

SW6 experience switching losses due to Coss and Cg despite their soft-switching transitions. As they both conduct only a part of the current in only one of the four converter states, it is clear that the switching losses are more signiﬁcant, and that there is no advantage in increasing them beyond the minimum size at the detriment of the other switches. SW7 conducts part of the current in three out of four converter states, but also experiences hard switching. It is thus sized larger than Amin, but smaller than SW1 and SW4.

When optimizing for Nishijima mode (operating conditions 2, 3, 4, 7, 8 and 11), SW7 is always held at Amin. This is explained by the fact that this switch conducts a small portion of the current, and only in two of the four converter states (see Fig. 6.2). As a result of this its conduction losses are very small. There is thus no beneﬁt to increasing its area to reduce the on-resistance, while doing so would increase the switching and gating losses. SW1 and SW4 tend to be among the smaller switches, since they undergo hard-switching. Other than this, the results vary greatly based on the value of M(D) and the resulting balance of switching and conduction losses. For example, when M(D) is very low (operating conditions 3, 7, and 11), thus making the input current, and therefore the current through SW1, very low, SW1 is held at the minimum allowable area as switching losses are more dominant. However for larger values of M(D) (operating conditions 4 and 8), the area of SW1 is increased to account for the higher current it conducts. A similar observation can be made for SW4. The optimal sizes of the remaining switches do not follow such a pattern and appear to be speciﬁc to each operating condition.

When optimizing for Meynard mode (operating conditions 5, 9, 10, and 12), SW6 is always sized to Amin, analogous to the infrequently conducting switches in the previous cases. SW2 are SW3 are always sized identically or near identically, since they both undergo soft-switching and conduct the same RMS current [102]. The same is true for SW1 and SW4, although these are always smaller than the previous pair due to the inﬂuence of hard-switching. One might expect that SW5 and SW7, being always on and conducting approximately half the load current in at least two of the converter states would be apportioned a large part of the chip, similar to their always-on counterparts in 2-phase interleaved buck mode. This, however, is not the case, and for example in operating conditions 5 and 9 SW5 is assigned the minimum area. It is clearly more beneﬁcial to reduce conduction losses in the switching MOSFETs in this mode. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 85

These results underline the need for the structured, quick optimization procedure described in the previous Section. Taking into account the conﬂicting directions into which each of three modes points the design decisions would, in the absence of the optimization procedure, take weeks or months. Instead, the decision was reduced to one of 12 optimal designs in approximately 15 minutes. To achieve a more accurate comparison, each of these 12 designs was then simulated in Cadence, at each of the 12 operating conditions in all three modes (where possible). For the sake of brevity, only a small portion of these simulation results is shown here.

The simulated efﬁciencies of designs #3, #8, and #9 from Table 6.3 are shown in Fig. 6.7. In

Fig. 6.7a, all three designs are shown simulated in 2-phase interleaved buck mode for operating condition 1. As can be seen, all three designs perform similarly, and despite neither being optimized for the 2-phase interleaved buck mode, they outperform the reference efﬁciency curve, except at the very lowest load current. Design #8 achieves slightly better efﬁciency than

#3 and slightly poorer efﬁciency than #9. Similar results were found when the designs were simulated at other operating conditions in the 2-phase interleaved buck mode.

Fig. 6.7b shows the efficiency of three designs in both the Nishijima and Meynard modes for operating condition 3. All simulated efficiencies outperform the reference efficiency curve across the entire load current range. As expected, design #3 performs the best as it was optimized for this operating condition. Design #8 outperforms #9. It can be seen that, as argued in Section 6.1 and [102, 103], peak efficiency at high load currents is achieved in Nishijima mode, while peak efficiency at low load currents is achieved in Meynard mode. This is the case regardless of whether the converter designs were derived by optimizing for only the Nishijima or Meynard mode over the entire load current range. It can be seen that for design #3, which was optimized for this operating condition in Nishijima mode, the efficiency advantage of its

Meynard mode appears only at the very lowest load currents. For the other two designs, the

Meynard mode becomes more efﬁcient at around the midpoint of the load range.

Fig. 6.7c shows the efficiency of all three designs in again the same two modes, but for operating condition 7. The Nishijima modes do not exceed the reference curve below 0.6 A, but all three designs exceed it easily in Meynard mode. The efficiencies of #3 and #8 are very close, while that of #9 is significantly lower.

The same patterns shown in Fig. 6.7 were seen when simulating the efﬁciency in the re- 86 6.4. VERIFICATION

Table 6.3: Optimization Results for Different Operating Conditions (Switch Areas in mm2)

# Vin : Vout SW1 SW2 SW3 SW4 SW5 SW6 SW7 Mode 1 5 : 3.3 V 0.764 0.35 0.35 0.79 0.458 0.35 0.44 2-phase int. buck 2 5 : 1 V 0.393 0.797 0.695 0.39 0.393 0.482 0.35 Nishijima 3 12 : 1.2 V 0.35 0.735 0.74 0.35 0.35 0.63 0.35 Nishijima 4 12 : 2.5 V 0.408 0.756 0.4683 0.414 0.425 0.464 0.35 Nishijima 5 12 : 5 0.568 0.602 0.602 0.568 0.35 0.35 0.459 Meynard 6 12 : 9 V 0.738 0.35 0.35 0.771 0.47 0.35 0.471 2-phase int. buck 7 24 : 2.5 V 0.35 0.713 0.797 0.35 0.368 0.572 0.35 Nishijima 8 24 : 5 V 0.434 0.645 0.708 0.443 0.462 0.458 0.35 Nishijima 9 24 : 9 V 0.559 0.609 0.608 0.559 0.35 0.35 0.464 Meynard 10 36 : 9 V 0.519 0.636 0.635 0.518 0.391 0.35 0.45 Meynard 11 48 : 5 V 0.35 0.608 0.859 0.356 0.439 0.538 0.35 Nishijima 12 48 : 12 V 0.514 0.63 0.63 0.513 0.4 0.35 0.466 Meynard

maining operating modes. Design #8, which was optimized for Vin : Vout = 24:5 V in Nishijima mode, had a good performance in all of the operating conditions overall, usually exceeding the reference curve over nearly the entire load range in each case. Expectedly, it was inferior to the designs optimized for a particular operating condition, but otherwise performed better than most of the other designs. For this reason, design #8 was chosen for implementation. The breakdown of the total area by switch is shown in Fig. 6.8a. The layout of the seven switches in Cadence is shown in Fig. 6.9a and is discussed in more detail in [108].

6.4 Veriﬁcation

The fabricated 7SFC prototype IC is shown in Fig. 6.9b. More details on its testing are given in [108]. A comparison of efﬁciency curves from GeckoCIRCUITS simulations – based on which the switch areas were selected – and Cadence simulations, at operating condition 8, are given in Fig. 6.10. The curves for both the Nishijima and Meynard modes are shown. It can be seen that the curves follow the same trend, indicating that the modeling behind the optimization procedure is accurate. The average error between the two sets of simulation curves is 4.2% for

Nishijima mode and 2.2% for Meynard mode. More insight can be gained by looking at the switch characteristics relevant to the efﬁciency simulations. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 87

80 Efficiency Efficiency (%)

70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load current (A)

Reference Design #3 Design #8 Design #9

(a) Simulations at operating condition 1, 5 : 3.3 V. All three designs operating in 2-phase interleaved buck mode.

90 88 86 84 82 80 78

Efficiency Efficiency (%) 76 74 72 70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load current (A)

Reference Design #3, Nishijima Design #8, Nishijima Design #3, Meynard Design #8, Meynard Design #9, Nishijima Design #9, Meynard (b) Simulations at operating condition 3, 12 : 1.2 V, in the Nishijima and Meynard modes.

90 88 86 84 82 80 78

Efficiency Efficiency (%) 76 74 72 70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load current (A)

Reference Design #3, Nishijima Design #8, Nishijima Design #3, Meynard Design #8, Meynard Design #9, Nishijima Design #9, Meynard (c) Simulations at operating condition 7, 24 : 2.5 V, in the Nishijima and Meynard modes.

Figure 6.7: Efﬁciency calculated from Cadence simulations for designs #3, #8, and #9 from Table 6.3, in different modes of operation at three different operating conditions. Reference efﬁciency curves for each of the operating conditions are also included. 88 6.4. VERIFICATION

2 2 Asw2 = 0.645 mm Asw2 = 0.756 mm 18.4% 21.7% 2 2 Asw3 = 0.708 mm Asw3 = 0.701 mm

20.2% 2 20% 2 Asw1 = 0.434 mm Asw1 = 0.412 mm 12.4% 11.8%

2 2 Asw7 = 0.35 mm Asw7 = 0.35 mm

2 10% 2 10% Asw4 = 0.443 mm Asw4 = 0.422 mm 12.7% 12% A = 0.458 mm2 2 2 sw6 2 Asw6 = 0.375 mm Asw5 = 0.462 mm 13.1% Asw5 = 0.484 mm 10.7% 13.2% 13.8% (a) (b)

Figure 6.8: The breakdown of the total area of 3.5 mm2 by MOSFET resulting from (a) the original optimization procedure and (b) the improved optimization procedure for the selected optimized design, #8.

SW4 SW1 SW2

SW1 SW4 SW2

SW3

SW6 SW5 SW7 SW3 SW6

SW5 SW7 (a) (b)

Figure 6.9: The (a) layout of the seven MOSFETs in Cadence for the selected optimized design, #8, and (b) the fabricated 7SFC converter power stage IC. CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 89

Table 6.4: Comparison of Switch Characteristics

Design Stage Post-Optimization Layout, Pre-Extraction Layout, Post-Extraction RDS,on (mΩ) Cg (pF) Coss (pF) RDS,on (mΩ) Cg (pF) Coss (pF) RDS,on (mΩ) Cg (pF) Coss (pF)

SW1 63.6 303.1 123.3 66 292 118 81.9 327 162.1 SW2 42.8 450.4 183.2 46.2 417 169 66 468 224 SW3 39.9 494.4 201.1 42.6 452.6 184.2 59 508 253 SW4 62.3 309.3 125.8 66.7 289 119 88.7 324 156 SW5 59.7 322.6 131.2 63 303 124 88.1 344 164 SW6 60.2 319.8 130.1 65.2 295 120 77.4 331 161 SW7 78.8 244.4 99.4 86.3 223 91 113.1 251 120

Table 6.4 lists three sets of numbers. In the ﬁrst column are those calculated by the optimization procedure based on the values in Table 6.1. The second and third columns show the values resulting from the actual Cadence design and layout of the chip, both pre- and post- extraction. The pre-extraction values were used in the Cadence simulations shown in this and the previous Section. The post-extraction values take into account all of the contributions of the physical layout, including, importantly, the effect of the routing of the interconnections between the different switches, as much as possible. As measuring these values on the fabricated

IC is impractical, the post-extraction values are the best available approximation of the actual characteristics behind the experimental measurements.

It can be seen that the characteristic values of the switches calculated by the optimization procedure are in close agreement to their pre-extraction values. As a rule, the post-optimization on-resistances are lower than the pre-extraction values (by 6.9% on average) while the capacitance values are consistently higher (by 7.5% on average for Cg and 7.3% on average for Coss). The reason for this error is that at an advanced stage of the design of the IC, it became necessary to increase the guard rings for electrostatic discharge protection. Therefore the seven switches were all slightly smaller in the ﬁnal layout than in Table 6.3, which explains the higher resistance and the lower capacitance.

A larger discrepancy can be seen between the post-optimization values and the post-extraction values. As a rule, the post-extraction values are always higher. The average errors are 29.5% for RDS,on, 4.4% for Cg and 19.8% for Coss. This means of course that there is also a signiﬁcant difference between the pre- and post-extraction values. This is explained by the various parasitic effects between the different metal layers used to lay out the IC, as well as the resistances of the interconnections between the switches [110]. 90 6.5. IMPROVED OPTIMIZATION PROCEDURE

100

80 Efficiency Efficiency (%)

70 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load current (A)

Nishijima (GeckoCIRCUITS) Nishijima (Cadence) Meynard (GeckoCIRCUITS) Meynard (Cadence)

Figure 6.10: A comparison of GeckoCIRCUITS simulations and Cadence simulations of the laid out 7SFC design in operating condition 8.

6.5 Improved Optimization Procedure

The results from the previous Section suggest a potential improvement of the optimization procedure. Rather than simply considering an area Asw,i, it is advantageous to perform a two- dimensional optimization of each switch considering its length lsw,i and width wsw,i. In this way, it is possible to account for the added resistance of the metal interconnections between the switches, which depends on the ratio of lsw,i to wsw,i and the predominant direction of the current ﬂow [110]. The on-resistance of a switch can therefore be calculated as

RDS,on,ref lsw,i RDS,on,i = + Rmetal (6.15) lsw,iwsw,i wsw,i for a switch in which current ﬂow is predominantly along its length. In the opposite case, the second term would be multiplied by wsw,i instead. (6.8) thus becomes: lsw,i

2 RDS,on,ref lsw,i Pcond,i = Isw,i,RMS + Rmetal . (6.16) lsw,iwsw,i wsw,i

Through the extraction in Cadence of on-resistances of several different devices with different lsw,i:wsw,i ratios, it was found that Rmetal = 13.8 mΩ. (6.16) was substituted into (6.14). In order to preserve the layout in Fig. 6.9a, additional constraints were added as well. SW1, SW2, CHAPTER 6. 7SFC CONVERTER IC η OPTIMIZATION BY A CIRCUIT SIMULATION-COUPLED GEOMETRIC PROGRAM 91

Table 6.5: Effect of Interconnection Resistance

2 Area (mm ) RDS,on without Rmetal (mΩ) RDS,on including Rmetal (mΩ)

SW1 0.41 67 76.9

SW2 0.756 36.5 46.9

SW3 0.701 39.3 55.6

SW4 0.422 65.4 75.5

SW5 0.484 57 80.6

SW6 0.375 73.6 79.8

SW7 0.35 78.8 111.4 and SW4 were constrained to have the same length (lsw,1 = lsw,2 = lsw,3) as were switches

SW3, SW5, SW6, and SW7 (lsw,3 = lsw,5 = lsw,6 = lsw,7). Every instance of Asw,i in (6.14) was replaced with wsw,ilsw,i. The resulting converter design at operating condition 8 is shown in Fig. 6.8b). As can be seen, accounting for the metal resistance only changed the switch areas slightly in this case.

Table 6.5 shows the RDS,on of the seven switches produced by the optimizer, with and without the additional effect of the interconnection resistance (Rmetal). The added interconnection resistance accounts on average for 20.6% of the total. This is similar to the difference between the post-optimization and post-extraction values seen in Table 6.4. It can be concluded therefore that (6.14) has been successfully modiﬁed to account for the effect of Rmetal. CHAPTER

SEVEN

CONCLUSIONS AND FUTURE WORK

It has been demonstrated in this thesis that geometric programming, a type of convex optimization, can be used to efﬁciently and comprehensively model and optimize unidirectional non-isolated DC/DC converters for multiple objectives, over a wide range of design variables.

This was ﬁrst shown on the example of low-power ML-FC converters, for which it was possible to convert both the converter and component models into the posynomial form GPs require.

The validity of the GP model was veriﬁed by experimental measurements on a 15 V to 3.3 V,

9.9 W prototype.

The developed GP formulation allows Pareto fronts of multiple converters for a given design space to be produced in under one minute, allowing the objective and truly global comparison of different converter topologies without the need to apply overly simplifying assumptions or focus on only one aspect of the converters’ design. The GP formulation can also be used to quickly perform a more in-depth trade-off and sensitivity analysis of the design space. The optimization results presented conﬁrm the myriad advantages of using multi-level converter topologies for low-power applications.

It was then shown that GP modeling can be extended into the higher power domain via an example inductor optimization. A generalized posynomial modeling procedure was presented.

It was shown that his procedure can be used to successfully ﬁt inductor simulation data over a wide range of design variables to soft-max afﬁne posynomial functions. This makes possible the derivation of posynomial loss, volume, temperature and saturation of a number of core and

92 CHAPTER 7. CONCLUSIONS AND FUTURE WORK 93 wire pairs over their possible operating range, that can be entered into a database for converter optimization.

Finally, it has been demonstrated that even when geometric programming cannot be used to create a converter-level model, as is the case with the 7SFC converter, a component-level GP model can be coupled with a fast circuit simulator to overcome this limitation. The resulting hybrid optimization procedure has been used to greatly simplify and accelerate the design and efficiency optimization of a 7SFC converter power stage IC with a wide input and output voltage range and a maximum output current of 2 A. Once the implementation technology parameters are extracted from Cadence, the optimal sizes of the converter’s switches for a given operating condition can be calculated in little over a minute. It was further shown how the procedure can be extended to account for parasitic effects. The flexibility of the GP-circuit simulation approach allows it to be easily modified for the optimization of other complex converter topologies.

7.1 Future Work

This thesis is certainly not meant to be the final word on using GPs to optimize switching converters, but rather the opening up of a whole new field of study. There is much further work that can be done to apply geometric programming widely in power electronics. For example, it would need to be carefully considered how the GP model can be modified to account for bidirectional power flow and properly optimize bidirectional converters. Some more remarks on specific improvements are given below.

7.1.1 Magnetic Components

Chapter 5 has demonstrated one potential approach for deriving posynomial inductor models for higher power converters. While this approach was successful, it requires a large amount of simulation to derive the model, and the model is limited to one particular core size. Fur- ther study is needed to develop a more general approach through which families of inductor cores of different sizes could be modeled, as was done with low power components in Chapter

4. In [85], the author of this thesis has shown that it might be feasible to approximate physical models of inductors with posynomial functions directly, without performing simulations 94 7.1. FUTURE WORK of particular components. In this way an approximate physical model of an inductor may be constructed, which would be universally applicable. This idea warrants further study.

The GP modeling approach needs to be extended to transformers, as isolated converter topologies are very common. Transformer and inductor modeling is broadly similar and based on the same concepts, although of course transformers are usually more complex. If inductors can be successfully modeled by posynomials, there is no question that transformers can be as well.

7.1.2 AC/DC Converters and EMI Filters

There is no reason why AC/DC converters cannot be modeled as GPs as well. AC/DC converter design entails the derivation of average current and voltage stresses across the components, much in the same way as is done for DC/DC converters. There are some important details, however, to which attention must be paid. Since an AC voltage is applied to the semiconductors, their voltage-dependent characteristics, such as the output capacitance, must be evaluated based on data sheet curves at each value of the blocking voltage. This is more involved than in

DC/DC converters, where in most cases the same blocking voltage is always applied to a particular switch or diode. Therefore, accurate semiconductor loss models for AC/DC converters such as those presented in [31] must be converted into posynomial form, or approximated by posynomial functions.

EMI filters present an optimization problem in their own right [80,111]. Generally, a reduction in size of the AC/DC converter sans filter, achieved by increasing the switching frequency, is followed by an increase in conducted noise, which requires and increase in the volume of the EMI filter. Literature focuses on EMI filter volume minimization, but not as much on losses.

If an EMI filter topology was decided upon before the converter optimization, this would be fairly straightforward to add to the overall GP model. However, allowing all of the EMI filter design values – the number of stages and the distribution of filter attenuation across stages – to be free in the overall, global optimization might make the problem too large. Finally, an

EMI filter must be dimensioned according to the noise which must be attenuated. Differential mode noise can be extracted using circuit simulations, but posynomial models for the differen- CHAPTER 7. CONCLUSIONS AND FUTURE WORK 95 tial noise (or at least an estimate of it) of the converter topology being optimized would need to be developed. Most of the above can be said to apply to DC/AC converters as well. The hybrid optimization procedure presented in Chapter 6 could be modified for the optimization of high-power reconfigurable converter topologies, such as [112–115].

7.1.3 Generalized Geometric Programming

Generalized geometric programs (GGPs) [61] allow the use of posynomial functions raised to positive rational powers. Such generalized posynomials potentially allow the fitting of multidimensional data with higher accuracy. In [94] it is shown that data can be fit to generalized posynomials in the logarithmic domain using implicit soft-max affine (ISMA) functions. GGP models might be of particular use for higher power inductors and transformers.

7.2 Final Remarks

Although multi-objective converter optimization has long been a relevant and widely studied topic, a satisfactory, mathematically rigorous and widely applicable framework for converter optimization has so far been lacking. Furthermore, convex optimization, with its myriad advantages, was not widely applied in the ﬁeld of power electronics. It is the hope of the author that this thesis has shown the advantages of using geometric programming as that framework, and that it will serve to both point research on converter optimization in a new and fruitful direction, and give practicing engineers a valuable new tool for their daily work. Appendices

96 APPENDIX A: MATLAB CODE FOR ML-FC CONVERTER OPTIMIZATION

This Appendix contains the MATLAB code for the multi-objective η-ρ optimization of ML-FC converters described in Chapter 4. The code for setting up the CVX and YALMIP packages and their respective solvers is not included. The code using CVX includes the entire script from start to ﬁnish; the code using YALMIP shows only the part of the script which differs from the CVX version.

CVX

%Optimization of ML−FC buck converters %for losses and volume using CVX tic; Ns = [2 3 4]; %define number of levels to consider [k j] = size(Ns); all_opt_design = cell(j); for k = 1:j %Number of levels N = Ns(k);

%switch voltage rating Vr_switch = 0; if (N == 2) Vr_switch = 25; elseif (N == 3) Vr_switch = 20; elseif (N == 4) Vr_switch = 12; end

%switch characterization

97 98

h = 0; %height of switch package(m) Rthja_ref = 0; %junction to ambient temperature per switch(K/W) RdsonAswref = 0; %Rdson * reference Asw(ohm −m) Cossref_over_Aswref = 0; %Coss reference/ reference Asw(F/m^2) Qgref_over_Aswref = 0; %Total gate charge reference/ reference Asw(C/m^2) Qrrref_over_Aswref = 0; %Reference MOSFET body diode reference recovery charge/ reference Asw(C/m^2) alpha = 0; %coefficient for dependence of Rds_on on temperature tontoff = 0; %on+ off time for the switches(s) toffton = 0; %(off time − on time) for the switches(s) Aswref = 0; %area of one switch VF = 0; maxswitches = 15; minswitches = 1; if (Vr_switch == 25) h = 1e−3; Rthja_ref = 165; RdsonAswref = 9.801e−8; Cossref_over_Aswref = 2.75482e−5; alpha = 0.003636364; Aswref = 1.09e−5; tontoff = 5.93e−9; toffton = 3.42e−10; VF = 0.8; Qgref_over_Aswref = 4.59e−4; Qrrref_over_Aswref = 1.07e−03; minswitches = 1; elseif (Vr_switch == 20) h = 7.50e−4; Rthja_ref = 235; RdsonAswref = 0.000000052; Cossref_over_Aswref = 0.00005; alpha = 4.00e−3; Aswref = 4e−6; tontoff = 4.44e−9; toffton = 1.14e−10; VF = 0.8; Qgref_over_Aswref = 1.06e−3; Qrrref_over_Aswref = 2.68e−3; minswitches = 1; elseif (Vr_switch == 12) %A%B h = 7.50e−4;%6.20e−4; Rthja_ref = 210;%230; RdsonAswref = 0.000000028;%0.000000012; Cossref_over_Aswref = 0.000125;%0.000213333; alpha = 0.003076923;%0.002666667; Aswref = 4.00e−6;%1.50e−6; tontoff = 4.28e−9;%8e−9; 99

toffton = 1.17e−9;%1.32e−9; VF = 0.7;%0.8; Qgref_over_Aswref = 2.28e−3;%9.67e−03; Qrrref_over_Aswref = 3.25e−3;%9.87e−03; minswitches = 1; end

%General parameters Vin = 15; %input voltage(V) Vout = 3.3; %output voltage(V) Iout = 3; %load current(A) Tamb = 25; %ambient temperature(deg.C) Tjmax = 50; %maximum junction temperature(deg.C) deltaTmax = Tjmax − Tamb; %maximum allowed temperature rise fly_ripple = 4; %allowed ripple of fly caps. (%) deltaV_fly = Vin * (fly_ripple/100); %fly capacitor ripple voltage(V) out_ripple = 1.1; %allowed ripple of output cap (%) deltaV_out = Vout * (out_ripple/100); %output capacitor ripple voltage(V) vf = 1.2; %factor to multiply all volume by to account for PCB ripplemin = 10; %min. inductor current ripple (%) ripplemax = 50; %max. inductor current ripple (%) Iripplemin = ripplemin/100 * Iout; %min. inductor current ripple(A) Iripplemax = ripplemax/100 * Iout; %max. inductor current ripple(A) fripplemin = 500e3; %min. inductor ripple frequency(Hz) fripplemax = 2.5e6; %max. inductor ripple frequency(Hz) Vgs = 8; %gate−source voltage applied to each mosfet(V) l = 0; %region of operation, should bea value from1 to(N −1) D = Vout/Vin; %duty ratio %find region of operation based on duty ratio for m = 1:(N−1) if (D > ((m−1)/(N−1))) && (D <= (m/(N−1))) l = m; end end

%Iripple[pk−pk]=(R *Vin)/(fsw*L)=(R *(N−1)*Vin)/(fripple*L) %and soL=(R *(N−1)*Vin)/(fripple*Iripple) %below is the expression forR(N −1) r = l*(1 − ((N−1)/l)*D)*(D − ((l−1)/(N−1))); %IRMS_CFLY= Iout *sqrt(2*X)*sqrt(1+ (1/3)(0.5 *Iripple/Iout)^2 %below is the expression forX if (l == 1) X = D; elseif (l == (N−1)) X = (1 − D); else 100

X = 1/(N−1); end fprintf('N=%d,l=%d,r=%d,X=%d\n',N,l,r,X);

Vds = Vin / (N−1); %switch blocking voltage(V) %peak switch current should be Ids= Iout+ 0.5 *Iripple−pp %for conduction losses we use RMS

%Switch conduction loss coefficients %Pcond= pc1 *(Asw^−1)+ pc2 *((Asw^−1)*deltaT)+ pc3 *(Asw^−1)*Iripple^2+ pc4 *(( Asw^−1)*deltaT)*Iripple^2 pc1 = (N−1)*Iout*Iout*RdsonAswref; pc2 = (N−1)*Iout*Iout*RdsonAswref*alpha; pc3 = (N−1)*RdsonAswref/12; pc4 = (N−1)*RdsonAswref*alpha/12;

%Switch switching loss coefficients %Psw= ps1 *fripple+ ps2 *fripple*Iripple+ ps3 *fripple*Asw ps1 = 0.5*tontoff*Iout*((Vin/(N−1))+VF); ps2 = 0.25*toffton*((Vin/(N−1))+VF); ps3 = Cossref_over_Aswref*((Vin/(N−1))^2);

%Reverse recovery on lowside MOSFET body diode %Prr= Qrr *fripple*(Vin/(N−1))= Qrrref _over_Aswref*Asw*fripple*(Vin/(N−1)) %= pr *Asw*fripple pr = Qrrref_over_Aswref*Vin/(N−1);

%Gate drive losses %Pgate=(N −1)*2Qg*Vgs*fripple/(N−1)=2 *Qgref_over_Aswref*AswVgs*fripple %= pg *Asw*fripple pg = 2*Qgref_over_Aswref*Vgs;

%Inductor loss coefficients %Pind= pi1 *Iripple^pe1*fripple^pe2+ pi2 *fripple*Iripple^pe3 %+ pi3*Iripple^pe4; pi1 = 0.02401; pi2 = 6.381e−10; pi3_beforeIout = 0.002242; pi3 = pi3_beforeIout*(Iout^2); pe1 = 0.1302; pe2 = 0.06675; pe3 = 0.2853; pe4 = 2.774; max_ind_loss = 0.3; %maximum allowed inductor loss(W) to keep inductor below thermal limit

%Capacitor loss(ESR) coefficient − tan−delta %For the family of capacitors used, approximated to bea constant 0.02 101

%IRMS_FLY= Iout *sqrt(2*X)*sqrt(1+ (1/3) *(Iripple/2/Iout)^2) − PER CAP! tandelta = 0.02; %IRMS_COUT= Iripple/ (2 *sqrt(3)) %PCFLY=(N −2)*(IRMS_FLY^2)*ESR_FLY= %(N−2)*Iout^2*(2*X)*(1+(1/3)*(Iripple/2/Iout)^2)*tandelta/(2*pi*fripple*CFLY)= %pcf1+ pcf2 *(Iripple^2) pcf1 = (N−2)*Iout*tandelta*deltaV_fly/(pi*(N−1)); pcf2 = (N−2)*tandelta*deltaV_fly/(12*pi*(N−1)*Iout); %PCOUT= IRMS _COUT^2*ESR_COUT= %(Iripple^2/ 12) *tandelta/(2*pi*fripple*Cout)= %Iripple/12*(tandelta/(2pi))*8*deltaV_out= %pco*Iripple; pco = (tandelta*8*deltaV_out)/(24*pi);

%Switch volume coefficients %Volsw= vs *Asw %make larger by 50% to account for volume of gate drivers vs = vf*2*(N−1)*h*1.5;

%Inductor volume coefficients %Volind= vi1/(Iripple *fripple)+ vi2/fripple+ vi3 *Iripple/fripple vi1 = vf*0.005508*r*Iout*Iout*Vin; vi2 = vf*0.005508*r*Iout*Vin; vi3 = vf*0.005508*0.25*r*Vin;

%Capacitor volume coefficients − output cap. %Volcout= vco1 *Iripple/fripple+ vco2 vco1 = vf*(5.4982e−7*Vout + 1.74473e−6)*0.5*Vout/(8*out_ripple); vco2 = vf*2.7854e−10;

%Capacitor volume coefficients − flying cap. %Volcfly= vcf1/fripple+ vcf2 vcf1 = vf*(N−2)*X*Iout*Vin*(5.4982e−7*Vin/(N−1) + 1.74473e−6)/deltaV_fly; vcf2 = vf*(N−2)*2.7854e−10;

%Temperature rise coefficient %deltaTactual=(Pcond+ Psw) * tc/ Asw tc = Rthja_ref*Aswref/(2*(N−1));

%we need to normalize losss and volume to make the weighting factor gamma %meaningful; therefore we find first the maximum loss and maximum volume −> solve two GPs %and divide by this, ensuring the loss and volume always go from0 to1

%find maximum volume by minimizing loss cvx_begin gp variables Iripple fripple Asw deltaT 102

minimize(pc1*(Asw^−1) + pc2*((Asw^−1)*deltaT) + pc3*(Asw^−1)*(Iripple^2) + pc4*((Asw^−1)*deltaT)*(Iripple^2) + ps1*fripple + ps2*fripple*Iripple + ps3*fripple*Asw + pr*Asw*fripple + pg*Asw*fripple + pi1*(Iripple^pe1)*( fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3*Iripple^pe4 + pcf1 + pcf2 *(Iripple^2) + pco*Iripple) subject to %max. temperature constraint pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= deltaTmax; %actual temparature must be less than assumed temperature constraint pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= 1.1*deltaT; %bounds on variables Iripplemin <= Iripple <= Iripplemax; fripplemin <= fripple <= fripplemax; minswitches*Aswref <= Asw <= maxswitches*Aswref; deltaT >= 1; pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3* Iripple^pe4 <= max_ind_loss; cvx_end vol_max = vs*Asw + vi1/(Iripple*fripple) + vi2/fripple + vi3*Iripple/fripple + vco1*Iripple/fripple + vco2 + vcf1/fripple + vcf2;

%find maximum loss by minimizing volume cvx_begin gp variables Iripple fripple Asw deltaT minimize(vs*Asw + vi1/(Iripple*fripple) + vi2/fripple + vi3*Iripple/fripple + vco1*Iripple/fripple + vco2 + vcf1*(fripple^−1) + vcf2) subject to %max. temperature constraint pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= deltaTmax; %actual temparature must be less than assumed temperature constraint pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= 1.1*deltaT; %bounds on variables Iripplemin <= Iripple <= Iripplemax; fripplemin <= fripple <= fripplemax; minswitches*Aswref <= Asw <= maxswitches*Aswref; 103

deltaT >= 1; pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3* Iripple^pe4 <= max_ind_loss; cvx_end loss_max = pc1*(Asw^−1) + pc2*((Asw^−1)*deltaT) + pc3*(Asw^−1)*(Iripple^2) + pc4 *((Asw^−1)*deltaT)*(Iripple^2) + ps1*fripple + ps2*fripple*Iripple + ps3* fripple*Asw + pr*Asw*fripple + pg*Asw*fripple + pi1*(Iripple^pe1)*(fripple^ pe2) + pi2*fripple*(Iripple^pe3) + pi3*Iripple^pe4 + pcf1 + pcf2*(Iripple^2) + pco*Iripple; opt_designs = cell(21); %gamma weighting factor between losses and volume i = 1; for gamma = 0.00:0.05:1.0 gamma if (gamma == 1.0) gamma = 0.99999; end cvx_begin gp variables Iripple fripple Asw deltaT dual variables Imin Imax fmin fmax Amin Amax tm ti minimize((gamma/loss_max)*pc1*(Asw^−1) + (gamma/loss_max)*pc2*((Asw^−1)* deltaT) + (gamma/loss_max)*pc3*(Asw^−1)*(Iripple^2) + (gamma/loss_max )*pc4*((Asw^−1)*deltaT)*(Iripple^2) + (gamma/loss_max)*ps1*fripple + (gamma/loss_max)*ps2*fripple*Iripple + (gamma/loss_max)*ps3*fripple* Asw + (gamma/loss_max)*pr*Asw*fripple + (gamma/loss_max)*pg*Asw* fripple + (gamma/loss_max)*pi1*(Iripple^pe1)*(fripple^pe2) + (gamma/ loss_max)*pi2*fripple*(Iripple^pe3) + (gamma/loss_max)*pi3*Iripple^ pe4 + (gamma/loss_max)*pcf1 + (gamma/loss_max)*pcf2*(Iripple^2) + ( gamma/loss_max)*pco*Iripple + ((1−gamma)/vol_max)*vs*Asw + ((1−gamma) /vol_max)*vi1/(Iripple*fripple) + ((1−gamma)/vol_max)*vi2/fripple + ((1−gamma)/vol_max)*vi3*Iripple/fripple + ((1−gamma)/vol_max)*vco1* Iripple/fripple + ((1−gamma)/vol_max)*vco2 + ((1−gamma)/vol_max)*vcf1 *(fripple^−1) + ((1−gamma)/vol_max)*vcf2) subject to %max. temperature constraint tm : pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*( Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc* fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc* fripple + pr*tc*Asw*fripple <= deltaTmax; %actual temparature must be less than assumed temperature constraint pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*( Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc* fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc* fripple + pr*tc*Asw*fripple <= 1.1*deltaT; %bounds on variables Imin : Iripple >= Iripplemin; 104

Imax : Iripple <= Iripplemax; fmin : fripple >= fripplemin; fmax : fripple <= fripplemax; Amin : Asw >= minswitches*Aswref; Amax : Asw <= maxswitches*Aswref; deltaT >= 1; ti: pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3*Iripple^pe4 <= max_ind_loss; cvx_end

%calculate actual loss and volume sw_loss = ps1*fripple + ps2*fripple*Iripple + ps3*fripple*Asw; cond_loss = pc1*(Asw^−1) + pc2*((Asw^−1)*deltaT) + pc3*(Asw^−1)*(Iripple^2) + pc4*((Asw^−1)*deltaT)*(Iripple^2); qrr_loss = pr*Asw*fripple; gatedr_loss = pg*Asw*fripple; ind_loss = pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3 *Iripple^pe4; cfly_loss = pcf1 + pcf2*(Iripple^2); cout_loss = pco*Iripple; loss = sw_loss + cond_loss + qrr_loss + gatedr_loss + ind_loss + cfly_loss + cout_loss; actual_temp = pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1) *(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw ^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw* fripple; sw_vol = vs*Asw; ind_vol = vi1/(Iripple*fripple) + vi2/fripple + vi3*Iripple/fripple; co_vol = vco1*Iripple/fripple + vco2; cf_vol = vcf1/fripple + vcf2; vol = sw_vol + ind_vol + co_vol + cf_vol; L = (r*Vin)/(fripple*Iripple); Cout = 0.5*Iripple/(8*deltaV_out*fripple); Cfly = X*Iout*(N−1)/(fripple*deltaV_fly); opt_design = [gamma loss vol Asw fripple Iripple deltaT actual_temp L Cfly Cout cond_loss sw_loss qrr_loss gatedr_loss ind_loss cfly_loss cout_loss sw_vol ind_vol co_vol cf_vol ind_loss/ind_vol Imin Imax fmin fmax Amin Amax tm ti]; opt_designs{i} = opt_design; i = i + 1; end opt_data = cell2mat(opt_designs); all_opt_design{k} = opt_data; end %plot resulting Pareto fronts for k = 1:j opt_data = all_opt_design{k}; 105

level = Ns(k); plot(opt_data(:,2),opt_data(:,3)*1e9,'DisplayName',['N=' num2str(level)]); if (k == 1) hold end end execution_time = toc; execution_time title('Loss vs. Volume Pareto Curve'); xlabel('Total converter loss(W)'); ylabel('Total converter volume(mm^3)');

YALMIP

%Optimization of ML−FC buck converters %for losses and volume using YALMIP tic; Ns = [2 3 4]; [k j] = size(Ns); all_opt_design = cell(j); for k = 1:j %Number of levels N = Ns(k);

%[ ...] %[ ... the skipped part of the script − not shown here − % is the same as the CVX version ...] %[ ...]

%find maximum volume by minimizing loss sdpvar Iripple fripple Asw deltaT; minloss = pc1*(Asw^−1) + pc2*((Asw^−1)*deltaT) + pc3*(Asw^−1)*(Iripple^2) + pc4 *((Asw^−1)*deltaT)*(Iripple^2) + ps1*fripple + ps2*fripple*Iripple + ps3* fripple*Asw + pr*Asw*fripple + pg*Asw*fripple + pi1*(Iripple^pe1)*(fripple^ pe2) + pi2*fripple*(Iripple^pe3) + pi3*Iripple^pe4 + pcf1 + pcf2*(Iripple^2) + pco*Iripple; bounds = [Iripplemin <= Iripple <= Iripplemax, fripplemin <= fripple <= fripplemax, minswitches*Aswref <= Asw <= maxswitches*Aswref, deltaT >= 1]; thermal_constraints = [pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw 106

^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw ^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= deltaTmax, pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*( Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= 1.1* deltaT, pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3* Iripple^pe4 <= max_ind_loss]; constraints = [bounds, thermal_constraints]; options = sdpsettings('solver','gpposy'); solution = optimize(constraints,minloss,options); vol_max = value(vs*Asw + vi1/(Iripple*fripple) + vi2/fripple + vi3*Iripple/ fripple + vco1*Iripple/fripple + vco2 + vcf1/fripple + vcf2);

%find maximum loss by minimizing volume sdpvar Iripple fripple Asw deltaT; minvolume = vs*Asw + vi1/(Iripple*fripple) + vi2/fripple + vi3*Iripple/fripple + vco1*Iripple/fripple + vco2 + vcf1*(fripple^−1) + vcf2; bounds = [Iripplemin <= Iripple <= Iripplemax, fripplemin <= fripple <= fripplemax, minswitches*Aswref <= Asw <= maxswitches*Aswref, deltaT >= 1]; thermal_constraints = [pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw ^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw ^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= deltaTmax, pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*( Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= 1.1* deltaT, pi1*(Iripple^pe1)*(fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3* Iripple^pe4 <= max_ind_loss]; constraints = [bounds, thermal_constraints]; options = sdpsettings('solver','gpposy'); solution = optimize(constraints,minvolume,options); loss_max = value(pc1*(Asw^−1) + pc2*((Asw^−1)*deltaT) + pc3*(Asw^−1)*(Iripple^2) + pc4*((Asw^−1)*deltaT)*(Iripple^2) + ps1*fripple + ps2*fripple*Iripple + ps3*fripple*Asw + pr*Asw*fripple + pg*Asw*fripple + pi1*(Iripple^pe1)*( fripple^pe2) + pi2*fripple*(Iripple^pe3) + pi3*Iripple^pe4 + pcf1 + pcf2*( Iripple^2) + pco*Iripple); opt_designs = cell(21); %gamma weighting factor between losses and volume i = 1; for gamma = 0.00:0.05:1.00 gamma if (gamma == 1.0) gamma = 0.99999; end 107

sdpvar Iripple fripple Asw deltaT; multiobj = ((gamma/loss_max)*pc1*(Asw^−1) + (gamma/loss_max)*pc2*((Asw^−1)* deltaT) + (gamma/loss_max)*pc3*(Asw^−1)*(Iripple^2) + (gamma/loss_max)* pc4*((Asw^−1)*deltaT)*(Iripple^2) + (gamma/loss_max)*ps1*fripple + (gamma /loss_max)*ps2*fripple*Iripple + (gamma/loss_max)*ps3*fripple*Asw + ( gamma/loss_max)*pr*Asw*fripple + (gamma/loss_max)*pg*Asw*fripple + (gamma /loss_max)*pi1*(Iripple^pe1)*(fripple^pe2) + (gamma/loss_max)*pi2*fripple *(Iripple^pe3) + (gamma/loss_max)*pi3*Iripple^pe4 + (gamma/loss_max)*pcf1 + (gamma/loss_max)*pcf2*(Iripple^2) + (gamma/loss_max)*pco*Iripple + ((1−gamma)/vol_max)*vs*Asw + ((1−gamma)/vol_max)*vi1/(Iripple*fripple) + ((1−gamma)/vol_max)*vi2/fripple + ((1−gamma)/vol_max)*vi3*Iripple/fripple + ((1−gamma)/vol_max)*vco1*Iripple/fripple + ((1−gamma)/vol_max)*vco2 + ((1−gamma)/vol_max)*vcf1*(fripple^−1) + ((1−gamma)/vol_max)*vcf2); bounds = [Iripplemin <= Iripple <= Iripplemax, fripplemin <= fripple <= fripplemax, minswitches*Aswref <= Asw <= maxswitches*Aswref, deltaT >= 1]; thermal_constraints = [pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*( Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1*tc* fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr* tc*Asw*fripple <= deltaTmax, pc1*tc*(Asw^−2) + pc2*tc*((Asw^−2)*deltaT) + pc3*tc*(Asw^−1)*(Iripple^2) + pc4*tc*((Asw^−1)*deltaT)*(Iripple^2) + ps1 *tc*fripple*(Asw^−1) + ps2*tc*fripple*Iripple*(Asw^−1) + ps3*tc*fripple + pr*tc*Asw*fripple <= 1.1*deltaT, pi1*(Iripple^pe1)*(fripple^pe2) + pi2* fripple*(Iripple^pe3) + pi3*Iripple^pe4 <= max_ind_loss]; constraints = [bounds, thermal_constraints]; options = sdpsettings('solver','gpposy'); solution = optimize(constraints,multiobj,options);

vol = sw_vol + ind_vol + co_vol + cf_vol; L = (r*Vin)/(fripple*Iripple); Cout = 0.5*Iripple/(8*deltaV_out*fripple); Cfly = X*Iout*(N−1)/(fripple*deltaV_fly); opt_design = [gamma value(loss) value(vol) value(Asw) value(fripple) value( Iripple) value(deltaT) value(actual_temp) value(L) value(Cfly) value(Cout ) value(cond_loss) value(sw_loss) value(qrr_loss) value(gatedr_loss) value(ind_loss) value(cfly_loss) value(cout_loss) value(sw_vol) value( ind_vol) value(co_vol) value(cf_vol)]; opt_designs{i} = opt_design; i = i +1; end opt_data = cell2mat(opt_designs); all_opt_design{k} = opt_data; end %plot resulting Pareto fronts for k = 1:j opt_data = all_opt_design{k}; level = Ns(k); plot(opt_data(:,2),opt_data(:,3)*1e9,'DisplayName',['N=' num2str(level)]); if (k == 1) hold end end legend('show'); execution_time = toc; execution_time title('Loss vs. Volume Pareto Curve'); xlabel('Total converter loss(W)'); ylabel('Total converter volume(mm^3)'); APPENDIX B: MATLAB CODE FOR 7SFC CONVERTER OPTIMIZATION

This Appendix contains the MATLAB code for the hybrid simulation and GP optimization procedure of the 7SFC converter described in Chapter 6. The code for setting up the CVX and

YALMIP packages and their respective solvers is not included. The code for setting up the link between GeckoCIRCUITS and MATLAB is included, but commented out; for more details, re- fer to the GeckoCIRCUITS manual. A screenshot of the GeckoCIRCUITS model used in the optimization procedure is provided at the end of this Appendix.

tic; %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−−−−−−−−−−−−−−−−INITIAL SET−UP:−−−−−−−−−−−−−−−−−−−−−−−−% %NOTE: You comment these commands out in the script, and then run them %directly in the MATLAB terminal, once, prior to executing the script the %first time %−−−−−CLASSPATH COMMAND−−−−−% %javaaddpath'C:/GeckoCIRCUITS/GeckoCIRCUITS.jar' %−−−−−−−−−−−−−−−−−−−−−−−−−−−% %MAKE SURE THE ABOVE IS THE CORRECT PATH TO GECKOCIRCUITS ON YOUR MACHINE! %The above command is NOT NECESSARY if you have edited your classpath.txt %file properly! %−−−−−−−−IMPORT COMMAND−−−−−% %import('gecko.GeckoRemote.*') %−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−START GECKO−−−−−−−−% %startGui() %−−−−−−−−−−−−−−−−−−−−−−−−−−−% %NOTE: If above does not work, try startGui(PORT), where PORT isa free and %accessible port number on your machine, for example 43037. %ALSO, if prompted bye.g. Windows Firewall whether to allow network %accesss to the Java Runtime Environment, click on Allow Access.

109 110

%Administrator privileges might be required! %−−−−−−−−OPEN MODEL−−−−−−−−% %modelpath='C:/Users/EDISON/Documents/tmoianno/matlab/sevenswitch.ipes'; %openFile(modelpath); %−−−−−−−−−−−−−−−−−−−−−−−−−−−% %NOTE − MAKE SURE THE ABOVE PATH IS CORRECT! Or, alternatively, open the %file manually in GeckoCIRCUITS yourself. %−−−−−−−−START GECKO−−−−−−−−% %startGui() %−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−%

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−FIXED INPUT PARAMETERS TO BE SUPPLIED BY USER:−−−−−−−−%

%−−−−CONVERTER INPUT−OUTPUT PARAMETERS AND MODE OF OPERATION−−−−% Vin = 24; %converter input voltage Vout_ref = 5; %reference(desired) converter output voltage Vout = 5; %actual converter output voltage %NOTE: if simulating in closed−loop, make sure that Vout_ref= Vout; if %simulating in open−loop, you have the option to make Vout_ref slightly %larger to anticipate the expected losses and thus make the calculations %more accurate. By default they are the same, even for open−loop %simulations. Iout_actual = 2.0; %output load current AT WHICH TO PERFORM THE OPTIMIZATION Iout_rated = 2.0; %rated(full) load current of the converter %NOTE: Iout_actual is the operating point at which the converter %optimization will be performed,i.e. the losses will be minimized at that %output current subject to the constraints. Iout_rated is the 100% load %level of the converter. MAKE SURE THAT Iout_actual <= Iout_rated! If the %two are the same, then the converter is optimized at 100% load. mode = 1; %converter mode of operation %NOTE: MODE VARIABLE VALUES: %−−−−− 0(or any other number not1 −3): AUTOMATIC mode selection %−−−−− 1: NISHIJIMA MODE %−−−−− 2: MAYNARD MODE %−−−−− 3: INTERLEAVED2 −PHASE BUCK MODE %The AUTOMATIC mode selection logic is in the GeckoCIRCUITS simulation %file, in the JAVA−BLOCK labeled MODE. The default mode selection logic %is ifD> 0.5, use mode 3, otherwise if Iout _actual/Iout_rated< 0.25, use %mode2(Maynard), else use mode1(Nishijima). To change this, change the %code in the MODE Java block in the GeckoCIRCUITS file. Using automatic %mode means that if you optimize for say 80% load, but set also efficiency %targets for 20% load, you might havea converter optimized for the 80% %load level in Nishijima mode, while at the 20% the constraint will be %calculated from the Maynard mode. In other words, the efficiency target %constraints will take into account dynamic mode switching due to load 111

%changes. %NOTE that for modes1 and 2, the desired mode MAY NOT EQUAL ACTUAL MODE. %If you select mode1 or 2, but specify Vin/Vout> 0.5, then the simulation %model will AUTOMATICALLY switch to mode 3, and you will be optimizing an %interleaved2 −phase buck converter.

%−−−−−−−−−−−SWITCHING FREQUENCY AND PASSIVE COMPONENTS−−−−−−−−−−% fsw = 800e3; %switching frequency IN HERTZ(Hz) Cfly = 40e−6; %flying capacitor capacitance in FARADS(F) Cout = 200e−6; %output capacitor capacitance in FARADS(F) L = 1e−6; %output inductance PER INDUCTOR in HENRIES(H) RL = 3e−2; %inductor ESR PER INDUCTOR in OHMS − used to estimate inductor losses , set according to selected component

%−−−−−−−−−−−−−−−−−−BODY DIODE AND GATE DRIVER−−−−−−−−−−−−−−−−−−−% Vd_mos = 0.2; %approximate MOSFET body diode forward voltage drop in VOLTS(V) ton = 2e−9; %approximate MOSFET turn−on time in SECONDS(S) toff = 2e−9; %approximate MOSFET turn−off time in SECONDS(S) Vg = 5; %gate driver voltage in VOLTS(V)

%−−−−−−−−−−−−−−−−−−−−−MOSFET PARAMETERS−−−−−−−−−−−−−−−−−−−−−−−−% Rdson_mm2 = 27.58e−3; %on−resistance in OHMS PER MILLIMETER SQUARED(mm^2) Coss_mm2 = 284e−12; %output capacitance in FARADS(F) PER MILLIMETER SQUARED(mm ^2) Cin_mm2 = 698.3e−12; %input capacitance in FARADS(F) PER MILLIMETER SQUARED(mm ^2) %NOTE: This script ASSUMESA CONSTANT TEMPERATURE OF THE MOSFETS! Please %make sure that the values above ARE FOR THE CORRECT TEMPERATURE.

%−−−−−−−−−−−−−−−−−−−−−RDSON DELTA VALUES−−−−−−−−−−−−−−−−−−−−−−−−% %NOTE: Here add the factors(default=1 meaning no effect) and constant %deltas(default=0 meaning no effect) by which on −resistance of the %MOSFETS increase due to the routing. %If the effect is 1.2, that means Rdson is increased by 20% S1F = 1; %proportional effect of routing on Rdson of MOSFET1 S2F = 1; %proportional effect of routing on Rdson of MOSFET2 S3F = 1; %proportional effect of routing on Rdson of MOSFET3 S4F = 1; %proportional effect of routing on Rdson of MOSFET4 S5F = 1; %proportional effect of routing on Rdson of MOSFET5 S6F = 1; %proportional effect of routing on Rdson of MOSFET6 S7F = 1; %proportional effect of routing on Rdson of MOSFET7 S1D = 0; %constant delta added to Rdson of MOSFET1 due to routing − in OHMS (?) S2D = 0; %constant delta added to Rdson of MOSFET2 due to routing − in OHMS (?) S3D = 0; %constant delta added to Rdson of MOSFET3 due to routing − in OHMS (?) S4D = 0; %constant delta added to Rdson of MOSFET4 due to routing − in OHMS (?) S5D = 0; %constant delta added to Rdson of MOSFET5 due to routing − in OHMS (?) S6D = 0; %constant delta added to Rdson of MOSFET6 due to routing − in OHMS (?) S7D = 0; %constant delta added to Rdson of MOSFET7 due to routing − in OHMS (?) 112

%−−−−−−−−−−−−−−−−−−−−−−−EFFICIENCY TARGETS−−−−−−−−−−−−−−−−−−−−−−% Eff_100 = 0.8; %minimum target efficiency at 100% load Eff_80 = 0.85; %minimum target efficiency at 80% load Eff_60 = 0.7; %minimum target efficiency at 60% load Eff_40 = 0.6; %minimum target efficiency at 40% load Eff_20 = 0.5; %minimum target efficiency at 20% load %NOTE: Seta number from very small, close to zero(but not exactly zero!) %to 1. The converter losses will be minimized at Iout_actual, BUT subject %to the constraints above,i.e. the optimizer will attempt to minimize %losses at Iout_actual WHILE AT THE SAME TIME keeping the efficiency at %each of the five load levels above at least the above−specified value. %IMPORTANT NOTE: some combination of desired efficiencies may be %impossible! Therefore, if the solver is failing to finda solution, relax %the above constraints(or remove one, by setting it toe.g. 0.01).

%−−−−−−−−−−−−−−−−−−−−−−−−AREA CONSTRAINTS−−−−−−−−−−−−−−−−−−−−−−−% Max_Asw = 3.5; %MAXIMUM TOTAL area of all MOSFETS combined in MILLIMETRES SQUARED(mm^2) %NOTE: Below you can set the MINIMUM area for each MOSFET INDIVIDUALLY, in %MILLIMETERS SQUARED(mm^2). By default, it is defined asa proportion of the total %max. area. To TURN OFF these constraints, just set them to zero. Min_Asw1 = 0.1*Max_Asw; %MINIMUM area of MOSFET1(mm^2) Min_Asw2 = 0.1*Max_Asw; %MINIMUM area of MOSFET2(mm^2) Min_Asw3 = 0.1*Max_Asw; %MINIMUM area of MOSFET3(mm^2) Min_Asw4 = 0.1*Max_Asw; %MINIMUM area of MOSFET4(mm^2) Min_Asw5 = 0.1*Max_Asw; %MINIMUM area of MOSFET5(mm^2) Min_Asw6 = 0.1*Max_Asw; %MINIMUM area of MOSFET6(mm^2) Min_Asw7 = 0.1*Max_Asw; %MINIMUM area of MOSFET7(mm^2) %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−%

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−−−−−−−−−−−−CALCULATE LOAD CURVE VALUES:−−−−−−−−−−−−−−−%

%Calculate output load resistance from output voltage and current Rout = Vout / Iout_actual; Rout_rated = Vout / Iout_rated;

%Calculate currents and Routs at the different efficiency targets Iout_20 = 0.2*Iout_rated; Iout_40 = 0.4*Iout_rated; Iout_60 = 0.6*Iout_rated; Iout_80 = 0.8*Iout_rated; Iout_100 = Iout_rated; Rout_20 = Vout / Iout_20; Rout_40 = Vout / Iout_40; 113

Rout_60 = Vout / Iout_60; Rout_80 = Vout / Iout_80; Rout_100 = Vout / Iout_100; %Convert efficiency targets to Watts Pout_20 = Vout * Iout_20; Pout_40 = Vout * Iout_40; Pout_60 = Vout * Iout_60; Pout_80 = Vout * Iout_80; Pout_100 = Vout * Iout_100; Loss_20 = Pout_20/Eff_20 − Pout_20; %maximum allowed losses at 20% load in WATTS (W) Loss_40 = Pout_40/Eff_40 − Pout_40; %maximum allowed losses at 40% load in WATTS (W) Loss_60 = Pout_60/Eff_60 − Pout_60; %maximum allowed losses at 60% load in WATTS (W) Loss_80 = Pout_80/Eff_80 − Pout_80; %maximum allowed losses at 80% load in WATTS (W) Loss_100 = Pout_100/Eff_100 − Pout_100; %maximum allowed losses at 100% load in WATTS(W) Pout_part = [Pout_20 Pout_40 Pout_60 Pout_80 Pout_100]; %create cell array to store values loadcurve = cell(6,16); loadcurve{1,1} = ['Load%']; loadcurve{1,2} = ['IS_RMS']; loadcurve{1,3} = ['IS_ON']; loadcurve{1,4} = ['IS_OFF']; loadcurve{1,5} = ['VS']; loadcurve{1,6} = ['# Transitions']; loadcurve{1,7} = ['IL_RMS']; loadcurve{1,8} = ['Cond. Loss']; loadcurve{1,9} = ['Sw. Loss']; loadcurve{1,10} = ['Coss Loss']; loadcurve{1,11} = ['Gate Loss']; loadcurve{1,12} = ['Tot. Loss Per Switch']; loadcurve{1,13} = ['Ind. Loss']; loadcurve{1,14} = ['Load Current']; loadcurve{1,15} = ['Total Losses']; loadcurve{1,16} = ['Efficiency']; loadcurve{2,1} = [0.2]; loadcurve{3,1} = [0.4]; loadcurve{4,1} = [0.6]; loadcurve{5,1} = [0.8]; loadcurve{6,1} = [1.0]; loadcurve{2,14} = [Iout_20]; loadcurve{3,14} = [Iout_40]; loadcurve{4,14} = [Iout_60]; loadcurve{5,14} = [Iout_80]; loadcurve{6,14} = [Iout_100]; 114

Rout_part = [Rout_20 Rout_40 Rout_60 Rout_80 Rout_100]; %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−%

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−−−−−−−−CONNECTION TO GECKOCIRCUITS MODEL:−−−−−−−−−−−−−% connectToGecko(); %connect to GeckoCIRCUITS(if already connected, this does nothing)

%SET FIXED PARAMETERS% setParameter('SW_FREQ','const',fsw); %set switching frequency setParameter('VIN','const',Vin); %set input voltage setParameter('VOUT','const',Vout_ref); %set output voltage setParameter('MODE_PREF','const',mode); %set preferred mode of operation setParameter('ROUT','const',Rout); %set actual load resistance setParameter('R.out','R',Rout); %set actual load resistance(circuit component) setParameter('RATED_ROUT','const',Rout_rated); %set rated load resistance setParameter('L.1','L',L); %set inductance of inductor1 setParameter('R.L1','R',RL); %set ESR of inductor1 setParameter('L.2','L',L); %set inductance of inductor2 setParameter('R.L2','R',RL); %set ESR of inductor2 setParameter('C.FLY','C',Cfly); %set capacitance of flying capacitor setParameter('C.FLY','uC(0)',0.5*Vin); %set initial voltage of flying capacitor setParameter('C.out','C',Cout); %set capacitance of output capacitor setParameter('C.out','uC(0)',Vout_ref); %set initial voltage of output capacitor setParameter('MOSFET.1','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET1 setParameter('MOSFET.2','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET2 setParameter('MOSFET.3','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET3 setParameter('MOSFET.4','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET4 setParameter('MOSFET.5','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET5 setParameter('MOSFET.6','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET6 setParameter('MOSFET.7','ad_uF',Vd_mos); %set body diode forward voltage of MOSFET7

%TIME STEP FOR SIMULATION% dt = (1/fsw)/1250; %IMPORTANT! Time step must be small enough for proper simulation of flying cap voltage %The above givesa1 ns time step fora switching frequency of 800 kHz %SIMULATION TIME% tend = (1/fsw)*500; %simulate up to 500 cycles(to ensure steady state) %Simulation may end earlier each time if steady state is detected 115

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−%

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−SIMULATE TO EXTRACT VOLTAGES AND CURRENTS AND OPTIMIZE:−−−−% converged = false; steadyStateVars = {'IL1','IL2','V.Cfly','V.out'}; initSteadyStateDetection(steadyStateVars,fsw,dt,tend); %NOTE: Since the change of Rdson due to optimization changes the RMS %currents in the switches, we iterate until the RMS currents we started %with are the same as the RMS currents we end with(within some tolerance) allowable_error = 0.15; %The allowable error is defined by the norm of the relative error vectors %of the RMS currents before and after optimization. If we allow an error of %5% with each current, that givesa norm of sqrt(7 *0.05^2)= 0.13229 max_iterations = 5; %the maximum number of iterations allowed before we stop trying to achieve convergence iteration = 0; while (~converged) iteration = iteration + 1; fprintf('Iteration%d',iteration); %OPTIMIZATION POINT% %Here we simulate first with the operating point at which we are %optimizing setParameter('ROUT','const',Rout); %set actual load resistance setParameter('R.out','R',Rout); %set actual load resistance(circuit component) results = simulateToSteadyState(true,0.995,0.001); time = results(2); Ts = results(3); %Now extract all necessary voltages and currents %RMS CURRENTS% IS_RMS = zeros(7,1); IS_RMS(1) = getSignalRMS('IS1',time−Ts,time); IS_RMS(2) = getSignalRMS('IS2',time−Ts,time); IS_RMS(3) = getSignalRMS('IS3',time−Ts,time); IS_RMS(4) = getSignalRMS('IS4',time−Ts,time); IS_RMS(5) = getSignalRMS('IS5',time−Ts,time); IS_RMS(6) = getSignalRMS('IS6',time−Ts,time); IS_RMS(7) = getSignalRMS('IS7',time−Ts,time); %ON/OFF CURRENTS% IS_ON = zeros(7,1); IS_ON(1) = abs(getSignalAvg('IS1_ON',time−Ts,time)); IS_ON(2) = abs(getSignalAvg('IS2_ON',time−Ts,time)); IS_ON(3) = abs(getSignalAvg('IS3_ON',time−Ts,time)); IS_ON(4) = abs(getSignalAvg('IS4_ON',time−Ts,time)); IS_ON(5) = abs(getSignalAvg('IS5_ON',time−Ts,time)); IS_ON(6) = abs(getSignalAvg('IS6_ON',time−Ts,time)); IS_ON(7) = abs(getSignalAvg('IS7_ON',time−Ts,time)); 116

IS_OFF = zeros(7,1); IS_OFF(1) = abs(getSignalAvg('IS1_OFF',time−Ts,time)); IS_OFF(2) = abs(getSignalAvg('IS2_OFF',time−Ts,time)); IS_OFF(3) = abs(getSignalAvg('IS3_OFF',time−Ts,time)); IS_OFF(4) = abs(getSignalAvg('IS4_OFF',time−Ts,time)); IS_OFF(5) = abs(getSignalAvg('IS5_OFF',time−Ts,time)); IS_OFF(6) = abs(getSignalAvg('IS6_OFF',time−Ts,time)); IS_OFF(7) = abs(getSignalAvg('IS7_OFF',time−Ts,time)); %BLOCKING VOLTAGES% VS = zeros(7,1); VS(1) = abs(getSignalMax('VS1',time−Ts,time)); VS(2) = abs(getSignalMax('VS2',time−Ts,time)); VS(3) = abs(getSignalMax('VS3',time−Ts,time)); VS(4) = abs(getSignalMax('VS4',time−Ts,time)); VS(5) = abs(getSignalMax('VS5',time−Ts,time)); VS(6) = abs(getSignalMax('VS6',time−Ts,time)); VS(7) = abs(getSignalMax('VS7',time−Ts,time)); %NUMBER OF TRANSITIONS% ST = zeros(7,1); ST(1) = round(abs(getSignalAvg('S1_T',time−Ts,time))); ST(2) = round(abs(getSignalAvg('S2_T',time−Ts,time))); ST(3) = round(abs(getSignalAvg('S3_T',time−Ts,time))); ST(4) = round(abs(getSignalAvg('S4_T',time−Ts,time))); ST(5) = round(abs(getSignalAvg('S5_T',time−Ts,time))); ST(6) = round(abs(getSignalAvg('S6_T',time−Ts,time))); ST(7) = round(abs(getSignalAvg('S7_T',time−Ts,time))); %INDUCTOR RMS CURRENT% IL = zeros(2,1); IL(1) = getSignalRMS('IL1',time−Ts,time); IL(2) = getSignalRMS('IL2',time−Ts,time); %SIMULATE OVER ENTIRE SPECIFIED LOAD CURVE% %Now we simulate over the load curve points for which we have %efficiency targets for i=1:5 setParameter('ROUT','const',Rout_part(i)); %set actual load resistance setParameter('R.out','R',Rout_part(i)); %set actual load resistance( circuit component) initSteadyStateDetection(steadyStateVars,fsw,dt,tend); results = simulateToSteadyState(false,0.995,0.001); time = results(2); Ts = results(3); %Now extract all necessary voltages and currents at the part load %RMS CURRENTS% IS_RMS_PART = zeros(7,1); IS_RMS_PART(1) = getSignalRMS('IS1',time−Ts,time); IS_RMS_PART(2) = getSignalRMS('IS2',time−Ts,time); IS_RMS_PART(3) = getSignalRMS('IS3',time−Ts,time); IS_RMS_PART(4) = getSignalRMS('IS4',time−Ts,time); 117

IS_RMS_PART(5) = getSignalRMS('IS5',time−Ts,time); IS_RMS_PART(6) = getSignalRMS('IS6',time−Ts,time); IS_RMS_PART(7) = getSignalRMS('IS7',time−Ts,time); loadcurve{i+1,2} = IS_RMS_PART; %ON/OFF CURRENTS% IS_ON_PART = zeros(7,1); IS_ON_PART(1) = abs(getSignalAvg('IS1_ON',time−Ts,time)); IS_ON_PART(2) = abs(getSignalAvg('IS2_ON',time−Ts,time)); IS_ON_PART(3) = abs(getSignalAvg('IS3_ON',time−Ts,time)); IS_ON_PART(4) = abs(getSignalAvg('IS4_ON',time−Ts,time)); IS_ON_PART(5) = abs(getSignalAvg('IS5_ON',time−Ts,time)); IS_ON_PART(6) = abs(getSignalAvg('IS6_ON',time−Ts,time)); IS_ON_PART(7) = abs(getSignalAvg('IS7_ON',time−Ts,time)); loadcurve{i+1,3} = IS_ON_PART; IS_OFF_PART = zeros(7,1); IS_OFF_PART(1) = abs(getSignalAvg('IS1_OFF',time−Ts,time)); IS_OFF_PART(2) = abs(getSignalAvg('IS2_OFF',time−Ts,time)); IS_OFF_PART(3) = abs(getSignalAvg('IS3_OFF',time−Ts,time)); IS_OFF_PART(4) = abs(getSignalAvg('IS4_OFF',time−Ts,time)); IS_OFF_PART(5) = abs(getSignalAvg('IS5_OFF',time−Ts,time)); IS_OFF_PART(6) = abs(getSignalAvg('IS6_OFF',time−Ts,time)); IS_OFF_PART(7) = abs(getSignalAvg('IS7_OFF',time−Ts,time)); loadcurve{i+1,4} = IS_OFF_PART; %BLOCKING VOLTAGES% VS_PART = zeros(7,1); VS_PART(1) = abs(getSignalMax('VS1',time−Ts,time)); VS_PART(2) = abs(getSignalMax('VS2',time−Ts,time)); VS_PART(3) = abs(getSignalMax('VS3',time−Ts,time)); VS_PART(4) = abs(getSignalMax('VS4',time−Ts,time)); VS_PART(5) = abs(getSignalMax('VS5',time−Ts,time)); VS_PART(6) = abs(getSignalMax('VS6',time−Ts,time)); VS_PART(7) = abs(getSignalMax('VS7',time−Ts,time)); loadcurve{i+1,5} = VS_PART; %NUMBER OF TRANSITIONS% ST_PART = zeros(7,1); ST_PART(1) = round(abs(getSignalAvg('S1_T',time−Ts,time))); ST_PART(2) = round(abs(getSignalAvg('S2_T',time−Ts,time))); ST_PART(3) = round(abs(getSignalAvg('S3_T',time−Ts,time))); ST_PART(4) = round(abs(getSignalAvg('S4_T',time−Ts,time))); ST_PART(5) = round(abs(getSignalAvg('S5_T',time−Ts,time))); ST_PART(6) = round(abs(getSignalAvg('S6_T',time−Ts,time))); ST_PART(7) = round(abs(getSignalAvg('S7_T',time−Ts,time))); loadcurve{i+1,6} = ST_PART; %INDUCTOR RMS CURRENT% IL_PART = zeros(2,1); IL_PART(1) = getSignalRMS('IL1',time−Ts,time); IL_PART(2) = getSignalRMS('IL2',time−Ts,time); loadcurve{i+1,7} = IL_PART; 118

end %GEOMETRIC PROGRAM TO OPTIMIZE SWITCH AREAS% %Now, using the extracted voltages and currents, we size each switch %for minimum losses at the selected operating point cvx_begin gp variables A1 A2 A3 A4 A5 A6 A7 %switch areas in mm^2 %minimize total losses at selected optimization point minimize((IS_RMS(1)^2)*(S1F*Rdson_mm2/A1) + (IS_RMS(1)^2)*S1D + 0.5*VS (1)*ST(1)*fsw*(IS_ON(1)*ton + IS_OFF(1)*toff) + 0.5*Coss_mm2*A1*(VS (1)^2)*ST(1)*fsw + Cin_mm2*A1*(Vg^2)*ST(1)*fsw ... + (IS_RMS(2)^2)*(S2F*Rdson_mm2/A2) + (IS_RMS(2)^2)*S2D + 0.5*VS (2)*ST(2)*fsw*(IS_ON(2)*ton + IS_OFF(2)*toff) + 0.5*Coss_mm2 *A2*(VS(2)^2)*ST(2)*fsw + Cin_mm2*A2*(Vg^2)*ST(2)*fsw ... + (IS_RMS(3)^2)*(S3F*Rdson_mm2/A3) + (IS_RMS(3)^2)*S3D + 0.5*VS (3)*ST(3)*fsw*(IS_ON(3)*ton + IS_OFF(3)*toff) + 0.5*Coss_mm2 *A3*(VS(3)^2)*ST(3)*fsw + Cin_mm2*A3*(Vg^2)*ST(3)*fsw ... + (IS_RMS(4)^2)*(S4F*Rdson_mm2/A4) + (IS_RMS(4)^2)*S4D + 0.5*VS (4)*ST(4)*fsw*(IS_ON(4)*ton + IS_OFF(4)*toff) + 0.5*Coss_mm2 *A4*(VS(4)^2)*ST(4)*fsw + Cin_mm2*A4*(Vg^2)*ST(4)*fsw ... + (IS_RMS(5)^2)*(S5F*Rdson_mm2/A5) + (IS_RMS(5)^2)*S5D + 0.5*VS (5)*ST(5)*fsw*(IS_ON(5)*ton + IS_OFF(5)*toff) + 0.5*Coss_mm2 *A5*(VS(5)^2)*ST(5)*fsw + Cin_mm2*A5*(Vg^2)*ST(5)*fsw ... + (IS_RMS(6)^2)*(S6F*Rdson_mm2/A6) + (IS_RMS(6)^2)*S6D + 0.5*VS (6)*ST(6)*fsw*(IS_ON(6)*ton + IS_OFF(6)*toff) + 0.5*Coss_mm2 *A6*(VS(6)^2)*ST(6)*fsw + Cin_mm2*A6*(Vg^2)*ST(6)*fsw ... + (IS_RMS(7)^2)*(S7F*Rdson_mm2/A7) + (IS_RMS(7)^2)*S7D + 0.5*VS (7)*ST(7)*fsw*(IS_ON(7)*ton + IS_OFF(7)*toff) + 0.5*Coss_mm2 *A7*(VS(7)^2)*ST(7)*fsw + Cin_mm2*A7*(Vg^2)*ST(7)*fsw) %constraints subject to %max total area A1 + A2 + A3 + A4 + A5 + A6 + A7 <= Max_Asw; %minimum area for each switch A1 >= Min_Asw1; A2 >= Min_Asw2; A3 >= Min_Asw3; A4 >= Min_Asw4; A5 >= Min_Asw5; A6 >= Min_Asw6; A7 >= Min_Asw7; %maximum losses(minimum efficiency) at 20% load (loadcurve{2,2}(1)^2)*(S1F*Rdson_mm2/A1) + (loadcurve{2,2}(1)^2)*S1D + 0.5*loadcurve{2,5}(1)*loadcurve{2,6}(1)*fsw*(loadcurve{2,3}(1) *ton + loadcurve{2,4}(1)*toff) + 0.5*Coss_mm2*A1*(loadcurve {2,5}(1)^2)*loadcurve{2,6}(1)*fsw + Cin_mm2*A1*(Vg^2)*loadcurve {2,6}(1)*fsw ... + (loadcurve{2,2}(2)^2)*(S2F*Rdson_mm2/A2) + (loadcurve{2,2}(2) ^2)*S2D + 0.5*loadcurve{2,5}(2)*loadcurve{2,6}(2)*fsw*( 119

loadcurve{2,3}(2)*ton + loadcurve{2,4}(2)*toff) + 0.5* Coss_mm2*A2*(loadcurve{2,5}(2)^2)*loadcurve{2,6}(2)*fsw + Cin_mm2*A2*(Vg^2)*loadcurve{2,6}(2)*fsw ... + (loadcurve{2,2}(3)^2)*(S3F*Rdson_mm2/A3) + (loadcurve{2,2}(3) ^2)*S3D + 0.5*loadcurve{2,5}(3)*loadcurve{2,6}(3)*fsw*( loadcurve{2,3}(3)*ton + loadcurve{2,4}(3)*toff) + 0.5* Coss_mm2*A3*(loadcurve{2,5}(3)^2)*loadcurve{2,6}(3)*fsw + Cin_mm2*A3*(Vg^2)*loadcurve{2,6}(3)*fsw ... + (loadcurve{2,2}(4)^2)*(S4F*Rdson_mm2/A4) + (loadcurve{2,2}(4) ^2)*S4D + 0.5*loadcurve{2,5}(4)*loadcurve{2,6}(4)*fsw*( loadcurve{2,3}(4)*ton + loadcurve{2,4}(4)*toff) + 0.5* Coss_mm2*A4*(loadcurve{2,5}(4)^2)*loadcurve{2,6}(4)*fsw + Cin_mm2*A4*(Vg^2)*loadcurve{2,6}(4)*fsw ... + (loadcurve{2,2}(5)^2)*(S5F*Rdson_mm2/A5) + (loadcurve{2,2}(5) ^2)*S5D + 0.5*loadcurve{2,5}(5)*loadcurve{2,6}(5)*fsw*( loadcurve{2,3}(5)*ton + loadcurve{2,4}(5)*toff) + 0.5* Coss_mm2*A5*(loadcurve{2,5}(5)^2)*loadcurve{2,6}(5)*fsw + Cin_mm2*A5*(Vg^2)*loadcurve{2,6}(5)*fsw ... + (loadcurve{2,2}(6)^2)*(S6F*Rdson_mm2/A6) + (loadcurve{2,2}(6) ^2)*S6D + 0.5*loadcurve{2,5}(6)*loadcurve{2,6}(6)*fsw*( loadcurve{2,3}(6)*ton + loadcurve{2,4}(6)*toff) + 0.5* Coss_mm2*A6*(loadcurve{2,5}(6)^2)*loadcurve{2,6}(6)*fsw + Cin_mm2*A6*(Vg^2)*loadcurve{2,6}(6)*fsw ... + (loadcurve{2,2}(7)^2)*(S7F*Rdson_mm2/A7) + (loadcurve{2,2}(7) ^2)*S7D + 0.5*loadcurve{2,5}(7)*loadcurve{2,6}(7)*fsw*( loadcurve{2,3}(7)*ton + loadcurve{2,4}(7)*toff) + 0.5* Coss_mm2*A7*(loadcurve{2,5}(7)^2)*loadcurve{2,6}(7)*fsw + Cin_mm2*A7*(Vg^2)*loadcurve{2,6}(7)*fsw <= Loss_20; %maximum losses(minimum efficiency) at 40% load (loadcurve{3,2}(1)^2)*(S1F*Rdson_mm2/A1) + (loadcurve{3,2}(1)^2)*S1D + 0.5*loadcurve{3,5}(1)*loadcurve{3,6}(1)*fsw*(loadcurve{3,3}(1) *ton + loadcurve{3,4}(1)*toff) + 0.5*Coss_mm2*A1*(loadcurve {3,5}(1)^2)*loadcurve{3,6}(1)*fsw + Cin_mm2*A1*(Vg^2)*loadcurve {3,6}(1)*fsw ... + (loadcurve{3,2}(2)^2)*(S2F*Rdson_mm2/A2) + (loadcurve{3,2}(2) ^2)*S2D + 0.5*loadcurve{3,5}(2)*loadcurve{3,6}(2)*fsw*( loadcurve{3,3}(2)*ton + loadcurve{3,4}(2)*toff) + 0.5* Coss_mm2*A2*(loadcurve{3,5}(2)^2)*loadcurve{3,6}(2)*fsw + Cin_mm2*A2*(Vg^2)*loadcurve{3,6}(2)*fsw ... + (loadcurve{3,2}(3)^2)*(S3F*Rdson_mm2/A3) + (loadcurve{3,2}(3) ^2)*S3D + 0.5*loadcurve{3,5}(3)*loadcurve{3,6}(3)*fsw*( loadcurve{3,3}(3)*ton + loadcurve{3,4}(3)*toff) + 0.5* Coss_mm2*A3*(loadcurve{3,5}(3)^2)*loadcurve{3,6}(3)*fsw + Cin_mm2*A3*(Vg^2)*loadcurve{3,6}(3)*fsw ... + (loadcurve{3,2}(4)^2)*(S4F*Rdson_mm2/A4) + (loadcurve{3,2}(4) ^2)*S4D + 0.5*loadcurve{3,5}(4)*loadcurve{3,6}(4)*fsw*( loadcurve{3,3}(4)*ton + loadcurve{3,4}(4)*toff) + 0.5* Coss_mm2*A4*(loadcurve{3,5}(4)^2)*loadcurve{3,6}(4)*fsw + 120

Cin_mm2*A4*(Vg^2)*loadcurve{3,6}(4)*fsw ... + (loadcurve{3,2}(5)^2)*(S5F*Rdson_mm2/A5) + (loadcurve{3,2}(5) ^2)*S5D + 0.5*loadcurve{3,5}(5)*loadcurve{3,6}(5)*fsw*( loadcurve{3,3}(5)*ton + loadcurve{3,4}(5)*toff) + 0.5* Coss_mm2*A5*(loadcurve{3,5}(5)^2)*loadcurve{3,6}(5)*fsw + Cin_mm2*A5*(Vg^2)*loadcurve{3,6}(5)*fsw ... + (loadcurve{3,2}(6)^2)*(S6F*Rdson_mm2/A6) + (loadcurve{3,2}(6) ^2)*S6D + 0.5*loadcurve{3,5}(6)*loadcurve{3,6}(6)*fsw*( loadcurve{3,3}(6)*ton + loadcurve{3,4}(6)*toff) + 0.5* Coss_mm2*A6*(loadcurve{3,5}(6)^2)*loadcurve{3,6}(6)*fsw + Cin_mm2*A6*(Vg^2)*loadcurve{3,6}(6)*fsw ... + (loadcurve{3,2}(7)^2)*(S7F*Rdson_mm2/A7) + (loadcurve{3,2}(7) ^2)*S7D + 0.5*loadcurve{3,5}(7)*loadcurve{3,6}(7)*fsw*( loadcurve{3,3}(7)*ton + loadcurve{3,4}(7)*toff) + 0.5* Coss_mm2*A7*(loadcurve{3,5}(7)^2)*loadcurve{3,6}(7)*fsw + Cin_mm2*A7*(Vg^2)*loadcurve{3,6}(7)*fsw <= Loss_40; %maximum losses(minimum efficiency) at 60% load (loadcurve{4,2}(1)^2)*(S1F*Rdson_mm2/A1) + (loadcurve{4,2}(1)^2)*S1D + 0.5*loadcurve{4,5}(1)*loadcurve{4,6}(1)*fsw*(loadcurve{4,3}(1) *ton + loadcurve{4,4}(1)*toff) + 0.5*Coss_mm2*A1*(loadcurve {4,5}(1)^2)*loadcurve{4,6}(1)*fsw + Cin_mm2*A1*(Vg^2)*loadcurve {4,6}(1)*fsw ... + (loadcurve{4,2}(2)^2)*(S2F*Rdson_mm2/A2) + (loadcurve{4,2}(2) ^2)*S2D + 0.5*loadcurve{4,5}(2)*loadcurve{4,6}(2)*fsw*( loadcurve{4,3}(2)*ton + loadcurve{4,4}(2)*toff) + 0.5* Coss_mm2*A2*(loadcurve{4,5}(2)^2)*loadcurve{4,6}(2)*fsw + Cin_mm2*A2*(Vg^2)*loadcurve{4,6}(2)*fsw ... + (loadcurve{4,2}(3)^2)*(S3F*Rdson_mm2/A3) + (loadcurve{4,2}(3) ^2)*S3D + 0.5*loadcurve{4,5}(3)*loadcurve{4,6}(3)*fsw*( loadcurve{4,3}(3)*ton + loadcurve{4,4}(3)*toff) + 0.5* Coss_mm2*A3*(loadcurve{4,5}(3)^2)*loadcurve{4,6}(3)*fsw + Cin_mm2*A3*(Vg^2)*loadcurve{4,6}(3)*fsw ... + (loadcurve{4,2}(4)^2)*(S4F*Rdson_mm2/A4) + (loadcurve{4,2}(4) ^2)*S4D + 0.5*loadcurve{4,5}(4)*loadcurve{4,6}(4)*fsw*( loadcurve{4,3}(4)*ton + loadcurve{4,4}(4)*toff) + 0.5* Coss_mm2*A4*(loadcurve{4,5}(4)^2)*loadcurve{4,6}(4)*fsw + Cin_mm2*A4*(Vg^2)*loadcurve{4,6}(4)*fsw ... + (loadcurve{4,2}(5)^2)*(S5F*Rdson_mm2/A5) + (loadcurve{4,2}(5) ^2)*S5D + 0.5*loadcurve{4,5}(5)*loadcurve{4,6}(5)*fsw*( loadcurve{4,3}(5)*ton + loadcurve{4,4}(5)*toff) + 0.5* Coss_mm2*A5*(loadcurve{4,5}(5)^2)*loadcurve{4,6}(5)*fsw + Cin_mm2*A5*(Vg^2)*loadcurve{4,6}(5)*fsw ... + (loadcurve{4,2}(6)^2)*(S6F*Rdson_mm2/A6) + (loadcurve{4,2}(6) ^2)*S6D + 0.5*loadcurve{4,5}(6)*loadcurve{4,6}(6)*fsw*( loadcurve{4,3}(6)*ton + loadcurve{4,4}(6)*toff) + 0.5* Coss_mm2*A6*(loadcurve{4,5}(6)^2)*loadcurve{4,6}(6)*fsw + Cin_mm2*A6*(Vg^2)*loadcurve{4,6}(6)*fsw ... + (loadcurve{4,2}(7)^2)*(S7F*Rdson_mm2/A7) + (loadcurve{4,2}(7) 121

^2)*S7D + 0.5*loadcurve{4,5}(7)*loadcurve{4,6}(7)*fsw*( loadcurve{4,3}(7)*ton + loadcurve{4,4}(7)*toff) + 0.5* Coss_mm2*A7*(loadcurve{4,5}(7)^2)*loadcurve{4,6}(7)*fsw + Cin_mm2*A7*(Vg^2)*loadcurve{4,6}(7)*fsw <= Loss_60; %maximum losses(minimum efficiency) at 80% load (loadcurve{5,2}(1)^2)*(S1F*Rdson_mm2/A1) + (loadcurve{5,2}(1)^2)*S1D + 0.5*loadcurve{5,5}(1)*loadcurve{5,6}(1)*fsw*(loadcurve{5,3}(1) *ton + loadcurve{5,4}(1)*toff) + 0.5*Coss_mm2*A1*(loadcurve {5,5}(1)^2)*loadcurve{5,6}(1)*fsw + Cin_mm2*A1*(Vg^2)*loadcurve {5,6}(1)*fsw ... + (loadcurve{5,2}(2)^2)*(S2F*Rdson_mm2/A2) + (loadcurve{5,2}(2) ^2)*S2D + 0.5*loadcurve{5,5}(2)*loadcurve{5,6}(2)*fsw*( loadcurve{5,3}(2)*ton + loadcurve{5,4}(2)*toff) + 0.5* Coss_mm2*A2*(loadcurve{5,5}(2)^2)*loadcurve{5,6}(2)*fsw + Cin_mm2*A2*(Vg^2)*loadcurve{5,6}(2)*fsw ... + (loadcurve{5,2}(3)^2)*(S3F*Rdson_mm2/A3) + (loadcurve{5,2}(3) ^2)*S3D + 0.5*loadcurve{5,5}(3)*loadcurve{5,6}(3)*fsw*( loadcurve{5,3}(3)*ton + loadcurve{5,4}(3)*toff) + 0.5* Coss_mm2*A3*(loadcurve{5,5}(3)^2)*loadcurve{5,6}(3)*fsw + Cin_mm2*A3*(Vg^2)*loadcurve{5,6}(3)*fsw ... + (loadcurve{5,2}(4)^2)*(S4F*Rdson_mm2/A4) + (loadcurve{5,2}(4) ^2)*S4D + 0.5*loadcurve{5,5}(4)*loadcurve{5,6}(4)*fsw*( loadcurve{5,3}(4)*ton + loadcurve{5,4}(4)*toff) + 0.5* Coss_mm2*A4*(loadcurve{5,5}(4)^2)*loadcurve{5,6}(4)*fsw + Cin_mm2*A4*(Vg^2)*loadcurve{5,6}(4)*fsw ... + (loadcurve{5,2}(5)^2)*(S5F*Rdson_mm2/A5) + (loadcurve{5,2}(5) ^2)*S5D + 0.5*loadcurve{5,5}(5)*loadcurve{5,6}(5)*fsw*( loadcurve{5,3}(5)*ton + loadcurve{5,4}(5)*toff) + 0.5* Coss_mm2*A5*(loadcurve{5,5}(5)^2)*loadcurve{5,6}(5)*fsw + Cin_mm2*A5*(Vg^2)*loadcurve{5,6}(5)*fsw ... + (loadcurve{5,2}(6)^2)*(S6F*Rdson_mm2/A6) + (loadcurve{5,2}(6) ^2)*S6D + 0.5*loadcurve{5,5}(6)*loadcurve{5,6}(6)*fsw*( loadcurve{5,3}(6)*ton + loadcurve{5,4}(6)*toff) + 0.5* Coss_mm2*A6*(loadcurve{5,5}(6)^2)*loadcurve{5,6}(6)*fsw + Cin_mm2*A6*(Vg^2)*loadcurve{5,6}(6)*fsw ... + (loadcurve{5,2}(7)^2)*(S7F*Rdson_mm2/A7) + (loadcurve{5,2}(7) ^2)*S7D + 0.5*loadcurve{5,5}(7)*loadcurve{5,6}(7)*fsw*( loadcurve{5,3}(7)*ton + loadcurve{5,4}(7)*toff) + 0.5* Coss_mm2*A7*(loadcurve{5,5}(7)^2)*loadcurve{5,6}(7)*fsw + Cin_mm2*A7*(Vg^2)*loadcurve{5,6}(7)*fsw <= Loss_80; %maximum losses(minimum efficiency) at 100% load (loadcurve{6,2}(1)^2)*(S1F*Rdson_mm2/A1) + (loadcurve{6,2}(1)^2)*S1D + 0.5*loadcurve{6,5}(1)*loadcurve{6,6}(1)*fsw*(loadcurve{6,3}(1) *ton + loadcurve{6,4}(1)*toff) + 0.5*Coss_mm2*A1*(loadcurve {6,5}(1)^2)*loadcurve{6,6}(1)*fsw + Cin_mm2*A1*(Vg^2)*loadcurve {6,6}(1)*fsw ... + (loadcurve{6,2}(2)^2)*(S2F*Rdson_mm2/A2) + (loadcurve{6,2}(2) ^2)*S2D + 0.5*loadcurve{6,5}(2)*loadcurve{6,6}(2)*fsw*( 122

loadcurve{6,3}(2)*ton + loadcurve{6,4}(2)*toff) + 0.5* Coss_mm2*A2*(loadcurve{6,5}(2)^2)*loadcurve{6,6}(2)*fsw + Cin_mm2*A2*(Vg^2)*loadcurve{6,6}(2)*fsw ... + (loadcurve{6,2}(3)^2)*(S3F*Rdson_mm2/A3) + (loadcurve{6,2}(3) ^2)*S3D + 0.5*loadcurve{6,5}(3)*loadcurve{6,6}(3)*fsw*( loadcurve{6,3}(3)*ton + loadcurve{6,4}(3)*toff) + 0.5* Coss_mm2*A3*(loadcurve{6,5}(3)^2)*loadcurve{6,6}(3)*fsw + Cin_mm2*A3*(Vg^2)*loadcurve{6,6}(3)*fsw ... + (loadcurve{6,2}(4)^2)*(S4F*Rdson_mm2/A4) + (loadcurve{6,2}(4) ^2)*S4D + 0.5*loadcurve{6,5}(4)*loadcurve{6,6}(4)*fsw*( loadcurve{6,3}(4)*ton + loadcurve{6,4}(4)*toff) + 0.5* Coss_mm2*A4*(loadcurve{6,5}(4)^2)*loadcurve{6,6}(4)*fsw + Cin_mm2*A4*(Vg^2)*loadcurve{6,6}(4)*fsw ... + (loadcurve{6,2}(5)^2)*(S5F*Rdson_mm2/A5) + (loadcurve{6,2}(5) ^2)*S5D + 0.5*loadcurve{6,5}(5)*loadcurve{6,6}(5)*fsw*( loadcurve{6,3}(5)*ton + loadcurve{6,4}(5)*toff) + 0.5* Coss_mm2*A5*(loadcurve{6,5}(5)^2)*loadcurve{6,6}(5)*fsw + Cin_mm2*A5*(Vg^2)*loadcurve{6,6}(5)*fsw ... + (loadcurve{6,2}(6)^2)*(S6F*Rdson_mm2/A6) + (loadcurve{6,2}(6) ^2)*S6D + 0.5*loadcurve{6,5}(6)*loadcurve{6,6}(6)*fsw*( loadcurve{6,3}(6)*ton + loadcurve{6,4}(6)*toff) + 0.5* Coss_mm2*A6*(loadcurve{6,5}(6)^2)*loadcurve{6,6}(6)*fsw + Cin_mm2*A6*(Vg^2)*loadcurve{6,6}(6)*fsw ... + (loadcurve{6,2}(7)^2)*(S7F*Rdson_mm2/A7) + (loadcurve{6,2}(7) ^2)*S7D + 0.5*loadcurve{6,5}(7)*loadcurve{6,6}(7)*fsw*( loadcurve{6,3}(7)*ton + loadcurve{6,4}(7)*toff) + 0.5* Coss_mm2*A7*(loadcurve{6,5}(7)^2)*loadcurve{6,6}(7)*fsw + Cin_mm2*A7*(Vg^2)*loadcurve{6,6}(7)*fsw <= Loss_100; cvx_end %CALCULATE NEW RDSON% Rdson = zeros(7,1); Rdson(1) = S1F*Rdson_mm2/A1 + S1D; Rdson(2) = S2F*Rdson_mm2/A2 + S2D; Rdson(3) = S3F*Rdson_mm2/A3 + S3D; Rdson(4) = S4F*Rdson_mm2/A4 + S4D; Rdson(5) = S5F*Rdson_mm2/A5 + S5D; Rdson(6) = S6F*Rdson_mm2/A6 + S6D; Rdson(7) = S7F*Rdson_mm2/A7 + S7D; %SET AND RE−SIMULATE OPERATING POINT% setParameter('MOSFET.1','rON',Rdson(1)); %set on−resistance of MOSFET1 setParameter('MOSFET.2','rON',Rdson(2)); %set on−resistance of MOSFET2 setParameter('MOSFET.3','rON',Rdson(3)); %set on−resistance of MOSFET3 setParameter('MOSFET.4','rON',Rdson(4)); %set on−resistance of MOSFET4 setParameter('MOSFET.5','rON',Rdson(5)); %set on−resistance of MOSFET5 setParameter('MOSFET.6','rON',Rdson(6)); %set on−resistance of MOSFET6 setParameter('MOSFET.7','rON',Rdson(7)); %set on−resistance of MOSFET7 setParameter('ROUT','const',Rout); %set actual load resistance setParameter('R.out','R',Rout); %set actual load resistance(circuit 123

component) initSteadyStateDetection(steadyStateVars,fsw,dt,tend); results = simulateToSteadyState(false,0.995,0.001); time = results(2); Ts = results(3); IS_RMS_NEW = zeros(7,1); IS_RMS_NEW(1) = getSignalRMS('IS1',time−Ts,time); IS_RMS_NEW(2) = getSignalRMS('IS2',time−Ts,time); IS_RMS_NEW(3) = getSignalRMS('IS3',time−Ts,time); IS_RMS_NEW(4) = getSignalRMS('IS4',time−Ts,time); IS_RMS_NEW(5) = getSignalRMS('IS5',time−Ts,time); IS_RMS_NEW(6) = getSignalRMS('IS6',time−Ts,time); IS_RMS_NEW(7) = getSignalRMS('IS7',time−Ts,time); error = abs((IS_RMS − IS_RMS_NEW))./IS_RMS_NEW; error_norm = norm(error); fprintf('Error:%f\n',error _norm); if (error_norm <= allowable_error) converged = true; else converged = false; end

if (iteration >= max_iterations) converged = true; end end %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−%

%−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% %−−−−−−−−−−−POST−PROCESSING(GATHERING DATA, PLOTTING): −−−−−−−−−% disp('Optimization finished, now postprocessing...');

%total MOSFET area(mm^2) A_tot = A1+A2+A3+A4+A5+A6+A7; %Createa pie chart showing distribution of MOSFET area to each MOSFET pie_title = strcat({'Total area='}, num2str(A_tot),' mm^2'); pie_title = pie_title{1}; fig1 = figure('Name','Switch Area'); pie_labels = {strcat({'A1='}, num2str(A1),' mm^{2}'),strcat({'A2='}, num2str( A2),' mm^{2}'),strcat({'A3='}, num2str(A3),' mm^{2}'),strcat({'A4='}, num2str(A4),' mm^{2}'),strcat({'A5='}, num2str(A5),' mm^{2}'),strcat({'A6= '},num2str(A6),' mm^{2}'),strcat({'A7='}, num2str(A7),' mm^{2}')}; pie_labels = {pie_labels{1}{1},pie_labels{2}{1},pie_labels{3}{1},pie_labels {4}{1},pie_labels{5}{1},pie_labels{6}{1},pie_labels{7}{1}}; pie([A1 A2 A3 A4 A5 A6 A7],pie_labels); title({'MOSFET Area Breakdown',pie_title}); 124

%On−resistance per MOSFET %The Rdson values INCLUDE both the scaling factors and constant deltas! fig2 = figure('Name','Switch On−Resistance'); bar([1 2 3 4 5 6 7],Rdson.*1e3); title({'On−Resistance for each MOSFET','(includes the scaling factor and deltas due to routing)'}); xlabel('Switch#'); ylabel('R_{DS,ON}(m\Omega)');

%Calculate loss by type for each switch − requires to take same values %again from the simulation(with the new Rdson) IS_ON(1) = abs(getSignalAvg('IS1_ON',time−Ts,time)); IS_ON(2) = abs(getSignalAvg('IS2_ON',time−Ts,time)); IS_ON(3) = abs(getSignalAvg('IS3_ON',time−Ts,time)); IS_ON(4) = abs(getSignalAvg('IS4_ON',time−Ts,time)); IS_ON(5) = abs(getSignalAvg('IS5_ON',time−Ts,time)); IS_ON(6) = abs(getSignalAvg('IS6_ON',time−Ts,time)); IS_ON(7) = abs(getSignalAvg('IS7_ON',time−Ts,time)); IS_OFF(1) = abs(getSignalAvg('IS1_OFF',time−Ts,time)); IS_OFF(2) = abs(getSignalAvg('IS2_OFF',time−Ts,time)); IS_OFF(3) = abs(getSignalAvg('IS3_OFF',time−Ts,time)); IS_OFF(4) = abs(getSignalAvg('IS4_OFF',time−Ts,time)); IS_OFF(5) = abs(getSignalAvg('IS5_OFF',time−Ts,time)); IS_OFF(6) = abs(getSignalAvg('IS6_OFF',time−Ts,time)); IS_OFF(7) = abs(getSignalAvg('IS7_OFF',time−Ts,time)); %the trailing zeros are to accommodate the graphing of the inductor losses RMS_LOSS = [(IS_RMS_NEW(1)^2)*Rdson(1) (IS_RMS_NEW(2)^2)*Rdson(2) (IS_RMS_NEW(3) ^2)*Rdson(3) (IS_RMS_NEW(4)^2)*Rdson(4) (IS_RMS_NEW(5)^2)*Rdson(5) ( IS_RMS_NEW(6)^2)*Rdson(6) (IS_RMS_NEW(7)^2)*Rdson(7)]; SW_LOSS = [0.5*VS(1)*ST(1)*fsw*(IS_ON(1)*ton + IS_OFF(1)*toff) 0.5*VS(2)*ST(2)* fsw*(IS_ON(2)*ton + IS_OFF(2)*toff) 0.5*VS(3)*ST(3)*fsw*(IS_ON(3)*ton + IS_OFF(3)*toff) 0.5*VS(4)*ST(4)*fsw*(IS_ON(4)*ton + IS_OFF(4)*toff) 0.5*VS(5) *ST(5)*fsw*(IS_ON(5)*ton + IS_OFF(5)*toff) 0.5*VS(6)*ST(6)*fsw*(IS_ON(6)*ton + IS_OFF(6)*toff) 0.5*VS(7)*ST(7)*fsw*(IS_ON(7)*ton + IS_OFF(7)*toff)]; COSS_LOSS = [0.5*Coss_mm2*A1*(VS(1)^2)*ST(1)*fsw 0.5*Coss_mm2*A2*(VS(2)^2)*ST(2) *fsw 0.5*Coss_mm2*A3*(VS(3)^2)*ST(3)*fsw 0.5*Coss_mm2*A4*(VS(4)^2)*ST(4)*fsw 0.5*Coss_mm2*A5*(VS(5)^2)*ST(5)*fsw 0.5*Coss_mm2*A6*(VS(6)^2)*ST(6)*fsw 0.5* Coss_mm2*A7*(VS(7)^2)*ST(7)*fsw]; GATE_LOSS = [Cin_mm2*A1*(Vg^2)*ST(1)*fsw Cin_mm2*A2*(Vg^2)*ST(2)*fsw Cin_mm2*A3 *(Vg^2)*ST(3)*fsw Cin_mm2*A4*(Vg^2)*ST(4)*fsw Cin_mm2*A5*(Vg^2)*ST(5)*fsw Cin_mm2*A6*(Vg^2)*ST(6)*fsw Cin_mm2*A7*(Vg^2)*ST(7)*fsw]; IL(1) = getSignalRMS('IL1',time−Ts,time); IL(2) = getSignalRMS('IL2',time−Ts,time); IND_LOSS = [(IL(1)^2)*RL (IL(2)^2)*RL]; S1_LOSS = [RMS_LOSS(1) SW_LOSS(1) COSS_LOSS(1) GATE_LOSS(1) 0 0]; S2_LOSS = [RMS_LOSS(2) SW_LOSS(2) COSS_LOSS(2) GATE_LOSS(2) 0 0]; S3_LOSS = [RMS_LOSS(3) SW_LOSS(3) COSS_LOSS(3) GATE_LOSS(3) 0 0]; S4_LOSS = [RMS_LOSS(4) SW_LOSS(4) COSS_LOSS(4) GATE_LOSS(4) 0 0]; 125

S5_LOSS = [RMS_LOSS(5) SW_LOSS(5) COSS_LOSS(5) GATE_LOSS(5) 0 0]; S6_LOSS = [RMS_LOSS(6) SW_LOSS(6) COSS_LOSS(6) GATE_LOSS(6) 0 0]; S7_LOSS = [RMS_LOSS(7) SW_LOSS(7) COSS_LOSS(7) GATE_LOSS(7) 0 0]; L_LOSS = [0 0 0 0 IND_LOSS(1) IND_LOSS(2)]; lossmatrix = [S1_LOSS; S2_LOSS; S3_LOSS; S4_LOSS; S5_LOSS; S6_LOSS; S7_LOSS; L_LOSS]; barlabels = {'S1','S2','S3','S4','S5','S6','S7','L'}; %Plot loss by type as stacked bar graph − for optimized point fig3 = figure('Name','Converter Loss Breakdown For Optimization Point'); bar(lossmatrix,'stacked'); set(gca,'XTick', 1:8,'XTickLabel', barlabels); xlabel('Component'); ylabel('Losses(W)'); title({'Loss Breakdown By Component',strcat('at the optimized−for operating point(', num2str(Iout_actual),'A)')}); legend('Conduction','Turn−on/off','Coss','Gate drive','L.1','L.2'); legend('show'); %total loss at optimization point tot_loss = sum(RMS_LOSS) + sum(SW_LOSS) + sum(COSS_LOSS) + sum(GATE_LOSS) + sum( IND_LOSS); %efficiency at optimization point efficiency = (Vout*Iout_actual) / (Vout*Iout_actual + tot_loss);

%Recalculate load curve disp('Resimulating the load curve...'); for i=1:5 setParameter('ROUT','const',Rout_part(i)); %set actual load resistance setParameter('R.out','R',Rout_part(i)); %set actual load resistance(circuit component) initSteadyStateDetection(steadyStateVars,fsw,dt,tend); results = simulateToSteadyState(false,0.995,0.001); time = results(2); Ts = results(3); %Now extract all necessary voltages and currents at the part load %RMS CURRENTS% IS_RMS_PART = zeros(7,1); IS_RMS_PART(1) = getSignalRMS('IS1',time−Ts,time); IS_RMS_PART(2) = getSignalRMS('IS2',time−Ts,time); IS_RMS_PART(3) = getSignalRMS('IS3',time−Ts,time); IS_RMS_PART(4) = getSignalRMS('IS4',time−Ts,time); IS_RMS_PART(5) = getSignalRMS('IS5',time−Ts,time); IS_RMS_PART(6) = getSignalRMS('IS6',time−Ts,time); IS_RMS_PART(7) = getSignalRMS('IS7',time−Ts,time); loadcurve{i+1,2} = IS_RMS_PART; %ON/OFF CURRENTS% IS_ON_PART = zeros(7,1); IS_ON_PART(1) = abs(getSignalAvg('IS1_ON',time−Ts,time)); IS_ON_PART(2) = abs(getSignalAvg('IS2_ON',time−Ts,time)); 126

IS_ON_PART(3) = abs(getSignalAvg('IS3_ON',time−Ts,time)); IS_ON_PART(4) = abs(getSignalAvg('IS4_ON',time−Ts,time)); IS_ON_PART(5) = abs(getSignalAvg('IS5_ON',time−Ts,time)); IS_ON_PART(6) = abs(getSignalAvg('IS6_ON',time−Ts,time)); IS_ON_PART(7) = abs(getSignalAvg('IS7_ON',time−Ts,time)); loadcurve{i+1,3} = IS_ON_PART; IS_OFF_PART = zeros(7,1); IS_OFF_PART(1) = abs(getSignalAvg('IS1_OFF',time−Ts,time)); IS_OFF_PART(2) = abs(getSignalAvg('IS2_OFF',time−Ts,time)); IS_OFF_PART(3) = abs(getSignalAvg('IS3_OFF',time−Ts,time)); IS_OFF_PART(4) = abs(getSignalAvg('IS4_OFF',time−Ts,time)); IS_OFF_PART(5) = abs(getSignalAvg('IS5_OFF',time−Ts,time)); IS_OFF_PART(6) = abs(getSignalAvg('IS6_OFF',time−Ts,time)); IS_OFF_PART(7) = abs(getSignalAvg('IS7_OFF',time−Ts,time)); loadcurve{i+1,4} = IS_OFF_PART; %BLOCKING VOLTAGES% VS_PART = zeros(7,1); VS_PART(1) = abs(getSignalMax('VS1',time−Ts,time)); VS_PART(2) = abs(getSignalMax('VS2',time−Ts,time)); VS_PART(3) = abs(getSignalMax('VS3',time−Ts,time)); VS_PART(4) = abs(getSignalMax('VS4',time−Ts,time)); VS_PART(5) = abs(getSignalMax('VS5',time−Ts,time)); VS_PART(6) = abs(getSignalMax('VS6',time−Ts,time)); VS_PART(7) = abs(getSignalMax('VS7',time−Ts,time)); loadcurve{i+1,5} = VS_PART; %NUMBER OF TRANSITIONS% ST_PART = zeros(7,1); ST_PART(1) = round(abs(getSignalAvg('S1_T',time−Ts,time))); ST_PART(2) = round(abs(getSignalAvg('S2_T',time−Ts,time))); ST_PART(3) = round(abs(getSignalAvg('S3_T',time−Ts,time))); ST_PART(4) = round(abs(getSignalAvg('S4_T',time−Ts,time))); ST_PART(5) = round(abs(getSignalAvg('S5_T',time−Ts,time))); ST_PART(6) = round(abs(getSignalAvg('S6_T',time−Ts,time))); ST_PART(7) = round(abs(getSignalAvg('S7_T',time−Ts,time))); loadcurve{i+1,6} = ST_PART; %INDUCTOR RMS CURRENT% IL_PART = zeros(2,1); IL_PART(1) = getSignalRMS('IL1',time−Ts,time); IL_PART(2) = getSignalRMS('IL2',time−Ts,time); loadcurve{i+1,7} = IL_PART; RMS_LOSS_PART = [(IS_RMS_PART(1)^2)*Rdson(1) (IS_RMS_PART(2)^2)*Rdson(2) ( IS_RMS_PART(3)^2)*Rdson(3) (IS_RMS_PART(4)^2)*Rdson(4) (IS_RMS_PART(5)^2) *Rdson(5) (IS_RMS_PART(6)^2)*Rdson(6) (IS_RMS_PART(7)^2)*Rdson(7)]; loadcurve{i+1,8} = RMS_LOSS_PART; SW_LOSS_PART = [0.5*VS_PART(1)*ST_PART(1)*fsw*(IS_ON_PART(1)*ton + IS_OFF_PART(1)*toff) 0.5*VS_PART(2)*ST_PART(2)*fsw*(IS_ON_PART(2)*ton + IS_OFF_PART(2)*toff) 0.5*VS_PART(3)*ST_PART(3)*fsw*(IS_ON_PART(3)*ton + IS_OFF_PART(3)*toff) 0.5*VS_PART(4)*ST_PART(4)*fsw*(IS_ON_PART(4)*ton + 127

IS_OFF_PART(4)*toff) 0.5*VS_PART(5)*ST_PART(5)*fsw*(IS_ON_PART(5)*ton + IS_OFF_PART(5)*toff) 0.5*VS_PART(6)*ST_PART(6)*fsw*(IS_ON_PART(6)*ton + IS_OFF_PART(6)*toff) 0.5*VS_PART(7)*ST_PART(7)*fsw*(IS_ON_PART(7)*ton + IS_OFF_PART(7)*toff)]; loadcurve{i+1,9} = SW_LOSS_PART; COSS_LOSS_PART = [0.5*Coss_mm2*A1*(VS_PART(1)^2)*ST_PART(1)*fsw 0.5*Coss_mm2 *A2*(VS_PART(2)^2)*ST_PART(2)*fsw 0.5*Coss_mm2*A3*(VS_PART(3)^2)*ST_PART (3)*fsw 0.5*Coss_mm2*A4*(VS_PART(4)^2)*ST_PART(4)*fsw 0.5*Coss_mm2*A5*( VS_PART(5)^2)*ST_PART(5)*fsw 0.5*Coss_mm2*A6*(VS_PART(6)^2)*ST_PART(6)* fsw 0.5*Coss_mm2*A7*(VS_PART(7)^2)*ST_PART(7)*fsw]; loadcurve{i+1,10} = COSS_LOSS_PART; GATE_LOSS_PART = [Cin_mm2*A1*(Vg^2)*ST_PART(1)*fsw Cin_mm2*A2*(Vg^2)*ST_PART (2)*fsw Cin_mm2*A3*(Vg^2)*ST_PART(3)*fsw Cin_mm2*A4*(Vg^2)*ST_PART(4)*fsw Cin_mm2*A5*(Vg^2)*ST_PART(5)*fsw Cin_mm2*A6*(Vg^2)*ST_PART(6)*fsw Cin_mm2*A7*(Vg^2)*ST_PART(7)*fsw]; loadcurve{i+1,11} = GATE_LOSS_PART; TOT_MOS_LOSS_PART = RMS_LOSS_PART + SW_LOSS_PART + COSS_LOSS_PART + GATE_LOSS_PART; loadcurve{i+1,12} = TOT_MOS_LOSS_PART; IND_LOSS_PART = [(IL_PART(1)^2)*RL (IL_PART(2)^2)*RL]; loadcurve{i+1,13} = IND_LOSS_PART; %total losses tot_loss_part = sum(RMS_LOSS_PART) + sum(SW_LOSS_PART) + sum(COSS_LOSS_PART) + sum(GATE_LOSS_PART) + sum(IND_LOSS_PART); loadcurve{i+1,15} = tot_loss_part; %efficiency loadcurve{i+1,16} = Pout_part(i) / (Pout_part(i) + tot_loss_part); %now plot for this load level the loss breakdown S1_LOSS_PART = [RMS_LOSS_PART(1) SW_LOSS_PART(1) COSS_LOSS_PART(1) GATE_LOSS_PART(1) 0 0]; S2_LOSS_PART = [RMS_LOSS_PART(2) SW_LOSS_PART(2) COSS_LOSS_PART(2) GATE_LOSS_PART(2) 0 0]; S3_LOSS_PART = [RMS_LOSS_PART(3) SW_LOSS_PART(3) COSS_LOSS_PART(3) GATE_LOSS_PART(3) 0 0]; S4_LOSS_PART = [RMS_LOSS_PART(4) SW_LOSS_PART(4) COSS_LOSS_PART(4) GATE_LOSS_PART(4) 0 0]; S5_LOSS_PART = [RMS_LOSS_PART(5) SW_LOSS_PART(5) COSS_LOSS_PART(5) GATE_LOSS_PART(5) 0 0]; S6_LOSS_PART = [RMS_LOSS_PART(6) SW_LOSS_PART(6) COSS_LOSS_PART(6) GATE_LOSS_PART(6) 0 0]; S7_LOSS_PART = [RMS_LOSS_PART(7) SW_LOSS_PART(7) COSS_LOSS_PART(7) GATE_LOSS_PART(7) 0 0]; L_LOSS_PART = [0 0 0 0 IND_LOSS_PART(1) IND_LOSS_PART(2)]; lossmatrix_part = [S1_LOSS_PART; S2_LOSS_PART; S3_LOSS_PART; S4_LOSS_PART; S5_LOSS_PART; S6_LOSS_PART; S7_LOSS_PART; L_LOSS_PART]; figure('Name',strcat(num2str(loadcurve{i+1,1}*100),'% Load Converter Loss Breakdown')); bar(lossmatrix_part,'stacked'); 128

set(gca,'XTick', 1:8,'XTickLabel', barlabels); xlabel('Component'); ylabel('Losses(W)'); title({'Loss Breakdown By Component',strcat('at part load(', num2str( loadcurve{i+1,1}*100),'%,',num2str(loadcurve{i+1,14}),'A)')}); legend('Conduction','Turn−on/off','Coss','Gate drive','L.1','L.2'); legend('show'); end

%Plot efficiency curves fig9 = figure('Name','Efficiency Curves'); switch mode case 1 des_mode ='desired mode(Nishijima)'; case 2 des_mode ='desired mode(Maynard)'; case 3 des_mode ='desired mode (2ph. interleaved)'; otherwise des_mode ='desired mode(AUTOMATIC)'; end Iout = [Iout_20 Iout_40 Iout_60 Iout_80 Iout_100]; EffRef = [Eff_20 Eff_40 Eff_60 Eff_80 Eff_100]; plot(Iout,EffRef.*100,'−*'); hold; plot([Iout_actual],[efficiency*100],'x'); Eff_over_Range = [loadcurve{2,16} loadcurve{3,16} loadcurve{4,16} loadcurve {5,16} loadcurve{6,16}]; plot(Iout,Eff_over_Range.*100,'−o');

%Now simulate this converter in the other operating modes disp('Resimulating in other converter modes...'); other_modes = [0 1 2 3]; others = {'−−+','−−s','−−d','−−v'}; oth = {'','',''}; j = 1; for k=1:length(other_modes) other_mode = other_modes(k); if (mode ~= other_mode) switch other_mode case 1 oth_mode ='other mode(Nishijima)'; case 2 oth_mode ='other mode(Maynard)'; case 3 oth_mode ='other mode (2ph. interleaved)'; otherwise oth_mode ='other mode(AUTOMATIC)'; 129

end oth{j} = oth_mode; setParameter('MODE_PREF','const',other_mode); %set preferred mode of operation %simulate load curve in the other mode eff_part = ones(5,1); for i=1:5 setParameter('ROUT','const',Rout_part(i)); %set actual load resistance setParameter('R.out','R',Rout_part(i)); %set actual load resistance (circuit component) initSteadyStateDetection(steadyStateVars,fsw,dt,tend); results = simulateToSteadyState(false,0.995,0.001); time = results(2); Ts = results(3); %Now extract all necessary voltages and currents at the part load %RMS CURRENTS% IS_RMS_PART = zeros(7,1); IS_RMS_PART(1) = getSignalRMS('IS1',time−Ts,time); IS_RMS_PART(2) = getSignalRMS('IS2',time−Ts,time); IS_RMS_PART(3) = getSignalRMS('IS3',time−Ts,time); IS_RMS_PART(4) = getSignalRMS('IS4',time−Ts,time); IS_RMS_PART(5) = getSignalRMS('IS5',time−Ts,time); IS_RMS_PART(6) = getSignalRMS('IS6',time−Ts,time); IS_RMS_PART(7) = getSignalRMS('IS7',time−Ts,time); %ON/OFF CURRENTS% IS_ON_PART = zeros(7,1); IS_ON_PART(1) = abs(getSignalAvg('IS1_ON',time−Ts,time)); IS_ON_PART(2) = abs(getSignalAvg('IS2_ON',time−Ts,time)); IS_ON_PART(3) = abs(getSignalAvg('IS3_ON',time−Ts,time)); IS_ON_PART(4) = abs(getSignalAvg('IS4_ON',time−Ts,time)); IS_ON_PART(5) = abs(getSignalAvg('IS5_ON',time−Ts,time)); IS_ON_PART(6) = abs(getSignalAvg('IS6_ON',time−Ts,time)); IS_ON_PART(7) = abs(getSignalAvg('IS7_ON',time−Ts,time)); IS_OFF_PART = zeros(7,1); IS_OFF_PART(1) = abs(getSignalAvg('IS1_OFF',time−Ts,time)); IS_OFF_PART(2) = abs(getSignalAvg('IS2_OFF',time−Ts,time)); IS_OFF_PART(3) = abs(getSignalAvg('IS3_OFF',time−Ts,time)); IS_OFF_PART(4) = abs(getSignalAvg('IS4_OFF',time−Ts,time)); IS_OFF_PART(5) = abs(getSignalAvg('IS5_OFF',time−Ts,time)); IS_OFF_PART(6) = abs(getSignalAvg('IS6_OFF',time−Ts,time)); IS_OFF_PART(7) = abs(getSignalAvg('IS7_OFF',time−Ts,time)); %BLOCKING VOLTAGES% VS_PART = zeros(7,1); VS_PART(1) = abs(getSignalMax('VS1',time−Ts,time)); VS_PART(2) = abs(getSignalMax('VS2',time−Ts,time)); VS_PART(3) = abs(getSignalMax('VS3',time−Ts,time)); VS_PART(4) = abs(getSignalMax('VS4',time−Ts,time)); 130

VS_PART(5) = abs(getSignalMax('VS5',time−Ts,time)); VS_PART(6) = abs(getSignalMax('VS6',time−Ts,time)); VS_PART(7) = abs(getSignalMax('VS7',time−Ts,time)); %NUMBER OF TRANSITIONS% ST_PART = zeros(7,1); ST_PART(1) = round(abs(getSignalAvg('S1_T',time−Ts,time))); ST_PART(2) = round(abs(getSignalAvg('S2_T',time−Ts,time))); ST_PART(3) = round(abs(getSignalAvg('S3_T',time−Ts,time))); ST_PART(4) = round(abs(getSignalAvg('S4_T',time−Ts,time))); ST_PART(5) = round(abs(getSignalAvg('S5_T',time−Ts,time))); ST_PART(6) = round(abs(getSignalAvg('S6_T',time−Ts,time))); ST_PART(7) = round(abs(getSignalAvg('S7_T',time−Ts,time))); %INDUCTOR RMS CURRENT% IL_PART = zeros(2,1); IL_PART(1) = getSignalRMS('IL1',time−Ts,time); IL_PART(2) = getSignalRMS('IL2',time−Ts,time); RMS_LOSS_PART = [(IS_RMS_PART(1)^2)*Rdson(1) (IS_RMS_PART(2)^2)* Rdson(2) (IS_RMS_PART(3)^2)*Rdson(3) (IS_RMS_PART(4)^2)*Rdson(4) (IS_RMS_PART(5)^2)*Rdson(5) (IS_RMS_PART(6)^2)*Rdson(6) ( IS_RMS_PART(7)^2)*Rdson(7)]; SW_LOSS_PART = [0.5*VS_PART(1)*ST_PART(1)*fsw*(IS_ON_PART(1)*ton + IS_OFF_PART(1)*toff) 0.5*VS_PART(2)*ST_PART(2)*fsw*(IS_ON_PART(2) *ton + IS_OFF_PART(2)*toff) 0.5*VS_PART(3)*ST_PART(3)*fsw*( IS_ON_PART(3)*ton + IS_OFF_PART(3)*toff) 0.5*VS_PART(4)*ST_PART (4)*fsw*(IS_ON_PART(4)*ton + IS_OFF_PART(4)*toff) 0.5*VS_PART(5)* ST_PART(5)*fsw*(IS_ON_PART(5)*ton + IS_OFF_PART(5)*toff) 0.5* VS_PART(6)*ST_PART(6)*fsw*(IS_ON_PART(6)*ton + IS_OFF_PART(6)* toff) 0.5*VS_PART(7)*ST_PART(7)*fsw*(IS_ON_PART(7)*ton + IS_OFF_PART(7)*toff)]; COSS_LOSS_PART = [0.5*Coss_mm2*A1*(VS_PART(1)^2)*ST_PART(1)*fsw 0.5* Coss_mm2*A2*(VS_PART(2)^2)*ST_PART(2)*fsw 0.5*Coss_mm2*A3*( VS_PART(3)^2)*ST_PART(3)*fsw 0.5*Coss_mm2*A4*(VS_PART(4)^2)* ST_PART(4)*fsw 0.5*Coss_mm2*A5*(VS_PART(5)^2)*ST_PART(5)*fsw 0.5* Coss_mm2*A6*(VS_PART(6)^2)*ST_PART(6)*fsw 0.5*Coss_mm2*A7*( VS_PART(7)^2)*ST_PART(7)*fsw]; GATE_LOSS_PART = [Cin_mm2*A1*(Vg^2)*ST_PART(1)*fsw Cin_mm2*A2*(Vg^2) *ST_PART(2)*fsw Cin_mm2*A3*(Vg^2)*ST_PART(3)*fsw Cin_mm2*A4*(Vg ^2)*ST_PART(4)*fsw Cin_mm2*A5*(Vg^2)*ST_PART(5)*fsw Cin_mm2*A6*( Vg^2)*ST_PART(6)*fsw Cin_mm2*A7*(Vg^2)*ST_PART(7)*fsw]; TOT_MOS_LOSS_PART = RMS_LOSS_PART + SW_LOSS_PART + COSS_LOSS_PART + GATE_LOSS_PART; IND_LOSS_PART = [(IL_PART(1)^2)*RL (IL_PART(2)^2)*RL]; %total losses tot_loss_part = sum(RMS_LOSS_PART) + sum(SW_LOSS_PART) + sum( COSS_LOSS_PART) + sum(GATE_LOSS_PART) + sum(IND_LOSS_PART); %efficiency eff_part(i) = Pout_part(i) / (Pout_part(i) + tot_loss_part); end 131

plot(Iout,eff_part.*100,others{k}); j = j+1; end end legend({'reference floor','optimization point',des_mode,oth{1},oth{2},oth{3}}); title('Converter Efficiency over Load Range'); xlabel('Load Current(A)'); ylabel('Efficiency (%)');

%disconnect from GeckoCIRCUITS disconnectFromGecko();

%Createa final table for output containg the MOSFET parameters switchnames = {'S1','S2','S3','S4','S5','S6','S7'}; Rdson_pure = zeros(7,1); Rdson_pure(1) = Rdson_mm2/A1; Rdson_pure(2) = Rdson_mm2/A2; Rdson_pure(3) = Rdson_mm2/A3; Rdson_pure(4) = Rdson_mm2/A4; Rdson_pure(5) = Rdson_mm2/A5; Rdson_pure(6) = Rdson_mm2/A6; Rdson_pure(7) = Rdson_mm2/A7; Coss = zeros(7,1); Coss(1) = Coss_mm2*A1; Coss(2) = Coss_mm2*A2; Coss(3) = Coss_mm2*A3; Coss(4) = Coss_mm2*A4; Coss(5) = Coss_mm2*A5; Coss(6) = Coss_mm2*A6; Coss(7) = Coss_mm2*A7; Cin = zeros(7,1); Cin(1) = Cin_mm2*A1; Cin(2) = Cin_mm2*A2; Cin(3) = Cin_mm2*A3; Cin(4) = Cin_mm2*A4; Cin(5) = Cin_mm2*A5; Cin(6) = Cin_mm2*A6; Cin(7) = Cin_mm2*A7; varnames = {'Area_mm2','RDSon_norouting_mOhms','RDSon_wrouting_mOhms','Coss_pF', 'Cin_pF'}; MOSFET_TABLE = table([A1; A2; A3; A4; A5; A6; A7],Rdson_pure.*1e3,Rdson.*1e3, Coss.*1e12,Cin.*1e12,'RowNames',switchnames,'VariableNames',varnames) display('Done.'); %−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−% execution_time = toc; execution_time 132

GeckoCIRCUITS model of the 7SFC converter used in the hybrid optimization procedure. BIBLIOGRAPHY

[1] R. W. Erickson and D. Maksimovi´c, Fundamentals of Power Electronics, 2nd ed. Kluwer

Academic Publishers, 2001.

[2] M. H. Rashid, Ed., Power Electronics Handbook, 3rd ed. Butterworth-Heinemann, 2010.

[3] M. Yamada, N. B. Tran, T. Miyazaki, Y. Yoshihara, and R. Fujimoto, “All-Digital Single-

Inductor Multiple-Output DC-DC Converter with over 65.3% Efﬁciency in 1 uW to 50

mW Load Range and 86.3% Peak Efﬁciency,” in Proc. 2016 IEEE Asian Solid-State Circuits

Conference (A-SSCC 2016), Toyama, Japan, November 2016.

[4] M. Tarulli, “New Generation of Programmable Neuroprostheses – Switched Mode Power

Supply Functional Electrical Stimulator,” Master’s thesis, University of Toronto, 2009,

ISBN 9780494765562.

[5] B. K. Bose, “Energy, Environment, and Advances in Power Electronics,” IEEE Transactions

on Power Electronics, vol. 15, no. 4, pp. 688–701, July 2000.

[6] G. Andersson, “Power Electronics Solutions for Sustainability,” in Proc. 2004 IEEE Power

Engineering Society General Meeting, Denver, CO, USA, June 2004.

[7] S. Roberts, DC/DC Book of Knowledge, 2nd ed. RECOM Engineering GmbH, 2015.

[8] A. Radi´c, “Practical Volume-Reduction Strategies for Low-Power High-Frequency

Switch Mode Power Supplies,” Ph.D. dissertation, University of Toronto, 2014, ISBN

9781321413045.

133 134 BIBLIOGRAPHY

[9] M. Djuri´c, “iPad Wi-Fi Teardown,” March 2010. [Online]. Available: https:

//www.iﬁxit.com/Teardown/iPad+Wi-Fi+Teardown/2183

[10] iFixit.com, “iPad Air LTE Teardown,” November 2013. [Online]. Available: https:

//www.iﬁxit.com/Teardown/iPad+Air+Teardown/18907

[11] “Google & IEEE Little Box Challenge,” 2016. [Online]. Available: https://

littleboxchallenge.com

[12] “Little Box Challenge by CET+T Power,” 2016. [Online]. Available: http:

//littleboxchallengecetpower.com/#thanks

[13] C. Gammeter, F. Krismer, and J. W. Kolar, “Comprehensive Conceptualization, Design,

and Experimental Veriﬁcation of a Weight-Optimized All-SiC 2 kV/700 V DAB for an Air-

borne Wind Turbine,” IEEE Journal of Emerging and Selected Topics in Power Electronics,

vol. 4, no. 2, pp. 638–656, June 2016.

[14] H. Wang, K. Ma, and F. Blaabjerg, “Design for Reliability of Power Electronic Systems,”

in Proc. 38th Annual Conference of the IEEE Industrial Society (IECON 2012), Montreal,

QC, Canada, October 2012.

[15] Y. Song and B. Wang, “Survey on Reliability of Power Electronic Systems,” IEEE Transac-

tions on Power Electronics, vol. 28, no. 1, pp. 591–604, January 2013.

[16] H. S. Chung, H. Wang, F. Blaabjerg, and M. Pecht, Reliability of Power Electronic Converter

Systems. The Institution of Engineering and Technology, December 2015.

[17] J. Biela, D. Hassler, J. Miniböck, and J. W. Kolar, “Optimal Design of a 5kW/dm3 / 98.5%

Efﬁcient TCM Resonant Transition Single-Phase PFC Rectiﬁer,” in Proc. of the IEEE/IEEJ

International Power Electronics Conference (ECCE Asia 2010), Sapporo, Japan, June 2010,

pp. 1709–1716.

[18] S. Boyd and L. Vandenberghe, Convex Optimization. Cambridge University Press, March

2004. BIBLIOGRAPHY 135

[19] S. Boyd and S.-J. Kim, “Geometric Programming for Circuit Optimization,” in Proc. of

International Symposium of Physical Design (ISPD), San Francisco, CA, USA, April 2005,

pp. 44–45.

[20] J. Kim, L. Vanderberghe, and C. K. Yang, “Convex Piecewise-Linear Modeling Method for

Circuit Optimization Via Geometric Programming,” IEEE Transactions on Computer-Aided

Design of Integrated Circuits and Systems, vol. 29, pp. 1823–1827, 2010.

[21] N. Murgovski, L. Johannesson, J. Sjoberg, and B. Egardt, “Component sizing of a plug-in

hybrid electric powertrain via convex optimization,” Elsevier Mechatronics, vol. 22, pp.

106–120, January 2012.

[22] J. Kim and M. Lee, “A Semiblind Digital-Domain Calibration of Pipelined A/D Convert-

ers via Convex Optimization,” IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, vol. 23, pp. 1375–1379, July 2015.

[23] A. T. Bryant, D. M. Jaeggi, G. T. Parks, and P. R. Palmer, “The inﬂuence of operating

conditions on multi-objective optimization of power electronic devices and circuits,” in

Proc. of the 2005 Industrial Applications Conference, 40th Annual IAS Meeting, vol. 2,

Kowloon, Hong Kong, China, October 2005, pp. 1449–1456.

[24] C.-K. Chew and S. R. R. Kondapalli, “Modeling, Analysis, Simulation and Design Opti-

mization (Genetic Algorithm) of dc-dc Converter for Uninterruptible Power Supply Ap-

plications,” in Proc. 2005 International Conference on Power Electronics and Drives Systems

(PEDS 2005), vol. 2, Kuala Lumpur, Malaysia, November 2005, pp. 1530–1535.

[25] T. Takayama and D. Maksimovi´c, “A power stage optimization method for monolithic

DC-DC converters,” in Proc. 37th IEEE Power Electronics Specialists Conference, 2006

(PESC ’06), Jeju, South Korea, June 2006.

[26] D. V. Malyna, J. L. Duarte, M. A. M. Hendrix, and F. B. M. van Horck, “Optimization

of combined thermal and electrical behavior of power converters using multi-objective

genetic algorithms,” in Proc. 2007 European Conference on Power Electronics and Applica-

tions (EPE ’07), Aalborg, Denmark, September 2007. 136 BIBLIOGRAPHY

[27] C. Larouci, M. Boukhnifer, and A. Chaibet, “Design of Power Converters by Optimization

Under Multiphysic Constraints: Application to a Two-Time-Scale AC/DC–DC Converter,”

IEEE Transactions on Industrial Electronics, vol. 57, no. 11, pp. 3746–3753, November

2010.

[28] T. Soeiro, J. Biela, J. Mühlethaler, and J. W. Kolar, “Optimal Design of Resonant DC-DC

Converter for Electrostatic Precipitators,” in Proc. of the IEEE/IEEJ International Power

Electornics Conference (ECCE Asia 2010), Sapporo, Japan, June 2010, pp. 2294–2301.

[29] U. Badstübner, J. Biela, and J. W. Kolar, “Design of an 99%-Efﬁcient, 5kW, Phase-Shift

PWM DC-DC Converter for Telecom Applications,” in Proc. 25th Applied Power Electronics

Conference and Exposition (APEC 2010), Palm Springs, CA, USA, February 2010.

[30] U. Badstübner, A. Stupar, and J. W. Kolar, “Sensitivity of Telecom Dc-Dc Converter Op-

timization to the Level of Detail of the System Model,” in Proc. 26th Applied Power Elec-

tronics Conference and Exposition (APEC 2011), Forth Worth, TX, USA, March 2011, pp.

585–592.

[31] A. Stupar, T. Friedli, J. Miniböck, and J. W. Kolar, “Towards a 99% Efﬁcient Three-Phase

Buck-Type PFC Rectiﬁer for 400-V DC Distribution Systems,” IEEE Transactions on Power

Electronics, vol. 27, no. 4, pp. 1732–1744, April 2012.

[32] L. Marco, A. Poveda, F. Guinjoan, D. Maksimovi´c, and E. Alarcón, “A design-oriented op-

timization framework for envelope trackers: Application to a sliding-mode control buck

converter for EDGE,” in Proc. 15th International Power Electronics and Motion Conference

(EPE-PEMC 2012), Novi Sad, Serbia, September 2012, pp. LS8d.2–1 – LS8d.2–6.

[33] S. H. Kang, D. Maksimovi´c, and I. Cohen, “Efﬁciency Optimization in Digitally Controlled

Flyback DC-DC Converters Over Wide Ranges of Operating Conditions,” IEEE Transac-

tions on Power Electronics, vol. 27, no. 8, pp. 3734–3748, August 2012.

[34] H. Visairo, M. A. Medina, and J. M. Ramirez, “Use of Evolutionary Algorithms for Design

Optimization of Power Converters,” in Proc. 22nd International Conference on Electrical BIBLIOGRAPHY 137

Communications and Computers (CONIELECOMP 2012), Cholula, Puebla, Mexico, Febru-

ary 2012, pp. 268–272.

[35] U. Badstübner, J. Miniböck, and J. W. Kolar, “Experimental Veriﬁcation of the

Efﬁciency/Power-Density (η-ρ) Pareto Front of Single-Phase Double-Boost and TCM

PFC Rectiﬁer Systems,” in Proc. 28th Applied Power Electronics Conference and Exposition

(APEC 2013), Long Beach, CA, USA, March 2013, pp. 1050–1057.

[36] C. Marxgut, J. Mühlethaler, F. Krismer, and J. W. Kolar, “Multiobjective Optimization of

Ultraﬂat Magnetic Components With PCB-Integrated Core,” IEEE Transactions on Power

Electronics, vol. 28, no. 7, pp. 3591–3602, July 2013.

[37] T. Soeiro, J. Mühlethaler, J. Linnér, P. Ranstad, and J. W. Kolar, “Automated Design of

a High-Power High-Frequency LCC Resonant Converter for Electrostatic Precipitators,”

IEEE Transactions on Industrial Electronics, vol. 60, no. 11, pp. 4805–4819, November

2013.

[38] T. Diekhans and R. W. De Doncker, “A Pareto-Based Comparison of Power Electronic

Topologies for Inductive Power Transfer,” in Proc. International Exhibition and Confer-

ence for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management

- PCIM Europe 2015, Nuremberg, Germany, May 2015.

[39] R. Bosshard, J. W. Kolar, J. Mühlethaler, I. Stevanovi´c, B. Wunsch, and F. Canales, “Mod-

eling and η − α-Pareto Optimization of Inductive Power Transfer Coils for Electric Vehi-

cles,” IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 3, no. 1, pp.

50–64, March 2015.

[40] D. Bortis, D. Neumayr, and J. W. Kolar, “ηρ-Pareto Optimization and Comparative Eval-

uation of Inverter Concepts considered for the GOOGLE Little Box Challenge,” in Proc.

2016 IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2016),

Trondheim, Norway, June 2016. 138 BIBLIOGRAPHY

[41] R. Bosshard and J. W. Kolar, “Multi-Objective Optimization of 50 kW/85 kHz IPT System

for Public Transport,” IEEE Journal of Emerging and Selected Topics on Power Electronics,

vol. 4, no. 4, pp. 1370–1382, December 2016.

[42] R. Burkart and J. W. Kolar, “Comparative η−ρ−σ Pareto Optimization of Si and SiC Mul-

tilevel Dual-Active-Bridge Topologies With Wide Input Voltage Range,” IEEE Transactions

on Power Electronics, vol. 32, no. 7, pp. 5258–5270, July 2017.

[43] F. Haizoune, H. J. Bergveld, J. Popovi´c-Gerber, and J. A. Ferreira, “Topology compari-

son and design optimisation of the buck converter and the single-inductor dual-output

converter for system-in-package in 65nm CMOS,” in Proc. IEEE 6th International Power

Electronics and Motion Control Conference (IPEMC ’09), Wuhan, China, May 2009.

[44] G. Sizikov, A. Kolodny, and Fridman, “Efﬁciency optimization of integrated DC-DC buck

converters,” in Proc. 17th IEEE International Conference on Electronics, Circuits, and Sys-

tems (ICECS 2010), Athens, Greece, December 2010.

[45] P. Callemeyn, D. De Jonghe, G. Gielen, and M. Steyart, “Optimization of fully-integrated

power converter circuits comprising tapered inductor layout and temperature effects,”

in Proc. 2012 International Conference on Synthesis, Modeling, Analysis and Simulation

Methods and Applications to Circuit Design (SMACD 2012), Seville, Spain, September

2012.

[46] P. Zhou, W. H. Choi, B. Kim, C. H. Kim, and S. S. Sapatnekar, “Optimization of on-chip

switched-capacitor DC-DC converters for high-performance applications,” in Proc. 2012

IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2012), San Jose,

CA, USA, November 2012.

[47] N. Wang, J. Barry, J. Hannon, S. Kulkarni, R. Foley, K. McCarthy, K. Rodgers, F. Wal-

dron, M. Barry, D. Casey, J. Rohan, J. O’Brian, M. Hegarty, A.-M. Kelleher, S. Roy, and

C. Ó Mathúna, “High frequency DC-DC converter with co-packaged planar inductor and

power IC,” in Proc. IEEE 63rd Electronic Components and Technology Conference (ECTC

2013), Las Vegas, NV, USA, May 2013. BIBLIOGRAPHY 139

[48] B. Choi and D. Maksimovi´c, “Loss modeling and optimization for monolithic implemen-

tation of the three-level buck converter,” in Proc. 2013 IEEE Energy Conversion Congress

and Exposition (ECCE 2013), Denver, CO, USA, October 2013.

[49] N. Dias and M. Santos, “Efﬁciency optimization of multi-mode monolithic DC-DC con-

verters,” in Proc. 2014 Conference on Design of Circuits and Integrated Circuits (DCIS

2014), Madrid, Spain, November 2014.

[50] V. Švikovi´c, J. Cortes, P. Alou, J. Oliver, J. A. Cobos, G. Maderbacher, and C. Sandner,

“Energy-Based switches losses model for the optimization of PwrSoC buck converter,” in

Proc. IEEE 15th Workshop on Control and Modeling for Power Electronics (COMPEL 2014),

Santander, Spain, June 2014.

[51] T. Tanzawa, “An Optimum Design for Integrated Switched-Capacitor Dickson Charge

Pump Multipliers With Area Power Balance,” IEEE Transactions on Power Electronics,

vol. 29, no. 2, pp. 534–538, February 2014.

[52] Y. Geng and D. Ma, “A 100-MHz Breakdown-Resilient Power Converter With Fully Mono-

lithic Implementation on Nanoscale CMOS Process,” IEEE Transactions on Industrial Elec-

tronics, vol. 62, no. 9, pp. 5529–5538, September 2015.

[53] A. H. Shaltout and S. Gregori, “Efﬁciency optimization for monolithic step-up dc-dc con-

verters,” in Proc. IEEE 28th Canadian Conference on Electrical and Computer Engineering

(CCECE 2015), Halifax, NS, Canada, May 2015.

[54] P. A. M. Bezerra, F. Krismer, T. M. Andersen, J. W. Kolar, A. Sridhar, T. Brunschwiler,

T. Toiﬂ, M. Jatlaoui, F. Voiron, Z. Pavlovi´c, N. Wang, N. Cordero, C. Rabot, and

C. Ó Mathúna, “Modeling and multi-objective optimization of 2.5D inductor-based

Fully Integrated Voltage Regulators for microprocessor applications,” in Proc. IEEE 13th

Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference

(COBEP/SPEC 2015), Fortaleza, Brazil, November 2015.

[55] A. Sepahvand, Y. Momenroodaki, P. Zhang, Z. Popovi´c, and D. Maksimovi´c, “Monolithic

multilevel GaN converter for envelope tracking in RF power ampliﬁers,” in Proc. 2016 140 BIBLIOGRAPHY

IEEE Energy Conversion Congress and Exposition (ECCE 2016). Milwaukee, WI, USA,

September 2016.

[56] E. Abramov, A. Cervera, and M. M. Peretz, “Optimal design of a voltage regulator based

resonant switched-capacitor converter IC,” in Proc. 2016 IEEE Applied Power Electronics

Conference and Exposition (APEC 2016), Long Beach, CA, USA, March 2016.

[57] Y. Zhang, M. Rodríguez, and D. Maksimovi´c, “Very High Frequency PWM Buck Convert-

ers Using Monolithic GaN Half-Bridge Power Stages With Integrated Gate Drivers,” IEEE

Transactions on Power Electronics, vol. 31, no. 11, pp. 7926–7942, November 2016.

[58] T. M. Andersen, F. Krismer, J. W. Kolar, T. Toiﬂ, C. Menolﬁ, L. Kull, T. Morf, M. Kossel,

M. Brändli, and P. A. Francese, “Modeling and Pareto Optimization of On-Chip Switched

Capacitor Converters,” IEEE Transactions on Power Electronics, vol. 32, no. 1, pp. 363–

377, January 2017.

[59] S. Balachandran and F. C. Lee, “Algorithms for Power Converter Design Optimization,”

IEEE Transactions on Aerospace and Electronic Systems, vol. AES-17, no. 3, pp. 422–432,

May 1981.

[60] U. Ribes-Mallada, R. Leyva, and P. Garcés, “Optimization of DC-DC Converters via Ge-

ometric Programming,” Mathematical Problems in Engineering, vol. 2011, no. Article ID

458083, pp. 1–19, July 2011.

[61] S. Boyd, S.-J. Kim, L. Vandenberghe, and A. Hassibi, “A tutorial on geometric program-

ming,” Optimization and Engineering, vol. 8, no. 1, pp. 67–127, April 2007.

[62] A. Mutapˇci´c, K. Koh, S. Kim, L. Vandenberghe, and S. Boyd, “GGPLAB:

A Simple Matlab Toolbox for Geometric Programming.” [Online]. Available:

https://stanford.edu/~boyd/ggplab/

[63] J. Löfberg, “YALMIP : A Toolbox for Modeling and Optimization in MATLAB,” in Proceed-

ings of the CACSD Conference, New Orleans, LA, USA, February 2004.

[64] M. Grant and S. Boyd, “CVX: Matlab Software for Disciplined Convex Programming.”

[Online]. Available: http://cvxr.com/cvx/ BIBLIOGRAPHY 141

[65] MOSEK ApS, “MOSEK Optimization Software.” [Online]. Available: https://www.

mosek.com/products/mosek/

[66] T. Meynard and H. Foch, “Multi-level conversion: high voltage choppers and voltage-

source inverters,” in Proc. 23rd Annual IEEE Power Electronics Specialists Conference (PESC

’92), vol. 1, Toledo, Spain, July 1992, pp. 397–403.

[67] ——, “Multilevel converters and derived topologies for high power conversion,” in Proc.

1995 IEEE 21st International Conference on Industrial Electronics, Control, and Instrumen-

tation (IECON ’95), Orladno, FL, USA, July 1995, pp. 21–26.

[68] T. Meynard, H. Foch, J. Courault, R. Jakob, and M. Nahrstaedt, “Multicell converters:

basic concepts and industry applications,” IEEE Transactions on Industrial Electronics,

vol. 49, no. 5, pp. 955–964, October 2002.

[69] V. Yousefzadeh, E. Alarcón, and D. Maksimovi´c, “Three-Level Buck Converter for Enve-

lope Tracking in RF Power Ampliﬁers,” in Proc. Twentieth Annual IEEE Power Electronics

Conference and Expo., 2005 (APEC 2005), vol. 3, Austin, TX, USA, March 2005, pp.

1588–1594.

[70] Y. Lei, W. C. Liu, and R. C. N. Pilawa-Podgurski, “An analytical method to evaluate

ﬂying capacitor multilevel converters and hybrid switched-capacitor converters for large

voltage conversion ratios,” in Proc. 2015 IEEE Workshop on Control and Modeling for

Power Electronics (COMPEL 2015), Vancouver, BC, Canada, July 2015.

[71] D. Reusch, F. Lee, and M. Xu, “Three level buck converter with control and soft startup,”

in Proc. 26th IEEE Energy Convers. Congres. Expo. (ECCE 2009), San Jose, CA, USA,

September 2009, pp. 31–35.

[72] G. V. Piqué and E. Alarcón, CMOS Integrated Switching Power Converters: A Structured

Design Approach. Springer-Verlag New York, 2011.

[73] W. Kim, D. Brooks, and G.-Y. Wei, “A Fully-Integrated 3-Level DC-DC Converter for

Nanosecond-Scale DVFS,” IEEE Journal of Solid-State Circuits, vol. 47, no. 1, pp. 206–

219, January 2012. 142 BIBLIOGRAPHY

[74] N. Vukadinovi´c, A. Prodi´c, B. A. Miwa, C. B. Arnold, and M. W. Baker, “Skip-duty control

method for minimizing switching stress in low-power multi-level Dc-Dc converters,” in

Proc. 16th IEEE Workshop on Control and Modeling for Power Electronics (COMPEL 2015),

Vancouver, BC, Canada, July 2015.

[75] ——, “Volume and Efﬁciency Comparison Between Multi-Level Dc-Dc Converters and

Buck Converter for Low-Power Mobile Applications,” in Proc. 18th International Power

Electronics Symposium Ee2015, Novi Sad, Serbia, October 2015.

[76] ——, “Extended Wide-Load Range Model for Multi-Level DC-DC Converters and a Practi-

cal Dual-Mode Digital Controller,” in Proc. 31st IEEE Applied Power Electronics Conference

and Exposition (APEC 2016), Long Beach, CA, USA, March 2016, pp. 1597–1602.

[77] A. Stupar, T. McRae, N. Vukadinovi´c, A. Prodi´c, and J. Taylor, “Multi-Objective Opti-

mization and Comparison of Multi-Level DC-DC Converters Using Convex Optimization

Methods,” in Proc. 2016 18th European Conference on Power Electronics and Applications

(EPE’16 ECCE Europe), Karlsruhe, Germany, September 2016.

[78] N. Vukadinovi´c, A. Prodi´c, B. A. Miwa, C. B. Arnold, and M. W. Baker, “Ripple Minimizing

Digital Controller For Flying Capacitor Dc-Dc Converters Based on Dynamic Mode Levels

Switching,” in Proc. 2017 IEEE Applied Power Conference and Exposition (APEC 2017),

Tampa, FL, USA, March 2017.

[79] M. Rodríguez, A. Rodríguez, P. Fernández Miaja, D. González Lamar, and J. S. Zúniga,

“An Insight into the Switching Process of Power MOSFETs: An Improved Analytical

Losses Model,” IEEE Transactions on Power Electronics, vol. 25, no. 6, pp. 1626–1640,

June 2010.

[80] K. Raggl, T. Nussbaumer, and J. W. Kolar, “Guideline for a Simpliﬁed Differential-Mode

EMI Filter Design,” IEEE Transactions on Industrial Electronics, vol. 57, no. 3, pp. 1031–

1040, March 2010. BIBLIOGRAPHY 143

[81] J. Reinert, A. Brockmeyer, and R. W. A. A. De Doncker, “Calculation of Losses in Ferro-

and Ferrimagnetic Materials Based on the Modiﬁed Steinmetz Equation,” IEEE Transac-

tions on Industry Applications, vol. 37, no. 4, pp. 1055–1061, July/August 2001.

[82] J. Mühlethaler, J. Biela, J. W. Kolar, and A. Ecklebe, “Improved Core-Loss Calculation

for Magnetic Components Employed in Power Electronic Systems,” IEEE Transactions on

Power Electronics, vol. 27, no. 2, pp. 964–973, February 2012.

[83] J. Mühlethaler, “Modeling and Multi-Objective Optimization of Inductive Power Com-

ponents,” Ph.D. dissertation, Swiss Federal Institute of Technology (ETH Zürich), 2012,

Diss. Nr. 20217.

[84] A. Reatti and M. K. Kazimierczuk, “Comparison of various methods for calculating the AC

resistance of inductors,” IEEE Transactions on Magnetics, vol. 38, no. 3, pp. 1512–1518,

May 2002.

[85] A. Stupar, J. Taylor, and A. Prodi´c, “Posynomial Models of Inductors for Optimization of

Power Electronic Systems by Geometric Programming,” in Proc. 2016 IEEE Workshop on

Control and Modeling for Power Electronics (COMPEL 2016), Trondheim, Norway, June

2016.

[86] Würth Elektronik, “REDEXPERT.” [Online]. Available: https://www.we-online.com/

redexpert/

[87] J. Mühlethaler, J. Biela, J. W. Kolar, and A. Ecklebe, “Core Losses Under the DC Bias Con-

dition Based on Steinmetz Parameters,” IEEE Transactions on Power Electronics, vol. 27,

no. 2, pp. 953–963, February 2012.

[88] Y. Lei, W. C. Liu, and R. C. N. Pilawa-Podgurski, “An Analytical Method to Evaluate

and Design Hybrid Switched-Capacitor and Multilevel Converters,” IEEE Transactions on

Power Electronics, Early Access 2017, DOI 10.1109/TPEL.2017.2690324.

[89] U. Drofenik, G. Laimer, and J. W. Kolar, “Theoretical Converter Power Density Limits

for Forced Convection Cooling,” in Proc. 2005 Power Conversion and Intelligent Motion

Conference (PCIM Europe 2005), Nuremberg, Germany, June 2005. 144 BIBLIOGRAPHY

[90] U. Drofenik, A. Stupar, and J. W. Kolar, “Analysis of Theoretical Limits of Forced-Air

Cooling Using Advanced Composite Materials with High Thermal Conductivities,” IEEE

Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 4, pp.

528–535, April 2011.

[91] A. Stupar, U. Drofenik, and J. W. Kolar, “Optimization of Phase Change Material Heat

Sinks for Low Duty Cycle High Peak Load Power Supplies,” IEEE Transactions on Com-

ponents, Packaging and Manufacturing Technology, vol. 2, no. 1, pp. 102–115, January

2012.

[92] C. Gammeter, F. Krismer, and J. W. Kolar, “Weight Optimization of a Cooling System

Composed of Fan and Extruded-Fin Heat Sink,” IEEE Transactions on Industrial Electron-

ics, vol. 51, no. 1, pp. 509–520, January/February 2015.

[93] A. Magnani and S. Boyd, “Convex piecewise-linear ﬁtting,” Optimization and Engineer-

ing, vol. 10, no. 1, pp. 1–17, March 2009.

[94] W. Hoburg, P. Kirschen, and P. Abbeel, “Data Fitting with Geometric-Programming-

Compatible Softmax Functions,” Optimization and Engineering, vol. 17, no. 4, pp. 897–

918, August 2016.

[95] J. Mühlethaler, M. Schweizer, R. Blattman, J. W. Kolar, and A. Ecklebe, “Optimal Design

of LCL Harmonic Filters for Three-Phase PFC Rectiﬁers,” IEEE Transactions on Power

Electronics, vol. 28, no. 7, pp. 3114–3125, July 2013.

[96] Q. Li, M. A. E. Andersen, and O. C. Thomsen, “Research on Power Factor Correction Boost

Inductor Design Optimization - Efﬁciency vs. Power Density,” in Proc. 8th International

Conference on Power Electronics - ECCE Asia 2011, Jeju, South Korea, May - June 2011,

pp. 728–735.

[97] X. Wang, H. Zeng, D. Gunasekaran, and F. Z. Peng, “Multi-objective Design and Op-

timization of Inductors: A Generalized Software-Driven Approach,” in Proc. 17th IEEE

Workshop on Control and Modeling for Power Electronics (COMPEL 2016), Trondheim,

Norway, June 2016. BIBLIOGRAPHY 145

[98] K. Watanabe, F. Campelo, Y. Ilijima, K. Kawano, T. Matsuo, T. Mifune, and H. Igarashi,

“Optimization of Inductors Using Evolutionary Algorithms and Its Experimental Valida-

tion,” IEEE Transactions on Magnetics, vol. 46, no. 8, pp. 3393–3396, August 2010.

[99] T. Sato, W. K., H. Igarashi, T. Matsuo, T. Mifune, K. Kawano, M. Suzuki, Y. Uehara,

and A. Furuya, “3-D Optimization of Ferrite Inductor Considering Hysteresis Loss,” IEEE

Transactions on Magnetics, vol. 49, no. 5, pp. 2129–2013, May 2013.

[100] Gecko-Simulations AG, “GeckoMAGNETICS magnetic component simulation and design

tool.” [Online]. Available: http://gecko-simulations.com/geckomagnetics.html

[101] J. Mühlethaler, “GeckoMAGNETICS Comparison to Experimental Results - Loss

and Temperature Measurements,” March 2016. [Online]. Available: http://

gecko-simulations.com/downloads/GeckoM_acc.pdf

[102] P. Jain, “Wide-Range 7-Switch Flying Capacitor Based DC-DC Converter for Point-of-

Load Applications,” Master’s thesis, University of Toronto, 2015, ISBN 9781339270111.

[103] P. Jain, A. Prodi´c, and A. Gerfer, “Wide-input High Power Density Flexible Converter

Topology for Dc-Dc Applications,” in Proc. 2016 IEEE Applied Power Electronics Conference

and Exposition (APEC 2016), Long Beach, CA, USA, March 2016.

[104] K. Nishijima, K. Harada, T. Nakano, T. Nabeshima, and T. Sato, “A Double Step-Down

Two-Phase Buck Converter for VRM,” in Proc. 2005 European Conference on Power Elec-

tronics and Applications (EPE 2005), Dresden, Germany, September 2005.

[105] P. S. Shenoy, M. Amaro, J. Morroni, and D. Freeman, “Comparison of a Buck Converter

and a Series Capacitor Buck Converter for High-Frequency, High-Conversion-Ratio Volt-

age Regulators,” IEEE Transactions on Power Electronics, vol. 31, no. 10, pp. 7006–7015,

October 2016.

[106] D. Baba, “Beneﬁts of a multiphase buck converter,” Texas Instruments Analog Applications

Journal, no. 1Q 2012, pp. 8–13, 2012. 146 BIBLIOGRAPHY

[107] A. Radić, Z. Lukić, A. Prodić, and R. H. de Nie, “Minimum-Deviation Digital Controller IC

for DC-DC Switch-Mode Power Supplies,” IEEE Transactions on Power Electronics, vol. 28,

no. 9, pp. 4281–4298, September 2013.

[108] T. Moiannou, P. Jain, and A. Prodi´c, “Upcoming publication on the 7SFC converter in an

IEEE journal,” to be submitted for review by the end of 2017.

[109] Gecko-Simulations AG, “GeckoCIRCUITS power electronics circuit simulator.” [Online].

Available: http://gecko-simulations.com/geckocircuits.html

[110] F. Neveu, “Design and Implementation of High Frequency 3D DC-DC Converter,” Ph.D.

dissertation, L’Institut National des Sciences Appliquées (INSA Lyon), 2015, N°ordre

2015ISAL0133.

[111] D. O. Boillat, F. Krismer, and J. W. Kolar, “EMI Filter Volume Minimization of a Three-

Phase/Level T-Type PWM Converter System,” IEEE Transactions on Power Electronics,

vol. 32, no. 4, pp. 2473–2480, April 2017.

[112] J. Z. Bebi´c, P. W. Lehn, and M. R. Iravani, “The Hybrid Power Flow Controller - A New

Concept for Flexible AC Transmission,” in Proc. 2006 IEEE Power Engineering Society

General Meeting, Montreal, QC, Canada, June 2006.

[113] S. Ali Nabavi Niaki, M. R. Iravani, and M. Noroozian, “Power-Flow Model and Steady-

State Analysis of the Hybrid Flow Controller,” IEEE Transactions on Power Delivery,

vol. 23, no. 4, pp. 2330–2338, October 2008.

[114] M. Momayyezan, B. Hredzak, and V. G. Agelidis, “Integrated Reconﬁgurable Converter

Topology for High-Voltage Battery Systems,” IEEE Transactions on Power Electronics,

vol. 31, no. 3, pp. 1968–1979, March 2016.

[115] E. Chemali and A. Emadi, “On the Concept of a Novel Reconﬁgurable Multi-Source

Inverter,” in Proc. 2017 IEEE Transportation Electriﬁcation Conference and Expo. (ITEC

2017), Chicago, IL, USA, June 2017.