APPENDIX a Resources and References
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Essional-Software-Testing-With-Visual
Arnold ffirs.tex V4 - 08/02/2007 10:24am Page v Professional Software Testing with Visual Studio® 2005 Team System ToolsforSoftwareDevelopers andTestEngineers Tom Arnold Dominic Hopton Andy Leonard Mike Frost Wiley Publishing, Inc. Arnold frontcover1.tex V4 - 08/02/2007 10:23am Page ii Arnold frontcover1.tex V4 - 08/02/2007 10:23am Page i Professional Software Testing with Visual Studio® 2005 Team System Introduction . .xxiii Chapter 1: Introduction to VSTEST and VSTESD . 1 Chapter 2: A Quick Tour of VSTEST and VSTESD . 15 Chapter 3: Unit Testing with VSTEST and VSTESD . 41 Chapter 4: Testing the Database . 73 Chapter 5: Web Testing . 125 Chapter 6: Using Manual, Ordered, and Generic Test Types . 165 Chapter 7: Load Testing . 191 Chapter 8: Using Code Analysis and Dynamic Analysis. 243 Chapter 9: VSTEST and VSTESD within the Software Development LifeCycle.....................................................273 Appendix A: Installing Team Explorer . 305 Appendix B: Creating and Running a Web Test: A High-Level Walk-Through ...............................................313 Appendix C: Creating and Running a Unit Test: A High-Level Walk-Through ...............................................319 Appendix D: Creating and Running a Load Test: A High-Level Walk-Through ...............................................327 Appendix E: Creating and Running a Manual Test: A High-Level Walk-Through ...............................................339 Appendix F: Other Sources of Information . 347 Index....................................................................351 Arnold frontcover1.tex V4 - 08/02/2007 10:23am Page ii Arnold ffirs.tex V4 - 08/02/2007 10:24am Page iii Professional Software Testing with Visual Studio® 2005 Team System Arnold ffirs.tex V4 - 08/02/2007 10:24am Page iv Arnold ffirs.tex V4 - 08/02/2007 10:24am Page v Professional Software Testing with Visual Studio® 2005 Team System ToolsforSoftwareDevelopers andTestEngineers Tom Arnold Dominic Hopton Andy Leonard Mike Frost Wiley Publishing, Inc. -
Did Your Tests Pass Or Fail? Answering with Automation
Presentation P R E S E N T A T I O N Bio T6 Thursday, March 8, 2001 11:30 AM DID YOUR TESTS PASS OR FAIL? ANSWERING WITH AUTOMATION Noel Nyman Microsoft International Conference On Software Test Automation March 5-8, 2001 San Jose, CA, USA Did Your Tests Pass or Fail? Using Self-Verifying Data with Hard-to-Automate Applications Noel Nyman Desktop Applications Automation Test Lead Microsoft Windows Systems Group Agenda § Self-Verifying Data review üHow to use SVD to tell that your tests pass § Automating problem applications üIdeas on how to automate apps when your automation tools can’t see parts of them § Demos § Resources for more information § Questions 2 Self-Verifying Data • Has codes embedded in the data that act as an oracle and can tell you if the data is… üLegal - is this data from the correct data set? üValid - is this data that should be here? üCorrect type – is this data the type we’re looking üFrom correct record – data from the record we asked for? üAccurate - are characters missing, munged? § SVD data is like a debug build of an app 3 Benefits of Using SVD § No separate oracle needed § Can be scaled to very large data sets § Can be used with rich data not easily verified by humans § Easy to verify with automated testing § Adding additional test data usually doesn’t require updating automated tests 4 SVD Example First name from a rich data set… First name with embedded SVD codes… SVD codes replaced with evocative tags… 5 Automating Problem Apps § Forget capture/replay – if it works well for you, you don’t have a “problem -
CS 110 Discussion 15 Programming with SIMD Intrinsics
CS 110 Discussion 15 Programming with SIMD Intrinsics Yanjie Song School of Information Science and Technology May 7, 2020 Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 1 / 21 Table of Contents 1 Introduction on Intrinsics 2 Compiler and SIMD Intrinsics 3 Intel(R) SDE 4 Application: Horizontal sum in vector Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 2 / 21 Table of Contents 1 Introduction on Intrinsics 2 Compiler and SIMD Intrinsics 3 Intel(R) SDE 4 Application: Horizontal sum in vector Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 3 / 21 Introduction on Intrinsics Definition In computer software, in compiler theory, an intrinsic function (or builtin function) is a function (subroutine) available for use in a given programming language whose implementation is handled specially by the compiler. Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 4 / 21 Intrinsics in C/C++ Compilers for C and C++, of Microsoft, Intel, and the GNU Compiler Collection (GCC) implement intrinsics that map directly to the x86 single instruction, multiple data (SIMD) instructions (MMX, Streaming SIMD Extensions (SSE), SSE2, SSE3, SSSE3, SSE4). Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 5 / 21 x86 SIMD instruction set extensions MMX (1996, 64 bits) 3DNow! (1998) Streaming SIMD Extensions (SSE, 1999, 128 bits) SSE2 (2001) SSE3 (2004) SSSE3 (2006) SSE4 (2006) Advanced Vector eXtensions (AVX, 2008, 256 bits) AVX2 (2013) F16C (2009) XOP (2009) FMA FMA4 (2011) FMA3 (2012) AVX-512 (2015, 512 bits) Yanjie Song (S.I.S.T.) CS 110 Discussion 15 2020.05.07 6 / 21 SIMD extensions in other ISAs There are SIMD instructions for other ISAs as well, e.g. -
PGI Compilers
USER'S GUIDE FOR X86-64 CPUS Version 2019 TABLE OF CONTENTS Preface............................................................................................................ xii Audience Description......................................................................................... xii Compatibility and Conformance to Standards............................................................xii Organization................................................................................................... xiii Hardware and Software Constraints.......................................................................xiv Conventions.................................................................................................... xiv Terms............................................................................................................ xv Related Publications.........................................................................................xvii Chapter 1. Getting Started.....................................................................................1 1.1. Overview................................................................................................... 1 1.2. Creating an Example..................................................................................... 2 1.3. Invoking the Command-level PGI Compilers......................................................... 2 1.3.1. Command-line Syntax...............................................................................2 1.3.2. Command-line Options............................................................................ -
Intel Hardware Intrinsics in .NET Core
Han Lee, Intel Corporation [email protected] Notices and Disclaimers No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. This document contains information on products, services and/or processes in development. All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest forecast, schedule, specifications and roadmaps. Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at intel.com, or from the OEM or retailer. The products and services described may contain defects or errors known as errata which may cause deviations from published specifications. Current characterized errata are available on request. No product or component can be absolutely secure. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548- 4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, and other Intel product and solution names in this presentation are trademarks of Intel *Other names and brands may be claimed as the property of others © Intel Corporation. 2 What Do These Have in Common? Domain Example Image processing Color extraction High performance computing (HPC) Matrix multiplication Data processing Hamming code Text processing UTF-8 conversion Data structures Bit array Machine learning Classification For performance sensitive code, consider using Intel® hardware intrinsics 3 Objectives . -
Optimizing Subroutines in Assembly Language an Optimization Guide for X86 Platforms
2. Optimizing subroutines in assembly language An optimization guide for x86 platforms By Agner Fog. Copenhagen University College of Engineering. Copyright © 1996 - 2012. Last updated 2012-02-29. Contents 1 Introduction ....................................................................................................................... 4 1.1 Reasons for using assembly code .............................................................................. 5 1.2 Reasons for not using assembly code ........................................................................ 5 1.3 Microprocessors covered by this manual .................................................................... 6 1.4 Operating systems covered by this manual................................................................. 7 2 Before you start................................................................................................................. 7 2.1 Things to decide before you start programming .......................................................... 7 2.2 Make a test strategy.................................................................................................... 9 2.3 Common coding pitfalls............................................................................................. 10 3 The basics of assembly coding........................................................................................ 12 3.1 Assemblers available ................................................................................................ 12 3.2 Register set -
Automatic SIMD Vectorization of Fast Fourier Transforms for the Larrabee and AVX Instruction Sets
Automatic SIMD Vectorization of Fast Fourier Transforms for the Larrabee and AVX Instruction Sets Daniel S. McFarlin Volodymyr Arbatov Franz Franchetti Department of Electrical and Department of Electrical and Department of Electrical and Computer Engineering Computer Engineering Computer Engineering Carnegie Mellon University Carnegie Mellon University Carnegie Mellon University Pittsburgh, PA USA 15213 Pittsburgh, PA USA 15213 Pittsburgh, PA USA 15213 [email protected] [email protected] [email protected] Markus Püschel Department of Computer Science ETH Zurich 8092 Zurich, Switzerland [email protected] ABSTRACT General Terms The well-known shift to parallelism in CPUs is often associated Performance with multicores. However another trend is equally salient: the increasing parallelism in per-core single-instruction multiple-date Keywords (SIMD) vector units. Intel’s SSE and IBM’s VMX (compatible to Autovectorization, super-optimization, SIMD, program generation, AltiVec) both offer 4-way (single precision) floating point, but the Fourier transform recent Intel instruction sets AVX and Larrabee (LRB) offer 8-way and 16-way, respectively. Compilation and optimization for vector extensions is hard, and often the achievable speed-up by using vec- 1. Introduction torizing compilers is small compared to hand-optimization using Power and area constraints are increasingly dictating microar- intrinsic function interfaces. Unfortunately, the complexity of these chitectural developments in the commodity and high-performance intrinsics interfaces increases considerably with the vector length, (HPC) CPU space. Consequently, the once dominant approach of making hand-optimization a nightmare. In this paper, we present a dynamically extracting instruction-level parallelism (ILP) through peephole-based vectorization system that takes as input the vector monolithic out-of-order microarchitectures is being supplanted by instruction semantics and outputs a library of basic data reorgani- designs with simpler, replicable architectural features. -
Micro Focus Visual COBOL 6.0 for Visual Studio
Micro Focus Visual COBOL 6.0 for Visual Studio Release Notes Micro Focus The Lawn 22-30 Old Bath Road Newbury, Berkshire RG14 1QN UK http://www.microfocus.com © Copyright 2020 Micro Focus or one of its affiliates. MICRO FOCUS, the Micro Focus logo and Visual COBOL are trademarks or registered trademarks of Micro Focus or one of its affiliates. All other marks are the property of their respective owners. 2020-06-16 ii Contents Micro Focus Visual COBOL 6.0 for Visual Studio Release Notes ..................5 What's New ......................................................................................................... 6 .NET Core ........................................................................................................................... 6 COBOL Application Console Size .......................................................................................6 COBOL Language Enhancements ......................................................................................6 Code Analysis ..................................................................................................................... 7 Code Analyzer Refactoring ................................................................................................. 7 Compiler Directives ............................................................................................................. 7 Containers ...........................................................................................................................8 Database Access - DB2 ECM ............................................................................................ -
Examview Test Generator User Guide Version 11 Examview Test Generator 2
ExamView Test Generator User Guide Version 11 ExamView Test Generator 2 © 2017 Turning Technologies, LLC. All rights reserved. TurningPoint® is a registered trademark and ExamView™ is a trademark of Turning Technologies, LLC. Other trademarked product names mentioned in this document are owned by their respective companies. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Turning Technologies, LLC. For information, address Turning Technologies, LLC, 255 West Federal Street, Youngstown, OH 44503 USA. FCC Statement This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. IC Statement This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. -
Rational® Clearcase®
Rational Software Corporation® Rational® ClearCase® Command Reference (A–L) VERSION: 2003.06.00 AND LATER PART NUMBER: 800-026163-000 UNIX/WINDOWS EDITION Legal Notices Copyright © 1992-2003 Rational Software Corporation . All Rights Reserved. Part Number: 800–026163–000 Version Number: 2003.06.00 This manual (the "Work") is protected under the copyright laws of the United States and/or other jurisdictions, as well as various international treaties. Any reproduction or distribution of the Work is expressly prohibited without the prior written consent of Rational Software Corporation. The Work is furnished under a license and may be used or copied only in accordance with the terms of that license. Unless specifically allowed under the license, this manual or copies of it may not be provided or otherwise made available to any other person. No title to or ownership of the manual is transferred. Read the license agreement for complete terms. Rational Software Corporation, Rational, Rational Suite, Rational Suite ContentStudio, Rational Apex, Rational Process Workbench, Rational Rose, Rational Summit, Rational Unified process, Rational Visual Test, AnalystStudio, ClearCase, ClearCase Attache, ClearCase MultiSite, ClearDDTS, ClearGuide, ClearQuest, PerformanceStudio, PureCoverage, Purify, Quantify, Requisite, RequisitePro, RUP, SiteCheck, SiteLoad, SoDa, TestFactory, TestFoundation, TestMate and TestStudio are registered trademarks of Rational Software Corporation in the United States and are trademarks or registered trademarks in other countries. The Rational logo, Connexis, ObjecTime, Rational Developer Network, RDN, ScriptAssure, and XDE, among others, are trademarks of Rational Software Corporation in the United States and/or in other countries. All other names are used for identification purposes only and are trademarks or registered trademarks of their respective companies. -
Research Collection
Research Collection Doctoral Thesis Building Abstractions for Staged DSLs in Performance-Oriented Program Generators Author(s): Stojanov, Alen Publication Date: 2019-05 Permanent Link: https://doi.org/10.3929/ethz-b-000372536 Rights / License: In Copyright - Non-Commercial Use Permitted This page was generated automatically upon download from the ETH Zurich Research Collection. For more information please consult the Terms of use. ETH Library alen stojanov BUILDINGABSTRACTIONSFORSTAGEDDSLSIN PERFORMANCE-ORIENTEDPROGRAMGENERATORS diss. eth no. 26058 BUILDINGABSTRACTIONSFORSTAGEDDSLS INPERFORMANCE-ORIENTEDPROGRAM GENERATORS A dissertation submitted to attain the degree of doctor of sciences of eth zurich (Dr. sc. ETH Zurich) presented by alen stojanov Dipl., Eidgenössisches Polytechnikum born on 1 September 1987 citizen of North Macedonia and Bulgaria accepted on the recommendation of Prof. Dr. Markus Püschel, examiner Prof. Dr. Tiark Rompf, co-examiner Prof. Dr. Zhendong Su, co-examiner 2019 Alen Stojanov: Building Abstractions for Staged DSLs in Performance-Oriented Program Generators, © 2019 To Gordana, my mother. To this very day, you would still say: “Ajde Alen, xto qekax?” I will forever remember your words. These simple words, that hold the meaning of: “Come on, Alen, what are you waiting for?”, have been the driving force throughout this journey. Well mom, I won’t be waiting anymore. Abstract Developing high-performance code for numerical domains is challenging, as it requires hand-in-hand specialization with the continuous evolution of modern hardware. Program generators based on domain-specific languages (DSLs) can provide a solution to the challenge of re-specializing programs and libraries as new architectures emerge. However, such code generators are difficult to design as they require DSLs that reason about high-level mathematical domains, and employ analysis and transformation steps to map these domains to low-level hardware instructions. -
In the GNU Fortran Compiler
Using GNU Fortran For gcc version 12.0.0 (pre-release) (GCC) The gfortran team Published by the Free Software Foundation 51 Franklin Street, Fifth Floor Boston, MA 02110-1301, USA Copyright c 1999-2021 Free Software Foundation, Inc. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3 or any later version published by the Free Software Foundation; with the Invariant Sections being \Funding Free Software", the Front-Cover Texts being (a) (see below), and with the Back-Cover Texts being (b) (see below). A copy of the license is included in the section entitled \GNU Free Documentation License". (a) The FSF's Front-Cover Text is: A GNU Manual (b) The FSF's Back-Cover Text is: You have freedom to copy and modify this GNU Manual, like GNU software. Copies published by the Free Software Foundation raise funds for GNU development. i Short Contents 1 Introduction ::::::::::::::::::::::::::::::::::::::::: 1 Invoking GNU Fortran 2 GNU Fortran Command Options :::::::::::::::::::::::: 7 3 Runtime: Influencing runtime behavior with environment variables ::::::::::::::::::::::::::::::::::::::::::: 33 Language Reference 4 Fortran standards status :::::::::::::::::::::::::::::: 39 5 Compiler Characteristics :::::::::::::::::::::::::::::: 45 6 Extensions :::::::::::::::::::::::::::::::::::::::::: 51 7 Mixed-Language Programming ::::::::::::::::::::::::: 73 8 Coarray Programming :::::::::::::::::::::::::::::::: 89 9 Intrinsic Procedures ::::::::::::::::::::::::::::::::: 113