Intel La-9241P

A B C D E

1 1

Compal Confidential 2 2 Intel Haswell rPGA Processor with Lynx Point-H Viper MXM Date : 2012/12/20 Version 0.5 3 3

4 4

Compal Electronics, Inc. Security Classification 2011/06/29 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 1of 56 A B C D E www.vinafix.vn Cover Page LA-9241P

Compal Confidential Model Name : File Name :

1 1

LVDS Panel Conn. DDR3-SO-DIMM2,BANK 0, 4 1, 2, 3 Ch B Page 12

eDP to LVDS eDP Panel Conn. eDP DeMUX eDP RTD 2136 Page 22 PS8321 Page 36 Intel DDR3-SO-DIMM1,BANK 0, 3 1, 2, 3 DP Conn DPC eDPF DDR3L 1333MHz 1.35V Ch A DP MUX Haswell Page 11 Page 39 PS8338 rPGA Processor MXM3.0 Conn Page 36 rPGA947 Dock Conn DPD AMD: PEGx16 Page 33 DPE nVidia: 37.5mm*37.5mm Page 4,5,6,7,8,9,10 Page 35 X4 USB3.0 x3 FDI x2 DMI x4 X4 Dock Conn CRT Dock x1 Page 33 VGA Switch 100MHz 100MHz Mini DP Conn. CRT 2 2.7GT/s 5GT/s 2 ThunderBolt Page 33 2 to 2 X1 Smart card Controller Cactus Ridge VGA Conn MAX14885EETL AU9540A51 Page 37 Page 39 CRT CRT USB 3.0 x4 X1 Page 36 Page 36 Intel USB 2.0 x 11 WWANPage 25 SIM Card Page 25 X4 Lynx PointPCH FPR Validity VFM471 PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz 695pin BGA X1 HDA Codec Digital MIC Page 28 Page 22 SATAx4 IDT 92HD91 HD Audio Port 8 Port 6 Port 5 Port 7 Port 1 Port 2 Port 0 20mm*20mm X1 Webcam Page 13,14,15,16,17,18,19,20,21 Page 26 Combo Jack Page 22 (GEN1 1.5Gb/S Page 39 GEN2 3Gb/S SPI X1 GEN3 6Gb/S) USB2.0 Card Reader GLAN WLAN ODD mSATA SATA HDD SPK conn Page 39 Controller Intel Expresscard (MINI card) Conn. Conn. Conn. Page 27 LPCBUS BIOS SPI ROM x1, X1 Clarkville WLAN Page 25 16 MB Page 30 Page 39 Page 23Page 23 Page 23 X1 Page 39 Page 25

Page 29 33MHz Dock Page 33

3 SD/MMC Slot Port 6 Port 13 3 USB 2.0 Bus RJ45 Conn. Page 29 Docking connector: RJ45 Accelerometer USB30*1 ST HP3DC2 EC ROM USB20*1 2MB DP*2 Page 30 CPU FAN1 conn.Page 28 Super I/O TPM1.2 Parallel port KBC Page 30 Page 32 SPI(PCH) Serial port SMSC LPC47N217 Infineon SLB9656/9635Page 28 SMSC KBC1126 PS2 Page 24 PS2 Touch Pad Int.KBD Line in/Line out SATAx2 Touch pad daughter board SMBus (PCH) VGA Page 38 Page 38 RTC CKT. Page 13 4 4 Power On/Off CKT.

Security Classification DC/DC interface CKT. Page 34 2012/03/23 2011/06/29 Deciphered Date Compal Electronics, Inc. Issued Date

Compal Secret Data Title

A B C D E Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 2of 56 Block Diagrams LA-9241P

D D

C C

B B

A A

Compal Electronics, Inc.

Security Classification SecurityIssued Classification Date 2012/03/23 Deciphered Date 2011/06/29

Compal Secret Data Title

Size Document Number Rev 5 4 www.vinafix.vn3 2 Custom 1 0.5 Date: Thursday,SMBus December block 20, 2012 diagram_DSCSheet 3of 56 LA-9241P

+VCCIOA_OUT

PEG_COMP 2 1 D 24.9_0402_1% RC1 D CAD Note: Trace width=12 mils ,Spacing=15mil Max length= 400 mils.

Haswell rPGA EDS JCPU1A

E23 PEG_COMP PEG_RCOMP M29 PEG_CRX_GTX_N0 PEG_CRX_GTX_N[0..15] [35] PEG_CTX_GRX_P[0..15] D21 PEG_RXN_0 K28 PEG_CTX_GRX_P[0..15] [35] [14] DMI_CRX_PTX_N0 DMI_CRX_PTX_N0 PEG_CRX_GTX_N1 C21 DMI_RXN_0 PEG_RXN_1 M31 PEG_CTX_GRX_N[0..15] [14] DMI_CRX_PTX_N1 DMI_CRX_PTX_N1 PEG_CRX_GTX_N2 DMI_CRX_PTX_N2 B21 DMI_RXN_1 PEG_RXN_2 L30 PEG_CRX_GTX_N3 PEG_CTX_GRX_N[0..15] [35] [14] DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 A21 DMI_RXN_2 PEG_RXN_3 M33 PEG_CRX_GTX_N4 [14] DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5 DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6 [14] DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 C20 DMI_RXP_0 PEG_RXN_6 L34 PEG_CRX_GTX_N7 [14] DMI_CRX_PTX_P1 PEGPEG DMI_CRX_PTX_P2 B20 DMI_RXP_1 PEG_RXN_7 E29 PEG_CRX_GTX_N8 [14] DMI_CRX_PTX_P2 DMI_RXP_2 PEG_RXN_8 DMI_CRX_PTX_P3 A20 DMI D28 PEG_CRX_GTX_N9 [14] DMI_CRX_PTX_P3 DMI_RXP_3 PEG_RXN_9 E31 PEG_CRX_GTX_N10 DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_CRX_GTX_N11 [14] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 C17 DMI_TXN_0 PEG_RXN_11 E35 PEG_CRX_GTX_N12 PEG_CTX_GRX_C_P0 CC12 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P0 [14] DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_CRX_GTX_N13 PEG_CTX_GRX_C_N0 CC22 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N0 [14] DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 A17 DMI_TXN_2 PEG_RXN_13 E33 PEG_CRX_GTX_N14 [14] DMI_CTX_PRX_N3 DMI_TXN_3 PEG_RXN_14 E32 PEG_CRX_GTX_N15 PEG_CTX_GRX_C_P1 CC32 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P1 PEG_CRX_GTX_P[0..15] [35] DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PEG_CRX_GTX_P0 PEG_CTX_GRX_C_N1 CC42 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N1 [14] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 C18 DMI_TXP_0 PEG_RXP_0 L28 PEG_CRX_GTX_P1 [14] DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_CRX_GTX_P2 PEG_CTX_GRX_C_P2 CC52 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P2 [14] DMI_CTX_PRX_P2 C DMI_CTX_PRX_P3 A18 DMI_TXP_2 PEG_RXP_2 K30 PEG_CRX_GTX_P3 PEG_CTX_GRX_C_N2 CC62 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N2 C [14] DMI_CTX_PRX_P3 DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4 PEG_RXP_4 K32 PEG_CRX_GTX_P5 PEG_CTX_GRX_C_P3 CC72 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P3 PEG_RXP_5 L35 PEG_CRX_GTX_P6 PEG_CTX_GRX_C_N3 CC82 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N3 PEG_RXP_6 K34 PEG_CRX_GTX_P7 PEG_RXP_7 F29 PEG_CRX_GTX_P8 PEG_CTX_GRX_C_P4 CC92 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P4 PEG_RXP_8 H29 FDI E28 2 1 [14] FDI_CSYNC FDI_CSYNC PEG_CRX_GTX_P9 PEG_CTX_GRX_C_N4 CC10 0.22U_0402_6.3V6K PEG_CTX_GRX_N4 J29 FDI_CSYNC PEG_RXP_9 F31 [14] FDI_INT FDI_INT PEG_CRX_GTX_P10 DISP_INT PEG_RXP_10 E30 PEG_CRX_GTX_P11 PEG_CTX_GRX_C_P5 CC112 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P5 PEG_RXP_11 F35 PEG_CRX_GTX_P12 PEG_CTX_GRX_C_N5 CC122 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N5 PEG_RXP_12 E34 PEG_CRX_GTX_P13 PEG_RXP_13 F33 PEG_CRX_GTX_P14 PEG_CTX_GRX_C_P6 CC132 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P6 PEG_RXP_14 D32 PEG_CRX_GTX_P15 PEG_CTX_GRX_C_N6 CC142 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N6 PEG_RXP_15 H35 PEG_CTX_GRX_C_N0 PEG_TXN_0 H34 PEG_CTX_GRX_C_N1 PEG_CTX_GRX_C_P7 CC152 1 0.22U_0402_6.3V6K PEG_CTX_GRX_P7 PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 PEG_CTX_GRX_C_N7 CC162 1 0.22U_0402_6.3V6K PEG_CTX_GRX_N7 PEG_TXN_2 H32 PEG_CTX_GRX_C_N3 PEG_TXN_3 J31 PEG_CTX_GRX_C_N4 PEG_CTX_GRX_C_P8 CC171 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P8 PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 PEG_CTX_GRX_C_N8 CC181 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N8 PEG_TXN_5 C33 PEG_CTX_GRX_C_N6 PEG_TXN_6 B32 PEG_CTX_GRX_C_N7 PEG_CTX_GRX_C_P9 CC191 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P9 PEG_TXN_7 B31 PEG_CTX_GRX_C_N8 PEG_CTX_GRX_C_N9 CC201 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N9 PEG_TXN_8 A30 PEG_CTX_GRX_C_N9 PEG_TXN_9 B29 PEG_CTX_GRX_C_N10 PEG_CTX_GRX_C_P10 CC211 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P10 PEG_TXN_10 A28 PEG_CTX_GRX_C_N11 PEG_CTX_GRX_C_N10 CC221 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N10 PEG_TXN_11 B27 PEG_CTX_GRX_C_N12 PEG_TXN_12 A26 PEG_CTX_GRX_C_N13 PEG_CTX_GRX_C_P11 CC231 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P11 PEG_TXN_13 B25 PEG_CTX_GRX_C_N14 PEG_CTX_GRX_C_N11 CC241 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N11 PEG_TXN_14 A24 PEG_CTX_GRX_C_N15 PEG_TXN_15 J35 PEG_CTX_GRX_C_P0 PEG_CTX_GRX_C_P12 CC251 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P12 PEG_TXP_0 G34 PEG_CTX_GRX_C_P1 PEG_CTX_GRX_C_N12 CC261 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N12 PEG_TXP_1 H33 PEG_CTX_GRX_C_P2 B PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 PEG_CTX_GRX_C_P13 CC271 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P13 B PEG_TXP_3 H31 PEG_CTX_GRX_C_P4 PEG_CTX_GRX_C_N13 CC281 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N13 PEG_TXP_4 H30 PEG_CTX_GRX_C_P5 PEG_TXP_5 B33 PEG_CTX_GRX_C_P6 PEG_CTX_GRX_C_P14 CC291 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P14 PEG_TXP_6 A32 PEG_CTX_GRX_C_P7 PEG_CTX_GRX_C_N14 CC301 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N14 PEG_TXP_7 C31 PEG_CTX_GRX_C_P8 PEG_TXP_8 B30 PEG_CTX_GRX_C_P9 PEG_CTX_GRX_C_P15 CC311 2 0.22U_0402_6.3V6K PEG_CTX_GRX_P15 PEG_TXP_9 C29 PEG_CTX_GRX_C_P10 PEG_CTX_GRX_C_N15 CC321 2 0.22U_0402_6.3V6K PEG_CTX_GRX_N15 PEG_TXP_10 B28 PEG_CTX_GRX_C_P11 PEG_TXP_11 C27 PEG_CTX_GRX_C_P12 PEG_TXP_12 B26 PEG_CTX_GRX_C_P13 PEG_TXP_13 C25 PEG_CTX_GRX_C_P14 PEG_TXP_14 B24 PEG_CTX_GRX_C_P15 PEG_TXP_15

INTEL_HASWELL_HASWELL 1 OF 9

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 4of 56 5 4 3 2 1 www.vinafix.vn DMI,PEG LA-9241P

+VCCIO_OUT

SM_DRAMPWROK with DDR Power Gating Topology 0.1U_0402_16V4Z 0.1U_0402_16V4Z

1 1 +VCCIO_OUT +VCCIO_OUT CC33 CC34

+1.35VS 2 2 +5VDS JXDP1 1 2 3 GND0 GND1 4 CC35 1 XDP_PREQ# OBSFN_A0 OBSFN_C0 CFG17 1 2 5 6 CFG17 [8] RC5 XDP_PRDY# OBSFN_A1 OBSFN_C1 CFG16 08/10 Add RC106 and change UC1.1 connection to VR_ON 7 8 CFG16 [8] GND2 GND3 9/11 Delete RC106 1.8K_0402_1% 9 10 0.1U_0402_10V6K CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 09/23 Change netname to PWR_GD Place near JXDP1 [8] CFG0 11 12 CFG8 [8] UC1 CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 [8] CFG1 13 14 CFG9 [8] 2 15 15 GND4 GND5 16 B CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 [30,31,47] PWR_GD 4 [8] CFG2 17 18 CFG10 [8] 2 P O PM_DRAM_PWRGD_CPU CFG3 19 OBSDATA_A3 OBSDATA_C3 20CFG11 D A [8] CFG3 GND6 GND7 CFG11 [8] D [14] PM_DRAM_PWRGD 21 22 XDP_OBS0 OBSFN_B0 OBSFN_D0 CFG19 1 2 G 23 24 OBSFN_B1 OBSFN_D1 CFG19 [8] 74AHC1G09GW_TSSOP5 1 XDP_OBS1 25 26CFG18 +3VS GND8 GND9 CFG18 [8] RC9 100K_0402_1% 3 Part Number = SA00003Y000 RC10 27 28 3.3K_0402_1% CFG4 29 OBSDATA_B0 OBSDATA_D0 30CFG12 [8] CFG4 CFG12 [8] CFG5 31 OBSDATA_B1 OBSDATA_D1 32CFG13 [8] CFG5 33 GND10 GND11 34 CFG13 [8] OBSDATA_B2 OBSDATA_D2

2 CFG6 35 36CFG14 OBSDATA_B3 OBSDATA_D3 [8] CFG6 CFG7 37 38CFG15 CFG14 [8] RC5 need to close to1 JCPU1[8] 2 CFG7 39 GND12 GND13 40 CFG15 [8] 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42 H_CPUPWRGD RC13 1K_0402_1% H_CPUPWRGD_XDP HOOK1 ITPCLK#/HOOK5 07/30 Non Install QC1 43 44 [14,30] ON/OFFBTN# 45 VCC_OBS_AB VCC_OBS_CD 46 2 1 10/18 Delete QC1 and RC12 09/23 Change netname to VGATE HOOK2 RESET#/HOOK6 09/26 Change netname1 to 2PM_PWROK. Add RC107 47 XDP_RST#_R48 PLT_RST# [9] CPU_PWR_DEBUG HOOK3 DBR#/HOOK7 PLT_RST# [13,14,25,28,29,30,35,37,39] RC107 0_0402_5% 49 XDP_DBRESET#50 RC16 1K_0402_1% [14,30] PM_PWROK 51 GND14 GND15 52 SDA TD0 53 XDP_TDO54 [11,12,13,16,28,38] DDR_XDP_WAN_SMBDAT 55 SCL TRST# 56 XDP_TRST# 57 TCK1 TDI 58 [11,12,13,16,28,38] DDR_XDP_WAN_SMBCLK XDP_TDI 59 TCK0 TMS 60 2 1 XDP_TCLK GND16 GND17 XDP_TMS CFG3 RC105 1K_0402_1% SAMTE_BSH-030-01-L-D-A CONN@ KBC_PROC_HOT_R [24,47] KBC_PROC_HOT_R +VCCIO_OUT 07/25 Delete RC24

1 2 1 2 Haswell rPGA EDS AP32JCPU1B AP3 @ SKTOCC SM_RCOMP_0 AR3 RC22 0_0402_5% MISC RC23 62_0402_5% PAD T120@ CPU_DETECT# AN32 SM_RCOMP_1 SM_RCOMP0AP2 CATERR SM_RCOMP_2 AR27 THERMAL SM_RCOMP1AN3 BSS138W-7-F_SOT323-3 3 1 PECI SM_DRAMRST #4/9 change by HP requirement PAD T118@ H_CATERR# AK31 SM_RCOMP2 QC2

FC_AK31 DDR3DDR3 D 09/11 Delete1 RC27 and2 connect CPU.AM35H_PECI pin to PCH_THERMTRIP#_RAM30 DDR3_DRAMRST#_CPUAR29 DDR3_DRAMRST#_CPU [30] H_PECI PROCHOT PRDY CPU_DRAM_RST# [11] #4/9 change by PAD T1 @ AM35 AT29 G THERMTRIP PREQ AM34 4.99K_0402_1% KBC_PROC_HOTHP requirementRC26 56_0402_5% KBC_PROC_HOT_R TCK XDP_PRDY# S PCH_THERMTRIP#_R XDP_PREQ#AN33 [18,24,35] PCH_THERMTRIP#_R TMS S D C 2N7002KW_SOT323-32 Q59 XDP_TCLKAM33 C TRST RC28 AT28 XDP_TMSAM31 2 AL34 PM_SYNC TDI AL33 1 XDP_TRST# 1 [24,30] KBC_PROC_HOT# 09/11 Connect CPU.AT26 pin to CPU_PLTRST# AC10 PWRGOOD PWR TDO AP33 1 2 G [14] H_PM_SYNC H_PM_SYNC SM_DRAMPWROK JTAG JTAG DBR XDP_TDI H_CPUPWRGD AT26 XDP_TDO [18] H_CPUPWRGD PLTRSTIN AR30 PM_DRAM_PWRGD_CPU XDP_DBRESET# RC25 3.3K_0402_5%D BPM_N_0 AN31 XDP_DBRESET# [14] DDR_RST_EN [16] 3 CPU_PLTRST# [18] CPU_PLTRST# G28 BPM_N_1 AN29 XDP_OBS0 2 H28 DPLL_REF_CLKN BPM_N_2 AP31 G DPLL_REF_CLKP BPM_N_3 XDP_OBS1 S 10/12 Reserve RC108

F27 CLOCK AP30 XDP_OBS2_R 10/18 Uninstall QC3 10/18 Change RC108 to 10k ohms, and install RC108 [15] CLK_CPU_DPLL# E27 SSC_DPLL_REF_CLKN BPM_N_4 AN28 T144@ PAD 2

SSC_DPLL_REF_CLKP BPM_N_5 XDP_OBS3_R 1 [15] CLK_CPU_DPLL D26 AP29 T145@ PAD RC108 BCLKN BPM_N_6 [15] CLK_CPU_SSC_DPLL# E26 XDP_OBS4_RAP28 09/11 T146Noninstall@ PAD RC36, RC38, RC40, RC43, RC45, RC47 @ 10K_0402_1% BCLKP BPM_N_7

XDP_OBS5_R 1 [15] CLK_CPU_SSC_DPLL 11/07 T147Delete@ PADRC36, RC38, RC40, RC43, RC45, RC47 by [30,45] KBC_DS3_EN QC3 ESD request. Add T144, T145, T146, T147, T148, T149 [15] CLK_CPU_DMI# XDP_OBS6_R T148@ PAD 2N7002_SOT23 XDP_OBS7_R [15] CLK_CPU_DMI T149@ PAD

For ESD concern, please put near CPU 2 3 INTEL_HASWELL_HASWELL 2 OF 9

09/11 Change RC55.1 connection to H_CPUPWRGD PU/PD for JTAG signals

2 1 +3VS

XDP_DBRESET# RC52 1K_0402_1%

+1.05VS H_CPUPWRGD

2 1 B 09/11 Delete RC66 RC55 B 1 10K_0402_1% DDR3 COMPENSATION1 2SIGNALS XDP_TDO RC57 51_0402_1%2 1 1 2 2 1 2 CAD Note: SM_RCOMP0 RC591 100_0402_1%2 XDP_TCLK RC60 51_0402_1% Avoid stub in the PWRGD path SM_RCOMP1 RC61 75_0402_1% XDP_TRST# RC62 51_0402_1% while placing resistors RC25 & RC130 SM_RCOMP2 RC65 100_0402_1% CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil

A A

Compal Electronics, Inc.

Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title Security Classification Size Document Number Rev Compal Secret Data Custom 0.5 5 4 3 2 Date: Thursday, December 20, 20121 Sheet 5of 56 www.vinafix.vn PM,XDP,CLK LA-9241P

D D

Haswell rPGA EDS JCPU1C Haswell rPGA EDS JCPU1D [11] DDR_A_D[0..63] AR15 AC7 [12] DDR_B_D[0..63] SA_DQ_0 RSVD DDR_A_D0 AT14 U4 M_CLK_A_DDR#0 AR18 AG8 @ T3 PAD~D SA_DQ_1 SA_CK_N_0 M_CLK_A_DDR#0 [11] SB_DQ_0 RSVD DDR_A_D1 AM14 V4 M_CLK_A_DDR0 DDR_B_D0 AT18 Y4M_CLK_B_DDR#0 SA_DQ_2 SA_CK_P_0 M_CLK_A_DDR0 [11] SB_DQ_1 SB_CKN0 M_CLK_B_DDR#0 [12] DDR_A_D2 AN14 AD9 DDR_B_D1 AM17 AA4M_CLK_B_DDR0 SA_DQ_3 SA_CKE_0 DDR_CKE0_DIMMA [11] SB_DQ_2 SB_CK0 M_CLK_B_DDR0 [12] DDR_A_D3 AT15 U3DDR_CKE0_DIMMAM_CLK_A_DDR#1 DDR_B_D2 AM18 AF10 SA_DQ_4 SA_CK_N_1 M_CLK_A_DDR#1 [11] SB_DQ_3 SB_CKE_0 DDR_CKE0_DIMMB [12] DDR_A_D4 AR14 V3 M_CLK_A_DDR1 DDR_B_D3 AR17 DDR_CKE0_DIMMBY3M_CLK_B_DDR#1 SA_DQ_5 SA_CK_P_1 M_CLK_A_DDR1 [11] SB_DQ_4 SB_CKN1 M_CLK_B_DDR#1 [12] DDR_A_D5 AN15 AC9 DDR_B_D4 AT17 AA3M_CLK_B_DDR1 SA_DQ_6 SA_CKE_1 DDR_CKE1_DIMMA [11] SB_DQ_5 SB_CK1 M_CLK_B_DDR1 [12] DDR_A_D6 AM15 U2DDR_CKE1_DIMMAM_CLK_A_DDR#2 DDR_B_D5 AN17 AG10 SA_DQ_7 SA_CK_N_2 M_CLK_A_DDR#2 [11] SB_DQ_6 SB_CKE_1 DDR_CKE1_DIMMB [12] DDR_A_D7 AM9 V2 M_CLK_A_DDR2 DDR_B_D6 AN18 DDR_CKE1_DIMMBY2M_CLK_B_DDR#2 SA_DQ_8 SA_CK_P_2 M_CLK_A_DDR2 [11] SB_DQ_7 SB_CKN2 M_CLK_B_DDR#2 [12] DDR_A_D8 AN9 AD8 DDR_CKE2_DIMMA DDR_B_D7 AT12 AA2M_CLK_B_DDR2 SA_DQ_9 SA_CKE_2 DDR_CKE2_DIMMA [11] SB_DQ_8 SB_CK2 M_CLK_B_DDR2 [12] DDR_A_D9 AM8 U1 M_CLK_A_DDR#3 DDR_B_D8 AR12 AG9DDR_CKE2_DIMMB SA_DQ_10 SA_CK_N_3 M_CLK_A_DDR#3 [11] SB_DQ_9 SB_CKE_2 DDR_CKE2_DIMMB [12] DDR_A_D10 AN8 V1 M_CLK_A_DDR3 DDR_B_D9 AN12 Y1M_CLK_B_DDR#3 SA_DQ_11 SA_CK_P_3 M_CLK_A_DDR3 [11] SB_DQ_10 SB_CKN3 M_CLK_B_DDR#3 [12] DDR_A_D11 AR9 AC8 DDR_CKE3_DIMMA DDR_B_D10 AM11 AA1M_CLK_B_DDR3 AT9 SA_DQ_12 SA_CKE_3 DDR_CKE3_DIMMA [11] AT11 SB_DQ_11 SB_CK3 AF9 M_CLK_B_DDR3 [12] DDR_A_D12 SA_DQ_13 DDR_B_D11 SB_DQ_12 SB_CKE_3 DDR_CKE3_DIMMB DDR_A_D13 AR8 M7 DDR_B_D12 AR11 DDR_CKE3_DIMMB [12] SA_DQ_14 SA_CS_N_0 DDR_CS0_DIMMA# [11] SB_DQ_13 DDR_A_D14 AT8 L9DDR_CS0_DIMMA# DDR_B_D13 AM12 P4 AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS1_DIMMA# [11] AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS0_DIMMB# [12] DDR_A_D15 DDR_CS1_DIMMA#DDR_CS2_DIMMA# DDR_B_D14 DDR_CS0_DIMMB# AK9 SA_DQ_16 SA_CS_N_2 M10 DDR_CS2_DIMMA# [11] AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS1_DIMMB# [12] DDR_A_D16 DDR_CS3_DIMMA# DDR_B_D15 DDR_CS1_DIMMB#DDR_CS2_DIMMB# AJ6 SA_DQ_17 SA_CS_N_3 M8 DDR_CS3_DIMMA# [11] AR6 SB_DQ_16 SB_CS_N_2 P1 DDR_CS2_DIMMB# [12] DDR_A_D17 DDR_B_D16 DDR_CS3_DIMMB# AK6 SA_DQ_18 SA_ODT_0 L7 M_A_ODT0 [11] AM5 SB_DQ_17 SB_CS_N_3 DDR_CS3_DIMMB# [12] DDR_A_D18 M_A_ODT0 DDR_B_D17 AJ10 SA_DQ_19 SA_ODT_1 L8 M_A_ODT1 [11] AM6 SB_DQ_18 R4 M_A_ODT2 DDR_A_D19 AK10 SA_DQ_20 SA_ODT_2 L10M_A_ODT1 M_A_ODT2 [11] DDR_B_D18 AT5 SB_DQ_19 SB_ODT_0 R3 M_B_ODT0 [12] M_A_ODT3 DDR_A_D20 AJ7 SA_DQ_21 SA_ODT_3 V5 M_A_ODT3 [11] DDR_B_D19 AT6 SB_DQ_20 SB_ODT_1M_B_ODT0R1 M_B_ODT1 [12] M_B_ODT2 DDR_A_D21 AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS0 [11] DDR_B_D20 AN5 SB_DQ_21 SB_ODT_2M_B_ODT1P2 M_B_ODT2 [12] M_B_ODT3 DDR_A_D22 AF4 SA_DQ_23 SA_BS_1 AD1DDR_A_BS0 DDR_A_BS1 [11] DDR_B_D21 AN6 SB_DQ_22 SB_ODT_3 R7 M_B_ODT3 [12] DDR_A_D23 SA_DQ_24 SA_BS_2 DDR_A_BS1 DDR_B_D22 SB_DQ_23 SB_BS_0 DDR_B_BS0 C AF5 DDR_A_BS2 [11] AJ4 P8 DDR_B_BS0 [12] C DDR_A_D24 AF1 SA_DQ_25 V10DDR_A_BS2 DDR_B_D23 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS1 [12] DDR_A_D25 AF2 SA_DQ_26 VSS U6 DDR_B_D24 AJ1 SB_DQ_25 SB_BS_2DDR_B_BS1 DDR_B_BS2 [12] DDR_A_D26 AG4 SA_DQ_27 SA_RAS U7 DDR_A_RAS# [11] DDR_B_D25 AJ2 SB_DQ_26 DDR_B_BS2R10 DDR_A_D27 AG5 SA_DQ_28 SA_WE U8DDR_A_RAS# DDR_A_WE# [11] DDR_B_D26 AM1 SB_DQ_27 VSS R6 DDR_B_RAS# DDR_A_D28 AG1 SA_DQ_29 SA_CAS DDR_A_WE# DDR_A_CAS# [11] DDR_B_D27 AN1 SB_DQ_28 SB_RAS P6 DDR_B_RAS# [12] SA_DQ_30 SB_DQ_29 SB_WE DDR_B_WE# DDR_A_D29 AG2 V8DDR_A_CAS# DDR_A_MA[0..15] [11] DDR_B_D28 AK2 P7 DDR_B_WE# [12] DDR_A_D30 J1 SA_DQ_31 SA_MA_0 AC6 DDR_B_D29 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# [12] DDR_A_D31 J2 SA_DQ_32 SA_MA_1 V9DDR_A_MA0 DDR_B_D30 L2 SB_DQ_31 DDR_B_CAS#R8 DDR_B_MA[0..15] [12] DDR_A_D32 J5 SA_DQ_33 SA_MA_2 U9DDR_A_MA1 DDR_B_D31 M2 SB_DQ_32 SB_MA_0 Y5DDR_B_MA0 DDR_A_D33 H5 SA_DQ_34 SA_MA_3 AC5DDR_A_MA2 DDR_B_D32 L4 SB_DQ_33 SB_MA_1 Y10DDR_B_MA1 DDR_A_D34 H2 SA_DQ_35 SA_MA_4 AC4DDR_A_MA3 DDR_B_D33 M4 SB_DQ_34 SB_MA_2 AA5DDR_B_MA2 DDR_A_D35 H1 SA_DQ_36 SA_MA_5 AD6DDR_A_MA4 DDR_B_D34 L1 SB_DQ_35 SB_MA_3 Y7DDR_B_MA3 SA_DQ_37 SA_MA_6 SB_DQ_36 SB_MA_4 DDR_B_MA4 DDR_A_D36 J4 AC3DDR_A_MA5 DDR_B_D35 M1 AA6 SA_DQ_38 SA_MA_7 SB_DQ_37 SB_MA_5 DDR_B_MA5 DDR_A_D37 H4 AD5DDR_A_MA6 DDR_B_D36 L5 Y6 SA_DQ_39 SA_MA_8 SB_DQ_38 SB_MA_6 DDR_B_MA6 DDR_A_D38 F2 AC2DDR_A_MA7 DDR_B_D37 M5 AA7 SA_DQ_40 SA_MA_9 SB_DQ_39 SB_MA_7 DDR_B_MA7 DDR_A_D39 F1 V6DDR_A_MA8 DDR_B_D38 G7 Y8 SA_DQ_41 SA_MA_10 SB_DQ_40 SB_MA_8 DDR_B_MA8 DDR_A_D40 D2 AC1DDR_A_MA9 DDR_B_D39 J8 AA10 SA_DQ_42 SA_MA_11 SB_DQ_41 SB_MA_9 DDR_B_MA9 DDR_A_D41 D3 AD4DDR_A_MA10 DDR_B_D40 G8 R9 D1 SA_DQ_43 SA_MA_12 V7 G9 SB_DQ_42 SB_MA_10 Y9DDR_B_MA10 DDR_A_D42 SA_DQ_44 SA_MA_13 DDR_A_MA11 DDR_B_D41 SB_DQ_43 SB_MA_11 DDR_B_MA11 DDR_A_D43 F3 AD3DDR_A_MA12 DDR_B_D42 J7 AF7 C3 SA_DQ_45 SA_MA_14 AD2 J9 SB_DQ_44 SB_MA_12 P9DDR_B_MA12 DDR_A_D44 SA_DQ_46 SA_MA_15 DDR_A_MA13 DDR_B_D43 SB_DQ_45 SB_MA_13 DDR_B_MA13 DDR_A_D45 B3 DDR_A_MA14 DDR_B_D44 G10 AA8 B5 SA_DQ_47 J10 SB_DQ_46 SB_MA_14 AG7DDR_B_MA14 DDR_A_D46 DDR_A_MA15 DDR_B_D45 E6 SA_DQ_48 AP15 A8 SB_DQ_47 SB_MA_15 DDR_B_MA15 DDR_A_D47 DDR_A_DQS#[0..7] [11] DDR_B_D46 A5 SA_DQ_49 SA_DQS_N_0 AP8 B8 SB_DQ_48 DDR_A_D48 DDR_B_D47 D6 SA_DQ_50 SA_DQS_N_1 AJ8 A9 SB_DQ_49 AP18 DDR_A_D49 DDR_A_DQS#0 DDR_B_D48 DDR_B_DQS#[0..7] [12] D5 SA_DQ_51 SA_DQS_N_2 AF3 B9 SB_DQ_50 SB_DQS_N_0 AP11DDR_B_DQS#0 DDR_A_D50 E5 SA_DQ_52 SA_DQS_N_3 J3DDR_A_DQS#1 DDR_B_D49 D8 SB_DQ_51 SB_DQS_N_1 AP5DDR_B_DQS#1 DDR_A_D51 B6 SA_DQ_53 SA_DQS_N_4 E2DDR_A_DQS#2 DDR_B_D50 E8 SB_DQ_52 SB_DQS_N_2 AJ3DDR_B_DQS#2 DDR_A_D52 A6 SA_DQ_54 SA_DQS_N_5 C5DDR_A_DQS#3 DDR_B_D51 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#3 DDR_A_D53 E12 SA_DQ_55 SA_DQS_N_6 C11DDR_A_DQS#4 DDR_B_D52 E9 SB_DQ_54 SB_DQS_N_4 H9DDR_B_DQS#4 DDR_A_D54 SA_DQ_56 SA_DQS_N_7 DDR_A_DQS#5 DDR_B_D53 SB_DQ_55 SB_DQS_N_5 DDR_B_DQS#5 D12 AP14 DDR_A_DQS[0..7] [11] E15 C8 DDR_A_D55 B11 SA_DQ_57 SA_DQS_P_0 AP9DDR_A_DQS#6 DDR_B_D54 D15 SB_DQ_56 SB_DQS_N_6 C14DDR_B_DQS#6 DDR_A_D56 SA_DQ_58 SA_DQS_P_1 DDR_A_DQS#7 DDR_B_D55 SB_DQ_57 SB_DQS_N_7 DDR_B_DQS#7 A11 AK8 A15 AP17 DDR_B_DQS[0..7] [12] B DDR_A_D57 SA_DQ_59 SA_DQS_P_2 DDR_A_DQS0 DDR_B_D56 SB_DQ_58 SB_DQS_P_0 B 07/10 Change by HP request E11 AG3 B15 AP12 DDR_A_D58 D11 SA_DQ_60 SA_DQS_P_3 H3DDR_A_DQS1 DDR_B_D57 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_A_D59 B12 SA_DQ_61 SA_DQS_P_4 E3DDR_A_DQS2 DDR_B_D58 D14 SB_DQ_60 SB_DQS_P_2DDR_B_DQS0AK3 DDR_A_D60 A12 SA_DQ_62 SA_DQS_P_5 C6DDR_A_DQS3 DDR_B_D59 A14 SB_DQ_61 SB_DQS_P_3DDR_B_DQS1M3 DDR_A_D61 AM3 SA_DQ_63 SA_DQS_P_6 C12DDR_A_DQS4 DDR_B_D60 B14 SB_DQ_62 SB_DQS_P_4DDR_B_DQS2H8 SM_VREF SA_DQS_P_7 SB_DQ_63 SB_DQS_P_5 +SM_VREF_CA DDR_A_D62 F16 DDR_A_DQS5 DDR_B_D61 DDR_B_DQS3C9 DDR_A_D63 F13 SA_DIMM_VREFDQ DDR_A_DQS6 DDR_B_D62 SB_DQS_P_6DDR_B_DQS4C15 +DIMM01_VREF_DQ SB_DIMM_VREFDQ SB_DQS_P_7 +DIMM23_VREF_DQ DDR_A_DQS7 DDR_B_D63 DDR_B_DQS5 DDR_B_DQS6

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS7 CC84 CC85 CC86 INTEL_HASWELL_HASWELL 4 OF 9 07/10 Delete by HP request 1 1 1 INTEL_HASWELL_HASWELL 3 OF 9

08/03 Add CC84, CC85, CC86 2 2 2

A A

Compal Electronics, Inc.

Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

Compal Secret Data Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 6of 56 5 4 www.vinafix.vn3 2 1 DDRIII LA-9241P

D D

COMPENSATION PU FOR eDP

+VCCIOA_OUT

EDP_COMP 2 1 24.9_0402_1% RC77 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils.

JCPU1HHaswell rPGA EDS

T28 M27 EDP_CPU_C_AUX# C1261 2 0.1U_0402_25V6 EDP_CPU_AUX# [36] U28 DDIB_TXBN_0 EDP_AUXN N27 EDP_CPU_C_AUX C1271 2 0.1U_0402_25V6 T30 DDIB_TXBP_0 EDP_AUXP P27 EDP_HPD EDP_CPU_AUX [36] DDIB_TXBN_1 EDP_HPD C U30 eDP E24 EDP_COMP C U29 DDIB_TXBP_1 EDP_RCOMP R27 T119@ PAD V29 DDIB_TXBN_2 EDP_DISP_UT IL U31 DDIB_TXBP_2 V31 DDIB_TXBN_3 DDIB_TXBP_3 P35 EDP_CPU_C_LANE_N0 C1281 2 0.1U_0402_25V6 EDP_CPU_LANE_N0 [36] T34 EDP_TXN_0 R35 EDP_CPU_C_LANE_P0 C1291 2 0.1U_0402_25V6 EDP_CPU_LANE_P0 [36] U34 DDIC_TXCN_0 EDP_TXP_0 N34 EDP_CPU_C_LANE_N1 C1301 2 0.1U_0402_25V6 EDP_CPU_LANE_N1 [36] U35 DDIC_TXCP_0 EDP_TXN_1 P34 EDP_CPU_C_LANE_P1 C1311 2 0.1U_0402_25V6 V35 DDIC_TXCN_1 EDP_TXP_1 P33 FDI_CTX_PRX_N0 EDP_CPU_LANE_P1 [36] U32 DDIC_TXCP_1 FDI_TXN_0 R33 FDI_CTX_PRX_P0 FDI_CTX_PRX_N0 [14] FDI_CTX_PRX_P0 [14] T32 DDIC_TXCN_2 FDI_TXP_0 N32 FDI_CTX_PRX_N1 FDI_CTX_PRX_N1 [14] U33 DDIC_TXCP_2 FDI_TXN_1 P32 FDI_CTX_PRX_P1 V33 DDIC_TXCN_3 FDI_TXP_1 FDI_CTX_PRX_P1 [14] DDIC_TXCP_3 P29 R29 DDID_TXDN_0 N28 DDID_TXDP_0 P28 DDID_TXDN_1 DDI P31 DDID_TXDP_1 R31 DDID_TXDN_2 N30 DDID_TXDP_2 P30 DDID_TXDN_3 DDID_TXDP_3 08/07 Change RC78 to 10K

INTEL_HASWELL_HASWELL 8 OF 9 +VCCIO_OUT

D 1 HPD INVERSION FOR EDP 10K_0402_5% G RC78 S B B 2

EDP_HPD 1 2 [36] CPU_EDP_HPD# QH1 BSS138W-7-F_SOT323-3 100K_0402_5%

3 SB000002X00 1 RC79 2

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 7of 56 5 4 3 2 1 www.vinafix.vn CPU-FDI,eDP,DDI LA-9241P

CFG2 1K_0402_1% 1 @ RC80

D D 2

PEG Static Lane Reversal - CFG2 is for the 16x 1:(Default) Normal Operation; Lane # CFG2 definition matches socket pin map definition 0:Lane Reversed

Haswell rPGA EDS JCPU1I

CFG4 AT1 1K_0402_1% AT2 RSVD_TP C23 AD10 RSVD_TP RSVD_TP B23 1 RC81 RSVD RSVD_TP D24 A34 RSVD_TP D23 A35 RSVD_TP RSVD_TP RSVD_TP @T15 PAD~D W29 2 @T12 PAD~D W28 RSVD_TP AT31 CFG_RCOMP G26 RSVD_TP CFG_RCOMP AR21 H_CPU_RSVD CFG16 CFG16 [5] W33 TESTLO_G26 CFG_16 AR23 CFG18 CFG18 [5] AL30 VSS CFG_18 AP21 CFG17 @T16 PAD~D CFG17 [5] AL29 RSVD CFG_17 AP23 CFG19 @T17 PAD~D CFG19 [5] C F25 RSVD CFG_19 Display Port Presence Strap C +VCC_CORE VCC C35 AR33 B35 RSVD_TP RSVD G6 1 : Disabled; No Physical Display Port RSVD_TP FC_G6 AM27 AL25 RSVD AM26 CFG4 attached to Embedded Display Port RSVD_TP RSVD F5 @T26 PAD~D W30 RSVD AM2 0 : Enabled; An external Display Port device is @T28 PAD~D W31 RSVD_TP RSVD K6 H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port TESTLO E18 AT20 RSVD [5] CFG0 CFG0 AR20 CFG_0 U10 [5] CFG1 CFG1 CFG6 CFG2 AP20 CFG_1 RSVD P10 [5] CFG2 CFG3 AP22 CFG_2 RSVD CFG5 [5] CFG3 1K_0402_1% CFG4 AT22 CFG_3 B1 1K_0402_1%

[5] CFG4 1 1 CFG5 AN22 CFG_4 NC A2 @ [5] CFG5 @ CFG6 AT25 CFG_5 RSVD AR1 [5] CFG6 RC82 RC83 CFG7 AN23 CFG_6 RSVD_TP [5] CFG7 CFG8 AR24 CFG_7 E21 [5] CFG8 CFG9 AT23 CFG_8 RSVD_TP E20

[5] CFG9 2 2 CFG10 AN20 CFG_9 RSVD_TP 07/10 Delete RC106 and RC107 [5] CFG10 CFG11 AP24 CFG_10 AP27 [5] CFG11 CFG12 AP26 CFG_11 VSS AR26 [5] CFG12 CFG13 AN25 CFG_12 VSS [5] CFG13 CFG14 AN26 CFG_13 AL31 [5] CFG14 CFG15 AP25 CFG_14 VSS AL32 [5] CFG15 CFG_15 VSS PCIE Port Bifurcation Straps 9 OF 9 2 1 H_CPU_TESTLO 11: (Default) x16 - Device 1 functions 1 and 2 disabled INTEL_HASWELL_HASWELL RC84 49.9_0402_1% B 2 1 CFG_RCOMP 10: x8, x8 - Device 1 function 1 enabled ; function 2 B RC85 49.9_0402_1% 2 1 H_CPU_RSVD CFG[6:5] disabled RC86 49.9_0402_1% 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7 CFG9 1K_0402_1%

09/21 Reserve CFG9 PD RC106 1 1K_0402_1% @ 1 @ RC87 RC106 2 2

PEG DEFER TRAINING 1: (Default) PEG Train immediately CFG7 following xxRESETB de assertion 0: PEG Wait for BIOS for training

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 8of 56 5 4 3 2 1 www.vinafix.vn CPU-RSVD,CFG LA-9241P

+1.35VS Source J4 +1.35V 1 2 1 2 JUMP_43X79 B+ SI7326DN-T1-E3_PAK1212-8 +1.35VS Haswell rPGA EDS +VCC_CORE QC4 @ JCPU1E 1 2 AA26

1 5 3 VCC AA28

2 K27 VCC AA34 RSVD VCC RC88 R6 20K_0402_5% RC89 L27 AA30

1 RSVD VCC 100K_0402_5% @ 470_0603_5% T27 AA32 4 V27 RSVD VCC AB26

2 RSVD VCC D @ AB29 D

1 VCC +1.35VS AB25 RUN_ON_CPU1.5VS3 VCC 6 AB27

2 VCC 3 AB28 @ QC5B VCC 1 1 2N7002DWH_SOT363-6 CC382 1 0.1U_0402_10V6K AB11 AB30 2 2N7002DWH_SOT363-6 AB2 VDDQ VCC AB31 [34,49] SLP_S3 VDDQ VCC QC5A @ @ @ 5 SLP_S3 CC402 1 0.1U_0402_10V6K AB5 AB33 11/06 Change QC5A.2 and QC5B.5 connection to SLP_S3 AB8 VDDQ VCC AB34 RC92 CC39 VDDQ VCC 1 2 AE11 AB32 330K_0402_5% 0.1U_0402_25V6 VDDQ VCC 2 4 AE2 AC26 AE5 VDDQ VCC AB35 09/11 Delete RC93 and connect SLP_S3# to QC5.5 AE8 VDDQ VCC AC28 AH11 VDDQ VCC AD25 K11 VDDQ VCC AC30 VDDQ VCC 10/18 Delete Q80, R461, Q2, RC90. Modify +1.35VS power circuit N11 AD28 12/12RUN_ON_CPU1.5VS3 Uninstall QC4,RC92,CC39,RC89,QC5 [11,12] and RC88. Add J4. N8 VDDQ VCC AC32 12/13 Install RC88 T11 VDDQ VCC AD31 T2 VDDQ VCC AC34 T5 VDDQ VCC AD34 T8 VDDQ VCC AD26 W11 VDDQ VCC AD27 W2 VDDQ VCC AD29 VDDQ VCC 10/16 Add Q80 W5 AD30 W8 VDDQ VCC AD32 VDDQ VCC AD33 N26 VCC AD35 K26 RSVD VCC AE26 +VCC_CORE AL27 VCC VCC AE32 09/11 ChangeAK27 netnameRSVD to VCCSENSE VCC AE28 RSVD VCC AE30 VCC AG28 VCC AG34 VCC AE34 VCC AF25 VCC AF26 AL35 VCC AF27 C VCCSENSE C E17 VCC_SENSE VCC AF28 AN35 RSVD VCC AF29 VCCIO_OUT VCC 07/25 Delete RC96 +VCCIO_OUT A23 AF30 @ T54 PAD~D F22 FC_A23 VCC AF31 +VCCIOA_OUT W32 VCOMP_OUT VCC AF32 AL16 RSVD VCC AF33 J27 RSVD # 04/02 change Pin name VCC AF34 AL13 RSVD by Intel update VCC AF35 RSVD VCC AG26 VCC AH26 AM28 VCC AH29 [47] VR_SVID_ALRT# VR_SVID_ALRT# AM29 VIDALERT VCC AG30 [47] VR_SVID_CLK VR_SVID_CLK AL28 VIDSCLK VCC AG32 VR_SVID_DAT VIDSOUT VCC +1.05VS [47] VR_SVID_DAT AH32 AP35 VCC AH35 150_0402_1% H27 VSS VCC AH25 AP34 PWR_DEBUG VCC AH27 RC98 [5] CPU_PWR_DEBUG AT35 VSS VCC AH28

1 AR35 RSVD_TP VCC AH30 @ T50 PAD~D AR32 RSVD_TP VCC AH31 @ T51 PAD~D AL26 RSVD_TP VCC AH33 @ T52 PAD~D AT34 RSVD_TP VCC AH34 @ T53 PAD~D AL22 VSS VCC AJ25

2 AT33 VSS VCC AJ26 AM21 VSS VCC AJ27 CPU_PWR_DEBUG AM25 VSS VCC AJ28 AM22 VSS VCC AJ29 VSS# 04/02 change Pin name VCC AM20 by Intel update AJ30 AM24 VSS VCC AJ31 AL19 VSS VCC AJ32 AM23 VSS VCC AJ33 +VCC_CORE VSS VCC 100_0402_1% AT32 AJ34 VSS VCC AJ35 VCC VCC_SENSE RC101 G25 B VCC H25 B VCC

1 J25 VCC K25 VCC L25 ++VCC_CORE+ VCC M25 CAD Note: RC101 SHOULD BE PLACED CLOSE TO CPU Y25 VCC N25 +1.35VS VCC VCC 2 Y26 P25 09/11 Delete RC102 and RC103 VDDQ DECOUPLING Y27 VCC VCC R25 VCC VCC 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M [47] VCCSENSE VCCSENSE 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M Y28 T25 Y29 VCC VCC VCC 1 1 Y30 U25 330U_D2_2V_Y 330U_D2_2V_Y CC47 CC48 CC49 CC50 CC51 CC42 CC43 CC44 CC45 CC46 Y31 VCC VCC U26 CAD Note: RC104 SHOULD BE PLACED CLOSE TO CPU 1 1 1 1 1 1 1 1 1 1 VCC VCC CC41 CC87 08/06Y32 Reserve CC87 V25 @ Y33 VCC VCC V26

100_0402_1% VCC VCC [10,47] VSSSENSE VSSSENSE Y34 2 2 2 2 2 2 2 2 2 2 2 2 Y35 VCC W26

RC104 VCC VCC W27 VCC 1

INTEL_HASWELL_HASWELL 5 OF 9 2 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M CH6 CH7 CH8 CH9 CH10 CH11 CH1 CH2 CH3 CH4 CH5

1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2

A A

Compal Electronics, Inc.

Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

Compal Secret Data Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 9of 56 5 4 www.vinafix.vn3 2 1 CPU- PWR LA-9241P

HaswellJCPU1F rPGA EDS Haswell rPGAJCPU1G EDS D D A10 AK34 B34 K10 A13 VSS VSS AK5 B4 VSS VSS K2 A16 VSS VSS AL1 B7 VSS VSS K29 A19 VSS VSS AL10 C1 VSS VSS K3 A22 VSS VSS AL11 C10 VSS VSS K31 A25 VSS VSS AL12 C13 VSS VSS K33 A27 VSS VSS AL14 C16 VSS VSS K35 A29 VSS VSS AL15 C19 VSS VSS K4 A3 VSS VSS AL17 C2 VSS VSS K5 A31 VSS VSS AL18 C22 VSS VSS K7 A33 VSS VSS AL2 C24 VSS VSS K8 A4 VSS VSS AL20 C26 VSS VSS K9 A7 VSS VSS AL21 C28 VSS VSS L11 AA11 VSS VSS AL23 C30 VSS VSS L26 AA25 VSS VSS E22 C32 VSS VSS L6 AA27 VSS VSS AL3 C34 VSS VSS M11 AA31 VSS VSS AL4 C4 VSS VSS M26 AA29 VSS VSS AL5 C7 VSS VSS M28 AB1 VSS VSS AL6 D10 VSS VSS M30 AB10 VSS VSS AL7 D13 VSS VSS M32 AA33 VSS VSS AL8 D16 VSS VSS M34 AA35 VSS VSS AL9 D19 VSS VSS M6 AB3 VSS VSS AM10 D22 VSS VSS N1 AC25 VSS VSS AM13 D25 VSS VSS N10 AC27 VSS VSS AM16 D27 VSS VSS N2 AB4 VSS VSS AM19 D29 VSS VSS N29 AB6 VSS VSS E25 D31 VSS VSS N3 AB7 VSS VSS AM32 D33 VSS VSS N31 AB9 VSS VSS AM4 D35 VSS VSS N33 AC11 VSS VSS AM7 D4 VSS VSS N35 AD11 VSS VSS AN10 D7 VSS VSS N4 C AC29 VSS VSS AN13 E1 VSS VSS N5 C AC31 VSS VSS AN16 E10 VSS VSS N6 AC33 VSS VSS AN19 E13 VSS VSS N7 AC35 VSS VSS AN2 E16 VSS VSS N9 AD7 VSS VSS AN21 E4 VSS VSS P11 AE1 VSS VSS AN24 E7 VSS VSS P26 AE10 VSS VSS AN27 F10 VSS VSS P5 AE25 VSS VSS AN30 F11 VSS VSS R11 AE29 VSS VSS AN34 F12 VSS VSS R26 AE3 VSS VSS AN4 F14 VSS VSS R28 AE27 VSS VSS AN7 F15 VSS VSS R30 AE35 VSS VSS AP1 F17 VSS VSS R32 AE4 VSS VSS AP10 F18 VSS VSS R34 AE6 VSS VSS AP13 F20 VSS VSS R5 AE7 VSS VSS AP16 F21 VSS VSS T1 AE9 VSS VSS AP19 F23 VSS VSS T10 AF11 VSS VSS AP4 F24 VSS VSS T29 AF6 VSS VSS AP7 F26 VSS VSS T3 AF8 VSS VSS W25 F28 VSS VSS T31 AG11 VSS VSS AR10 F30 VSS VSS T33 AG25 VSS VSS AR13 F32 VSS VSS T35 AE31 VSS VSS AR16 F34 VSS VSS T4 AG31 VSS VSS AR19 F4 VSS VSS T6 AE33 VSS VSS AR2 F6 VSS VSS T7 AG6 VSS VSS AR22 F7 VSS VSS T9 AH1 VSS VSS AR25 F8 VSS VSS U11 AH10 VSS VSS AR28 F9 VSS VSS U27 AH2 VSS VSS AR31 G1 VSS VSS V11 AG27 VSS VSS AR34 G11 VSS VSS V28 AG29 VSS VSS AR4 G2 VSS VSS V30 AH3 VSS VSS AR7 G27 VSS VSS V32 AG33 VSS VSS AT10 G29 VSS VSS V34 B AG35 VSS VSS AT13 G3 VSS VSS W1 B AH4 VSS VSS AT16 G31 VSS VSS W10 AH5 VSS VSS AT19 G33 VSS VSS W3 AH6 VSS VSS AT21 G35 VSS VSS W35 AH7 VSS VSS AT24 G4 VSS VSS W4 09/11 Change netname to VSSSENSE AH8 VSS VSS AT27 G5 VSS VSS W6 AH9 VSS VSS AT3 H10 VSS VSS W7 AJ11 VSS VSS AT30 H26 VSS VSS W9 AJ5 VSS VSS AT4 H6 VSS VSS Y11 AK11 VSS VSS AT7 H7 VSS VSS H11 AK25 VSS VSS B10 J11 VSS VSS AL24 AK26 VSS VSS B13 J26 VSS VSS F19 AK28 VSS VSS B16 J28 VSS VSS T26 AK29 VSS VSS B19 J30 VSS VSS AK35 AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE [47,9] AK32 VSS VSS B22 J34 VSS RSVD E19 VSS VSS J6 VSS VSS K1 VSS VSS

INTEL_HASWELL_HASWELL 6 OF 9 INTEL_HASWELL_HASWELL 7 OF 9

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 10of 56 5 4 3 2 1 www.vinafix.vn CPU-VSS LA-9241P

Populate RD1, De-Populate RD7 for Intel DDR3 JDIMM1 H=5.2mm BOT VREFDQ multiple methods M1 Populate RD7, De-Populate RD1 for Intel DDR3 JDIMM1 H=4mm TOP 07/10 Change by HP request VREFDQ multiple methods M3 [12,9] RUN_ON_CPU1.5VS3 07/10 Change by HP request +1.35V +DIMM_A_DQ +1.35V +1.35V 2 07/17 Rename JP3 to JDIMM1

QD1 1 JDIMM3 2N7002KW_SOT323-3 +DIMM_A_DQ

+1.35V +1.35V 1K_0402_5% +DIMM01_VREF_DQ07/10 Change by HP G request DDR_A_D4 JDIMM1 1 2 DDR_A_D0 DDR_A_D5 2.2U_0402_6.3V6M 0.1U_0402_16V4Z RD2 VREF_DQ VSS1 3 1 +1.35V 3 4 DDR_A_D1

2 VSS2 DQ4 D RD24 1K_0402_1% DDR_A_D4 5 6 DDR_A_DQS#0 D S D 1 2 DDR_A_D01 2 DDR_A_D5 7 DQ0 DQ5 8 DDR_A_DQS0

1 DDR_A_D1 1 1 CD1 CD2 2.2U_0402_6.3V6M 0.1U_0402_16V4Z VREF_DQ VSS1 DQ1 VSS3 3 4 DDR_A_DQS#0 RD6 33_0402_5%08/03 Change RD6 to 33 ohms All VREF traces should 9 10 DDR_A_D2 DDR_A_D6 VSS2 DQ4 [12] DDR3_DRAMRST#_R CPU_DRAM_RST# [5] VSS4 DQS#0 5 6 DDR_A_DQS0 11 12 DDR_A_D3 DDR_A_D7

1K_0402_1% DQ0 DQ5 have 10 mil trace width DM0 DQS0 1 1 7 8 13 14

CD3 CD4 DQ1 VSS3 VSS5 VSS6 All VREF traces should DDR_A_D29 10 DDR_A_D6 1 2 2 2 15 16 DDR_A_D8 DDR_A_D12 RD23 have 10 mil trace width 2 DDR_A_D311 VSS4 DQS#0 12 DDR_A_D7 17 DQ2 DQ6 18 DDR_A_D9 DDR_A_D13 13 DM0 DQS0 14 19 DQ3 DQ7 20 2 2 DDR_A_D815 VSS5 VSS6 16 DDR_A_D12 21 VSS7 VSS8 22 DDR_A_DQS#1 DDR_A_D917 DQ2 DQ6 18 DDR_A_D13 23 DQ8 DQ12 24 DDR_A_DQS1 DDR3_DRAMRST#_R DQ3 DQ7 DQ9 DQ13 DDR_A_DQS#119 20 25 26 DDR_A_D10 DDR_A_D14 [6] DDR_A_D[0..63] VSS7 VSS8 VSS9 VSS10 DDR_A_DQS121 22 DDR3_DRAMRST#_R 27 28 DDR_A_D11 DDR_A_D15 23 DQ8 DQ12 24 29 DQS#1 DM1 30 [6] DDR_A_DQS[0..7] DQ9 DQ13 DQS1 RESET# DDR_A_D1025 26 DDR_A_D14 31 32 DDR_A_D16 DDR_A_D20 DDR_A_D1127 VSS9 VSS10 28 DDR_A_D15 33 VSS11 VSS12 34 DDR_A_D17 DDR_A_D21 [6] DDR_A_DQS#[0..7] 29 DQS#1 DM1 30 35 DQ10 DQ14 36 DDR_A_D16DQS1 RESET# DDR_A_D20 DQ11 DQ15 DDR_A_DQS#2 [6] DDR_A_MA[0..15] 31 32 37 38 DDR_A_D1733 VSS11 VSS12 34 DDR_A_D21 39 VSS13 VSS14 40 DDR_A_DQS2 DQ10 DQ14 DQ16 DQ20 DDR_A_D22 DDR_A_DQS#235 36 41 42 DDR_A_D18 DDR_A_D23 37 DQ11 DQ15 38 43 DQ17 DQ21 44 DDR_A_DQS2VSS13 VSS14 VSS15 VSS16 DDR_A_D19 39 40 DDR_A_D22 45 46 DDR_A_D28 DDR_A_D1841 DQ16 DQ20 42 DDR_A_D23 47 DQS#2 DM2 48 DDR_A_D24 DDR_A_D29 DDR_A_D1943 DQ17 DQ21 44 49 DQS2 VSS17 50 DDR_A_D25 VSS15 VSS16 VSS18 DQ22 Layout Note: 45 46 DDR_A_D28 51 52 DDR_A_DQS#3 DDR_A_D2447 DQS#2 DM2 48 DDR_A_D29 53 DQ18 DQ23 54 DDR_A_DQS3 Place near JDIMM1 DDR_A_D2549 DQS2 VSS17 50 55 DQ19 VSS19 56 DDR_A_DQS#3 DDR_A_D26 DDR_A_D30 51 VSS18 DQ22 52 57 VSS20 DQ28 58 DDR_A_DQS3 DDR_A_D27 DDR_A_D31 53 DQ18 DQ23 54 59 DQ24 DQ29 60 DQ19 VSS19 DQ25 VSS21 +1.35V DDR_A_D2655 56 DDR_A_D30 61 62 DDR_A_D2757 VSS20 DQ28 58 DDR_A_D31 63 VSS22 DQS#3 64 59 DQ24 DQ29 60 65 DM3 DQS3 66 DQ25 VSS21 VSS23 VSS24 DDR_CKE2_DIMMA DDR_CKE3_DIMMA 61 62 [6] 67DDR_CKE2_DIMMA 68 DDR_CKE3_DIMMA [6] 63 VSS22 DQS#3 64 69 DQ26 DQ30 70 65 DM3 DQS3 66 71 DQ27 DQ31 72 DDR_A_MA15 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_A_BS2 DDR_A_MA14 [6] DDR_CKE0_DIMMA 67 VSS23 VSS24 68 DDR_CKE1_DIMMA [6] VSS25 VSS26 C C 69 DQ26 DQ30 70 DQ27 DQ31 DDR_A_MA15 DDR_A_MA12 DDR_A_MA11 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K DDR_A_BS271 72 DDR_A_MA14 DDR_A_MA9 DDR_A_MA7 [6] DDR_A_BS2 VSS25 VSS26 73 74 DDR_A_MA12 DDR_A_MA11 75 CKE0 CKE1 76 DDR_A_MA8 DDR_A_MA6 VDD1 VDD2 CD5 CD6 CD7 CD8 DDR_A_MA9 DDR_A_MA7 DDR_A_MA5 DDR_A_MA4 1 1 1 1 77 78 73 74 79 NC1 A15 80 DDR_A_MA875 CKE0 CKE1 76 DDR_A_MA6 81 BA2 A14 82 DDR_A_MA3 DDR_A_MA2 DDR_A_MA5 DDR_A_MA4 DDR_A_MA1 DDR_A_MA0 77 VDD1 VDD2 78 83 VDD3 VDD4 84 2 2 2 2 NC1 A15 A12/BC# A11 DDR_A_MA379 80 DDR_A_MA2 85 86 M_CLK_A_DDR2 M_CLK_A_DDR3 BA2 A14 [6] M_CLK_A_DDR2A9 A7 M_CLK_A_DDR3 [6] +1.35V DDR_A_MA181 82 DDR_A_MA0 87 88 M_CLK_A_DDR#2 M_CLK_A_DDR#3 83 VDD3 VDD4 84 [6]89 M_CLK_A_DDR#2VDD5 VDD6 90 M_CLK_A_DDR#3 [6] + M_CLK_A_DDR085 A12/BC# A11 86 M_CLK_A_DDR1 91 A8 A6 92 DDR_A_MA10 DDR_A_BS1 [6] M_CLK_A_DDR0 M_CLK_A_DDR1 [6] M_CLK_A_DDR#0A9 A7 M_CLK_A_DDR#1 A5 A4 DDR_A_BS0 DDR_A_RAS# [6] M_CLK_A_DDR#0 87 88 M_CLK_A_DDR#1 [6] 93 94 89 VDD5 VDD6 90 95 VDD7 VDD8 96 DDR_A_MA1091 A8 A6 92 DDR_A_BS1 DDR_A_BS1 [6] 97 A3 A2 98 DDR_A_WE# DDR_CS2_DIMMA# DDR_CS2_DIMMA# [6] DDR_A_BS0 DDR_A_RAS# DDR_A_CAS# M_A_ODT2 [6] DDR_A_BS0 93 A5 A4 94 DDR_A_RAS# [6] 99 A1 A0 100 M_A_ODT2 [6] VDD7 VDD8 VDD9 VDD10 95 96 101 102 +DIMM_VREF_CA @ CD16 [6] DDR_A_WE# DDR_A_WE#A3 A2 DDR_CS0_DIMMA# DDR_CS0_DIMMA# [6] CK0 CK1 DDR_A_MA13 M_A_ODT3 M_A_ODT3 [6] 330U_B2_2.5VM_R15M 97 98 103 104 [6] DDR_A_CAS# DDR_A_CAS# M_A_ODT0 M_A_ODT0 [6] DDR_CS3_DIMMA# 99 A1 A0 100 [6] 105DDR_CS3_DIMMA#CK0# CK1# 106 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M VDD9 VDD10 +DIMM_VREF_CA VDD11 VDD12 DDR_A_MA13101 102 M_A_ODT1 M_A_ODT1 [6] 107 108 DDR_CS1_DIMMA#CK0 CK1 A10/AP BA1 [6] DDR_CS1_DIMMA# 103 104 109 110 105 CK0# CK1# 106 111 BA0 RAS# 112 DDR_A_D32 DDR_A_D36 107 VDD11 VDD12 108 +1.35V 113 VDD13 VDD14 114 DDR_A_D33 DDR_A_D37 CD9 CD10 CD11 CD12 CD13 CD14 CD15 SGA00004400 A10/AP BA1 RD26 1K_0402_1% WE# S0# 109 110 1 115 116 1 DDR_A_D32BA0 RAS# DDR_A_D36 CAS# ODT0 DDR_A_DQS#4 1 1 1 1 1 1 1 DDR_A_D33111 112 DDR_A_D37 117 118 DDR_A_DQS4 113 VDD13 VDD14 114 119 VDD15 VDD16 120 +SM_VREF_CA DDR_A_D38 DDR_A_DQS#4115 WE# S0# 116 121 A13 ODT1 122 DDR_A_D34 DDR_A_D39 2 DDR_A_DQS4117 CAS# ODT0 118 QD2 123 S1# NC2 124 DDR_A_D35 2 2.2U_0402_6.3V6M 0.1U_0402_16V4Z 2 2 2 2 2 2 2 2 119 VDD15 VDD16 120 DDR_A_D38 2N7002KW_SOT323-3 125 VDD17 VDD18 126 DDR_A_D44 DDR_A_D34121 A13 ODT1 122 DDR_A_D39 127 NCTEST VREF_CA 128 DDR_A_D40 DDR_A_D45 DDR_A_D35123 S1# NC2 124 RUN_ON_CPU1.5VS3 129 VSS27 VSS28 130 DDR_A_D41 2.2U_0402_6.3V6M 0.1U_0402_16V4Z DDR_A_D44 CD17 DDR_A_DQS#5CD18 125 VDD17 VDD18 126 1 2 131 DQ32 DQ36 132 DDR_A_D40 DDR_A_D45 DDR_A_DQS5 127 NCTEST VREF_CA 128 133 DQ33 DQ37 134 DDR_A_D41VSS27 VSS28 1K_0402_1% VSS29 VSS30 1 1

129 130 DDR_A_DQS#5 CD19 CD20 135 136 DDR_A_D42 DDR_A_D46 B DQ32 DQ36 DQS#4 DM4 B 131 132 DDR_A_DQS5RD25 137 138 DDR_A_D43 DDR_A_D47 DQ33 DQ37 DQS4 VSS31 133 134 1 1 1 3 139 140 Layout Note: DDR_A_D42135 VSS29 VSS30 136 DDR_A_D46 141 VSS32 DQ38 142 DDR_A_D48 2 2 DDR_A_D52 DQS#4 DM4 DQ34 DQ39 Place near JDIMM1.203,204 DDR_A_D43137 138 DDR_A_D47 143 144 DDR_A_D49 DDR_A_D53 139 DQS4 VSS31 140 145 DQ35 VSS33 146 DDR_A_D48 DDR_A_D52 DDR_A_DQS#6 141 VSS32 DQ38 142 2 2 147 VSS34 DQ44 148 DDR_A_D49DQ34 DQ39 DDR_A_D53 DQ40 DQ45 DDR_A_DQS6 143 144 149 150 DDR_A_D54 145 DQ35 VSS33 146 DD SS 151 DQ41 VSS35 152 +0.675VS DDR_A_DQS#6VSS34 DQ44 VSS36 DQS#5 DDR_A_D50 DDR_A_D55 DDR_A_DQS6147 148 153 154 DDR_A_D51 149 DQ40 DQ45 150 DDR_A_D54 155 DM5 DQS5 156 DDR_A_D60 DDR_A_D50DQ41 VSS35 DDR_A_D55 VSS37 VSS38 DDR_A_D56 DDR_A_D61 151 152 GG 157 158 DDR_A_D51153 VSS36 DQS#5 154 159 DQ42 DQ46 160 DDR_A_D57 155 DM5 DQS5 156 DDR_A_D60 161 DQ43 DQ47 162 DDR_A_DQS#7 DDR_A_D56VSS37 VSS38 DDR_A_D61 VSS39 VSS40 DDR_A_DQS7 DDR_A_D57157 158 163 164 159 DQ42 DQ46 160 165 DQ48 DQ52 166 DQ43 DQ47 DDR_A_DQS#7 DQ49 DQ53 DDR_A_D58 DDR_A_D62 161 162 DDR_A_DQS7 167 168 DDR_A_D59 DDR_A_D63 163 VSS39 VSS40 164 +3VS 169 VSS41 VSS42 170 DDR_A_D58165 DQ48 DQ52 166 DDR_A_D62 171 DQS#6 DM6 172 DDR_A_D59167 DQ49 DQ53 168 DDR_A_D63 173 DQS6 VSS43 174 DDR_XDP_WAN_SMBDAT +3VS 08/07 Change JDIMM1 footprint 169 VSS41 VSS42 170 175 VSS44 DQ54 176 DDR_XDP_WAN_SMBCLK

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 171 DQS#6 DM6 172 177 DQ50 DQ55 +0.675VS178 +0.675VS 173 DQS6 VSS43 174 DDR_XDP_WAN_SMBDAT [12,13,16,28,38,5] 179 DQ51 VSS45 180 175 VSS44 DQ54 176 DDR_XDP_WAN_SMBCLK [12,13,16,28,38,5] 181 VSS46 DQ60 182 CD21 CD22 CD23 CD24 +0.675VS 177 DQ50 DQ55 178 +0.675VS 183 DQ56 DQ61 184 DQ51 VSS45 DQ57 VSS47 LCN_DAN06-K4406-0102 1 1 1 1 179 180 185 186 CONN@ 181 VSS46 DQ60 182 187 VSS48 DQS#7 188 183 DQ56 DQ61 184FOX_AS0A626-U4RN-7F 189 DM7 DQS7 190 185 DQ57 VSS47 186CONN@ 191 VSS49 VSS50 192 2 2 2 2 187 VSS48 DQS#7 188 193 DQ58 DQ62 194 189 DM7 DQS7 190 195 DQ59 DQ63 196 0.1U_0402_16V4Z 191 VSS49 VSS50 192 2.2U_0402_6.3V6M 197 VSS51 VSS52 198 193 DQ58 DQ62 194 199 SA0 EVENT# 200 195 DQ59 DQ63 196 CD26 201 VDDSPD SDA 202 0.1U_0402_16V4Z 2.2U_0402_6.3V6M VSS51 VSS52 CD25 SA1 SCL 197 198 1 203 204 199 SA0 EVENT# 200 VTT1 VTT2 A CD28 1 A 201 VDDSPD SDA 202 205 206 CD27 Standard 203 SA1 SCL 204 G1 G2 1 VTT1 VTT2 2 1 Reverse 205 206 2 G1 G2 Title 2 Compal Secret Data 2 Security Classification Size Document Number Rev CompalCustom Electronics, Inc. 0.5 2012/03/23 Deciphered Date 2011/06/29 Date: Thursday, December 20, 2012 Sheet 11of 56 Issued Date

5 4 3 2 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRIII DIMM1&2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9241P

www.vinafix.vn 5 4 3 2 1

Populate RD4, De-Populate RD8 for Intel DDR3 VREFDQ multiple methods M1 07/10 Change by HP request Populate RD8, De-Populate RD4 for Intel DDR3 [11,9] RUN_ON_CPU1.5VS3 JDIMM4 H=5.2mm BOT 2 VREFDQ multiple methods M3 JDIMM2 H=9.2mm TOP QD3 07/10 Change by HP request +DIMM_B_DQ

G 2N7002KW_SOT323-3 4/16 change by HP requirement +1.35V +1.35V +DIMM23_VREF_DQ JDIMM4 +DIMM_B_DQ 3 1 +1.35V +1.35V +1.35V

S D RD27 1K_0402_1% DDR_B_D4 JDIMM2 1 2 1 DDR_B_D02 DDR_B_D5 VREF_DQ VSS RD28 1 3 DDR_B_D14

DDR_B_D4 0.1U_0402_16V4Z 5 VSS DQ4 6 DDR_B_DQS#0 DQ0 DQ5 D DDR_B_D01 2 DDR_B_D5 7 8 DDR_B_DQS0 D 2.2U_0402_6.3V6M DDR_B_D13 VREF_DQ VSS1 4 1K_0402_1% 9 DQ1 VSS 10 DDR_B_DQS#0 1 DDR_B_D2 DDR_B_D6 CD30 0.1U_0402_16V4Z 5 VSS2 DQ4 6 11 VSS DQS0# 12 DDR_B_DQS0 2 DDR_B_D3 DDR_B_D7 7 DQ0 DQ5 8 13 DM0 DQS0 14

CD31 DQ1 VSS3 All VREF traces should VSS VSS 1 1 DDR_B_D29 10 DDR_B_D6 15 DDR_B_D816 DDR_B_D12

CD32 VSS4 DQS#0 DQ2 DQ6 DDR_B_D311 12 DDR_B_D7 have 10 mil trace width 2 17 DDR_B_D918 DDR_B_D13 All VREF traces should 13 DM0 DQS0 14 19 DQ3 DQ7 20 have 10 mil trace width DDR_B_D815 VSS5 VSS6 16 DDR_B_D12 21 VSS DDR_B_DQS#1VSS 22 2 2 DDR_B_D917 DQ2 DQ6 18 DDR_B_D13 23 DQ8 DQ12DDR_B_DQS124 DDR3_DRAMRST#_R [6] DDR_B_D[0..63] 19 DQ3 DQ7 20 25 DQ9 DQ13 26 DDR_B_DQS#1VSS7 VSS8 VSS DDR_B_D10VSS DDR_B_D14 DDR_B_DQS121 22 DDR3_DRAMRST#_R 27 DDR_B_D1128 DDR_B_D15 [6] DDR_B_DQS[0..7] 23 DQ8 DQ12 24 DDR3_DRAMRST#_R [11] 29 DQS1# DM1 30 DQ9 DQ13 DQS1 RESET# DDR_B_D1025 26 DDR_B_D14 31 DDR_B_D1632 DDR_B_D20 [6] DDR_B_DQS#[0..7] VSS9 VSS10 VSS VSS DDR_B_D1127 28 DDR_B_D15 33 DDR_B_D1734 DDR_B_D21 29 DQS#1 DM1 30 35 DQ10 DQ14 36 [6] DDR_B_MA[0..15] DDR_B_D1631 DQS1 RESET# 32 DDR_B_D20 37 DQ11 DQ15DDR_B_DQS#238 DDR_B_D1733 VSS11 VSS12 34 DDR_B_D21 39 VSS DDR_B_DQS2VSS 40 35 DQ10 DQ14 36 41 DQ16 DQ20 42 DDR_B_D22 DDR_B_DQS#2DQ11 DQ15 DQ17 DQ21DDR_B_D18 DDR_B_D23 DDR_B_DQS237 38 43 DDR_B_D1944 39 VSS13 VSS14 40 45 VSS VSS 46 DQ16 DQ20 DDR_B_D22 DQS2# DM2 DDR_B_D28 DDR_B_D1841 42 DDR_B_D23 47 DDR_B_D2448 DDR_B_D29 DDR_B_D1943 DQ17 DQ21 44 49 DQS2 DDR_B_D25VSS 50 VSS15 VSS16 VSS DQ22 Layout Note: 45 46 DDR_B_D28 51 52 DDR_B_DQS#3 DDR_B_D2447 DQS#2 DM2 48 DDR_B_D29 53 DQ18 DQ23 54 DDR_B_DQS3 Place near JDIMM2 DDR_B_D2549 DQS2 VSS17 50 55 DQ19 VSS 56 51 VSS18 DQ22 52 DDR_B_DQS#3 57 VSS DQ28DDR_B_D2658 DDR_B_D30 DDR_B_DQS3 DDR_B_D27 DDR_B_D31 53 DQ18 DQ23 54 59 DQ24 DQ29 60 55 DQ19 VSS19 56 61 DQ25 VSS 62 DDR_B_D26VSS20 DQ28 DDR_B_D30 VSS DQS3# DDR_B_D2757 58 DDR_B_D31 63 64 +1.35V 59 DQ24 DQ29 60 65 DM3 DQS3DDR_CKE2_DIMMB66 DDR_CKE3_DIMMB [6] DDR_CKE2_DIMMB DDR_CKE3_DIMMB [6] 61 DQ25 VSS21 62 67 VSS VSS 68 63 VSS22 DQS#3 64 69 DQ26 DQ30 70 DDR_B_MA15 65 DM3 DQS3 66 71 DQ27 DQ31DDR_B_BS272 DDR_B_MA14 DDR_CKE0_DIMMBVSS23 VSS24 DDR_CKE1_DIMMB VSS VSS [6] DDR_CKE0_DIMMB 67 68 DDR_CKE1_DIMMB [6] DDR_B_MA12 DDR_B_MA11 69 DQ26 DQ30 70 C DQ27 DQ31 DDR_B_MA15 DDR_B_MA9 DDR_B_MA7 C @ DDR_B_BS271 72 DDR_B_MA14 73 74 11/06 Add C511 by rf request [6] DDR_B_BS2 VSS25 VSS26 75 CKE0 CKE1 76 VDD DDR_B_MA8VDD DDR_B_MA6 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 100P_0402_50V8J DDR_B_MA12 DDR_B_MA11 77 DDR_B_MA578 DDR_B_MA4 DDR_B_MA9 DDR_B_MA7 79 NC A15 80 73 74 81 BA2 DDR_B_MA3A14 82 DDR_B_MA2 CKE0 CKE1 VDD VDD CD33 CD34 CD35 CD36 C511 DDR_B_MA8 DDR_B_MA6 DDR_B_MA1 DDR_B_MA0 1 1 1 1 1 75 76 83 84 DDR_B_MA577 VDD1 VDD2 78 DDR_B_MA4 85 A12/BC# A11 86 M_CLK_B_DDR2 M_CLK_B_DDR3 NC1 A15 [6] M_CLK_B_DDR2A9 A7 M_CLK_B_DDR3 [6] DDR_B_MA379 80 DDR_B_MA2 87 M_CLK_B_DDR#288 M_CLK_B_DDR#3 BA2 A14 [6] M_CLK_B_DDR#2VDD VDD M_CLK_B_DDR#3 [6] DDR_B_MA181 82 DDR_B_MA0 89 90 +1.35V2 2 2 2 2 83 VDD3 VDD4 84 91 A8 A6 92 A12/BC# A11 A5 DDR_B_MA10A4 DDR_B_BS1 M_CLK_B_DDR085 86 M_CLK_B_DDR1 93 DDR_B_BS094 DDR_B_RAS# + [6] M_CLK_B_DDR0 M_CLK_B_DDR1 [6] M_CLK_B_DDR#087 A9 A7 88 M_CLK_B_DDR#1 95 VDD VDD 96 [6] M_CLK_B_DDR#0 M_CLK_B_DDR#1 [6] 89 VDD5 VDD6 90 97 A3 DDR_B_WE#A2 98 DDR_CS2_DIMMB# A8 A6 A1 A0 DDR_CS2_DIMMB# [6] DDR_B_MA1091 92 DDR_B_BS1 DDR_B_BS1 [6] 99 DDR_B_CAS#100 M_B_ODT2 M_B_ODT2 [6] DDR_B_BS0A5 A4 DDR_B_RAS# VDD VDD [6] DDR_B_BS0 93 94 DDR_B_RAS# [6] 101 102 +DIMM_VREF_CA VDD7 VDD8 CK0 DDR_B_MA13CK1 M_B_ODT3 M_B_ODT3 [6] DDR_B_WE#95 96 DDR_CS0_DIMMB# 103 DDR_CS3_DIMMB#104 [6] DDR_B_WE# 97 A3 A2 98 DDR_CS0_DIMMB# [6] [6] DDR_CS3_DIMMB#105 CK0# CK1# 106 @ CD44 [6] DDR_B_CAS# DDR_B_CAS#A1 A0 M_B_ODT0 M_B_ODT0 [6] VDD VDD 330U_B2_2.5VM_R15M 99 100 107 108 VDD9 VDD10 A10/AP BA1 DDR_B_MA13101 102 M_B_ODT1 +DIMM_VREF_CA 109 110

10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M M_B_ODT1 [6] DDR_CS1_DIMMB#103 CK0 CK1 104 111 BA0 RAS#DDR_B_D32112 DDR_B_D36 [6] DDR_CS1_DIMMB# 105 CK0# CK1# 106 113 VDD DDR_B_D33VDD 114 DDR_B_D37 107 VDD11 VDD12 108 115 WE# S0# 116 109 A10/AP BA1 110 117 CAS# ODT0DDR_B_DQS#4118 CD37 CD38 CD39 CD40 CD41 CD42 CD43 DDR_B_D32BA0 RAS# DDR_B_D36 VDD DDR_B_DQS4VDD 1 DDR_B_D33111 112 DDR_B_D37 119 120 DDR_B_D38 113 VDD13 VDD14 114 121 A13 ODT1 122 1 1 1 1 1 1 1 WE# S0# S1# DDR_B_D34NC DDR_B_D39 DDR_B_DQS#4115 116 123 DDR_B_D35124 2.2U_0402_6.3V6M 0.1U_0402_16V4Z DDR_B_DQS4117 CAS# ODT0 118 125 VDD VDD 126 DDR_B_D44 119 VDD15 VDD16 120 DDR_B_D38 127 TEST VREF_CADDR_B_D40128 DDR_B_D45 2 2 2 2 2 2 2 2 DDR_B_D34121 A13 ODT1 122 DDR_B_D39 129 VSS DDR_B_D41VSS 130 DDR_B_D35123 S1# NC2 124 131 DQ32 DQ36 132 CD45 DDR_B_DQS#5CD46 2.2U_0402_6.3V6M 0.1U_0402_16V4Z 125 VDD17 VDD18 126 DDR_B_D44 133 DQ33 DQ37 134 DDR_B_DQS5 DDR_B_D40 DDR_B_D45 1 1 127 NCTEST VREF_CA 128 135 VSS VSS 136 DDR_B_D41 DDR_B_D42 DDR_B_D46 129 VSS27 VSS28 130 137 DQS4# DM4 138 DQ32 DQ36 DDR_B_DQS#5 CD47 CD48 DQS4 DDR_B_D43VSS DDR_B_D47 Layout Note: 131 132 DDR_B_DQS5 139 140 DQ33 DQ37 VSS DQ38 2 2 B 133 134 1 1 141 DDR_B_D48142 DDR_B_D52 B Place near JDIMM2.203,204 DDR_B_D42135 VSS29 VSS30 136 DDR_B_D46 143 DQ34 DQ39DDR_B_D49144 DDR_B_D53 DDR_B_D43137 DQS#4 DM4 138 DDR_B_D47 145 DQ35 VSS 146 139 DQS4 VSS31 140 147 VSS DQ44DDR_B_DQS#6148 +0.675VS DDR_B_D48141 VSS32 DQ38 142 DDR_B_D522 2 149 DQ40 DQ45DDR_B_DQS6150 DDR_B_D49 DDR_B_D53 DDR_B_D54 143 DQ34 DQ39 144 151 DQ41 VSS 152 DQ35 VSS33 VSS DQS5#DDR_B_D50 DDR_B_D55 DDR_B_DQS#6145 146 153 DDR_B_D51154 147 VSS34 DQ44 148 155 DM5 DQS5 156 DDR_B_DQS6DQ40 DQ45 VSS VSS DDR_B_D60 149 150 DDR_B_D54 157 DDR_B_D56158 DDR_B_D61 DDR_B_D50151 DQ41 VSS35 152 DDR_B_D55 159 DQ42 DQ46DDR_B_D57160 DDR_B_D51153 VSS36 DQS#5 154 161 DQ43 DQ47 162 DDR_B_DQS#7 155 DM5 DQS5 156 DDR_B_D60 163 VSS VSS 164 DDR_B_DQS7 DDR_B_D56157 VSS37 VSS38 158 DDR_B_D61 165 DQ48 DQ52 166 DDR_B_D57 DDR_B_D58 DDR_B_D62 159 DQ42 DQ46 160 167 DQ49 DQ53 168 DQ43 DQ47 DDR_B_DQS#7 VSS DDR_B_D59VSS DDR_B_D63 161 162 DDR_B_DQS7 +3VS 169 170 163 VSS39 VSS40 164 171 DQS6# DM6 172 DQ48 DQ52 DQS6 VSS DDR_B_D58165 166 DDR_B_D62 173 174 DDR_XDP_WAN_SMBDAT

1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K DDR_B_D59167 DQ49 DQ53 168 DDR_B_D63 175 VSS DQ54 176 DDR_XDP_WAN_SMBCLK +3VS VSS41 VSS42 DQ50 DQ55 169 170 08/07 Change JDIMM2 footprint 177 +0.675VS178 +0.675VS 171 DQS#6 DM6 172 179 DQ51 VSS 180 CD49 CD50 CD51 CD52 173 DQS6 VSS43 174 DDR_XDP_WAN_SMBDAT [11,13,16,28,38,5] 181 VSS DQ60 182 VSS44 DQ54 DQ56 DQ61 1 1 1 1 175 176 DDR_XDP_WAN_SMBCLK [11,13,16,28,38,5] 183 184 +0.675VS177 DQ50 DQ55 178 +0.675VS 185 DQ57 VSS 186 DQ51 VSS45 VSS DQS7# 179 180 187 188 LCN_DAN06-K4406-0103 181 VSS46 DQ60 182 189 DM7 DQS7 190 CONN@ 2 2 2 2 183 DQ56 DQ61 184TYCO_2-2013311-4 191 VSS VSS 192 185 DQ57 VSS47 186CONN@ 193 DQ58 DQ62 194 187 VSS48 DQS#7 188 195 DQ59 DQ63 196 0.1U_0402_16V4Z 189 DM7 DQS7 190 2.2U_0402_6.3V6M 197 VSS VSS 198 191 VSS49 VSS50 192 199 SA0 EVENT# 200 193 DQ58 DQ62 194 CD54 201 VDDSPD SDA 202 195 DQ59 DQ63 196 CD53 203 SA1 SCL 204 0.1U_0402_16V4Z 2.2U_0402_6.3V6M VSS51 VSS52 VTT VTT 197 198 1 1 199 SA0 EVENT# 200 205 206 CD56 Reverse 201 VDDSPD SDA 202 207 GND1 GND2 208 A CD55 A 203 SA1 SCL 204 BOSS1 BOSS2 VTT1 VTT2 2 2 1 1 Reverse 205 206 G1 G2

Title 2 2 Compal Secret Data Security Classification Size Document Number Rev CompalCustom Electronics, Inc. 0.5 2012/03/23 Deciphered Date 2011/06/29 Date: Thursday, December 20, 2012 Sheet 12of 56 Issued Date

5 4 3 2 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL DDRIII DIMM3&4 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9241P

www.vinafix.vn 5 4 3 2 1

+RTCVCC

330K_0402_5% 07/09 Delete by HP request. 1

RH6 07/09 Delete by HP request. 2

D PCH_INTVRMEN D

INTVRMEN - INTEGRATED SUS 1.05V VRM ENABLE High - Enable Internal VRs Low - Enable External VRs 07/09 Change by HP request. 10/26 Swap QH11A.2 and QH11B.5 connection [11,12,16,28,38,5] DDR_XDP_WAN_SMBDAT +3VS [11,12,16,28,38,5] DDR_XDP_WAN_SMBCLK

1 2 PLT_RST# PCH_RTCX1

[30,39] BAT_GRNLED# 2 2 @ HDA_SPKR 1 2 RH29 10K_0402_5% PCH_RTCX2 RH37 RH38 +3V_PCH 2 5 RH28 10M_0402_5% 10K_0402_5% QH11A QH11B 10K_0402_5% NO REBOOT STRAP 209/03 Instal1 RH31 1 6 4 3

09/19 Change QH11 to P MOS, change RH30 to 2.2K ohms 1 2 1 1

G G HDA_SDOUT YH1 DISABLED WHEN LOW (DEFAULT) RH30 2.2K_0402_5% ENABLED WHEN HIGH MESS84DW-G_SC88-6 MESS84DW-G_SC88-6 18P_0402_50V8J

S D S D 32.768KHZ_12.5PF_Q13FC1350000500 1 1

CH13 CH14 +3VS FLASH DESCRIPTOR SECURITY OVERRIDE 2 18P_0402_50V8J2 LOW = DESABLED (DEFAULT) 08/031 RH33.12 connection to GND 11/01 Change YH1 to small package C HIGH = ENABLED C @ HDD_HALTLED RH33 100K_0402_5% LPT_PCH_M_EDS UH1A REV = 5 BC8 B5 SATA_RXN_0 BE8 RTCX1 SATA_RXP_0SATA_PRX_DTX_N0 SATA_PRX_DTX_N0 [23] PCH_RTCX1 B4 SATA_PRX_DTX_P0AW8 RTCX2 SATA_TXN_0 AY8 SATA_PRX_DTX_P0 [23] HDD SATA_TXP_0 1 2 PCH_RTCX2 B9 RTC SATA_PTX_DRX_N0 SRTCRST# SATA_PTX_DRX_N0 [23] SATA_PTX_DRX_P0BC10 SATA_RXN_1 SATA_PTX_DRX_P0 [23] 1 2 SRTCRST# A8 BE10 +RTCVCC RH34 20K_0402_5% INTRUDER# SATA_RXP_1 SATA_PRX_DTX_N1 SATA_PRX_DTX_N1 [23] RH35 1M_0402_5% 1 2 INTRUDER# G10 SATA_PRX_DTX_P1AV10 INTVRMEN SATA_TXN_1 AW10 SATA_PRX_DTX_P1 [23] ODD SATA_TXP_1 1 2 PCH_INTVRMEN D9 SATA_PTX_DRX_N1 [25] WWAN_DET# RTCRST# SATA_PTX_DRX_N1 [23] RH230 0_0402_5% SATA_PTX_DRX_P1BB9 SATA_RXN_2 SATA_PTX_DRX_P1 [23] RH36 20K_0402_5% PCH_RTCRST# BD9 B25 SATA_RXP_2 SATASATA SATA_PRX_DTX_N2 HDA_BCLK AY13 SATA_PRX_DTX_N2 [33] DOCK_SATA5 SATA_PRX_DTX_P2 CMOS_CLR1 CMOS setting 1 2 1 2 [14] PCH_RTCRST# A22 SATA_TXN_2 AW13 SATA_PRX_DTX_P2 [33] 1 2 1 2 HDA_BIT_CLK HDA_SYNC SATA_TXP_2 SATA_PTX_DRX_N2 Shunt Clear CMOS AL10 BC12 SATA_PTX_DRX_N2 [33] HDA_SYNC SPKR SATA_RXN_3SATA_PTX_DRX_P2 BE12 SATA_PTX_DRX_P2 [33] Open Keep CMOS C24 SATA_RXP_3 HDA_SPKR HDA_RST# SATA_PRX_DTX_N3 [26] HDA_SPKR AR13 SATA_PRX_DTX_N3 [33] SATA_TXN_3SATA_PRX_DTX_P3 1 2 1 2 L22 AT13 SATA_PRX_DTX_P3 [33] DOCK_SATA3 ME_CLR1 TPM setting @ @ HDA_RST# HDA_SDI0 AZALIA SATA_TXP_3 ME1 SHORT PADS CMOS1 SHORT PADS SATA_PTX_DRX_N3 K22 SATA_PTX_DRX_N3 [33] 07/06 Follow HP'sHDA_SDI0 GPIO table HDA_SDI1 SATA_PTX_DRX_P3 Shunt Clear ME RTC Registers [26] HDA_SDI0 BD13 SATA_PTX_DRX_P3 [33] CH15 1U_0402_6.3V6K CH16CMOS place near1U_0402_6.3V6K DIMM G22 SATA_RXN4/PERN1 BB13 Open Keep ME RTC Registers HDA_SDI2 SATA_RXP4/PERP1 F22 AV15 HDA_SDI3 SATA_TXN4/PETN1 AW15 A24 SATA_TXP4/PETP1 HDA_SDO BC14 B B17 SATA_RXN5/PERN2 BE14 B HDA_SDOUT DOCKEN#/GPIO33 SATA_RXP5/PERP2 C22 SATA_PRX_DTX_N5AP15 mSATA HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 SATA_PRX_DTX_N5 [23] HDD_HALTLED SATA_PRX_DTX_P5AR15 [39] HDD_HALTLED SATA_TXP5/PETP2 SATA_PRX_DTX_P5 [23] HDA_SYNC Isolation Circuit +3V_PCH ISO_PREP# SATA_PTX_DRX_N5 +3VS [33,36] ISO_PREP# SATA_PTX_DRX_N5 [23] +5VS SATA_PTX_DRX_P5AY5 1 2 SATA_RCOMP SATA_PTX_DRX_P5 [23] 1 AP3 3 1 SATALED# 10K_0402_5% SATA_COMP R463 10K_0402_5% +3VS

2 2 1 AB3 AT1 R7 JTAG_TCK SATA0GP/GPIO21 QH2 SATA_ACT#

SATA_ACT# [33,39] 2 HDA_SYNC_R HDA_SYNC 1 2 AD1 AU2 JTAG_TMS SATA1GP/GPIO19 SG_IN [22] RH39@ 51_0402_1% PCH_JTAG_TCK SG_IN 1 09/21 2Non-install RH39, RH40, AE2 BD4 1 2 SB000002X00 RH41, RH44, RH48, RH47, RH46 JTAG_TDI SATA_IREF JTAG PCH_JTAG_TMS FN9 1 BSS138W-7-F_SOT323-3 RH40 @1 2 AD3 BA2 D G 200_0402_5% JTAG_TDO TP9 PAD~D T72 @ 10K_0402_5% 2 RH41 @ PCH_JTAG_TDI 1 2 F8 SATA_IREFBB2 +1.5VS UMA@

RH43 200_0402_5% 100_0402_1% 100_0402_1% 100_0402_1% TP25 TP8 RH42 0_0402_5% R8 G 1M_0402_5% RH44 @ PCH_JTAG_TDO S

S D C26 1 2 2 200_0402_5% RH46 RH47 RH48 TP22 PCH_TP25 AB6 RH237 1 RH45 0_0402_5% TP20 1 1 1 +3VS 2 @ @ @ 10K_0402_5% W=20mils

1 Q70

2 2 2 1 2 SATA Impedance Compensation 2N7002KW_SOT323-3 [14,25,28,29,30,35,37,39,5] PLT_RST# LYNXPOINT_BGA695 1 OF 11 1 2

+RTCVCC 2 +3VDS +BATT1.1 10/25 Delete RH50, RH52, RH53. Add RP6 3 1 4 HDA_SYNC_R5 +1.5VS [26] HDA_SYNC_AUDIO 3 1 2 1 RH513 33_0402_5%6 08/071 Change JBATT1 footprint A D40 2 2 7 SATA_COMP A 3 2 1 8 1W=20mils G1 RP6 CAD note:7.5K_0402_1% RH49 RH233 JBATT14 W=20mils W=20mils G2 27P_0402_50V8J +BATT_D HDA_SDOUT Place the resistor within 500 mils of the PCH. Avoid [26] HDA_SDOUT_AUDIO @ 1 HDA_RST# routing next to clock pins. 2 [26] HDA_RST_AUDIO# CH17 CH102 DAN202U_SC70 1K_0402_5% HDA_BIT_CLK Compal Electronics, Inc. [26] HDA_BITCLK_AUDIO

1U_0603_10V4ZPlace near PCH 2 33_8P4R_5% ACES_50271-00201-001 Security Classification CONN@ Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Compal Secret Data Title

Size Document Number Rev Custom 0.5 5 4 3 2 1 Date: PCH-RTC,HDA,SATA,XDPThursday, December 20, 2012 Sheet 13of 56 www.vinafix.vn LA-9241P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 1

+3VDS 07/23 Connection RH55.2 to +RTCVCC JME1 10/25 Delete RH56, RH57, RH59, RH60. Add RP7 +3VS +3V_PCH 1 +RTCVCC SLP_S3# 2 1 3 2 RP7 SLP_S5# PCI_PIRQC# 4 3 8 1 SYS_RESET# SLP_S4# PCI_PIRQA# [5] XDP_DBRESET# 1 2 5 4 7 2 SUS_PWR_ACK RH54 0_0402_5% SIO_SLP_A# 5 330K_0402_5% PCI_PIRQB# RH631 2 10K_0402_5% 6 2 PCI_PIRQD#6 3 7 6 16 5 4 PCH_PCIE_WAKE# 7 G2 RH55 RH641 2 10K_0402_5% PCH_RTCRST#8 15 8.2K_8P4R_5% [13] PCH_RTCRST# 9 8 G1 PCH_RI# PCH_DPWROK PM_RSMRST# 9 07/31 Correct netname RH721 2 10K_0402_5% 1 RH672 0_0402_5% ON/OFFBTN#10 PWRSV_SEL#

10 1 D 11 10K_0402_5%2 1 RH62 D 11 BATLOW# SYS_RESET#12 RP8 10/26 change RH75.2 connection to BATLOW# 12 RH751 2 10K_0402_5% 07/20 Add ME debug13 circuit 14 13 DSWODVREN DGPU_PWR_EN1 8 14FCI_10051922-1410ELF DGPU_HOLD_RST#2 710/25 Delete RH66, RH69, RH71. Add RP8 +3VS CONN@ ODD_DA#3 6 4 5 PM_CLKRUN# 10K_8P4R_5% 09/20 Change RH74 to 100k RH781 2 8.2K_0402_5% 08/10 Add RH245 NMI_SMI_DBG# 10/12 Delete RH245. Add UH6, CH116 1100K_0402_5%2 RH74 10/12 Delete VCC1_PWRGD connection to UH6.1 and 2. Then add R613 PCH_CRT_DDC_CLK between +3VDS and UH6 pin 1,2. change UH6.5 pin connection to +3VDS 2.2K_0402_5%2 1 RH76 10/25 Change RH70 to 200K 10/18 install R613, CH116 and UH6. Uninstall RH67 PCH_CRT_DDC_DAT SLP_LAN# 10/18 Uninstall R613, CH116 and UH6. Install RH68 2.2K_0402_5%2 1 RH77 RH70 200K_0402_5% 12/12 Delete UH6, R613 and CH116 DGPU_SELECT# 1 2 10K_0402_5% RH80 Camera_ON2 1 10K_0402_5% RH82 ACCEL_INT_R#2 1 DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP 8.2K_0402_5% RH83 2 1 UH1B REV = 5 HIGH = ENABLED (DEFAULT) 07/23 Add CR_SX_WARN# PU RH244 LPT_PCH_M_EDS STP_A16OVR LOW = A16 SWAP OVERRIDE TBT_RR_GPIO# 10/23 Change netname to TBT_RR_GPIO# DMI_CTX_PRX_N0 LOW = DISABLED 10K_0402_5% RH244 [4] DMI_CTX_PRX_N0 2 1 [4] DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 HIGH = DEFAULT AW22 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 [7] DMI_CTX_PRX_N2 AR20 DMI_RXN_0 [4] DMI_CTX_PRX_N2 DMI_RXN_1 [4] DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 AJ35 FDI_CTX_PRX_N1 FDI_CTX_PRX_N1 [7] AP17 FDI_RXN_0 DMI_CTX_PRX_P0 AV20 DMI_RXN_2 AL35 FDI_CTX_PRX_P0 UH1E REV = 5 [4] DMI_CTX_PRX_P0 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_P0 [7] [4] DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 LPT_PCH_M_EV AY22 AJ36 FDI_CTX_PRX_P1 PCH_CRT_BLU DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P1 [7] [36] PCH_CRT_BLU [4] DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 AP20 FDI DMI_CTX_PRX_P3 DMI_RXP_1 PCH_CRT_GRN [4] DMI_CTX_PRX_P3 AL36 [36] PCH_CRT_GRN T45 R40 AR17 FDI_RXP_1 VGA_BLUE DDPB_CTRLCLK DMI_CRX_PTX_N0 DMI PCH_CRT_RED C [4] DMI_CRX_PTX_N0 AW20 DMI_RXP_2 AV43 [36] PCH_CRT_RED U44 R39 C DMI_CRX_PTX_N1 [4] DMI_CRX_PTX_N1 DMI_RXP_3 TP16 VGA_GREEN DDPB_CTRLDATA PCH_CRT_DDC_CLK BD21 AY45 [36] PCH_CRT_DDC_CLK V45 R35 DMI_CRX_PTX_N2 [4] DMI_CRX_PTX_N2 DMI_TXN_0 TP5 VGA_RED DDPC_CTRLCLK DMI_CRX_PTX_N3 BE20 PCH_CRT_DDC_DAT [4] DMI_CRX_PTX_N3 DMI_TXN_1 AV45 [36] PCH_CRT_DDC_DAT M43 R36

TP15 VGA_DDC_CLK CRT DDPC_CTRLDATA DMI_CRX_PTX_P0 BD17 FDI_CSYNC HSYNC [4] DMI_CRX_PTX_P0 DMI_TXN_2 FDI_CSYNC [4] [36] PCH_CRT_HSYNC DMI_CRX_PTX_P1 BE18 AW44 RH84 20_0402_1%M45 N40 [4] DMI_CRX_PTX_P1 DMI_TXN_3 TP10 VGA_DDC_DATA DDPD_CTRLCLK FDI_INT VSYNC FDI_INT [4] [36] PCH_CRT_VSYNC DMI_CRX_PTX_P2 BB21 AL39 1 RH852 20_0402_1%N42 N38 [4] DMI_CRX_PTX_P2 DMI_TXP_0 FDI_CSYNC VGA_HSYNC DDPD_CTRLDATA DMI_CRX_PTX_P3 BC20 FDI_IREF CRT_IREF [4] DMI_CRX_PTX_P3 DMI_TXP_1 +1.5VS AL40 RH86 0_0402_5% 1 RH872 649_0402_1%N44 BB17 FDI_INT VGA_VSYNC H45 +1.5VS DMI_IREF RH88 0_0402_5% BC18 DMI_TXP_2 AT45 1 2 1 2 U40 DDPB_AUXN DMI_TXP_3 FDI_IREF DAC_IREF K43 1 2 BE16 AU42 BKL_PWM_PCHU39 DDPC_AUXN 10/16 Delete R230 DMI_IREF TP17 [35] BKL_PWM_PCH VGA_IRTN FDI_RCOMP +1.5VS J42 AW17 AU44 7.5K_0402_1% RH89 DISPLAY DISPLAY DDPD_AUXN TP12 TP13 [35] PANEL_BKEN_PCH LVDS +1.5VS DMI_RCOMP N36 H43 09/11RH90 Delete RH92, RH93, 7.5K_0402_1% RH221, RH94, RH95 ENVDD_PCHEDP_BKLTCTL DDPB_AUXP AV17 AR44 2 1 [35] ENVDD_PCH 07/06 Correct netname to follow GPIO table TP7 FDI_RCOMP K36 K45 1 2 AY17 EDP_BKLTEN DDPC_AUXP SUSACK# DMI_RCOMP DSWODVREN PCI_PIRQA#G36 J44 10/26 change PCH.U7 connection to BT_OFF EDP_VDDEN DDPD_AUXP SYS_RESET# PCH_DPWROK PCI_PIRQB# K40 R6 C8 H20 DDPB_HPD System Power PCH_PCIE_WAKE# PCI_PIRQC# [30,5] PM_PWROK SUSACK# DSWVRMEN PCH_PCIE_WAKE# [25] PIRQA# K38 Management DDPC_HPD PCH_PWROK_R AM1 L13 PM_CLKRUN# PCI_PIRQD#L20 [31] PCH_PWROK_R SYS_RESET# DPWROK PM_CLKRUN# [28,30,32] PIRQB# H39 DDPD_HPD PWRSV_SEL# PWRSV_SEL# [37] AD7 K3 BT_OFF DGPU_HOLD_RST#K17 [30,31] PM_APWROK SYS_PWROK WAKE# BT_OFF [25] [35] DGPU_HOLD_RST#09/20 Change to +3VS PIRQC# PCI ODD_DA# ODD_DA# [23] F10 AN7 SUSCLK_KBC M20 [5] PM_DRAM_PWRGD PWROK CLKRUN# SUSCLK_KBC [30] [35,36] DGPU_SELECT# PIRQD# G17 PIRQE#/GPIO2 NMI_SMI_DBG# NMI_SMI_DBG# [30] AB7 U7 SLP_S5# T85 PAD~D@ DGPU_PWR_ENA12 [30] PM_RSMRST# APWROK SUS_STAT#/GPIO61 [15,35] DGPU_PWR_EN 07/18 Delete PCH_GPIO55GPIO50 PD RH186. DGPU_SELECT#07/23 Add CR_SX_WARN# off page symbol F17 ACCEL_INT_R# 08/10 Change UH3.5 connection to +3V_PCH power rail 10/26 change PCH.K7 connection to BATLOW# T86 PAD~D @ ACCEL_INT# [28] B ME_SUS_PWR_ACK_RH3 Y6 SLP_S4# 10/23 Change netPCH_GPIO51 B13name to TBT_RR_GPIO# PIRQF#/GPIO3 0_0402_5% RH96 B [30] SUS_PWR_ACK SLP_S4# [45] +3VS RH97 0_0402_5% DRAMPWROK SUSCLK/GPIO62 RH147 100K_0402_5%GPIO52 L15 @ T87 PAD~D ON/OFFBTN# J2 Y7 SLP_S3# Camera_ONC12 PIRQG#/GPIO4 [30,5] ON/OFFBTN# SLP_S3# [30,31,34,45] [22] Camera_ON 11/06 Change PCH.D2 pin connection to DDR3_SET RSMRST# SLP_S5#/GPIO63 GPIO54 M15 2PLTRST# 1 AC_PRES_OUT SIO_SLP_A# 10/25 Add R247 TBT_RR_GPIO# PIRQH#/GPIO5 [30,35] AC_PRES_OUT 1 2 J4 C6 SIO_SLP_A# [30,31,46] [39] TBT_RR_GPIO#1 2 C10 SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# GPIO51 AD10 T88 PAD~D @ PME# [30] BATLOW# BATLOW# K1 H1 SIO_SLP_SUS# A10 PWRBTN# SLP_S3# SIO_SLP_SUS# GPIO53 T89 PAD~D @ LYNXPOINT_BGA695 5 OF 11 Y11 PCH_RI# E6 F3 H_PM_SYNC AL6 PLTRST# ACPRESENT/GPIO31 SLP_A# H_PM_SYNC [5] GPIO55 @ T90 PAD~D SLP_LAN#_R SLP_LAN# +3V_PCH K7 F1 SLP_LAN# [29,30] 10/17 ChangeBATLOW#/GPIO72 R614.1 connection to +3V_PCH SLP_SUS# RH247 10K_0402_5% CH20 DDR3_SET 10/18 Change R614 to 10K ohms, and connection R614.1 to PM_RSMRST# [45] DDR3_SET N4 AY3 10/23 UninstallRI# Q79, R614 PMSYNCH 12/12 Delete Q79, R615 07/18 Add QH12 to invertion PCH_GPIO55 signal 10/25 Delete RH98, RH99, RH100. Add RP9 0.1U_0402_16V4Z AB10 G5 1 2 07/23 Move QH12 to S/B. TP21LYNXPOINT_BGA695 4 OF 11 SLP_LAN# D208/10 Change UH7.5 connection to +3V_PCH power rail 1 2 SLP_WLAN#/GPIO29 UH3 5 PLTRST# PLT_RST# PLT_RST# [13,25,28,29,30,35,37,39,5]07/16 Add for ESD's request VCC

08/10 Change RH235 to 0ohms RP9 MC74VHC1G08DFT2G_SC70-51 IN1 GND 4 @ Boot BIOS Strap OUT CH107 PCH_CRT_BLU 2 3 22P_0402_50V8J PCH_CRT_GRN IN2 PCH_GPIO51 SATA1GP/ PCH_CRT_RED Boot BIOS Location GPIO19 1 9/13 Delete UH7, RH235. Move RH236, CH106 to page 31 8 1 150_1206_8P4R_1% 7 2 00 LPC 6 3 ENVDD_PCH 5 RH1014 100K_0402_5% 2

A 0 1 Reserved (NAND) A

1 0 PCI 1 2 Compal Electronics, Inc. 11 SPI Title

Security Classification Size Document Number Rev Issued Date 2012/03/23 Deciphered Date 2011/06/29 Custom 0.5 Date: Thursday, December 20, 2012 Sheet 14of 56

Compal Secret Data

5 4 3 2 1 PCH -DMI,FDI,PM,DP,CRT LA-9241P

+3V_PCH 10K_0402_5% 2 RH106 1 GFX_CLK_REQ# D D

07/23 Delete FN14 and FN15 off page symbol

LPT_PCH_M_EDS 09/11 Delete RH107, RH103, RH203, RH114, RH116, UH1C REV = 5 RH205, RH122, RH124, RH126, RH127, RH128, RH130

Y43 AB35 CLK_PCIE_VGA# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# [35] Y45 AB36 CLK_PCIE_VGA DGPU_PWR_EN [14,35] CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA [35]

2 1 AB1 AF6 2 +3V_PCH RH104 10K_0402_5% GFX_CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47 2N7002KW_SOT323-3 AA44 Y39 1 3 07/06 Follow HP's GPIO table [39] CLK_PCIE_CR# AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B PEG_CLK_REQ# [35] [39] CLK_PCIE_CR RH109 2 1 CLKOUT_PCIE_P_1 Y38 2 1 +3VS RH105 10K_0402_5% +3V_PCH AF1 CLKOUT_PEG_B_P 10K_0402_5%GG Q55 [39] CR_CLK_REQ# PCIECLKRQ1#/GPIO18 U4 WLAN_TRAMSIT_OFF# WLAN_TRAMSIT_OFF# [25] AB43 PEGB_CLKRQ#/GPIO56 [39] CLK_TB_REFCLK# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI# CLK_CPU_DMI#DD SS [5] AB45 CLKOUT_DMI [39] CLK_TB_REFCLK CLKOUT_PCIE_P_2 AF40 CLK_CPU_DMI CLK_CPU_DMI [5] 2 1 AF3 CLKOUT_DMI_P +3VS RH113 10K_0402_5% PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL# CLK_CPU_SSC_DPLL# [5] [39] TB_CLKREQ# AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL [5] C AD45 CLKOUT_PCIE_N_3 CLKOUT_DP_P C 2 1 T3 CLKOUT_PCIE_P_3 AF35 CLK_CPU_DPLL# +3V_PCH RH118 10K_0402_5% CLK_CPU_DPLL# [5] PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL [5] AF43 CLKOUT_DPNS_P AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# RH1212 1 10K_0402_5% V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI +3V_PCH PCIECLKRQ4#/GPIO26 CLKIN_DMI_P AE44 AR24 [39] CLK_PCIE_EXP# CLK_BUF_BCLK# AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 [39] CLK_PCIE_EXP CLK_BUF_BCLK CLKREQ_EXP# AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P [39] CLKREQ_EXP# 2 1 PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96# +3V_PCH RH125 10K_0402_5% AB40 CLKIN_DOT96N G33 08/06 Change ball name [29] CLK_PCIE_LAN# CLK_BUF_DOT96 AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P [29] CLK_PCIE_LAN CLK_PCIE_LAN_REQ1# AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD# [29] CLK_PCIE_LAN_REQ1# 2 1 PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD +3V_PCH RH128 10K_0402_5% AJ44 CLKIN_SATA_P [25] CLK_PCIE_MINI1# CLKOUT_PCIE_N_7 F45 CLK_PCH_14M AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK [25] CLK_PCIE_MINI1 11/01 Change YH2 to 2 1 CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK small package +3V_PCH RH131 10K_0402_5% MINI1_CLKREQ# Y3 AM43 XTAL25_IN [25] MINI1_CLKREQ# PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT 1 2 AH43 XTAL25_OUT RH132 1M_0402_5% CLKOUT_ITPXDP C40 AH45 CLKOUTFLEX0/GPIO64 PAD~D T91 @ YH2 2 1 CLKOUT_ITPXDP_P F38 SIO_14M 2 1 3 1 [30] CLK_PCI_KBC RH135 10_0402_5% RH136 22_0402_5% CLK_SIO_14M [32] 2 1 CLK_PCI0 D44 CLKOUTFLEX1/GPIO65 OUT IN [32] CLK_PCI_SIO RH137 10_0402_5% CLKOUT_33MHZ0 F36 4 2 CLK_PCI_LOOPBACK RH1382 1 22_0402_5% PCI_LOOPBACKOUT E44 CLKOUTFLEX2/GPIO66 PAD~D T92 @ NC NC 10/25 Delete RH141, RH234, RH139. Add RP10. CLKOUT_33MHZ1 F39 25MHZ_20PF_5YEA2500020BIF50Q3 CLK_PCI2 B42 CLKOUTFLEX3/GPIO67 18P_0402_50V8J 18P_0402_50V8J RP10 CLKOUT_33MHZ2 AM45 ICLK_IREF 1 2 ICLK_IREF +1.5VS 10/25 Delete RH108, RH110, RH111, RH112. Add RP11 8 1 F41 0_0402_5% RH140 1 1 B 7 2 CLKOUT_33MHZ3 AD39 B [28] CLK_PCI_TPM CH21 6 3 CLK_PCI4 A40 TP19 AD38 [30] CLK_PCI_DEBUG_KBC CH22 5 4 CLKOUT_33MHZ4 TP18 [25] CLK_PCI_DEBUG AN44 PCH_CLK_BIASREF 1 2 2 2 DIFFCLK_BIASREF +1.5VS 22_1206_8P4R_5% CLOCK SIGNAL 7.5K_0402_1% RH142

LYNXPOINT_BGA695 2 OF 11 PCIECLK REQ Pull UP Power Rail:

SUS Rail : 0 3 4 5 6 7 RP11 CLK_BUF_DMI 1 8 Core Rail: 1 2 CLK_BUF_DMI# 2 7 CLK_BUF_BCLK 3 6 CLK_BUF_BCLK# 4 5

10K_8P4R_5%

CLK_BUF_DOT96# RH1151 2 10K_0402_5% CLK_BUF_DOT96 RH1171 2 10K_0402_5%

CLK_BUF_CKSSCD# RH1191 2 10K_0402_5% CLK_BUF_CKSSCD RH1201 2 10K_0402_5%

CLK_PCH_14M RH1231 2 10K_0402_5%

A A

CLOCK TERMINATION for FCIM and need close to PCH Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 15of 56 5 4 3 2 1 www.vinafix.vn PCH- CLK LA-9241P

+3V_PCH

+3VS FPR_OFF 2 1 10K_0402_5% RH143 MEM_SMBCLK 2 1 2.2K_0402_5% RH144 MEM_SMBDATA08/07 Install 2RH148 and1 change value to 2.2K 2.2K_0402_5% RH146

2 10/18 Uninstall RH148 2N7002DWH_SOT363-6 DDR_RST_EN07/06 Add for 2NFC @function1 2.2K_0402_5% RH148 MEM_SMBCLK 6 1 NFC_RST# 2 1 DDR_XDP_WAN_SMBCLK [11,12,13,28,38,5] 10K_0402_5% RH149 QH3A SML1_SMBCLK 1 2 5 2.2K_0402_5% RH150 D SML1_SMBDATA 1 2 D MEM_SMBDATA 3 4 2.2K_0402_5% RH151 DDR_XDP_WAN_SMBDAT [11,12,13,28,38,5] 2N7002DWH_SOT363-6 10/09 Change to RH152, RH153 to 499ohms +3VS QH3B 11/09 Change RH152, RH153 to 2.2K ohms 1 2 SIRQ +3VM_LAN RH145 10K_0402_5% LAN_SMBCLK 2 1 2.2K_0402_5% RH152 UH1D LPT_PCH_M_EDSREV = 5 LAN_SMBDATA 2 1 2.2K_0402_5% RH153

07/06 Add for NFC function N7 FPR_OFF FPR_OFF [28] LPC_LAD0 A20 SMBALERT#/GPIO11 +3VS +3VS +3VS [25,28,30,32] LPC_LAD0 LAD_0 SMBus R10 MEM_SMBCLK LPC_LAD1 C20 SMBCLK [25,28,30,32] LPC_LAD1 LAD_1 U11 MEM_SMBDATA RH238 RH239 1 1 LPC_LAD2 A18 LPC SMBDATA 2.2K_0402_5% 2.2K_0402_5% [25,28,30,32] LPC_LAD2 LAD_2 N8 DDR_RST_EN DDR_RST_EN [5] LPC_LAD3 C18 SML0ALERT#/GPIO60 @ @ [25,28,30,32] LPC_LAD3 LAD_3 U8 LAN_SMBCLK LPC_LFRAME# B21 SML0CLK LAN_SMBCLK [29] 07/06 Add for NFC function 2 2 [25,28,30,32] LPC_LFRAME# 2 LFRAME# R7 LAN_SMBDATA 2N7002DWH_SOT363-6 D21 SML0DATA LAN_SMBDATA [29] [32] LPC_LDRQ0# LDRQ0# H6 NFC_RST# LAN_SMBCLK 6 @ 1 G20 SML1ALERT#/PCHHOT#/GPIO74 NFC_RST# [39] NFC_3S_SMBCLK [39] LDRQ1#/GPIO23 K6 SML1_SMBCLK QH10A SIRQ AL11 SML1CLK/GPIO58 5 [28,30,32] SIRQ SERIRQ N11 SML1_SMBDATA SML1DATA/GPIO75 LAN_SMBDATA 3 @ 4 C NFC_3S_SMBDAT [39] C AF11 CL_CLK1 2N7002DWH_SOT363-6 CL_CLK1 [25] PCH_SPI_CLK 1 2 PCH_SPI_CLK_R AJ11 SPI CL_CLK [30] PCH_SPI_CLK QH10B RH154 5_0402_1% SPI_CLK AF10 CL_DATA1 PCH_SPI_CS0# 1 2 PCH_SPI_CS0#_R AJ7 C-Link CL_DATA CL_DATA1 [25] [30] PCH_SPI_CS0# RH155 5_0402_1% SPI_CS0# AF7 CL_RST1# AL7 CL_RST# CL_RST1# [25] SPI_CS1# 2N7002DWH_SOT363-6 AJ10 QH9A SPI_CS2# BA45 SML1_SMBCLK 1 6 PCH_SPI_SI 2 1 PCH_SPI_SI_R AH1 TP1 PCH_KBC_I2CLK [30,35] [30] PCH_SPI_SI 07/19 RH156Add RH242 and RH243 5_0402_1% SPI_MOSI BC45 PCH_SPI_SO07/26 Install2 RH242 and1 RH244PCH_SPI_SO_R AH3 Thermal TP2 [30] PCH_SPI_SO 2 +3V_PCH RH157 5_0402_1% SPI_MISO BE43 QH9B PCH_SPI_WP# 1 2 PCH_SPI_WP#_R AJ4 TP4 SML1_SMBDATA 4 3 [30] PCH_SPI_WP# PCH_KBC_I2CDAT [30,35] RH242 15_0402_5% SPI_IO2 BE44 PCH_SPI_HOLD# 1 2 PCH_SPI_HOLD#_RAJ2 TP3 2N7002DWH_SOT363-6 [30] PCH_SPI_HOLD# RH243 15_0402_5% SPI_IO3 AY43 PCH_TD_IREF 1 2

5 +3V_PCH TD_IREF RH158 8.2K_0402_1%

LYNXPOINT_BGA695 3 OF 11

07/30 Add CH113 by RF request. PCH_SPI_CLK

@ CH113 07/09 Delete by HP request. 22P_0402_50V8J 2 B B

H1 H2 H6 H7 H8 H9 H10 H19 H20 H21 H22 H24 H25 H26 H_3P0 H_3P3 H_3P8 H_3P8 H_3P0 H_3P8 H_3P8 H_4P8X3P8 H_4P3 H_3P8 H_4P8X3P8 H_3P3 H_2P8 H_3P3 ZZZ1

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @ @ @ @ @ @ @ @ @ @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PCB MB

H27 H28 H29 H30 H31 H33 H35 H37 H38 H40 H42 H43 H44 H45 H_3P3 H_3P3 H_3P3 H_3P0 H_3P8 H_3P1N H_3P8 H_3P0 H_3P8 H_3P0 H_2P8 H_2P8 H_2P4X3P9N H_3P8X4P8N

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

07/20 Modify screw hole @ @ @ @ @ @ @ @ @ @ 07/23@ Modify@ screw @hole @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 08/06 Delete H23 09/12 Delete H4, H32, H34, H41. Add H42, H43, H44, H45, H46 09/21 Add H47, H48

H46 H47 H48 H49 H50 H_3P8 H_3P0N H_3P0N H_3P3 H_3P0 FD1 FD2 FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

A @ @ @ @ @ @ @ @ @ A 1 1 1 1 1 1 1 1 1

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 16of 56 5 4 3 2 1 www.vinafix.vn PCH - SPI, SMBUS,LPC LA-9241P

D D

07/17 Add by HP request.

UH1I REV = 5

PCIE_PRX_DTX_N1 AW31 B37 USBP0- [39] PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 AY31 PERN1/USB3RN3LPT_PCH_M_EDS USB2N0 D37 USBP0+ USBP0- [33] [39] PCIE_PRX_DTX_P1 ----->Docking USB 3.0 PERP1/USB3RP3 USB2P0 A38 USBP1- USBP0+ [33] USBP1- [40] CH1081 2 0.1U_0402_10V7K PCIE_PTX_DRX_N1 BE32 USB2N1 C38 USBP1+ [39] PCIE_PTX_C_DRX_N1 USBP1+ [40] ----->USB 3.0 Walkup port 2 CH1091 2 0.1U_0402_10V7K PCIE_PTX_DRX_P1 BC32 PETN1/USB3TN3 USB2P1 A36 [39] PCIE_PTX_C_DRX_P1 PETP1/USB3TP3 USB2N2 C36 ----->NA PCIE_PRX_DTX_N2 AT31 USB2P2 A34 [39] PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 AR31 PERN2/USB3RN4 USB2N3 C34 [39] PCIE_PRX_DTX_P2 ----->NA PERP2/USB3RP4 USB2P3 B33 USBP4- 1 2 PCIE_PTX_DRX_N2 BD33 USB2N4 D33 USBP4+ USBP4- [39] [39] PCIE_PTX_C_DRX_N2 CH110 0.1U_0402_10V7K ----->USB 3.0 Walkup port 3 1 2 PCIE_PTX_DRX_P2 BB33 PETN2/USB3TN4 USB2P4 F31 USBP5- USBP4+ [39] [39] PCIE_PTX_C_DRX_P2 CH111 0.1U_0402_10V7K PETP2/USB3TP4 USB2N5 G31 USBP5+ USBP5- [39] ----->USB 3.0 Walkup port 4 USB2P5 K31 USBP6- USBP5+ [39] PCIE_PRX_DTX_N3 AW33 USB2N6 L31 USBP6+ USBP6- [39] [39] PCIE_PRX_DTX_N3 USBP6+ [39] ----->Express card slot PCIE_PRX_DTX_P3 AY33 PERN_3 USB2P6 G29 USBP7- [39] PCIE_PRX_DTX_P3 USBP7- [37] PERP_3 USB2N7 H29 USBP7+ USBP7+ [37] ----->Smart card reader CH271 2 0.1U_0402_10V7K PCIE_PTX_DRX_N3 BE34 USB2P7 A32 USBP8- [39] PCIE_PTX_C_DRX_N3 USBP8- [28] CH281 2 0.1U_0402_10V7K PCIE_PTX_DRX_P3 BC34 PETN_3 USB2N8 C32 USBP8+ [39] PCIE_PTX_C_DRX_P3 USBP8+ [28] ----->Finger Print Reader PETP_3 USB2P8 A30 USBP9- PCIE_PRX_DTX_N4 AT33 USB2N9 C30 USBP9+ USBP9- [39] [39] PCIE_PRX_DTX_N4 ----->Walkup USB 2.0 port PCIE_PRX_DTX_P4 AR33 PERN_4 USB2P9 B29 USBP10- USBP9+ [39] [39] PCIE_PRX_DTX_P4 PERP_4 USB2N10 D29 USBP10+ USBP10- [22] USBP10+ [22] ----->USB Camera C CH291 2 0.1U_0402_10V7K PCIE_PTX_DRX_N4 BE36 USB2P10 A28 USBP11- C [39] PCIE_PTX_C_DRX_N4 USBP11- [33] CH301 2 0.1U_0402_10V7K PCIE_PTX_DRX_P4 BC36 PETN_4 USB2N11 C28 USBP11+ [39] PCIE_PTX_C_DRX_P4 PETP_4 USB2P11 USBP11+ [33] ----->Docking USB 2.0 port PCIe G26 USBP12- AW36 USB2N12 F26 USBP12- [25] [39] PCIE_PRX_EXPTX_N5 PCIE_PRX_EXPTX_N5 USBP12+ ----->WWAN PCIE_PRX_EXPTX_P5 AV36 PERN_5 USB2P12 F24 USBP13- USBP12+ [25] [39] PCIE_PRX_EXPTX_P5 USB USB PERP_5 USB2N13 G24 USBP13+ USBP13- [25] USBP13+ [25] Express card slot CH1001 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_N5_C BD37 USB2P13 ----->BT/WLAN Combo [39] PCIE_PTX_EXPRX_N5 CH991 2 0.1U_0402_10V7K PCIE_PTX_EXPRX_P5_C BB37 PETN_5 [39] PCIE_PTX_EXPRX_P5 PETP_5 AR26 USB3RN1 USBRBIAS PCIE_PRX_DTX_N6 AY38 USB3RN1 AP26 USB3RP1 USB3RN1 [33] [29] PCIE_PRX_DTX_N6 ----->Docking USB 3.0 22.6_0402_1% PCIE_PRX_DTX_P6 AW38 PERN_6 USB3RP1 BE24 USB3TN1 USB3RP1 [33]

[29] PCIE_PRX_DTX_P6 USB3TN1 [33] 1 PERP_6 USB3TN1 BD23 USB3TP1 USB3TP1 [33] RH159 GIGA LAN CH311 2 0.1U_0402_10V7K PCIE_PTX_DRX_N6 BC38 USB3TP1 AW26 USB3RN2 [29] PCIE_PTX_C_DRX_N6 USB3RN2 [40] 1 2 PCIE_PTX_DRX_P6 BE38 PETN_6 USB3RN2 AV26 USB3RP2 [29] PCIE_PTX_C_DRX_P6 CH32 0.1U_0402_10V7K ----->USB 3.0 Walkup port 2 PETP_6 USB3RP2 BD25 USB3TN2 USB3RP2 [40] PCIE_PRX_DTX_N7 AT40 USB3TN2 BC24 USB3TP2 USB3TN2 [40] [25] PCIE_PRX_DTX_N7 USB3TP2 [40] 2 PCIE_PRX_DTX_P7 AT39 PERN_7 USB3TP2 AW29 USB3RN5 [25] PCIE_PRX_DTX_P7 USB3RN5 [39] PERP_7 USB3RN5 AV29 USB3RP5 USB3RP5 [39] ----->USB 3.0 Walkup port 3 WLAN CH331 2 0.1U_0402_10V7K PCIE_PTX_DRX_N7 BE40 USB3RP5 BE26 USB3TN5 [25] PCIE_PTX_C_DRX_N7 USB3TN5 [39] CH341 2 0.1U_0402_10V7K PCIE_PTX_DRX_P7 BC40 PETN_7 USB3TN5 BC26 USB3TP5 [25] PCIE_PTX_C_DRX_P7 PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 [39] 10/26 Change PCH.P3 and RPH2.4 connection to WWAN_DET#_PCH USB3RN6 [39] 09/11 Change RPH1.3 PCIE_PRX_DTX_N8 AN38 USB3RN6 AP29 USB3RP6 [39] PCIE_PRX_DTX_N8 CAD NOTE: connection to TB_HOT_PLUG# PCIE_PRX_DTX_P8 AN39 PERN_8 USB3RP6 BD27 USB3TN6 USB3RP6 [39] ----->USB 3.0 Walkup port 4 [39] PCIE_PRX_DTX_P8 PERP_8 USB3TN6 USB3TN6 [39] Route single-end 50-ohms and max 500-mils length. BE28 USB3TP6 07/23 Delete off page symbol Card Reader 1 2 PCIE_PTX_DRX_N8 BD42 USB3TP6 USB3TP6 [39] Avoid routing next to clock pins or under stitching capacitors. [39] PCIE_PTX_C_DRX_N8 CH35 0.1U_0402_10V7K 1 2 PCIE_PTX_DRX_P8 BD41 PETN_8 K24 USBRBIAS [39] PCIE_PTX_C_DRX_P8 CH36 0.1U_0402_10V7K Recommended minimum spacing to other signal traces is 15 mils. PETP_8 USBRBIAS# K26 USBRBIAS 1 2 BE30 M33 +1.5VS PCH_PCIE_IREF RH160 0_0402_5% PCIE_IREF TP24 L33 07/18 Change net name to TB_HOT_PLUG# follow HP request. TP23 09/11 Delete RH165 +3V_PCH BC30 P3 WWAN_DET#_PCH WWAN_DET#_PCH [25] B TP11 OC0#/GPIO59 V1 USB_OC1#_R RPH1 B OC1#/GPIO40 U2 USB_OC2# USB_OC4#_R 4 5 BB29 OC2#/GPIO41 P1 USB_OC3# TB_HOT_PLUG# 3 6 TP6 OC3#/GPIO42 M3 USB_OC4#_R LED_LINK_LAN#_R 2 7 OC4#/GPIO43 T1 dGPU_HPD_INTR USB_OC3# 1 07/238 Modify pin define for layout smooth dGPU_HPD_INTR [35] 1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 +1.5VS LED_LINK_LAN#_R [29] RH164 7.5K_0402_1% PCIE_RCOMP OC6#/GPIO10 M1 10K_1206_8P4R_5% OC7#/GPIO14 TB_HOT_PLUG# [39] RPH2 LYNXPOINT_BGA695 9 OF 11 WWAN_DET#_PCH 4 5 dGPU_HPD_INTR 3 6 USB_OC2# 2 7 USB_OC1#_R 1 8

10K_1206_8P4R_5%

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 17of 56 5 4 3 2 1 www.vinafix.vn PCH-PCIE,USB LA-9241P

2N7002KW_SOT323-3 Q58 D 1 +3VS 2 +3VS G [30] OCP_PWM_OUT 2 1 S A20GATE 2 1 PCH_GPIO0 UH1F LPT_PCH_M_EDS REV = 5 10K_0402_5% RH166 RH167 10K_0402_5% 3 RCIN# 2 1 2 1 OCP_OC# PCH_GPIO0 AT8 10K_0402_5% RH168 BMBUSY#/GPIO0 RH169 100K_0402_5% 07/23 Correct Net name 2 1 ODD_EN OCP_OC# F13 TACH1/GPIO1 RH171 10K_0402_5% 1 2 DGPU_PWROK EC_SCI# A14 [30] EC_SCI# TACH2/GPIO6 RH175 8.2K_0402_5% THERM_SCI# G15 CPU/Misc TACH3/GPIO7 1 2 DOCK_ID0 PCH_GPIO8 Y1 PCH_GPIO8 GPIO8 10/26 Delete A20GATE off page symbol D RH177 10K_0402_5% D 1 2 DOCK_ID1 LAN_DIS# K13 [29] LAN_DIS# LAN_PHY_PWR_CTRL/GPIO12 AN10 RH172 10K_0402_5% TP14 A20GATE 1 2 KBC_SIO_RST# PCH_GPIO15 AB11 GPIO15 AY1 RH173 10K_0402_5% PECI PAD~D T104@ 1 2 EC_SCI# KBL_DET# AN2 10/29 Change RH179 to 100ohms [38] KBL_DET# SATA4GP/GPIO16 RH178 10K_0402_5% AT6 RCIN# RCIN# RCIN# 1 2 THERM_SCI# DGPU_PWROK C14 GPIO [35] DGPU_PWROK TACH0/GPIO17 RH240 10K_0402_5% AV3 H_CPUPWRGD +1.05VS 07/06 Add PU resistor PROCPWRGD H_CPUPWRGD [5] 1 2 WWAN_TRANSMIT_OFF# WWAN_TRANSMIT_OFF# BB4 [25] WWAN_TRANSMIT_OFF# SCLOCK/GPIO22 RH241 10K_0402_5% AV1 PCH_THERMTRIP#_R 2 1 Y10 THRMTRIP# 0.1U_0402_16V4Z PCH_GPIO24 GPIO24 RH179 100_0402_5% +3V_PCH 07/23 Delete PCH_GPIO24 off page symbol AU4 CPU_PLTRST# PLTRST_PROC# CPU_PLTRST# [5] 07/23 Delete FN_CLK2 off page symbolLANWAKE# R11 1

GPIO27 CH37 08/01[29] ChangeLANWAKE# net name to mSATA_DET# N10 10/26 Change net name to PCH_GPIO_35 AD11 VSS PCH_GPIO28 GPIO28 PCH_THERMTRIP#_R PCH_THERMTRIP#_R [24,35,5] 2 1 PCH_GPIO24 AN6 2 RH182 10K_0402_5% PCH_GPIO34 GPIO34 2 1 PCH_GPIO8 AP1 RH183 10K_0402_5% 10/26 Change net name to PCH_GPIO_36PCH_GPIO_35 GPIO35/NMI# 2 @ 1 LAN_DIS# 07/06 Change for NFC 08/01 Change net name to Sec_HDD_DET AT3 RH184 10K_0402_5%07/23 Follow VBK10. 07/23 Delete PCH_GPIO37 off page symbolPCH_GPIO_36 SATA2GP/GPIO36 2 1 NFC_INT10/24 Install RH185 AK1 RH185 10K_0402_5% PCH_GPIO37 SATA3GP/GPIO37 AT7 DOCK_ID0 SLOAD/GPIO38 AM3 A2 10/24 Change RH176.2 connection to GND. Install RH176 DOCK_ID1 2 1 SDATAOUT0/GPIO39 VSS A41 FPR_LOCK# AN4 VSS A43 RH176 10K_0402_5% FPR_LOCK# 07/06 Change[28] for NFCFPR_LOCK# SDATAOUT1/GPIO48 VSS A44 AK3 VSS B1 DGPU_PRSNT# 07/06 Follow HP's GPIO[35] tableDGPU_PRSNT# SATA5GP/GPIO49 VSS B2 U12 VSS B44 NFC_INT GPIO57 VSS +3VDS 10/25 Add LANWAKE# PU RH248 to +3VDS [39] NFC_INT B45 C16 VSS BA1 C ODD_EN C [23] ODD_EN TACH4/GPIO68 VSS BC1 2 1 D13 VSS BD1 LANWAKE# D3E_WAKE# D3E_WAKE# TACH5/GPIO69 VSS BD2 RH248 100K_0402_5% G13 VSS BD44 KBC_SIO_RST# [30,32] KBC_SIO_RST# TACH6/GPIO70 VSS BD45 H15 VSS BE2 GPS_XMIT_OFF# TACH7/GPIO71 VSS +3V_PCH [25] GPS_XMIT_OFF# BE3 VSS D1 4.7K_0402_5% BE41 VSS E1 BE5 VSS VSS E45

RH193 NCTF 2 C45 VSS VSS A4 A5 VSS VSS VSS 08/01 Change net name to mSATA_DET# 10/26 Change RH180.2 connection to PCH_GPIO_35. 1 Change RH180.1 connection to +3VSLYNXPOINT_BGA695 6 OF 11 PCH_GPIO28 1K_0402_1% 1 2 @ PCH_GPIO15 RH194

1 RH1811 2 1K_0402_1% +3VS PCH_GPIO_35 08/01 Change net name to Sec_HDD_DET RH1801 100K_0402_5%2 10/26 Change netname to PCH_GPIO_36 PCH_GPIO34 RH170 100K_0402_5% 2

PLL ON DIE VR ENABLE 2 1 ENABLED - HIGH(DEFAULT) PCH_GPIO_36 RH1982 1 10K_0402_5% DISABLED - LOW PCH_GPIO37 RH200 10K_0402_5% B B

+3VS 08/03 Delete RH201, RH202 1 2 SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK. KBL_DET# RH1972 1 10K_0402_5% WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER DGPU_PRSNT# RH199 10K_0402_5% PLRST_N DE-ASSERTS). Config GPIO16,49 NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.

USB X4,PCIEX8,SATAX6 11

USB X6,PCIEX8,SATAX4 01

A A

Compal Electronics, Inc.

Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

Compal Secret Data Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 18of 56 5 4 www.vinafix.vn3 2 1 PCH -GPIO,MISC,NTFC LA-9241P

D D

LH1 +VCCADAC 2 1 +1.5VS BLM18PG181SN1D_2P 0.01U_0402_16V7K 0.1U_0402_16V4Z 10U_0603_6.3V6M

1 1 1 CH40 CH41 CH42

2 2 2

UH1G LPT_PCH_M_EDS REV = 5 +1.5VS +1.05VS P45 VCCADAC1_5 AA24 P43 10U_0603_6.3V6M AA26 VCC CRT DAC VSS +1.05VS 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M AD20 VCC M31 1 1 1 1 +3VS 1U_0402_6.3V6K 1 AD22 VCC VCCADACBG3_3

CH38 CH39 CH43 CH44 CH45 @ VCC C AD24 1 C AD26 VCC BB44 CH46 2 2 2 2 AD28 VCC VCCVRM +3VS 2 AE18 VCC FDI AN34 AE20 VCC VCCIO 2 AE22 VCC AN35 AE24 VCC VCCIO +3V_PCH 0.1U_0402_16V4Z VCC AE26 R30 1 AG18 VCC HVCMOS VCC3_3_R30 R32 AG20 VCC VCC3_3_R32 0.1U_0402_16V4Z CH47 AG22 VCC Y12 +PCH_USB_DCPSUS1 T141@ PAD 1 AG24 VCC DCPSUS1 2 Y26 VCC AJ30 CH48 Core VCC VCCSUS3_3 AJ32 VCCSUS3_3 2 +1.05VM AJ26 +PCH_USB_DCPSUS3 +1.5VS T142@ PAD +PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 AA18 DCPSUSBYP DCPSUS3 AK20 +1.05VS U18 VCCASW VCCIO AK26 22U_0805_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K VCCASW VCCVRM +1.5VS 10U_0603_6.3V6M U20 AK28 1 U22 VCCASW VCCVRM @ 1 1 1 CH52 U24 VCCASW BE22 CH49 CH50 CH51 V18 VCCASW VCCVRM

PCIe/DMI 10U_0603_6.3V6M V20 VCCASW AK18 +1.5VS 2 +1.05VS 1 2 2 2 V22 VCCASW VCCIO @ V24 VCCASW AN11 CH53 Y18 VCCASW VCCVRM VCCASW SATA 10U_0603_6.3V6M 2 Y20 AK22 1 Y22 VCCASW VCCIO +1.05VS @ VCCASW AM18 CH54 VCCIO AM20 VCCIO AM22 2 B VCCMPHY VCCIO AP22 B VCCIO 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M AR22 1 1 1 1 1 VCCIO AT22 07/20 Delete CH60, CH62, CH63 VCCIO CH55 CH56 CH57 CH58 CH59

LYNXPOINT_BGA695 7 OF 11 2 2 2 2 2

1 2 +PCH_VCCDSW RH204 5.11_0402_1%~D +PCH_VCCDSW_R 1U_0402_6.3V6K 1 CH61

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 19of 56 5 4 3 2 1 www.vinafix.vn PCH- Power LA-9241P

D D

+3V_PCH 0_0402_5% 2 RH2081 UH1H LPT_PCH_M_EDS REV = 5 0.1U_0402_10V6K 2 110/18 Install RH209. Uninstall RH208 0_0402_5% @ RH20910/23 Install RH208. Uninstall RH209 +3V_PCH +3V_PCH +3VDS 1 CH64 R24 R20 CH104 0.1U_0402_10V6K R26 VCCSUS3_3 VCCSUS3_3 R22 1 2 R28 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 2 1 +1.05VS U26 GPIO/LPC 0.1U_0402_10V6K

CH65 VCCSUS3_3 A16 +PCH_VCCDSW3_3 M24 VCCDSW3_3

0.1U_0402_10V6K VSS AA14 1 2 +3VS DCPSST +PCH_VCCSST 2 +3VS U35 VCCUSBPLL CH66 0.1U_0402_10V6K 1 USB AE14 CH67 L24 VCC3_3 AF12 0.01U_0402_16V7K_X7R 0.1U_0402_10V6K VCC3_3 VCC3_3 AG14

VCC3_3 CH69 U30 +3V_PCH 1 2 CH68 VCCIO 1 +1.05VS V28 V30 VCCIO U36 Y30 VCCIO VCCIO +1.05VS

0.1U_0402_10V6K VCCIO 0.1U_0402_10V7K~D 2 +3V_PCH 2 07/19 Non Install CH101 07/20 Delete CH102 Y35 +1.5VS PAD @ T143 S2 DCPSUS2 Azalia 1 A26 1 CH70 AF34 VCCSUSHDA CH71

10U_0603_6.3V6M VCCVRM 1U_0402_6.3V6K 1 AP45 K8 +RTCVCC 1 2 CH72 +1.05VS_VCC VCC VCCSUS3_3 CH73 2 09/24 Change netname Y32 A6 +1.05VS VCCCLK VCCRTC 0.1U_0402_10V6K 0.1U_0402_10V6K 1U_0402_6.3V6K 2 M29 P14 2 C RTC +PCH_DCPRTC C +3VS VCCCLK3_3 DCPRTC P16 1 2 CH74 0.1U_0402_10V7K~D 1 1CH75 1CH76 CH77 L29 DCPRTC 07/25 Change power rail VCCCLK3_3 +1.05VS 1 2 L26 AJ12 CH1051 2 0.1U_0402_10V6K CH83 0.1U_0402_10V6K M26 VCCCLK3_3 V_PROC_IO AJ14 1 2 09/11 Delete RH226 2 2 2 VCCCLK3_3 CPU V_PROC_IO CH84 1U_0402_6.3V6K U32 VCCCLK3_3 V32 ICC AD12 VCCCLK3_3 VCCSPI +3V_PCH

SPI 1U_0402_6.3V6K AD34 +1.05VS VCCCLK P18 1U_0402_6.3V6K AA30 VCC P20 +3VS AA32 VCCCLK VCC 1 CH79 VCCCLK L17 VCCASW 1 CH92 AD35 Fuse +1.05VM VCCCLK R18 +1.05VS +1.05VS_VCC AG30 VCCASW 2 1 LH2 2 AG32 VCCCLK 2 +1.05VS_VCC VCCCLK AW40 4.7UH_LQM18FN4R7M00D_20% AD36 VCCVRM 10U_0603_6.3V6M 1U_0402_6.3V6K +1.5VS VCCCLK AK30 VCC3_3 +3VS CH80 CH81 1 1 AE30 0.1U_0402_10V6K AE32 VCCCLK Thermal AK32 VCCCLK VCC3_3

2 2 1 CH85

LYNXPOINT_BGA695 8 OF 11 2

B B 09/24 Delete+1.05VS RH213, RH216, and change netname. 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M CH91 CH87 CH88 CH89 CH90

1 CH86 1 1 1 1 1 @ 2 2 2 2 2 2

Place near pin AP45 Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 Place near pin AG30,AG32,AE30,AE32

+3VS 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K CH93 CH94 CH95 CH96

1 1 1 1

2 2 2 2

A Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32 A

Compal Electronics, Inc.

Security Classification Issued Date 2012/03/23 Deciphered Date 2011/06/29 Title

Compal Secret Data Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 20of 56 5 4 www.vinafix.vn3 2 1 PCH - Power LA-9241P

D D

UH1J LPT_PCH_M_EDS REV = 5 UH1K LPT_PCH_M_EDS REV = 5

AL34 K39 AA16 B19 AL38 VSS VSS L2 AA20 VSS VSS B23 AL8 VSS VSS L44 AA22 VSS VSS B27 AM14 VSS VSS M17 AA28 VSS VSS B31 AM24 VSS VSS M22 AA4 VSS VSS B35 AM26 VSS VSS N12 AB12 VSS VSS B39 AM28 VSS VSS N35 AB34 VSS VSS B7 AM30 VSS VSS N39 AB38 VSS VSS BA40 AM32 VSS VSS N6 AB8 VSS VSS BD11 AM16 VSS VSS P22 AC2 VSS VSS BD15 AN36 VSS VSS P24 AC44 VSS VSS BD19 AN40 VSS VSS P26 AD14 VSS VSS AY36 AN42 VSS VSS P28 AD16 VSS VSS AT43 AN8 VSS VSS P30 AD18 VSS VSS BD31 AP13 VSS VSS P32 AD30 VSS VSS BD35 AP24 VSS VSS R12 AD32 VSS VSS BD39 AP31 VSS VSS R14 AD40 VSS VSS BD7 AP43 VSS VSS R16 AD6 VSS VSS D25 C AR2 VSS VSS R2 AD8 VSS VSS AV7 C AK16 VSS VSS R34 AE16 VSS VSS F15 AT10 VSS VSS R38 AE28 VSS VSS F20 AT15 VSS VSS R44 AF38 VSS VSS F29 AT17 VSS VSS R8 AF8 VSS VSS F33 AT20 VSS VSS T43 AG16 VSS VSS BC16 AT26 VSS VSS U10 AG2 VSS VSS D4 AT29 VSS VSS U16 AG26 VSS VSS G2 AT36 VSS VSS U28 AG28 VSS VSS G38 AT38 VSS VSS U34 AG44 VSS VSS G44 D42 VSS VSS U38 AJ16 VSS VSS G8 AV13 VSS VSS U42 AJ18 VSS VSS H10 AV22 VSS VSS U6 AJ20 VSS VSS H13 AV24 VSS VSS V14 AJ22 VSS VSS H17 AV31 VSS VSS V16 AJ24 VSS VSS H22 AV33 VSS VSS V26 AJ34 VSS VSS H24 BB25 VSS VSS V43 AJ38 VSS VSS H26 AV40 VSS VSS W2 AJ6 VSS VSS H31 AV6 VSS VSS W44 AJ8 VSS VSS H36 AW2 VSS VSS Y14 AK14 VSS VSS H40 F43 VSS VSS Y16 AK24 VSS VSS H7 AY10 VSS VSS Y24 AK43 VSS VSS K10 AY15 VSS VSS Y28 AK45 VSS VSS K15 AY20 VSS VSS Y34 AL12 VSS VSS K20 AY26 VSS VSS Y36 AL2 VSS VSS K29 AY29 VSS VSS Y40 BC22 VSS VSS K33 AY7 VSS VSS Y8 BB42 VSS VSS BC28 B11 VSS VSS VSS VSS B15 VSS VSS LYNXPOINT_BGA695 11 OF 11

B LYNXPOINT_BGA695 10 OF 11 B

A A

Compal Electronics, Inc. Security Classification 2012/03/23 Deciphered Date 2011/06/29 Issued Date Compal Secret Data Title

Size Document Number Rev Custom 0.5

Date: Thursday, December 20, 2012 Sheet 21of 56 5 4 3 2 1 www.vinafix.vn PCH - GND LA-9241P

+3VDS ON W=60mils +LCDVDD C21 C3 1 1 1 @ 1 68P_0402_50V8J 1 7 0402 NPO J50V82P 680P_0402_50V7K SM010014520 3000ma C393 C497 C499 C394 10U_0603_6.3V6M 0.1U_0402_16V4Z VIN VOUT 220ohm@100mhz 2 1@ 1 2 8 2 2 2 VIN VOUT 1 2 DCR 0.04 1 @ 18P_0402_50V8J 4.7U_0603_6.3V6K +5VDS 0.1U_0402_16V4Z 18P_0402_50V8J 2 2 08/08 Reserve C449 by RF request 4 2 VBIAS 5 2 eDP PANEL Conn. 6 GND 9 07/23 Add C392 and C394 by RF request 1 C498 CT TPS22965DSGR_SON8_2X2GND 07/23 Add C392 and C394 by RF request W=60mils W=60mils 4700P_0402_16V7K

D 2 D 09/25 Change LCDVDD power rail solution. Delete R9, R10, R11, Q12, Q20, C1, C7, C8 Add U47, C497, C498, C499 Uninstall R494 11/06 Change C498 to 4700pF 07/06 Change for eDP MUX JEDP1

[36] EDP_SW_D3N [36] EDP_SW_D3P 1 2 1 [36] EDP_SW_D2N 2 [36] EDP_SW_D2P 3 4 3 5 4 [36] EDP_SW_D1N 5 [36] EDP_SW_D1P 6 7 6 [35] ENABLT ENABLT R12 [36] EDP_SW_D0N 8 7 2K_0402_5% [36] EDP_SW_D0P 9 8 10 9 [36] EDC_SW_AUX 10 1 R13 2 11 [36] EDC_SW_AUX# 11 1 100K_0402_5% 12 +LCDVDD 13 12 R179 R178 14 13 14 100K_0402_5%2 100K_0402_5% 15 16 15 16 2 1 2 17 +3VS 17 [13] SG_IN 18 EDP_SW_HPD18 +5VS [36] EDP_SW_HPD 19 1 ENABLT_R20 19 [35] INV_PWM INV_PWM 21 20 ENABLT_R +3VS [30,38,39] LID_SW# 21 D_MIC_CLK22 [26] D_MIC_CLK 22 D_MIC_DATA23 9/20 Change to commond part. [26] D_MIC_DATA 24 23 D3 24 R491 C83 25 07/31 Delete Q21,Q22,R454,R14. 25 1 2 100K_0402_5% 0.1U_0402_16V4Z 26 1 [14] Camera_ON 26 +5VS 27 28 27 RB751V-40_SOD323-2 28 1 29 11/01 Delete C23, C80, C82, C111 R15@ 0_0402_5% USB20_P10_R29 30 1 1 USB20_N10_R31 30 L3 2 31

32 4.7U_0603_6.3V6K 1U_0402_6.3V6K USB20_N10_R 2 INVPWR_B+ 33 32 [17] USBP10- 07/31 Delete +5VS_R_LOGO_KBL signal 34 33 2 2 1 2 35 34

USB20_P10_R C22 680P_0402_50V7K INV_PWM C84 C81 [17] USBP10+ 36 35 41 36 G1 ACES_50398-04071-001 WCM-2012-900T_4P 37 42 1 2 38 37 G2 43 CONN@ 1 @ 2 39 38 G3 44 08/03 Swap pin define for layout smooth 39 G4 09/12 Modify JEDP1 symbol and footprint. C R16 0_0402_5% D_MIC_CLK 40 45 C 40 G5 09/13 Modify JEDP1 symbol and footprint. 4 3 2 1 D_MIC_DATA 09/20 Correct circuit short issue, Modify pin define. 4 3 C500 C501

1 2 @ @

09/12 Modify JEDP1 symbol and footprint.

09/251 Reserve1 C500, C501 for ESD request

2 2 10P_0402_25V8K 10P_0402_25V8K

B B

A A

Title

Size Document Number Rev 0.5

Date: Thursday, December 20, 2012 Sheet 22of 56

Security Classification Compal Secret Data Security Classification Compal Electronics, Inc. Issued Date 2011/06/29 Deciphered Date 2011/06/29 eDP/LVDS CONN & Camera LA-9241P 5 4 3 www.vinafix.vn2 1

SATA HDD CONN. Place caps. JHDD1 CONN@ near HDD

1 CONN. GND 2 SATA_PTX_C_DRX_P0 0.01U_0402_16V7K_X7R1 2 C41 SATA_PTX_DRX_P0 [13] A+ 3 SATA_PTX_C_DRX_N0 0.01U_0402_16V7K_X7R1 2 C42 SATA_PTX_DRX_N0 [13] A- 4 SATA_PRX_C_DTX_N0 0.01U_0402_16V7K_X7R C43 GND 5 1 2 SATA_PRX_DTX_N0 [13] SATA_PRX_C_DTX_P0 0.01U_0402_16V7K_X7R C44 B- 6 1 2 SATA_PRX_DTX_P0 [13] B+ 7 GND

8 V33 9 V33 D 10 D V33 11 GND 12 +5VS GND 13 GND 14 V5 15 100mils V5 16 +5VS V5 17 GND

18 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 68P_0402_50V8J Reserved 23 19 1 1 1 1 24 GND GND 20 C45 C46 C47 C48 GND V12 21 V12 22 V12 2 2 2 2 SANTA_199201-1 07/30 Modify JHHD1 footprint.

11/07 Change C48 to 68pF

Placea caps. near HDD CONN.

+5VS +5V_ODD SATA ODD CONN. JODD1 Place caps.

@ near ODD R55 0_0805_5% SATA_PTX_C_DRX_P1 0.01U_0402_16V7K_X7RCONN. C49 SATA_PTX_DRX_P1 [13] 1 2 1 SATA_PTX_C_DRX_N1 0.01U_0402_16V7K_X7R C50 GND 2 1 2 SATA_PTX_DRX_N1 [13] A+ 3 SATA_PRX_C_DTX_N1 0.01U_0402_16V7K_X7R1 2 C51 A- SATA_PRX_DTX_N1 [13] 4 SATA_PRX_C_DTX_P1 0.01U_0402_16V7K_X7R C52 GND 5 1 2 SATA_PRX_DTX_P1 [13] B- 6 1 2 B+ 7 GND R56@ 0_0402_5% +5VS 3 1 Q24 SI2305CDS-T1-GE3_SOT23-3 8 1 2 C 2 DP +5V_ODD C 1 9 C53 S D 14 +5V 10 1U_0402_6.3V6K CC52

1 1 15 GND +5V 11 @ 0.1U_0402_10V6K R57 16 GND MD 12 GND GND 100K_0402_5% 2 G 17 SANTA_203801-113 GND CONN@GND 2

2 R539 ODD_DA# [14] 07/30 Modify JODD1 footprint. ODD_EN# 08/03 Modify JODD1 footprint. D Q25 08/03 Change JODD1 pin 16 and 17 to NC. 100K_0402_5% 10/31 Modify JODD1 footprint. 1 1 2 +5V_ODD G 07/12 Delete C54 and add R539 by HP request ODD_EN [18] ODD_EN S

2 3 2N7002_SOT23-3

07/06 Correct Net name to follow HP GPIO table 10U_0805_10V4K 0.1U_0402_10V6K 0.1U_0402_10V6K 68P_0402_50V8J 1 1 1 1

C55 C56 C57 C58 11/07 Change C58 to 68pF 2 2 2 2

Placea caps. near ODD CONN.

B B

+3VS +3VS mSATAJMINI1 Conn.

C59 C60 1 2 1 2 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 3 4 1 1 5 3 4 6 08/01 Modify SATA bus from port 2 to port 5 7 5 6 8 9 7 8 10 11 9 10 12 2 2 13 11 12 14 13 14 C61 0.01U_0402_16V7K SATA_PRX_C_DTX_P5 15 16 [13] SATA_PRX_DTX_P5 C62 0.01U_0402_16V7K SATA_PRX_C_DTX_N5 17 15 16 18 [13] SATA_PRX_DTX_N5 19 17 18 20 21 19 20 22 C631 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N5 23 21 22 24 [13] SATA_PTX_DRX_N5 23 24 [13] SATA_PTX_DRX_P5 C641 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P5 25 26 27 25 26 28 29 27 28 30 29 30 1 2 +3VS 31 32 1 2 33 31 32 34 35 33 34 36 37 35 36 38 39 37 38 40 41 39 40 42 08/01 DeletemSATA_DET# Q48 and add R565 41 42 [32] mSATA_DET# 43 44 10/26 Delete R565 45 43 44 46 47 45 46 48 49 47 48 50 51 49 BELLW_80003-102350 52 51 CONN@52 53 54 GND1 GND2 07/06 Change value to 10K +3VS R1316 10K_0402_5%

1 2

A A

LA-9241P Title

Size Document Number Rev Compal Secret Data Custom 0.5

Issued Date Date: Thursday, December 20, 2012 Sheet 23of 56 Compal Electronics, Inc.

Security Classification IBEX-M(1/6)-HDA/JTAG/SATA 5 4 3 2 1 2012/03/23 Deciphered Date 2010/03/31

PWM Fan Control circuit +5VS 07/12 Change U3 to TC7SET00 by HP request +5VS [30] TACH_FAN_IN JFAN1 #4/11 change by HP requirement 5 U3 22_0402_5% 1 [30] FAN_PWM 1 1 P 2 INB 2 D4 4 1 R602 C65 3 [30,5] KBC_PROC_HOT# 2 1 2 O 4 3 INA G 4

1 TC7SET00FU _SSOP5 2 1 5 G5 RB751V-40_SOD323-2 R133 3 @ 0.1U_0402_10V6K 6 G6 D +VCCIO_OUT 4.7K_0402_5% ACES_50273-0040N-001 D CONN@

2 C 07/12 Swap JFAN1 pin1 and pin 2 R166

#5/7 change by 1 B HP requirement R17 Q65 +5VS 1 2K_0402_5%2 2 MMBT3904_SOT23-3E 1 2 47K_0402_5% 3

[47,5] KBC_PROC_HOT_R Notes: Place Q65 close CPU side

28K_0402_1% +3VS R1315 R61 U38 C C

1 1 2 10/18 Install R492 and change R492.2 connection to PCH_THERMTRIP#_R 1 150_0402_1%2 5 SET R492 0_0402_5% VCC 08/01 PCH_THERMTRIP#_RChange netname to KBC_PWR_ON [18,35,5] 2 08/01 Change netname to KBC_PWR_ON 4 GMTGND G708T1U 0.1U_0402_16V4Z C66 HYST 3 1 2 OT# 2

B B

A A

Title LA-9241P

Size Document Number Rev Custom 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 24of 56 Issued Date 2012/03/23 Deciphered Date 2011/12/31 Thermal/FAN Compal Electronics, Inc. 5 4 www.vinafix.vn3 2 1

WWAN 07/06 Change to NFCC connector+3V_WWAN 07/24 Modify JMINI3 pin define. 07/25 Modify JMINI3 pin define.

+3V_WWAN @ @ @ WLAN 08/03 Modify JMINI3 footprint

JMINI3 CONN@ C69 39P_0402_50V8J C70 39P_0402_50V8J C71 39P_0402_50V8J 1 2 [13] WWAN_DET# GND 3P3VAUX 3 4 1 1 1 5 GND 3P3VAUX 6 WWAN_FULL_PWR T128@ PAD 7 GND FULL_CARD_PWR_OFF# 8 M_WXMIT_OFF# WLAN&BT Combo module circuits [17] USBP12+ 9 USB_D+ W_DISABLE1# 10 09/10 Delet T128 08/07 Add R567 and connection WW_LED# [17] USBP12- 11 USB_D- LED1# 2 2 2 BT BT #4/13 change by HP requirement R567.1 to WLAN_WKAE# GND 10/16 Install R567 on module on module 10/24 Delete R567 08/07 Add JMINI2.1 net name. Add R568 Enable Disable and connection R586.1 to KBC_DS3_EN 1 12 10/16 Change R568.1 connection to KBC_WAKE#. Delete R64 1 11/06 Change JMINI3.13 13 AUDIO0 14 10K_0402_5% R65 WWAN_DET#_PCH GND_WWAN AUDIO1 connection[17] toWWAN_DET#_PCH signal 15 16 2 1 BT_CRTL HI LO WLAN WWAN_DET#_PCH 09/10 Delet T126WLAN_WAKE# 17 RESERVED AUDIO2 18 RESERVED AUDIO3 +3VS +3VS +3V_AOAC WWAN_RSVD2 19 20 GPS_XMIT_OFF# [18] R5681 @ 2 0_0402_5% 21 GND IUM_RFU 22 +3V_WWAN BT_ON# LO HI [29,30] KBC_WAKE# 23 USB3_TX- UIM_RESET 24 UIM_RST R67 JMINI2 0.01U_0402_16V7K 0.1U_0402_10V6K 4.7U_0805_10V4Z 25 USB3_TX+ UIM_CLK 26 UIM_CLK 1 @ 2 1 2 C72 C73 C74 27 GND UIM_DATA 28 UIM_DATA 2 0_0402_5%WLAN_WAKE# 3 1 2 4 USB3RX- UIM_PWR [14] PCH_PCIE_WAKE# 3 4 29 30 UIM_PWR 1 1 1 5 6 31 USB3RX+ NC 32 1 3 7 5 6 8

GND GNSS0 GG 7 8 33 34 9 10 LPC_LFRAME# NC GNSS1 [15] MINI1_CLKREQ# 9 10 LPC_LFRAME# [16,28,30,32] 35 36 11 12 LPC_LAD3 37 NC GNSS2 38 2 2 2 Q69 13 11 12 14 LPC_LAD3 [16,28,30,32] GND GNSS3 13 14 LPC_LAD2 39 40 2N7002KW_SOT323-3 [15] CLK_PCIE_MINI1# 15 16 LPC_LAD2 [16,28,30,32] DD SS LPC_LAD1 NC GNSS4 [15] CLK_PCIE_MINI1 15 16 LPC_LAD1 [16,28,30,32] 41 42 17 18 LPC_LAD0 D10 RB751V-40_SOD323-2 NC NC 17 18 LPC_LAD0 [16,28,30,32] 43 44 PLT_RST# 19 20 2 1 45 GND NC 46 21 19 20 22 CLK_PCI_DEBUG 47 NC NC 48 [15] CLK_PCI_DEBUG 23 21 22 24 WLAN_TRAMSIT_OFF# [15] 49 NC NC 50 25 23 24 26 PLT_RST# [13,14,28,29,30,35,37,39,5] 51 GND NC 52 [17] PCIE_PRX_DTX_N7 27 25 26 28 53 ANTCTL0 COEX3 54 [17] PCIE_PRX_DTX_P7 29 27 28 30 55 ANTCTL1 COEX2 56 31 29 30 32 11/06 Change JMINI3.65 connection to GND. 57 ANTCTL2 COEX1 58 33 31 32 34 ANTCTL3 SIM_DET 10/24 Add R619, R620, R62133 34 59 60 [17] PCIE_PTX_C_DRX_N7 35 36 RESET# SUSCLK SIM_DET 09/10 Add R599 and R600 35 36 61 62 [17] PCIE_PTX_C_DRX_P7 37 38 PAD @T134 PLT_RST# PEDET 3P3VAUX 37 38 63 64 39 40 USBP13- [17] NGFF_WWAN_PEDET GND 3P3VAUX 39 40 65 66 41 42 USBP13+ [17] 67 GND 3P3VAUX 43 41 42 44 PAD @T135 OC_USB3 +3V_AOAC 43 44 68 R6191 2 0_0402_5% 45 46 GND1 45 46 NGFF_WWAN_USB3_OC 69 R6201 2 0_0402_5% 47 48 WL_LED# GND2 +3V_WWAN 47 48 R6211 2 0_0402_5% 49 50 [16] CL_CLK1 49 50 2 LOTES_APCI0018-P002A R5991 2 10K_0402_5% 51 52 2 [16] CL_DATA1 51 52 WLAN_TRAMSIT_OFF# [16] CL_RST1# 1 WWAN_FULL_PWR R6001 2 10K_0402_5% 53 54 07/16 Add for ESD's request GND1 GND2 @ C375 U5 WWAN_RSVD2 +3V_AOAC BELLW_80003-1023 22P_0402_50V8J

1 6 1 2 CH1 CH4 CONN@ R85 2 5 D Vn Vp 10K_0402_5% 3 4 D8 G

CH2 CH3 +3V_WWAN 1 2 2 S @ S DIO(BR) NUP4301MR6T1 TSOP-6 RB751V-40_SOD323-2 Q28 M_WXMIT_OFF# BT_ON +3V_WWAN [18] WWAN_TRANSMIT_OFF# 2N7002_SOT23-3 1 07/25 JSIM1.7 connection to SUM_DET D9 @ 2 JSIM1 CONN@ 3 5 1 1 +3VDS

GND VCC 3 6 2 18P_0402_50V8J 2 [14] BT_OFF 7 VPP RST 3

C76C76

I/O CLK UIM_PWR 4.7U_0805_10V4Z 0.1U_0402_10V6K Mini Card Power Rating S

4 1 DAN217T146_SC59-3 R81 2 S

NC C77 C78 G UIM_VPP UIM_RST G [39] UIM_VPP Power Primary Power (mA) Auxiliary Power (mA) UIM_DATA UIM_CLK 10K_0402_5% SIM_DET 2 Peak Normal Normal

9 1 1 D GND D 8 1 09/12 ModifyGND JSIM1 symbol and footprint. +3VS 1000 750 1 R83 07/19 Delete C79 2 2 +3V 330 250 250 (wake enable) @ 47K_0402_5% @ R84 3 1 2 2 Q27 For Wireless LAN +1.5VS 500 375 5 (Not wake enable)11/06 Change R458 to 0ohm SI2305CDS-T1-GE3_SOT23-3 07/19 Change power rail to +3VDS 2 HB_5680629-SICR11 220K_0402_1% 10/25[30] DeleteWWAN_DISABLE R89 08/01 Q68 and R459 uninstall 3 11/06 Delete Q68,3 R459 1 +3V_WWAN R457 200K_0402_5% R458 0_0402_5% 1 2 1 2 UIM_PWR 07/31 modify Q4A circuit. +3VDS 08/03 Q4.2 connection to BT_ON 07/19 Delete C85 07/31 Install Q29 and Q31 7W

47K WLAN_DISABLE [30] 1 10K R90 1K_0402_5% 10/24 Add PD R618 10/25 Delete R618 2

+3VS 2 3 6 Q29 Q4A 1 3 WL/BT_LED# +3V_AOAC DTA114YKAGZT146_SOT23-3 2N7002DW T/R7_SOT-363-6 WL/BT_LED# [39] 2 2 1 Q30 +3VDS

1 0.1U_0402_16V4Z 10K 10K AO3413L_SOT23-3 2

WL_LED# BT_ON 3

C86

47K 1 47K Q4B

5 G 2N7002DW T/R7_SOT-363-6 D S 4 1 WL_LED

4 4 2 LA-9241P

1 2 R94 100K_0402_5% WW_LED# Security Classification 3 2012/03/23 Deciphered Date 2010/03/31 WL_LED Q31 Issued Date DTA114YKAGZT146_SOT23-3 Compal Electronics, Inc. Compal Secret Data +3VS Title WWAN/NAND mini

A B C D E Size Document Number Rev 0.5

Date: Thursday, December 20, 2012 Sheet 25of 56

www.vinafix.vn 5 4 3 2 1

Notes: Keep PVDD supply and speaker traces routed on the DGND plane. Keep away from AGND and other analog signals

+3VS +AVDD_CODEC If Sense_A total length is greater than +3VS Place AVDD ,PVDD,and DVDD capacitor close to Codec PLACE CLOSE TO U1 PIN 13 6 inches, chagne C12 to 0.1uF

+5VS RA31 2 2.49K_0402_1% +AVDD_CODEC D 07/23 Delete RA7 D

0.1U_0402_25V6 SENSE_A CA1 1000P_0402_50V7K 2 1 1 1 CA8,CA10 near UA5 PIN45 1 2 CA2 CA5 1 1

CA4CA4 CA9,CA21 near UA5 PIN39 10U_0603_6.3V UA1 1 2 CA3CA3 2 2 CA6CA6 CA7CA7 SENSE_B RA41 2 2.49K_0402_1% +AVDD_CODEC 2 2 1 27 1 1 1 1 0.1U_0402_25V6 0.1U_0402_25V6 DVDD_CORE AVDD1 38 CA13 1000P_0402_50V7K

AVDD2 0.1U_0402_25V6 0.1U_0402_25V6 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 2 CA9CA9

3 45 CA10 CA10 If Sense_B is un-used, then pull high DVDD_IO PVDD1 2 2 2 2 @ 39 CA11 CA11 CA12 CA12 PVDD2 Sense_B to AVDD by 10Kohm resistor CA8 SENSE_A PLACE CLOSE TO U1 PIN 14 0.1U_0402_25V6 0.1U_0402_25V6 9 13 0.1U_0402_25V6 0.1U_0402_25V6 SENSE_A [27]

22P_0402_50V8J SENSE_B 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M DVDD SENSE_A SENSE_B [27] HDA_BITCLK_AUDIO RA9 14 1 2 1 2 SENSE_B DOCK_HP_L_CODEC [27] @ 33_0402_5% @ 28 HP0_PORTA_L 29 DOCK_HP_R_CODEC [27] HP0_PORTA_R External MIC HDA_BITCLK_AUDIO 23 [13] HDA_BITCLK_AUDIO VREFOUT_A 07/06 Delete MIC_SENSE# circuit 6 HP_OUT_L HDA_BITCLK HP_OUT_L [39]Combo Jack HDA_SDOUT_AUDIO 31 HP_OUT_R [13] HDA_SDOUT_AUDIO 5 HP1_PORTB_L 32 HP_OUT_R [39] HDA_SDO HP1_PORTB_R Headphone HDA_SYNC_AUDIO [13] HDA_SYNC_AUDIO 10 19 EXT_MIC_L [27] HDA_SYNC PORTC_L EXT_MIC_JACK [27] HDA_SDI0 SDIN_CODEC 20 [13] HDA_SDI0 2 1 8 PORTC_R 24 VREFOUT_MIC_JACK [27] 33_0402_5% RA11 HDA_SDI VREFOUT_C/GPIO4 HDA_RST_AUDIO# [13] HDA_RST_AUDIO# 11 15 HDA_RST# PORTE_L 9/20 Change to commondEAPD_L part. 16 [30] EC_MUTE# PORTE_R C 1 2 DOCK_LI_L_CODEC C DOCK_LI_L_CODEC [27] DH1 RB751V-40_SOD323-2 17 DOCK_LI_R_CODEC PORTF_L 18 DOCK_LI_R_CODEC [27] +3VS RA27 10K_0402_5% 1 2 47 PORTF_R SPKL+ SPKL+ [27] D_MIC_CLK 10/11 Change RA14 to 0 ohm. D_MIC_CLK_L_C EAPD 40 SPKL- [22] D_MIC_CLK RA12 100_0402_5% 2 1 2 SPK_PORTD_+L 41 SPKL- [27] [22] D_MIC_DATA D_MIC_DATA RA14 0_0402_5% D_MIC_DATA_C 2 1 4 DMIC_CLK/GPIO1 SPK_PORTD_-L SPKR+ SPKR+ [27] Internal SPKR(front stereo speaker) REC_MUTE_LED_CTRL DMIC0/GPIO2 44 SPKR- SPK_PORTD_+R SPKR- [27] [39] MUTE_LED_CNTR MUTE_LED_CNTR 48 43 46 SPDIFOUT0/GPIO3 SPK_PORTD_-R 2 DMIC1/GPIO0/SPDIFOUT1 25 MONO_OUT MONO_INR MONO_IN 10K_0402_5% 36 12 CA142 1 0.1U_0402_25V6 RA16 CA15 CAP+ PCBEEP 1 07/06 Delete MUTE LED circuit

1 4.7U_0603_6.3V6K 21 VREFFILT 22 2 35 CAP2 34 CAP- V- 37 Place close to Codec VREG(+2.5V) 7 DVSS 1 1 1 1 42 26 09/20 Delete RA13, CA20 PVSS AVSS1 30 49 AVSS2 33

PAD 92HD91B2X5NLGXWCX8_QFN48_7X709/03 Change UA1 P/N AVSS3 CA16 CA16 2 CA21 CA21 2 2 2 CA18 CA18 CA19 CA19 10U_0603_6.3V6M 10U_0603_6.3V6M 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K B Place C209,C210,CA87,CA89 close to Codec B

+AVDD_CODEC 1

RA17 REC_MUTE_CTRL_KB [38] D 10K_0402_5%

2 +AVDD_CODEC G RA18

1 2N7002KW_SOT323-3 CA22 S MONO_IN +5VS UA2 REC_MUTE_LED_CTRL CA23@ 0.1U_0402_25V6 1 0.1U_0402_25V62 1 100K_0402_5%2 2 5 3 6 W=40Mil 1 2 1 VOUT CA24@ 0.1U_0402_25V6 2 Q75 VIN 1 1 2 4 CA25@ 0.1U_0402_25V6 RA28 RA20 1 2 3 BYPASS HDA_SPKR RA19 1 10K_0402_5% [13] HDA_SPKR 10K_0402_5% EN CA271 @ 2 0.1U_0402_25V6 1 CA26 1 C87 1 1 07/20 HP's request. 2 QA1A 10K_0402_5% 1 HPA01085DBVR2 SOT23 5P CA29 0.01U_0402_16V7K GND 2 CA301 @ 2 0.1U_0402_25V6 DMN66D0LDW-7_SOT363-6 2 C88 10U_0805_10V6K 2 CA31 2 1 2 RA211 2 0_0805_5% 680P_0603_50V7K 2 SB Beep 0.1U_0402_25V6 CA28 CA28 1 1 2 GND GNDA 2 0.1U_0402_25V6 0.1U_0402_25V6

A A 680P_0603_50V7K 680P_0603_50V7K

Title Compal Electronics, Inc. Issued Date Size Document Number Rev Compal Secret Data Custom 0.5 Security Classification RA53 need under or near UA5 Date: Thursday, December 20, 2012 Sheet 26of 56 2012/03/23 Deciphered Date 2011/06/29 5 4 3 2 Audio IDT 92HD91 1 LA-XXXXP

RA22 Speaker Connector [26] VREFOUT_MIC_JACK JSPKR1 2.2K_0402_5% 6 LA3 G6 SPKR+ 5 EXT_MIC_L2 [26] SPKR+ G5 [26] EXT_MIC_JACK EXT_MIC_L2 [39] SPKR- 4 2 1 [26] SPKR- 4 SPKL+ 3 [26] SPKL+ 3 SPKL- 2 BK1608HS601-T_2P [26] SPKL- 2 1 1 C89 1 ACES_50273-0040N-001 07/16 Delete DA1 for ESD's request CONN@ 1 2 CA36 2200P_0402_50V7K 2200P_0402_50V7K 2200P_0402_50V7K 2200P_0402_50V7K 1 1 1 1 220P_0402_50V7K 1U_0402_6.3V6K 1U_0402_6.3V6K 2 D D 2 2 2 2 CA32CA32 CA33CA33 CA34CA34 CA35CA35 3 2 3 2 DA2 @

@ DA33 2 3 2 1 1 1 1 YSDA0502C C/A SOT-23 1 1 3.3_0402_5% 3.3_0402_5% 3.3_0402_5% 3.3_0402_5% 07/16 Change P/N for ESD's request YSDA0502C C/A SOT-231 1 07/20 Change P/N for ESD's request 2 2 2 2 RA25RA25 RA23RA23 RA26RA26 RA24RA24

7/13 Move to small board

Need place near Audio Codec (UA5)

DOCK Audio +AVDD_CODEC

C U6A C 07/06 Change C91 and C94 to 2.2uF as spec C90 +VREF_EQ 10/11 Change C91 and C94 to 150u MIC_OUT

8 EXT_MIC_L [26] 10/11 Change R97 and R98 to 1% 1U_0603_16V7 C92 P TLV2462CDR_SO8 C91 LA6 3 0.01U_0402_16V7K+ 1 2 1

OUT G [26] DOCK_HP_L_CODEC DLINE_OUT_L [33] 2 R97 2 IN--

150U_B2_6.3VM_R45M 30_0402_1% 4 +AVDD_CODEC BK1608HS601-T_2P C94 LA7 1 2 1 2 2 1 1 R96 [26] DOCK_HP_R_CODEC DLINE_OUT_R [33] R98 150U_B2_6.3VM_R45M 30_0402_1% +AVDD_CODEC BK1608HS601-T_2P C93 100K_0402_5% 100K_0402_5% R103 1 2 1 2 2 1 1

++ CA39 CA40 1 2 220P_0402_50V7K 220P_0402_50V7K 15P_0402_50V8J U6B 20K_0402_1% 20K_0402_1% R100 R101

1 2 2 1 1 1 1 +VREF_EQ 10/11 Change C95 to 0.47U X5R 8

++ 0.1U_0402_16V7K 10/11 Change R102 and R104 to 1% TLV2462CDR_SO8 100K_0402_5% C97P 2 2 CC55 5 2.2U_0402_6.3V6MR105 + 2 2

1 7 C95 6 OUT G LA8 - CC53 6.2K_0402_1% IN- 2 1 4 DOCK_LINE_IN_L BK1608HS601-T_2P R99 10K_0402_5% [26] DOCK_LI_L_CODEC DOCK_LINE_IN_L [33] 0.47U_0603_16V7X

2.2U_0402_6.3V6M R102 2 1 2 CC54 6.2K_0402_1% DOCK_LINE_IN_R C96 [26] DOCK_LI_R_CODEC DOCK_LINE_IN_R [33] EXT_MIC_JACK 1 2 2 1 1 2 1 2 1 2 68P_0402_50V8J 2.2U_0402_6.3V6M R104

B R106 @ @ R107 B 2K_0402_5% 2K_0402_5% 1 1 2 10/11 Non1 install 2R106 and R107 1 1

2 2 2

R167 SENSE_B [26] [39] HP_SENSE# SENSE_A [26] 20K_0402_1% 07/23 Combine with QA1B 11/05 Delete R174, QA1B. HP_SENSE# connection to R167.1 R108 39.2K_0402_1% 20K_0402_1% R109 1 2

10/11 Change to AGND 1 1 Q6A

[33] DOCK_HPS# 2N7002DW-T/R7_SOT363-6 [33] LINE_IN_SENSE 2N7002DW-T/R7_SOT363-6 2 2 Q6B 6 3 100K_0402_5% 100K_0402_5% R110 R111

1 2 51 10/11 Change1 to AGND 10/114 Change to AGND 2 2

A A

Title

Size Document Number Rev C 0.5

Date: Thursday, December 20, 2012 Sheet 27of 56

Issued Date Compal Secret Data Security Classification Deciphered Date CompalAudio Electronics, SPK Conn/Jack/MIC Inc. 5 4 3 2012/03/23 2 2012/10/21 1 www.vinafix.vn LA-9241P

+3VS +3VS +3VDS 1 1

TPM1.2 1 9656@ R113 R114 R112 0_0402_5% 0_0402_5% ACCELEROMETER +3VS 0.1U_0402_16V4Z 9656@ 9635@ 0_0402_5%

1 1 1 2 2 C98 C99 C100 2 1 1 0.1U_0402_16V4Z C101Base I/O Address +3VS RH219 2 2 2 0 = 02Eh 10K_0402_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z* 1 = 04Eh U11 24 19 10 5 2 1 R115 2 D 9635@ D VDD VDD VDD VDD 4.7K_0402_5% ACCEL_INT# ACCEL_INT#10/24 [14] change ACCEL_INT# LPC_LAD0 26 28 LPC_PD#_TPM +3VS connection to U9.11 [16,25,30,32] LPC_LAD0 2 LPC_LAD1 23 LAD0 NC 9 BADD [16,25,30,32] LPC_LAD1 LPC_LAD2 20 LAD1 TESTB1/LRESET# 8

[16,25,30,32] LPC_LAD2 1 LPC_LAD3 17 LAD2 TEST1 R116 U9 [16,25,30,32] LPC_LAD3 LAD3 4.7K_0402_5% 1 9 +3VS 14 TPM_XTALO 1 R117 Vdd_IO INT2 11 NC 13 TPM_XTALI @ 4 INT1 14 [11,12,13,16,38,5] DDR_XDP_WAN_SMBCLK SLB9656TT1.2 NC 9635@ 6 SCL/SPC VDD 2 [11,12,13,16,38,5] DDR_XDP_WAN_SMBDAT 21 4.7K_0402_5% 7 SDA/SDI/SDO 5 [15] CLK_PCI_TPM 22 LCLK 2 R1182 1 10K_0402_5% 8 SDO/SA0 GND 12 T108 PAD @ 2 +3VS [16,25,30,32] LPC_LFRAME# PLT_RST# 16 LFRAME# NC 6 CS GND 10 [13,14,25,29,30,35,37,39,5] PLT_RST# LRESET# GPIO T109 PAD @ RES 27 13 1 1 [16,30,32] SIRQ 1 PM_CLKRUN#_TPM 15 SERIRQ 1 C102 2 RES 15 C103 1 2 7 TEST NC 3 22P_0402_50V8J R121 3 NC RES 16 C104 +3VS PP NC NC RES R119 12 CLK_PCI_TPM 1 R120 2 1 2 0_0402_5% 0.1U_0402_16V7K 10U_0603_6.3V6M

1 07/26 Change U11 symbol and P/N to SLB9656. @ 4.7K_0402_5% NC 2 2

1 HP3DC2 R122 GND GND GND GND @ 33_0402_5% @ 2 9635@ R123 SLB9656TT1.2_TSSOP28 4

0_0402_5% 11 18 25 0_0402_5% 1 2 R124 2 @ 0_0402_5% 9635@ 18P_0402_50V8J +3VS TPM_XTALI C105 1 2 07/06 Delete LED1 2 1 2 1 R127 R126 9635@ @ Y1 9635@ 4.7K_0402_5% 32.768KHZ_12.5PF_FC-135

C 2 1 C 2 TPM_XTALO C106 1 2 9635@ LPC_PD#_TPM 10M_0402_5% 18P_0402_50V8J

9656@ PLT_RST# R1292 1 0_0402_5% BADD

R177 1 2 PM_CLKRUN#_TPM [14,30,32] PM_CLKRUN#

0_0402_5% Finger printer 9635@ 12/12 Add Q85

+3VS #4/15 Correct Net name. 1 C107 12/13 Change netname to FPR_OFF_C 0.1U_0402_16V4Z 2 +5VS JFP1 1 2 7/24 Modify pin define. 9/12 Modify JFP1 footprint R1312 1 0_0402_5% USB20_N8_R 3 1 2 4 [17] USBP8- 3 4 9/18 Modify JFP1 pin define [17] USBP8+ R1302 1 0_0402_5% USB20_P8_R 5 6 9/26 Modify JFP1 pin define to follow ME request. 2 7 5 6 8 B FPR_LOCK# 9 7 8 10 B [18] FPR_LOCK# 1 3 FPR_OFF_C07/16 Change P/N for ESD's request11 9 10 12 [16] FPR_OFF 11 12 ACES_85203-0602N-10 Q85 2 3 CONN@ 2N7002KW_SOT323-3 D11

SCA00000U10 YSLC05CH_SOT23-3 GG 1 DD SS

A LA-9241P A

Security Classification 2012/03/23 Deciphered Date 2006/09/25 Issued Date Compal Secret Data Title

Size Document Number Rev CompalTPM/Gsensor Electronics, Inc. 0.5 Date: Thursday, December 20, 2012 Sheet 28of 56 5 4 www.vinafix.vn3 2 1

W=60mils

+3VM_LAN +3VDS 10/26 Change R376 to 10k. Change R376.1 connection to +3VDS 1 0.1U_0402_16V4Z 22U_0603_6.3V6K R376 C109 1 C110 1 10K_0402_5% C108 1 1U_0402_6.3V6K 2 2 2 SLP_LAN 2 [34] SLP_LAN A 07/20 Change C110 to 22UF A 6 AMT@ Q7A [14,30] SLP_LAN# 2N7002DWH_SOT363-6 2 07/20 Change location to Q7A 1

07/23 Change R128 to 4.7K ohms

+3VM_LAN RJ-45 CONN. U10 07/11 Delete R135 by HP request 1 07/11 Delete R139 by HP request +3VM_LAN LAN_MDIP0 [15] CLK_PCIE_LAN_REQ1# [13,14,25,28,30,35,37,39,5] PLT_RST# LAN_MDIN0 10K_0402_5% R136 JP4 48 13 [15] CLK_PCIE_LAN CLK_REQ_N MDI_PLUS0 LAN_MDIP1 LAN_ACT# 2 R138 300_0603_5% 36 14 LAN_MDIN1 [15] CLK_PCIE_LAN# PE_RST_N MDI_MINUS0 1 MDO3-1 C115 0.1U_0402_10V7K PCIE_PRX_DTX_P6_C 44 17 LAN_MDIP2 1 2 MDO3+2 [17] PCIE_PRX_DTX_P6 PE_CLKP MDI_PLUS1 2 C116 0.1U_0402_10V7K PCIE_PRX_DTX_N6_C 45 18 LAN_MDIN2 @ 680P_0402_50V7K C114 MDO2+3 B [17] PCIE_PRX_DTX_N6 PE_CLKN MDI_MINUS1 07/11 Delete R140, R142 by HP request 4 3 B MDO2-4 1 2 38 20 LAN_MDIP3 1 2 MDO1+5 [17] PCIE_PTX_C_DRX_P6 PETp MDI_PLUS2 5 1 2 39 PCIE PCIE 21 LAN_MDIN3 MDO1-6 [17] PCIE_PTX_C_DRX_N6 MDI MDI LAN_SMBCLK PETn MDI_MINUS2 MDO0+7 6 16 [16] LAN_SMBCLK LAN_SMBDATA 41 23 R144 10K_0402_5% MDO0-8 7 G2 15 07/11 Delete R151,[16] R152LAN_SMBDATA by HP request PERp MDI_PLUS3 +3VM_LAN 8 G1 08/07 Add R569 and connection R569.1 to KBC_DS3_EN 42 24 9 R128 4.7K_0402_5% PERn MDI_MINUS3 10 9 10/16 Change R569.1 connection to KBC_WAKE#+3VM_LAN +3VM_LAN 10 10/25 Add Q63 6 47K_0402_5% 1 LED_LINK_LAN#2 R150 300_0603_5% 11 SVR_EN_N R145 12 11 1 2 1 1 2 13 12 ACES_87212-14G0 MMBT3904_SOT23-3 RSVD1_VCC3P3 @ 680P_0402_50V7K C118 13 CONN@

2 28 1 2 14 LANWAKE#_R SMB_CLK 14 [18] LANWAKE# 31 5 3 2 R569@ 0_0402_5% SMB_DATA VDD3P3_IN C117 1000P_0402_50V7K @ [25,30] KBC_WAKE# Q63 1 2 D12 10/26 Delete R153 11/02 Add C505 [18] LAN_DIS# SMBUS SMBUS 4 C505 10U_0603_6.3V6M SCA00000U10 1 3 2 VDD3P3_4 15 1 2 LANWAKE_N VDD3P3_15 19 1 2 YSLC05CH_SOT23-3 LED_LINK_LAN# VDD3P3_19 LAN_ACT# 3 29 07/16 Change P/N for ESD's request [33] LAN_ACT# LAN_DISABLE_N VDD3P3_29 1 2 BB 26 8 27 LED0 VDD0P9_8 11 1 T110 25 LED1 VDD0P9_11 16 CC EE T111 LED2 VDD0P9_16 +3VM_LAN R154@ 10K_0402_5% LAN_JTAG_TMS LEDLED R155@ 10K_0402_5% LAN_JTAG_TCK 22 32 VDD0P9_22 +1.05VM_LAN 34 JTAG_TDI 37 1 2 XTAL2 33 JTAG_TDO VDD0P9_37 XTAL1 JTAG_TMS LED_LINK_LAN#_R LED_LINK_LAN# R625 0_0402_5% 1 2 35 40 [17] LED_LINK_LAN#_R LED_LINK_LAN_DOCK# [33] JTAG_TCK VDD0P9_40 SHI00004C00 Q34 JTAGJTAG 43 07/06 Add by HP request VDD0P9_43 46 L15 2N7002_SOT23-3 R158 1K_0402_5% 9 VDD0P9_46 47 10 XTAL_OUT VDD0P9_47 4.7UH +-5% 1008HC-472EJFS-A 1 3 1 2 XTAL_IN DELTA_1008HC-472EJFS-A_2P 10/26 Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK# R159 3.01K_0402_1% C504 C373 C350 11/02 Reserve C504. connection to Q34.1.2 Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R. Change C350 to 47u. LAN_DIS# C 1 2 30 7 1 2 C TEST_EN CTRL_0P9 @ CLARKVILLE 1 2 12 49 RBIAS CTRL_0P9 1 1 1

DD SS 10/25 Delete R160, R161, R162, R163. Add RP12 2 2 2 47U_0805_4V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z TS1 LAN_MDIP0 MDO0+ GG

LAN_MDIN0 MDO0- RP12 +V_DAC 07/23 Change C121 to 1000pF 1 24 +V_DAC TD1+ TX1+ C120 0.01U_0402_16V7K 2 23 XTAL1 LAN_MDIP1TD1- TX1- MDO1+ C389 0.1U_0402_16V4Z 75_1206_8P4R_5% 3 22 5 4 LAN_MDIN1TDCT1 TXCT1 MDO1- XTAL2 C390 0.1U_0402_16V4Z 6 3 C121 4 21 7 2 LAN_MDIP2TDCT2 TXCT2 MDO2+ SE120102K90 1 07/23C3912 Add C389, 0.1U_0402_16V4ZC390, C391, C392. 8 1 1000P_1808_3KV 5 20 Y2 LAN_MDIN2TD2+ TX2+ MDO2- 1 C3922 1U_0402_6.3V4Z C124 C125 +V_DAC 6 19 2 C122 C123 33P_0402_50V8J 33P_0402_50V8J 1 2 TD2- TX2- 1 3 MDO0+ +V_DAC 7 18 0.1U_0402_16V4Z 4.7U_0603_6.3V6K MDO0+ [33] TD3+ TX3+ 1 2 D13 @ L16

3 2 1 IN 9/27 Change Y2 to 3225 package. MDO0- LAN_MDIP38 17 MDO3+ MDO0- [33] SCA00000U10

TD3- TX3- 1 1 OUT 1 1 2 1 1 MDO1+ LAN_MDIN3 MDO3- 07/16 Change P/N for ESD's request MDO1+ [33] 9 16 TDCT3 TXCT3 YSLC05CH_SOT23-3 100UH_SSC0301101MCF_0.18A_20% NC NC MDO1- MDO1- [33] 10 15 2 2 4 2 TDCT4 TXCT4350UH_NA0069RLF 2 2 MDO2+ SP050006Y00 MDO2+ [33] 11 14

D TD4+ TX4+ 2 D

25MHZ 18PF CRG3202518 +-20PPM MDO2- MDO2- [33] 12 13

TD4- TX4- 1 MDO3+ MDO3+ [33] Title LA-9241P MDO3- MDO3- [33] Size Document Number Rev 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 29of 56 Issued Date 2012/03/23 Deciphered Date 2009/12/31 Intel 82566 Nineveh Compal Electronics, Inc. 1 2 www.vinafix.vn3 4 5

7/13 Change by HP request +3VDS 07/09 Add by HP request. +3VDS +RTCVCC 07/10 Change R537 to 10K 07/20 Rearrange pin define 08/03 Change R540 to 4.7K LPC Debug Port for layout smooth. 10/16 Change R215.2 to GND 10/16 Delete R540, Q74 07/18 R215 install by HP request. 12/12 Add Q84 RP1 B+ 8 1 KSI0 1 1 1 1 1 1 1 JTAG_RST# 1 2 +3VS 7 2

KSI1 C179 C179 C180 C180 C181 C181 C182 C182 C183 C183 C184 C184 C185 C185 6 3 R215 100K_0402_5% KSI2

5 4 2 KSI3 2 2 2 2 2 2 2 09/10 Delete R216 Q84 07/18 R216 non install by GG HP request. 2N7002KW_SOT323-3 1 3 100K_0804_8P4R_5% JP6 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 7/13 Change by HP request 10/16 Delete C186 NMI_SMI_DBG# [14] 1 2 1

RP2 DD SS 2 1 8 [15] CLK_PCI_DEBUG_KBC 3 KSI7 3 2 7 BATLOW# [14] 4 3 6 KSI6 +RTCVCC LPC_LFRAME# 5 4 Layout note: Close to PIN68 to Close note: Layout PIN14 to Close note: Layout PIN37 to Close note: Layout PIN58 to Close note: Layout PIN84 to Close note: Layout 5 4 5 KSI5 PIN106 to Close note: Layout PIN119 to Close note: Layout 7/13 Add R543 SIRQ 6 KSI4 9/12 Delete R543 7 6 [13,14,25,28,29,35,37,39,5] PLT_RST# 09/12 Change RP1 and RP2 to 100K ohms. PVT_MOSI10/16 Delete R218 10/16 Remove currentNMI_SMI_DBG# VCC1_PWRGD connection to 8 7 Layout note: 2vias to GND 100K_0804_8P4R_5% 07/18 Non install R219 and install R218 JP6.16. Then add aLPC_LAD0 4.7 K resistor between JP6.16 9 8 and new signal VCC1_PWRGD_SUS#. 58 84 106 14 37 119 49 09/10 Delete R219 128U17 68 15 1 2 LPC_LAD1 10 9 FLDATAOUT CAP 10 PCH_SPI_SI 127 C187 4.7U_0805_10V4Z LPC_LAD2 11 [16] PCH_SPI_SI 97 *PVT_MOSI/GPIO54 93 07/18 change net name 12 11 LPC_LAD307/25 change net name 96 FLCS0# *GPIO145 98 1 2 13 12 PCH_SPI_CS0# SIO_SLP_A# 08/07 Change net name *PVT_CS0#/GPIO146 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 *GPIO157/BC_CLK 13

[16] PCH_SPI_CS0# *VBAT R222 0_0402_5% SIO_SLP_A# [14,31,46] PVT_CS# 95 100mA 2mA N2727122599 10/16 Change U7.125 connection to CHRG_RST, TX_STBY_LED# 12/12 Remove R611. Connect JP6.16 to14 VCC1_PWRGD_SUS# A FLDATAIN *GPIO160/BC_DAT SUS_PWR_ACK [14] 14 A PCH_SPI_SO 94 100 U7.126 connection to KBC_WAKE# 8051RX_CAPLED# 15 [16] PCH_SPI_SO *PVT_MISO/GPIO164 *GPIO161/BC_INT# 126 AC_PRES_OUT [14,35] 16 15 7/13 Delete R224 PVT_MISOand R460, beacuse no QW LED and CALC LED 10/23 Add R617 KBC_PWR_ON12/12 Delete R617, R227 8051_RECOVER#/_NUM_LOCK_LED# *JTAG_RST# *GPIO24/I2C3_CLK0 125 1 2 17 16 7/13 Delete R220, R223 and short to make layout easier 10/17 Change R227 toKBC_PWR_ON 10K [34,44] VCC1_PWRGD_SUS# 21 *GPIO25/I2C3_DAT0 R2371 15_0402_5%2 18 17 09/20 Change R227 toKBC_WAKE# 3K [25,29] KSO0 [38] KSO[0..13] 20 KSO0 124 10/16 Connect D21.2 to PM_APWROK.CHRG_RST Install [43] D21. R2351 15_0402_5%2 19 18 KSO0 KSO1 19 KSO1 *GPIO66 R2341 15_0402_5%2 20 19 7/13 Delete R496,R497,R498,R499 KSO1 18 KSO2 123 09/24 Non-install D21 KSO3 1 209/25 Install R237, R235, R234, 21R233,20 R231 KSO3 *GPIO44 21 KSO2 17 122 1 2 KSO2 R233R231 15_0402_5% 15_0402_5% 22 KSO3 16 KSO4 *GPIO135/KBRST 121 JTAG_RST# 23 22

Keyboard/Mouse Interface Keyboard/Mouse D21 RB751V-40_SOD323-2 KSO4 KSO5 *GPIO34/TACH2PWM_OUTKBRST# FET_A [51] 23 13 120 PM_APWROK [14,31] +3VDS 24 KSO5 KSO6 *GPIO133/PWM0FAN_PWM 7/13 Delete R236 24 12 118 FAN_PWM [24] 25 KSO6 10 KSO7 *GPIO136/PWM2 26 G1 BAT_GRNLED# [13,39] KSO7 9 KSO8 107 KBD_PWM_LED G2 KBD_PWM_LED [38] KSO8 8 KSO9 *GPIO30 79 08/07 Change JP6 footprint 7 KSO10 VREF_PCEI 80 1 2 PAD T121@ KSO9 10/12 Add R610. Change U17.85 connection netname to RSMRST#_EC ACES_50238-02471-002 KSO4 KSO10 6 KSO11 *GPIO131/PECI_DATA 81 CPPWR_EN [39] 10/18 Change R610 to 470 ohms PAD T122@ R238 43_0402_1% +1.05VS 7/13 Reserve R541 and R542 for NFC function CONN@ KSO5 KSO11 5 *KSO12/GPIO5 *GPIO7/KSO14H_PECI_R83 *KSO13/GPIO6 *GPIO10/KSO15 H_PECI [5] 7/19 Install R541, R542 KSO12 SLP_S3# [14,31,34,45] 7/26 Add R561, R562. Non install R541, R542 KSO13 8051_RECOVER#/_NUM_LOCK_LED#85 1 2 OUT1/RSMRST# 9/03 Non install R561, R562. install R541, R543 29 86 10/16 Delete R239,1 R2402 8051_RECOVER#/_NUM_LOCK_LED# [38] 9/12 Delete R561, R562. KSI0 *GPIO162/RXD R610 470_0402_5% +3VS 1 8 D44 3 28 RSMRST#_EC87 1 2 4.7K_0804_8P4R_5% [38] KSI[0..7] KSI1 *GPIO165/TXD/HSD_CS1# R541 0_0402_5% 2 7 +3VS KSI0 27 1 2 PM_RSMRST# [14] 3 6 1 26 KSI2 88 NFC_RX [39] TP_CLK PS2_CLK KSI1 R542 0_0402_5% 4 5 25 KSI3 *GPIO23/I2C1_DAT0 89 R252 10K_0402_5% 09/10 Delete R241 and connect EC_MUTE# to KBC.91 directly. TP_DATA KSI2 NFC_TX [39] 24 KSI4 *GPIO22/I2C1_CLK0 90 07/18 Install R242 Delete R242 and connect MAIN_BAT_DET# to KBC.92 directly. SP_CLK 2 KSI3 PCH_KBC_I2CDAT 23 KSI5 *GPIO21/I2C2_DAT0 91 PCH_KBC_I2CDAT [16,35] 10/16 Change R245.1 connection to KBC_WAKE# SP_DATA KSI4 KSI6 *GPIO20/I2C2_CLK0 PCH_KBC_I2CLK 22 92 PCH_KBC_I2CLK [16,35] RP3 KSI5 KSI7 *GPIO105/FAN_TACH1KBC_PROC_HOT# 10/16 Add a 680K PD for U7.102. Change U7.102 connection to PLT_DET. PS2_DATA 101 10/18 Change R615 to 470K KBC_PROC_HOT#ohms [24,5] KSI6 *GPIO140/TACH2PWM_IN 12/12 Change R615 to 100K ohms 10/16 Delete R247 12/12 Change R248 to 100k ohms 1 8 102 EC_MUTE# [26] 4.7K_0804_8P4R_5% BAT54CW_SOT323-3 KSI7 *GPIO45/A20M/PVT_CS#1 +3VDS 2 7 35 1 2 MAIN_BAT_DET# [42] 1 2 3 6 D45 3 *IMCLK/GPIO51 TACH_FAN_IN103 07/25 Change1 net2 name 10/16 Change R248 to 200k ohms. Change TACH_FAN_IN [24] R248.1 connection to VCC1_PWRGD_SUS# 4 5 PS2_CLK 61 *GPIO53/PS2CLK 105 R615 100K_0402_5% 08/10 Add VCC1_PWRGD off page R245symbol 08/07 Change 100K_0402_5% net name PS2_DATA 1 TP_CLK *GPIO50/KCLK *GPIO152/PS2DAT PLT_DET 10/26KBC_WAKE# Delete VCC1_PWRGD off pageR246 symbol 10K_0402_5% [38] TP_CLK 62 4 1 2 KBD_DATA KBD_DATA 66 *GPIO65/KDAT *GPIO11/KSO16KBD_CLK74 ADP_EN KBD_CLK [33] KBD_CLK 2 SP_CLK 67 *GPIO46/EMCLK *GPIO130KBD_DATA R248 100K_0402_5% RP4 [38] SP_CLK SP_DATA *GPIO47/EMDAT ON/OFFBTN# KBD_DATA [33] VCC1_PWRGD_SUS# 1 2 [38] SP_DATA ON/OFFBTN# [14,5] PS2_CLK 1 2 [33] PS2_CLK ADP_PRES [50] 7/13 Delete R244 KBD_CLK PS2_DATA 111 R2551 100K_0402_5%2 [33] PS2_DATA *I2C0_DATA0

SMSC_1322-NU_TQFP-128PSMSC_1322-NU_TQFP-128P 112 TX_STBY_LED# R2571 100K_0402_5%2 BAT54CW_SOT323-3 *I2C0_CLK0 07/20 Add D44 and D45 GeneralGeneral PurposePurpose I/OI/O InterfaceInterface 8051RX_CAPLED# +RTCVCC 55 109 R2631 100K_0402_5%2 CLKRUN# *I2C0_DATA1I2C_MAIN_DAT KBD_PWM_LED R259 10K_0402_5% 57 Access Bus Interface I2C_MAIN_CLK110 I2C_MAIN_DAT [42,43] KBC_PWR_ON 1 2 54 SER_IRQ *I2C0_CLK1 09/12 Delete R249, R251I2C_MAIN_CLK [42,43] 1 2 PCI_CLK 76 73 R4391 10K_0402_5%2 PM_CLKRUN# EC_SCI# *GPIO110I2C_BAY_DAT 08/10 ChangeON/OFFBTN_KBC# R253.2 connectionR268 to VR_ON 10K_0402_5% [14,28,32] PM_CLKRUN# SIRQ I2C_BAY_CLK I2C_BAY_DAT [42] 10/16 Change U17 pin 77 connectionCHRG_ADP_DET to VCC1_PWRGD_SUS# 1 2 [16,28,32] SIRQ Power Mgmt/SIRQ 108 09/10 Delete R253 andI2C_BAY_CLK R549 [42] 1 2 CLK_PCI_KBC 07/18 Non install R253 and install R254. PCH_KBC_I2CDAT R440R441 10K_0402_5% 10K_0402_5% [15] CLK_PCI_KBC 51 *GPIO12/KSO17 59 07/19 Delete R254, Add R549 1 2 EC_SCI# LAD[3] *ADC_TO_PWM_OUT/GPIO41 ON/OFFBTN_KBC# 09/12 Delete R256 PCH_KBC_I2CLK R442 10K_0402_5% [18] EC_SCI# 50 75 ON/OFFBTN_KBC# [33,38] 1 2 LAD[2] *GPIO13 07/18 Non install R258 and install R500 LID_SW# R443 10K_0402_5% 48 60 KSO17 [39] LAD[1] *nRESET_OUT#/GPIO121 OCP_PWM_OUT MAIN_BAT_DET# 09/10 Delete R262, R264. Change pin 71 netname to46 KBC_XTAL1 78 10/15 Reserve R624 and connectionOCP_PWM_OUT to SUSCLK_KBC [18] R4451 10K_0402_5%2 LPC_LAD3 LAD[0] *GPIO141/PWM3 77 KBC_DS3_EN TRAVEL_BAT_DET# R444 10K_0402_5% B 1 [16,25,28,32] LPC_LAD3 09/10 Delete R258, R500 and changeKBC_DS3_EN pin69 netname [45,5] to KBC_XTAL2 B LPC_LAD2 52 VCC1_RST# 38 TACH_FAN_IN [16,25,28,32] LPC_LAD2 12/12 Delete R605 LFRAME# LPC *ADC4/GPIO62 12/12 Install R624 PM_PWROK [14,5] R29507/18 100K_0402_5%Add R546 by HP request. 07/18 Non installLPC_LAD1 R264 and install53 R262 1 2 [16,25,28,32] LPC_LAD1 LPC_LAD0 LRESET# ADP_ID_CHK ON/OFFBTN# 07/18 Non install R266 [16,25,28,32] LPC_LAD0 09/25 Reserve R605 Bus 69 1 2 ADP_ID_CHK [50] 07/25 Change net name 2 *XTAL2 VCC1_PWRGD_SUS# 1 2 C188 09/10 Delete R266, netname MAIN_BAT_DET# 08/07 Change net name R493 100K_0402_5% LPC_LFRAME# 70 10/16 Change EC pin 41 and R436.1 joint 07/18 R436 change to 1K 09/21 R436 change to 100K PD 09/07 Delete TX_STBY_LED# offpage symbol 1U_0402_6.3V6K [16,25,28,32] LPC_LFRAME# R624 0_0402_5% EN_P1V5 [33,39,40,44,45] KBC_SIO_RST# 71 *VSS_VBAT point116 connection to iSCT_LED# 8051_RECOVER#/_NUM_LOCK_LED# [18,32] KBC_SIO_RST# 08/03 Change R437 to 33 ohms 07/24 Change net name*XTAL1 *GPIO163 113 R546 100K_0402_5% KBC_XTAL2 SUSCLK_KBC 10/16 change R436.2 connection to +3VDS *nBAT_LED#/GPIO154 115 SUSCLK_KBC [14] PVT_CS# 1 2 *nPWR_LED#/GPIO156 114 *GPIO155 7/13 Delete R269 1 KBC_XTAL12 39 1 *ADC3/GPIO61 09/10 Delete R271FET_B [51] *GPIO36 2 41 TX_STBY_LED#1 2 AMBER_BATLED# [39] 1 8

*PVT_SCLK/GPIO153 MiscellaneousMiscellaneous *GPIO206 1 C1892 2200P_0402_50V7K 3 42 1 2 +3VDS 2 7 A_GND R267 300_0402_5% *SHD_SCLK/GPIO122 *ADC2/GPIO60 8051RX_CAPLED# [38] 4.7K_0804_8P4R_5%10/12 Change R276.1 connection netname to RSMRST#_EC N27271393 30 65 3 6 [43] VOLTAGE_ADC 31 *GPIO31 GPIO33 64 R436 100K_0402_5% 4 5 [51] LATCHED_ALARM R437 33_0402_5% 32 *GPIO127 *GPIO27 63 R270 300_0402_5% PVT_SCLK iSCT_LED# iSCT_LED# [39] I2C_MAIN_CLK 33 *IMDAT/GPIO52 GPIO35 40 +3VDS PCH_SPI_CLK PCH_SPI_CLK_EC GPIO147 AVCCN27271143 I2C_MAIN_DAT [16] PCH_SPI_CLK 34 ADP_A_ID [50] WLAN_DISABLE GPIO151 TRAVEL_BAT_DET# I2C_BAY_CLK [25] WLAN_DISABLE 1 2 43 TRAVEL_BAT_DET# [42] *ADC1/GPIO57 LID_SW# I2C_BAY_DAT [43] CHRG_ADP_DET 1 2 44 LID_SW# [22,38,39] RP5 TP_DATA *ADC0/ADC_TO_PWM_IN/GPIO56 [38] TP_DATA ADP_EN [43] 1 2 WWAN_DISABLE [25] WWAN_DISABLE 07/18 Install R277 +3VDS 1 2 SLP_LAN# 08/10 Change R277.1 connection to VR_ON 07/23 Change C322 to 100pF 1 2 [14,29] SLP_LAN# N27271121 [43] CURRENT_ADC R273 300_0402_5% 09/12 Delete R278 10/16 Delete C322 1 2 [50] OCP_A_IN R272 300_0402_5%N27271128 MEC1322-NU VTQFP09/23 128P Change netname to PWR_GD 1 2 CPPWR_EN R274R276 10K_0402_5%1 10K_0402_5%2 *PWRGD VSS VSS VSS VSS VSS VSS VSS AVSS PM_PWROK R275R278 10K_0402_5%10/161 10K_0402_5%Change R2432 to 100K. Change R243.1 connection to CHRG_RST. Change R243.2 connection to GND RSMRST#_EC R2791 100K_0402_5%2

72 11 47 56 82 36 45 ADP_ID_CHK 1 2 104 117 FET_A R446 100K_0402_5% PWR_GD FET_B R280 100K_0402_5%1 2 [31,47,5] PWR_GD 1 2 1 2 KBC_PROC_HOT# R265 100K_0402_5% OCP_PWM_OUT R447 10K_0402_5% 1 2 1 2 KBC_DS3_EN 1 2 A_GND C191 2200P_0402_50V7K CHRG_RST R243 100K_0402_5% C190 2200P_0402_50V7K R281 0_0402_5% 09/10 Add C487, C488, and Y4 C192 2200P_0402_50V7K 11/01 Uninstall Y4, C487, C488 Layout note: ADC nets are spaced at least 20mils from any high speed switching signals to prevent cross talk that could add noise KBC_XTAL1 C487@ 10P_0402_25V8K

1 2

2 Y4 @ 32.768KHZ_12.5PF_FC-135 C488@ 10P_0402_25V8K 09/03 Change R282 to 10K

KBC_XTAL2 1

C 7/13 Change power rail C 7/13 Delete RH220 1 from +3V_SPI to +3VDS 07/24 Add C419 for EMI request 20mils 7/13 Change power rail from +3V_SPI to +3VDS 12/12 Change RH222, RH223, RH224 to 100K PCH_SPI_CLK_EC 2 SPI ROM (16MByte ) C419 33P_0402_50V8J @ 07/19 Add off page symbol 1 2 PCH_SPI_WP# and PCH_SPI_HOLD# 8 4 PVT ROM (IN) VCC VSS 8 4 10/16 Add R616 VCC VSS 3 1 W +3VDS 0.1U_0402_16V4Z 3 07/09 Delete 16 pin SPI ROM socket UH5 &UH1 45@ R282 10K_0402_5% 2MB 1 2 +3VDS 7 C193 W HOLD 1 2 7 &UH2 45@ 08/09 Correct UH5 and &UH1 SPI ROM size 2 07/18 Install U18 HOLD 1 2 1 08/09 Change UH5 footprint 07/25 Change U18 to scoket and add &UH2 +3VDS S U18 CONN@ 1 08/09 Correct U18 andS &UH2 SPI ROM size RH222 1 @ 2 6 C 1 2 6 100K_0402_5% PCH_SPI_WP# [16] PCH_SPI_WP# 5 2 128M2 W25Q128FVSIG1 SOIC8P C RH223 D Q PCH_SPI_CS0# PCH_SPI_HOLD# 5 2 100K_0402_5% [16] PCH_SPI_HOLD# D Q 16M W25Q16CVSSIG SOIC 8P R438 RH224 08/03 Add CH114 PCH_SPI_WP#100K_0402_5% PCH_SPI_CS0# 10K_0402_5%R616 1 1 1 PVT_CS# 07/23 Add CH112 for RF request 15_0402_5% PCH_SPI_HOLD# PCH_SPI_CLK R283 5_0402_1% 22P_0402_50V8J 07/24 Add R555 for EMI request 128M W25Q128FVSIG SOIC8P PVT_SCLK +3VDS +3VDS 2 20mils 2 CH1142 PCH_SPI_SI CONN@ PCH_SPI_SO_R_1 PCH_SPI_SO +3VDS R555 PVT_MOSI PVT_MISO 1 CH97 @ 0_0402_5% 0.1U_0402_16V4Z 16M W25Q16CVSSIG SOIC 8P 1 @ 2 CH98 22P_0402_50V8J @ CH112

2 22P_0402_50V8J +3VDS

+3VDS 08/07 Change net name

1 R560 2 R559 100K_0402_5% 100K_0402_5% 07/25 Add Q77 and R559 Q77A 1 2N7002KDW_SOT363-68051TX_STBYLED# [33,38,39] 2 5 6

D D 2 Q77B 2N7002KDW_SOT363-6 1 3 TX_STBY_LED# LA-9241P 4

Security Classification Compal Secret Data Issued Date 2012/03/23 Deciphered Date 2011/12/31

Title Compal Electronics,KBC1322 Inc.

1 2 3 4 Size Document Number 5 Rev 0.5

Date: Thursday, December 20, 2012 Sheet 30of 56 www.vinafix.vn THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. +3VS 09/03 Non install R284

2 R285 07/23 Change R286 to 10K C1941 R284 1 2 @ 40.2K_0402_1% 1M_0402_5% 2 3300P_0402_25V7K R286 +5VDS 09/11 Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON 2 10K_0402_5% 1 +5VS 1 2 09/03R288 Change R289 76.8K_0402_1% to 11.5K 1 8 U19A +0.675VS 1R289 2 11.5K_0402_1% 1R2902 10K_0402_5% 3 P PWR_GD + 1 PWR_GD [30,47,5] +5VL 1.75VREF 09/23 Change netname to PWR_GD 1 R2912 105K_0402_1% 2 O [49] 1.5VS_PG 10/31 Change R291.1 connection to G R5501 2 3.3K_0402_5% +5VL. Change R291 to 105K_1% - LM393DR2G_SO8 4 D41 1 R551 31.6K_0402_1% C195 [14,30,34,45] SLP_S3# R292 1 1 3.3K_0402_5%2 2 1000P_0402_50V7K

R552 1 2 PM_APWROK 2 1 3.3K_0402_5%2 3

DAP202UGT106_SC70-3 R294

1M_0402_5% 1 2 +5VDS

U19B 8 +3VS R297 76.8K_0402_1% R296 10K_0402_5% 1 2 1 2 1.75VREF5 P + +1.35VS 7 R293 30.9K_0402_1% 6 OG LM393DR2G_SO8 1 2 - 4 +1.05VS R553 24.3K_0402_1%

C196 1 R299 1 2 73.2K_0402_1% 3300P_0402_25V7K1

07/20 Follow VBK10 PWR_GD circuit

2 2

11/01 Change R304.1 connection to +5VL. Change R304 to 88.7k +-1% +5VL R304 88.7K_0402_1% +3VDS

1 2

C197 1 35.7K_0402_1% R306 +3V_PCH R309 R175 1 2 3.3K_0402_5% 1M_0402_5%

2 RH246

2 +5VDS 1 4.7K_0402_5% 1 2 R311 1 U20B +3VM_LAN R310 20.5K_0402_1% 2

8 R312 1M_0402_5% 3.3K_0402_5% PM_APWROK [14,30] [46] 1.05VM_PG R547 10K_0402_5% 09/23 Change netname to VGATE

P +5VDS 1000P_0402_50V7K 1000P_0402_50V7K C199 LM393DR2G_SO8 1 2 19.1K_0402_1% 1 2 5 R307 1 R313 + G 7 1 2

D43 1 1K_0402_5% 1 2 3300P_0402_25V7K 6 O

4 U20A R548 - [14,30,46] SIO_SLP_A# 1 [47] VGATE 3.3K_0402_5% 8 PCH_PWROK_R [14] 2 P 2 2 R301 LM393DR2G_SO8 1 2 2 3 CH115 0.22U_0402_6.3V6K+ G 1 1M_0402_5% 12/12O Change CH115 to 0.22uF

1 2 4 DAP202UGT106_SC70-3 C198 - 9/13 Modify power ok circuit 3 07/18 HP request 1 1 0.068U_0402_10V6K2

2 1 2

Title LA-9241P

Size Document Number Rev 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 31of 56 Issued Date 2012/03/23 Deciphered Date 2010/03/31 POK CKT Compal Electronics, Inc.

+5VS 10/25 Delete R318, R319, Parallel Port R321, R322. Add RP17

2 +3VS TO LPC47N217N RP17 DSR#1 D27 CTS#1 8 1 10/25 Delete R320, R477,RB751V-40_SOD323-2 7 2 R478, R464. Add RP13 RI#1

1 DCD#1 6 3 5 4 +5VS_PRN RP13 4.7K_0804_8P4R_5% LPTACK# A LPTERR# 8 1 A LPTAFD# 7 2 LPTSTB# 6 3 RXD1 R323 1K_0402_5% 10/25 Delete R465, R466, 5 4 1 2 R467, R472. Add RP14 4.7K_0804_8P4R_5% U22 LPC_LAD0 LPC_LAD0 [16,25,28,30] LPC_LAD1 RP14 9 LPC_LAD1 [16,25,28,30] LPD7 RXD1 LAD0 LPC_LAD2 [33] RXD1 11 LPC_LAD2 [16,25,28,30] LPTSLCT TXD1 LAD1 LPC_LAD3 8 1 [33] TXD1 54 12 LPC_LAD3 [16,25,28,30] LPTPE DSR#1 7 2 [33] DSR#1 55 RXD1 LAD2 13 LPTBUSY RTS#1 LPC_LFRAME# 6 3 [33] RTS#1 56 TXD1 LAD3 LPC_LFRAME# [16,25,28,30] 10/25 Delete R473, R474, CTS#1 LPC_LDRQ0# R475, R468. Add RP15 5 4 [33] CTS#1 1 DSR1# 14 LPC_LDRQ0# [16] 4.7K_0804_8P4R_5% [33] DTR#1 DTR#1 RTS1# LFRAME# RI#1 2 15 KBC_SIO_RST# [33] RI#1 CTS1# LDRQ# KBC_SIO_RST# [18,30] RP15 DCD#13 LPCPD#_SIO [33] DCD#1 4 DTR1# 16 LPD3 RI1# PCI_RESET# LPD4 5 17 PM_CLKRUN# +3VS DCD1# LPCPD# PM_CLKRUN# [14,28,30] LPD5 8 1 CLK_PCI_SIO SERIALSERIAL I/FI/F CLK_PCI_SIO [15] LPD6 7 2 LPTINIT# 18 SIRQ 10/25 Delete R469, R470, [33] LPTINIT# CLKRUN# SIRQ [16,28,30] R471, R479. Add RP16 6 3 LPTSLCTIN# 19 SIO_PME# LPCPD#_SIO R325 4.7K_0402_5% [33] LPTSLCTIN# LPCLPC I/FI/F PCI_CLK +3VS 4.7K_0804_8P4R_5%5 4 [33] LPD0 LPD035 20 R324 10K_0402_5% LPD136 INIT# SER_IRQ 6 CLK_SIO_14M1 2 1 2 [33] LPD1 CLK_SIO_14M [15] RP16 LPD237 SLCTIN# IO_PME# [33] LPD2 PD0 LPTSLCTIN# [33] LPD3 LPD339 8 LPD0 LPD440 PD1 CLOCK CLK14 SIO_GPIO41 10/26 Connect U22.26 pin to signal mSATA_DET# [33] LPD4 PD2 LPD1 8 1 [33] LPD5 LPD541 SIO_GPIO42 PD3 LPD2 7 2 [33] LPD6 LPD642 21 SIO_GPIO43 6 3 [33] LPD7 LPD743 PD4 GPIO41 22 SIO_GPIO44 LPTSLCTPD5 GPIO42 mSATA_DET# 4.7K_0804_8P4R_5%5 4 [33] LPTSLCT 44 24 mSATA_DET# [23] LPTPE SIO_GPIO46 [33] LPTPE 45 PD6 GPIO43 25 LPTINIT# R476 4.7K_0402_5% LPTBUSY SER_SHD_GPIO47 [33] LPTBUSY 47 PD7 GPIO44 26 LPTACK# SIO_GPIO10 [33] LPTACK# 48 SLCT GPIO45 27

LPTERR# GPIOGPIO SYSOPT [33] LPTERR# PE GPIO46 1 2 LPTAFD#49 28 SIO_GPIO12 [33] LPTAFD# 50 BUSY GPIO47 29

LPTSTB# SIO_IRQ 1 [33] LPTSTB# 51 ACK# GPIO10 30 ERROR# GPIO11/SYSOPT R327 52 PARALLELPARALLEL I/FI/F 31 SIO_GPIO23 10K_0402_5% B 53 ALF# GPIO12/IO_SMI# 32 B STROBE# GPIO13/IRQIN1 33 +3VS GPIO14/IRQIN2

10/26 Delete R481 34 2 R480 4.7K_0402_5% SIO_GPIO46 +3VS GPIO23 7 10 VTR R3281 2 4.7K_0402_5% SIO_GPIO23 23 VCC POWER 57 R329 4.7K_0402_5% SIO_GPIO41 38 VCC LPC47N217N-ABZJ_QFN56_8X8EPAD VCC R330 4.7K_0402_5%10/25 Delete SIO_GPIO42R484, R485, 46 R5541 @ 2 4.7K_0402_5% R486. Add RP18SIO_GPIO44 VCC 1 2 RP18 1 2 1 1 1 1 1 2

SIO_IRQ 0.1U_0402_16V4Z C201 0.1U_0402_16V4Z C202 0.1U_0402_16V4Z C203 4.7U_0805_10V4Z C204 SIO_GPIO12 SIO_GPIO10 2 2 2 2 07/198 Change R483.11 and R482.1 connection to +3VS. 7 2 Change4.7K_0804_8P4R_5% R330.1, R329.1, and R328.1 connection to GND 07/206 Reserve 3SIO_GPIO44 PD R554, and modify R328, R329,5 R330 value4 to 4.7K. Modify R482, R483 value to 10K

+3VS

R482 10K_0402_5% SIO_GPIO44 09/11 AddR483 R601 4.7K PU to 10K_0402_5% +3VS on signalSIO_GPIO43 SIO_GPIO42. Noninstall R601

R601@ 4.7K_0402_5% SIO_GPIO42 1 2 1 2 R331 10K_0402_5% SYSOPT 1 2 C C

1 2

CLK_PCI_SIO CLK_SIO_14M

R332 R333 @ 33_0402_5%Base I/O Address10_0402_5% 1 0 = 02Eh 1 1 = 04Eh

C205 C206 @ 2 82P 50V J NPO 0402 2 10P_0402_25V8K 11/07 Change R332 to 33 ohms, C205 to 82pF and install R332 and C205

1 1

2 2

D D

Title LA-9241P

Size Document Number Rev 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 32of 56 Issued Date 2012/03/23 Deciphered Date 2009/09/09 SUPER I/O LPC47N217N-ABZJ Compal Electronics, Inc. 1 2 www.vinafix.vn3 4 5

VA DOCK CONN. 184PIN +5VS +3V_PCH DOCKING CONNECT VA_ON#

(1) PCI Express x1 channels 1 (2) PS/2 Interfaces 0.1U_0603_50V4Z 0.1U_0603_50V4Z C207 C209 DOCK_ID R334 10K_0402_5% 1 (2) USB 2.channels 1 2 +5VS ISO_PREP# R337 10K_0402_5% R335 C208 (2) SATA Channels 1 2 (2) Display Port Channels 1 1 1K_0402_5% 0.1U_0402_16V4Z (1) Serial Port VIN VA 09/11 Change C299 to 0.01uF. Delete R336 and 2 (1) Parallel Port L27 connect C299.1 to ON/OFFBTN_KBC#. Connect 2 (1) Line In HCB2012KF-121T50_0805 2 2 ON/OFFBTN_KBC# to JDOCK1.49 (1) Line Out C210 C211 C212 C213 ON/OFFBTN_KBC# ON/OFFBTN_KBC# [30,38] (1) RJ45 (10/100/1000) 1 2 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (1) VGA (1) 2 LAN indicator LED's 1 1 1 1 2

1 L28 C299 (1) Power Button 5A D42 HCB2012KF-121T50_0805 A (1) I2C interface 0.01U_0402_16V7K_X7R A L30ESD24VC3-2_SOT23-3 2 2 2 2 1 1 2 09/11 Delete R351 and connect JDOCK1B 10/11 Non-install D42 EN_P1V5 to JDOCK1.140 @ 07/16 Add by ESD's request R168 100K_0402_5% 1 2 143 46 DPB_HPD 142 143 46 47 DCK1_HPD VA [36] DPB_HPD 142 47 DCK1_HPD [35] JDOCK1A [30,39,40,44,45] EN_P1V5 141 48 ON/OFFBTN_KBC#

3 2 ADP_SIGNAL ADP_SIGNAL 140 141 48 49 VA_ON# DPB_AUX 139 140 49 50 MXM_DCK_AUX DPB_AUX# 09/27 Delete R339, R341 09/27 Delete R340, R342 MXM_DCK_AUX# 12A 190 189 138 139 50 51 P1 G1 137 138 51 52 136 137 52 53 135 136 53 54 [29] MDO3+ 188 1 MDO1+ [29] 134 135 54 55 [29] MDO3- 188 1 MDO1- [29] 134 55 187 2 LPTSTB# 133 56 D_DDCDATA 187 2 [32] LPTSTB# 133 56 D_DDCDATA [36] 186 3 LPTAFD# 132 57 D_DDCCLK [29] MDO2+ 186 3 MDO0+ [29] [32] LPTAFD# 132 57 D_DDCCLK [36] 185 4 LPTERR# 131 58 [29] MDO2- MDO0- [29] [32] LPTERR# D_VSYNC [36] 184 185 4 5 LPTACK# 130 131 58 59 [32] LPTACK# D_HSYNC [36] 183 184 5 6 LPTBUSY 129 130 59 60 183 6 [32] LPTBUSY 129 60 182 7 [32] LPTPE LPTPE 128 61 R_DOCK_RED R_DOCK_RED [36] DETECT 182 7 LPTSLCT 128 61 LED_LINK_LAN_DOCK# [29] [32] LPTSLCT 127 62 LPD7 127 62 R_DOCK_GRN LAN_ACT# [29] [32] LPD7 126 63 R_DOCK_GRN [36] LPD6 126 63 R_DOCK_BLU +5VS 181 8 +5VS [32] LPD6 125 64 R_DOCK_BLU [36] 181 8 LPD5 125 64 180 9 [32] LPD5 124 65 180 9 LPD4 124 65 DCD#1 179 10 [32] LPD4 123 66 DCD#1 [32] 179 10 USB3TN1 LPD3 123 66 RI#1 178 11 USB3TN1 [17] [32] LPD3 122 67 RI#1 [32] 178 11 USB3TP1 LPD2 122 67 DTR#1 177 12 USB3TP1 [17] [32] LPD2 121 68 DTR#1 [32] LPD1 CTS#1 176 177 12 13 [32] LPD1 120 121 68 69 CTS#1 [32] USB3RN1 LPD0 RTS#1 175 176 13 14 USB3RN1 [17] [32] LPD0 119 120 69 70 RTS#1 [32] USB3RP1 LPTSLCTIN# DSR#1 175 14 USB3RP1 [17] [32] LPTSLCTIN# 119 70 DSR#1 [32] 174 15 LPTINIT# 118 71 TXD1 174 15 [32] LPTINIT# 118 71 TXD1 [32] 173 16 STB_LED#_R 117 72 RXD1 173 16 USBP0- [17] 117 72 RXD1 [32] 172 17 SATA_ACT# 116 73 172 17 USBP0+ [17] [13,39] SATA_ACT# 116 73 171 18 DOCK_ID 115 74 171 18 [36] DOCK_ID 115 74 170 19 ISO_PREP# 114 75 B 169 170 19 20 [13,36] ISO_PREP# 113 114 75 76 B 168 169 20 21 112 113 76 77 [13] SATA_PTX_DRX_P3 167 168 21 22 111 112 77 78 KBD_DATA [13] SATA_PTX_DRX_N3 KBD_DATA [30] 166 167 22 23 110 111 78 79 KBD_CLK KBD_CLK [30] 165 166 23 24 109 110 79 80 PS2_DATA [13] SATA_PRX_DTX_P3 PS2_DATA [30] 164 165 24 25 108 109 80 81 PS2_CLK 164 25 [13] SATA_PRX_DTX_N3 108 81 PS2_CLK [30] 163 26 107 82 LINE_IN_SENSE [27] 162 163 26 27 USBP11- 106 107 82 83 DOCK_HPS# 162 27 [17] USBP11- 106 83 DOCK_HPS# [27] [36] DPB_TXP0 161 28 USBP11+ 105 84 161 28 MXM_DCK_LANE_P0 [35] [17] USBP11+ 105 84 [36] DPB_TXN0 160 29 104 85 160 29 MXM_DCK_LANE_N0 [35] 104 85 DOCK_LINE_IN_L [27] 159 30 [13] SATA_PTX_DRX_P2 103 86 DOCK_LINE_IN_R [27] 159 30 103 86 [36] DPB_TXP1 158 31 MXM_DCK_LANE_P1 [35] [13] SATA_PTX_DRX_N2 102 87 DLINE_OUT_L [36] DPB_TXN1 157 158 31 32 MXM_DCK_LANE_N1 [35] 101 102 87 88 DLINE_OUT_L [27] DLINE_OUT_R 156 157 32 33 [13] SATA_PRX_DTX_P208/01 Modify SATA bus from port 5 to port 2 100 101 88 89 DLINE_OUT_R [27] [36] DPB_TXP2 156 33 MXM_DCK_LANE_P2 [35] [13] SATA_PRX_DTX_N2 100 89 155 34 99 90 DETECT [36] DPB_TXN2 154 155 34 35 MXM_DCK_LANE_N2 [35] 98 99 90 91 153 154 35 36 97 98 91 92 Quick SW[36] DPB_TXP3 152 153 36 37 MXM_DCK_LANE_P3 [35]GPU 96 97 92 93 [36] DPB_TXN3 151 152 37 38 MXM_DCK_LANE_N3 [35] 95 96 93 94 151 38 95 94 DPB_AUX 150 39 MXM_DCK_AUX [36] DPB_AUX 150 39 MXM_DCK_AUX [35] DPB_AUX# 149 40 MXM_DCK_AUX# [36] DPB_AUX# 148 149 40 41 MXM_DCK_AUX# [35] 147 148 41 42 146 147 42 43 192 191 145 146FOX_QL0094L-D26601-8H43 44 194 G2 G1 193 144 145 CONN@44 45 196 G4 G3FOX_QL0094L-D26601-8H195 144 45 198 G6 G5 CONN@197 200 G8 G7 199 G10 G9

R_DOCK_RED R343 150_0402_1% +5VDS R_DOCK_GRN R344 150_0402_1% R_DOCK_BLU R345 150_0402_1% C C

1 2 R346 1 2 07/18 change by HP request 1 10K_0402_5% 1 2 D R_DOCK_RED C214@ 0.1U_0402_16V4Z G STB_LED#_R R_DOCK_GRN C215@ 0.1U_0402_16V4Z R_DOCK_BLU C216@ 0.1U_0402_16V4Z

2 S

[30,38,39] 8051TX_STBYLED# 8051TX_STBYLED# Q35 2N7002_SOT23-3 1 2 1 1 2 1 2

2 3

D D

Title LA-9241P

Size Document Number Rev Custom 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 33of 56 Issued Date 2012/03/23 Deciphered Date 2009/12/31 DOCK CONN Compal Electronics, Inc. IN NC<-->COM NO<-->COM

1 2 3 4 5 L ON OFF

www.vinafix.vnH OFF ON

+3VALW TO +3VALW(PCH AUX Power) Short J1 for PCH VCCSUS3.3 +5VDS to +5VS Transfer +3VDS to +3VS Transfer +3VDS J1 @ +3V_PCH C490@ 0.01U_0402_16V7K U45 C493@ 0.01U_0402_16V7K U46 +5VDS 1 2 +5VS +3VDS 1 2 +3VS 1 2 SLP_S3# R603 0_0402_5% SLP_S3# R604 0_0402_5% 1 2 1 2 3 1 2 3 JUMP_43X79 ON ON 4.5A 6.5A 07/06 Swap Drain and Source 1 7 1 7 to aviod leakage issue 40mil VIN VOUT VIN VOUT Q40 AO3413L_SOT23-3 C492 C453 C454 C506 C507 C496 C452 C510 C509 C508 C455 C489 2 8 C494 2 8 VIN VOUT VIN VOUT 3 1 1 1 2 10U_0603_6.3V6M 68P_0402_50V8J 68P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 1 10U_0603_6.3V6M 68P_0402_50V8J 100P_0402_50V8J 1 1

SS DD @ @ @ @ @ @ 1 1 100P_0402_50V8J 1 100P_0402_50V8J 1 68P_0402_50V8J 1 10U_0603_6.3V6M 1 +5VDS 10U_0603_6.3V6M 1 +5VDS C224 2 @ R355 @ @ @ 4 4 1 10U_0603_6.3V6M C225 1U_0603_25V6 C220 470_0603_5% C491 4700P_0402_16V7KVBIAS 2 C495VBIAS 4700P_0402_16V7K 2

GG 5 5

10U_0603_6.3V6M 1 1 2 6 GND 9 2 2 2 2 1 2 6 GND 9 2 2

R489 2 2 1 2 2 2 2 CT GND 2 CT GND

2 1K_0402_5% 3 TPS22965DSGR_SON8_2X2 08/10 Reserve C453 and C454 for RF TPS22965DSGR_SON8_2X2 08/10 Reserve C452, C456, C457, C458 for RF 9/25 Change +5VS power rail soultion. Delete U24, C226, C221, C222. Add U45, R603, C489, C490, C491, C492 11/06 Reserve C510 by RF request 1 08/10 Reserve C455 for RF 9/26 Change C489, C492 to 10u. Change C490 to 0.01u 1 11/06 Add C506, C507, C508, C509 by RF reqeust 2 KBC_PWR_ON# B+ 11/06 Change C491 to 4700pF 09/25 Change +3VS power rail solution. +3VDS 5 Q18B Delete U25, C218, C223, C219, C227, R354, R356, R357, Q9. Add U46, R604, C493, C494, C495, C496

KBC_PWR_ON# 4 DMN66D0LDW-7_SOT363-6 [46] KBC_PWR_ON# R455 200K_0402_5% 09/26 Change C494, C496 to 10u. Change C493 to 0.01u 11/06 Change C495 to 4700pF 1 2 C456 C457 C458 R622 100K_0402_5% 10/25 Change R455 to 200k. Add PD R622. 1 10/26 Change2 R455.2 connection to B+ @ @ @ 6 1 1 1 68P_0402_50V8J 68P_0402_50V8J 68P_0402_50V8J DMN66D0LDW-7_SOT363-6 [30,44] KBC_PWR_ON Q18A 2 2 2 2 1

10/12 Change R455 to 47K. Add Q18A, C504, R609. Modify circuit 10/16 Delete C504, R609, R456, Q67B. Add R612. Modify circuit. 10/18 Change R612 to 4.7k ohms. Delete Q67A 10/23 Delete R612 Discharge circuit-2 for V-M +3VM_LAN

+3VDS 1 R360 07/10 Change R363 to 4.7K 470_0402_5%

10/26 Change Q36 to AO3413 1 R363

4.7K_0402_5% 2 3 D Q7B +3VDS AMT@ +3VM_LAN SLP_S32 SLP_LAN 2N7002DWH_SOT363-6 [49,9] SLP_S3 2 Q36 2 AO3413L_SOT23-3 G +3VALW to +3VM_LAN Transfer S 07/23 Remove Q37, R366, R361 4 [14,30,31,45] SLP_S3# 1 5

1.5A Q39 3 1 07/20 Delete C231 3 2

AMT@ 1 2N7002KW_SOT323-3 2

AMT@ R4881 R368 1K_0402_5% 100K_0402_5% 1 1

SLP_LAN 2

[29] SLP_LAN 0.1U_0402_16V4Z 2

C229 1U_0402_6.3V4Z C230 2 2 SS DD GG

+3VS +5VS +1.05VS

+1.05VM +1.05VS Q41 Discharge circuit-1 AO4430L_SO8 R369 R370 R373

+1.05VM to +1.05VS Transfer 1 1 1 470_0402_5% @ 220_0402_5%D @ 470_0402_5%D + G G S S

2 Q42A 2 2

6A 6 8 1 2N7002DW T/R7_SOT-363-6 SLP_S3 Q43 9/25 Uninstall SLP_S3R370, R373, Q43, Q44 7 2 C503 SLP_S3 09/26 Change Q42 to Dual channel 1 2N7002_SOT23-3 1 2N7002_SOT23-3 6 4 3 09/28 Add C503 @ @ @ 1 1 5

1 3 3 B+ R375 220K_0402_5% 1 1 2 2 2 2 2 C233 10U_0805_10V4Z C234 0.1U_0402_16V4Z

3 Q42B 2 2

SLP_S3 2N7002DW1 T/R7_SOT-363-6C235 10U_0805_10V4Z C232 330U_B2_2VM_R15M 09/26 Change netname to SLP_S3# 09/26 Change +1.05VS power circuit. 3 1 2 3 2 4 3300P_0402_25V7K 5

4 4 LA-9241P

Title

Size Document Number Rev 0.5

Date: Thursday, December 20, 2012 Sheet 34of 56

Security Classification Issued Date 2012/03/23 2009/12/31 Deciphered Date DC/DC Circuits Compal Secret Data Compal Electronics, Inc. A B www.vinafix.vnC D E

#4/6 change by HP PEG_CTX_GRX_P[0..15] [4] PEG_CTX_GRX_P[0..15] requirement PEG_CTX_GRX_N[0..15] [4] PEG_CTX_GRX_N[0..15] PCH_THERMTRIP#_R PCH_THERMTRIP#_R [18,24,5] PEG_CRX_GTX_P[0..15] [4] PEG_CRX_GTX_P[0..15] PEG_CRX_GTX_N[0..15] AC_PRES_OUT [4] PEG_CRX_GTX_N[0..15] AC_PRES_OUT [14,30]

B+ B+ PEX_RST 07/06 Swap PEG TX and RX 5/28 change by HP requirement JMXM1A JMXM1B 1 2 3 PWR_SRC PWR_SRC 4 158 159 PWR_SRC PWR_SRC Q82A R627 GND GND D 5 6 160 161 2 1 D 7 PWR_SRC PWR_SRC 8 2 2N7002KDW_SOT363-6 4.7K_0402_5% PEG_CTX_GRX_N3 162 PEX_TX3# PEX_RX3# PEG_CRX_GTX_C_N3163 CV1 0.22U_0402_6.3V6K2 1 PEG_CRX_GTX_N3 9 PWR_SRC PWR_SRC 10 1 6 10/18 change R137 to 4.7K PEG_CTX_GRX_P3 164 PEX_TX3 PEX_RX3 PEG_CRX_GTX_C_P3165 CV2 0.22U_0402_6.3V6K PEG_CRX_GTX_P3 11 PWR_SRC PWR_SRC 12 AC_PRES_OUT 10/29 Delete R137, Q82.B. Add D52 166 GND GND 167 13 PWR_SRC PWR_SRC 14 2 1 168 GND GND 169 15 PWR_SRC PWR_SRC 16 PEG_CRX_GTX_N2 CV3 0.22U_0402_6.3V6K2 1 PEG_CRX_GTX_C_N2 170 PEX_RX2# PEX_TX2# PEG_CTX_GRX_N2171 PWR_SRC PWR_SRC PEG_CRX_GTX_P2 CV4 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P2 PEX_RX2 PEX_TX2 PEG_CTX_GRX_P2 17 18 2 172 173 19 PWR_SRC PWR_SRC 20 3 1 2 1 174 GND GND 175 21 PWR_SRC PWR_SRC 22 MXM_THERMTRIP#B PCH_THERMTRIP#_R PEG_CRX_GTX_N1 CV5 0.22U_0402_6.3V6K2 1 PEG_CRX_GTX_C_N1 176 PEX_RX1# PEX_TX1# PEG_CTX_GRX_N1177 GND GND PEX_RX1 PEX_TX1 23 24 MMBT3904_SOT23-310/25 Change Q61 and Q62 to dual channel 7002 PEG_CRX_GTX_P1 CV6 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P1 178 PEG_CTX_GRX_P1179 GND GND GND GND 25 26 11/08 DeleteQ83 D52. Add Q83, R627 2 1 180 181 C 27 GND GND 28 E PEG_CRX_GTX_N0 CV7 0.22U_0402_6.3V6K2 1 PEG_CRX_GTX_C_N0 182 PEX_RX0# PEX_TX0# PEG_CTX_GRX_N0183 29 GND GND 30 PEG_CRX_GTX_P0 CV8 0.22U_0402_6.3V6K PEG_CRX_GTX_C_P0 184 PEX_RX0 PEX_TX0 PEG_CTX_GRX_P0185 31 GND GND 32 186 GND GND 187 33 GND GND 34 188 PEX_REFCLK# PEX_CLK_REQ# 189 35 GND GND 36 [15] CLK_PCIE_VGA# 190 PEX_REFCLK PEX_RST#PEX_RST191 PEG_CLK_REQ# [15] +5VS 37 GND GND 38 +3VS [15] CLK_PCIE_VGA 192 GND VGA_DDC_DAT 193 39 GND GND 40 194 RSVD VGA_DDC_CLK 195 GPU_VGA_DDC_DAT [36] 41 GND GND 42 196 RSVD VGA_VSYNC 197 GPU_VGA_DDC_CLK [36] 5V PRSNT_R# RSVD VGA_HSYNC GPU_VGA_VSYNC [36] 43 44 DGPU_PRSNT# 1 2 198 199 5V WAKE# DGPU_PRSNT# [18] 10/25 Change R607 and R608 to 10K RSVD GND GPU_VGA_HSYNC [36] 45 46 R6071 10K_0402_5%2 200 201 CRT 47 5V PWR_GOOD 48 10/29 Change R608 to 300 ohms. 202 RSVD VGA_RED 203 5V PWR_EN DGPU_PWROK R608 300_0402_5% LVDS_UCLK# VGA_GREEN 49 50 DGPU_PWR_EN DGPU_PWROK [18] 204 205 RED_R [36] +3VS 5V RSVD DGPU_PWR_EN [14,15] 09/27 Add R606, R607, R608 LVDS_UCLK VGA_BLUE GREEN_R [36] 51 52 10/18 Change R606,R607 and R608 to 4.7K 206 207 53 GND RSVD 54 208 GND GND 209 BLUE_R [36] GND RSVD LVDS_UTX3# LVDS_LCLK# 55 56 210 211 U37 57 GND RSVD 58 212 LVDS_UTX3 LVDS_LCLK 213 1 5 59 GND PWR_LEVEL 60 214 GND GND 215 4 IN1 2 2 R932 R92 R91 1 2 61 PEX_STD_SW# TH_OVERT# 62 1 2 216 LVDS_UTX2# LVDS_LTX3# 217 OUT DGPU_HOLD_RST#2 [14] 63 VGA_DISABLE# TH_ALERT# 64 218 LVDS_UTX2 LVDS_LTX3150_0402_1%219 150_0402_1%150_0402_1% IN2

DGPU_PWR_EN R487@ 4.7K_0402_5% R606 4.7K_0402_5% @ @ @ VCC 65 PNL_PWR_EN TH_PWM 66 +3VS 220 GND GND 221 12/20 Uninstall R91, R92, R93.PLT_RST# [13,14,25,28,29,30,37,39,5] ENAVDD_G 67 PNL_BL_EN GPIO0 68 DGPU_PWROK 222 LVDS_UTX1# LVDS_LTX2# 223 BL_EN_G 69 PNL_BL_PWM GPIO1 70 224 LVDS_UTX1 LVDS_LTX2 225 BL_PWM_G 1 1 1 71 HDMI_CEC GPIO2 72 1 6 226 GND GND 227 GND MC74VHC1G08DFT2G_SC70-5

2 1 73 DVI_HPD SMB_DAT 74 Q60A2 228 LVDS_UTX0# LVDS_LTX1# 229 75 LVDS_DDC_DAT SMB_CLK 76 MXM_PCH_KBC_I2CDAT PCH_KBC_I2CDAT [16,30] 230 LVDS_UTX0 LVDS_LTX1 231 3 10/11 Change DP port D to SWITCH LVDS_DDC_CLK GND MXM_PCH_KBC_I2CLK GND GND +3VS R63 100K_0402_5% 77 78 2 1 232 233 79 GND OEM 80 2N7002DW T/R7_SOT-363-6 4 3 2 1 234 DP_C_L0# LVDS_LTX0# 235 OEM OEM DP_C_L0 LVDS_LTX0# 5 Q60B 0.1U_0402_10V7K C24 MXM_eDP_C_LANE_N0 81 82 [36] MXM_eDP_LANE_N0 236 237 OEM OEM 0.1U_0402_10V7K C25 MXM_eDP_C_LANE_P0 GND GND C 83 84 PCH_KBC_I2CLK [16,30] [36] MXM_eDP_LANE_P0 2 1 238 239 C 85 OEM OEM 86 2 1 240 DP_C_L1# DP_D_L0# 241 OEM GND 2N7002DW T/R7_SOT-363-6 0.1U_0402_10V7K C26 MXM_eDP_C_LANE_N1 DP_C_L1 DP_D_L0 87 88 [36] MXM_eDP_LANE_N1 242 243 MXM_SYS_LANE_N0 [36] 1 2 89 GND PEX_TX15# 90 0.1U_0402_10V7K C272 MXM_eDP_C_LANE_P11 244 GND GND 245 [36] MXM_eDP_LANE_P1 MXM_SYS_LANE_P0 [36] 1 2 91 PEX_RX15# PEX_TX15 92 PEG_CTX_GRX_N15 2 1 246 DP_C_L2# DP_D_L1# 247 PEG_CRX_GTX_N15 0.22U_0402_6.3V6K CV9 PEG_CRX_GTX_C_N15 93 PEX_RX15 GND 94 PEG_CTX_GRX_P15 0.1U_0402_10V7K C28 MXM_eDP_C_LANE_N2 248 DP_C_L2 DP_D_L1 249 [36] MXM_eDP_LANE_N2 MXM_SYS_LANE_N1 [36] PEG_CRX_GTX_P15 0.22U_0402_6.3V6K 1 2CV10 PEG_CRX_GTX_C_P15 95 GND PEX_TX14# 96 0.1U_0402_10V7K C292 MXM_eDP_C_LANE_P21 250 GND GND 251 [36] MXM_eDP_LANE_P2 MXM_SYS_LANE_P1 [36] 1 2 97 PEX_RX14# PEX_TX14 98 PEG_CTX_GRX_N14 EDP 2 1 252 DP_C_L3# DP_D_L2# 253 PEG_CRX_GTX_N14 0.22U_0402_6.3V6K CV11 PEG_CRX_GTX_C_N14 99 PEX_RX14 GND 100 PEG_CTX_GRX_P14 0.1U_0402_10V7K C30 MXM_eDP_C_LANE_N3 254 DP_C_L3 DP_D_L2 255 [36] MXM_eDP_LANE_N3 MXM_SYS_LANE_N2 [36] SWITCH PEG_CRX_GTX_P14 0.22U_0402_6.3V6K 1 2CV12 PEG_CRX_GTX_C_P14 101 GND PEX_TX13# 102 0.1U_0402_10V7K C312 MXM_eDP_C_LANE_P307/091 Change by easy layout 256 GND GND 257 [36] MXM_eDP_LANE_P3 MXM_SYS_LANE_P2 [36] 1 2 103 PEX_RX13# PEX_TX13 104 PEG_CTX_GRX_N13 2 10/111 Change DP port C to eDP 258 DP_C_AUX# DP_D_L3# 259 PEX_RX13 GND DP_C_AUX DP_D_L3 PEG_CRX_GTX_N13 0.22U_0402_6.3V6K CV13 PEG_CRX_GTX_C_N13 105 106 PEG_CTX_GRX_P13 0.1U_0402_10V7K C32 GPU_C_AUX# 260 261 07/09 Change by easy layout GND PEX_TX12# [36] GPU_AUX# RSVD GND MXM_SYS_LANE_N3 [36] PEG_CRX_GTX_P13 0.22U_0402_6.3V6K 1 2CV14 PEG_CRX_GTX_C_P13 107 108 0.1U_0402_10V7K C33 GPU_C_AUX 262 263 PEX_RX12# PEX_TX12 RSVD DP_D_AUX# 1 2 109 110 PEG_CTX_GRX_N12 [36] GPU_AUX 264 265 MXM_SYS_LANE_P3 [36] PEX_RX12 GND RSVD DP_D_AUX PEG_CRX_GTX_N12 0.22U_0402_6.3V6K CV15 PEG_CRX_GTX_C_N12 111 112 PEG_CTX_GRX_P12 266 267 1 2 113 GND PEX_TX11# 114 268 RSVD DP_C_HPD 269 1 2 10/11 Change DPMXM_SYS_AUX# port B to DOCK [36] PEG_CRX_GTX_P12 0.22U_0402_6.3V6K CV16 PEG_CRX_GTX_C_P12 PEX_RX11# PEX_TX11 RSVD DP_D_HPD 1 2 115 116 PEG_CTX_GRX_N11 270 271 MXM_SYS_AUX [36] PEX_RX11 GND 07/09 Change by easy layout RSVD RSVD GPU_HPD [36] PEG_CRX_GTX_N11 0.22U_0402_6.3V6K CV17 PEG_CRX_GTX_C_N11 117 118 PEG_CTX_GRX_P11 10/11 Change DP port A to Thunder bolt272 R450273 10K_0402_5% DCK1_SYS_HPD 1 2 119 GND PEX_TX10# 120 274 RSVD RSVD 275 DCK1_SYS_HPD [36] PEG_CRX_GTX_P11 0.22U_0402_6.3V6K CV18 PEG_CRX_GTX_C_P11 PEX_RX10# PEX_TX10 RSVD RSVD 1 2 121 122 PEG_CTX_GRX_N10 276 277 123 PEX_RX10 GND 124 278 RSVD RSVD 279 PEG_CRX_GTX_N10 0.22U_0402_6.3V6K CV19 PEG_CRX_GTX_C_N10 PEG_CTX_GRX_P10 1 2 125 GND PEX_TX9# 126 280 RSVD DP_B_L0# 281 PEG_CRX_GTX_P10 0.22U_0402_6.3V6K CV20 PEG_CRX_GTX_C_P10 1 2 127 PEX_RX9# PEX_TX9 128 282 RSVD DP_B_L0 283 PEG_CTX_GRX_N9 129 PEX_RX9 GND 130 284 RSVD GND 285 MXM_DCK_LANE_N0 [33] PEG_CRX_GTX_N9 0.22U_0402_6.3V6K CV21 PEG_CRX_GTX_C_N9 PEG_CTX_GRX_P9 1 2 131 GND PEX_TX8# 132 2 1 286 GND DP_B_L1# 287 MXM_DCK_LANE_P0 [33] PEG_CRX_GTX_P9 0.22U_0402_6.3V6K 1 2CV22 PEG_CRX_GTX_C_P9 133 PEX_RX8# PEX_TX8 134 2 1 288 DP_A_L0# DP_B_L1 289 PEG_CTX_GRX_N8 135 PEX_RX8 GND 136 290 DP_A_L0 GND 291 MXM_DCK_LANE_N1 [33] PEG_CRX_GTX_N8 0.22U_0402_6.3V6K CV23 PEG_CRX_GTX_C_N8 GND PEX_TX7# PEG_CTX_GRX_P8 0.1U_0402_10V7K C34 MXM_TB_C_LANE_N0 GND DP_B_L2# 1 2 137 138 [39] MXM_TB_LANE_N0 2 1 292 293 MXM_DCK_LANE_P1 [33] PEG_CRX_GTX_P8 0.22U_0402_6.3V6K CV24 PEG_CRX_GTX_C_P8 PEX_RX7# PEX_TX7 0.1U_0402_10V7K C35 MXM_TB_C_LANE_P0 DP_A_L1# DP_B_L2 1 2 139 140 [39] MXM_TB_LANE_P0 2 1 294 295 PEX_RX7 GND PEG_CTX_GRX_N7 DP_A_L1 GND 141 142 296 297 MXM_DCK_LANE_N2 [33] PEG_CRX_GTX_N7 0.22U_0402_6.3V6K CV25 PEG_CRX_GTX_C_N7 GND PEX_TX6# PEG_CTX_GRX_P7 0.1U_0402_10V7K C36 MXM_TB_C_LANE_N1 GND DP_B_L3# 1 2 143 144 [39] MXM_TB_LANE_N1 2 1 298 299 MXM_DCK_LANE_P2 [33] PEG_CRX_GTX_P7 0.22U_0402_6.3V6K CV26 PEG_CRX_GTX_C_P7 PEX_RX6# PEX_TX6 0.1U_0402_10V7K C37 MXM_TB_C_LANE_P1 DP_A_L2# DP_B_L3 1 2 145 146 [39] MXM_TB_LANE_P1 2 1 300 301 Dock 147 PEX_RX6 GND 148 PEG_CTX_GRX_N6 302 DP_A_L2 GND 303 MXM_DCK_LANE_N3 [33] 07/09 Change by easy layout PEG_CRX_GTX_N6 0.22U_0402_6.3V6K 1 2CV27 PEG_CRX_GTX_C_N6 149 GND PEX_TX5# 150 PEG_CTX_GRX_P6 0.1U_0402_10V7K C382MXM_TB_C_LANE_N21 304 GND DP_B_AUX# 305 07/06 Swap PEG TX and RX [39] MXM_TB_LANE_N2 MXM_DCK_LANE_P3 [33] PEG_CRX_GTX_P6 0.22U_0402_6.3V6K 1 2CV28 PEG_CRX_GTX_C_P6 151 PEX_RX5# PEX_TX5 152 0.1U_0402_10V7K C392MXM_TB_C_LANE_P21 306 DP_A_L3# DP_B_AUX 307 1 2 PEX_RX5 GND PEG_CTX_GRX_N5 [39] MXM_TB_LANE_P2 DP_A_L3 DP_B_HPD 153 154 308 309 1 2 MXM_DCK_AUX# [33] PEG_CRX_GTX_N5 0.22U_0402_6.3V6K CV29 PEG_CRX_GTX_C_N5 GND PEX_TX4# PEG_CTX_GRX_P5 0.1U_0402_10V7K C40 MXM_TB_C_LANE_N3 GND DP_A_HPD 1 2 155 156 Thunder Bolt [39] MXM_TB_LANE_N3 310 311 MXM_DCK_AUX [33] PEG_CRX_GTX_P5 0.22U_0402_6.3V6K 1 2CV30 PEG_CRX_GTX_C_P5 157 PEX_RX4# PEX_TX4 0.1U_0402_10V7K C67 MXM_TB_C_LANE_P3 312 DP_A_AUX# 3V3 R448313 10K_0402_5% DCK1_HPD 08/09 Modify JMXM1 footprint [39] MXM_TB_LANE_P3 DCK1_HPD [33] PEX_RX4 PEG_CTX_GRX_N4 314 DP_A_AUX 3V3 R449 10K_0402_5% TB_HPD 08/09 Modify JMXM1 footprint TB_HPD [39] B PEG_CRX_GTX_N4 0.22U_0402_6.3V6K CV31 PEG_CRX_GTX_C_N4 PEG_CTX_GRX_P4 MXM_TB_AUX# 316 PRSNT_L# 315 B [39] MXM_TB_AUX# +3VS PEG_CRX_GTX_P4 0.22U_0402_6.3V6K CV32 PEG_CRX_GTX_C_P4 MXM_TB_AUX 318 GND GND 317 [39] MXM_TB_AUX 10U_0603_6.3V6M 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 1 0402 NPO J50V82P 0402 NPO J50V82P GND GND C347 C348 C349 C450 C451 6/2 change to fix MXM no function issue.

FOX_AS0B826-S43B1-7H CONN@ 2 @2 @2 CONN@ FOX_AS0B826-S43B1-7H 08/08 Reserve C450, C451 by RF request 100K_0402_5% 1 1

1 R169 2 2

D D 2 D 5/17 change by HP agree 3 5 1 Y0 VCC 4 +3VS dGPU_HPD_INTR G G G 6 Y1 Z 2 [17] dGPU_HPD_INTR U34S GND S S S ENAVDD_G [14] ENVDD_PCH ENAVDD [22] [14,36] DGPU_SELECT# 2 2 2 74LVC1G3157GW_SC-88-6 2N7002KW_SOT323-3 2N7002KW_SOT323-3 2N7002KW_SOT323-3

DCK1_SYS_HPD TB_HPD DCK1_HPD 3 5

1 Y0 VCC 4 1 1 1 6 Y1 Z 2 +3VS R451 Q51 R452 Q52 R453 Q53 U35S GND 100K_0402_5% 100K_0402_5% 100K_0402_5%

BL_EN_G 1 1 1

[14] PANEL_BKEN_PCH ENABLT [22] 3 3 3 DGPU_SELECT#

74LVC1G3157GW_SC-88-6 2 2 2 12/12 Change U34, U35, U36 to small package for material shortage issue. SZ A A 3 5 1 Y0 VCC 4 6 Y1 Z 2 +3VS LO Y0 S GND U36 LA-9241P BL_PWM_G [14] BKL_PWM_PCH INV_PWM [22] DGPU_SELECT# HI Y1 74LVC1G3157GW_SC-88-6 Security Classification Compal Secret Data Issued Date 2012/03/23 Deciphered Date 2009/09/09 Title

Size Document Number Rev CompalMXM Electronics, Inc. 0.5 Date: Thursday, December 20, 2012 Sheet 35of 56 5 4 3 2 1

www.vinafix.vn 1 2 3 4 5

07/17 Modify DP MUX solution to PI3VDP12412 07/17 Modify eDP MUX solution to PI3VDP12413 DP MUX

eDP MUX +3VS +3VS +3VS

1 1 1 1 CC72 CC73 CC74 CC83 1 C368 1U_0402_6.3V4Z C369 0.1U_0402_16V4Z C370 0.1U_0402_16V4Z C367 0.1U_0402_16V4Z 1U_0402_6.3V6K

07/27 Add R563, R564 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z R563 1 1 1 1 200K_0402_5% 2 2 2 2 +3VS A A 2 U42 2 2 2 2 U26 EDP_CPU_LANE_N0 42 12 12 42 DPA_TXN0 C3821 2 0.1U_0402_16V7K [7] EDP_CPU_LANE_N0 MB_DPA_TXN0 [39] EDP_CPU_LANE_P0 41 D0-A VDD 21 07/23 Modify net name 21 VDD 07/23 Modify netD0-A name 41 DPA_TXP0 C3811 2 0.1U_0402_16V7K [7] EDP_CPU_LANE_P0 MB_DPA_TXP0 [39] EDP_CPU_LANE_N1 40 D0+A VDD 34 34 VDD D0+A 40 DPA_TXN1 C3861 2 0.1U_0402_16V7K [7] EDP_CPU_LANE_N1 MB_DPA_TXN1 [39] EDP_CPU_LANE_P1 39 D1-A VDD VDD D1-A 39 DPA_TXP1 C3831 2 0.1U_0402_16V7K [7] EDP_CPU_LANE_P1 MB_DPA_TXP1 [39] 38 D1+A D1+A 38 DPA_TXN2 C3851 2 0.1U_0402_16V7K MB_DPA_TXN2 [39] From CPU R5641 2 200K_0402_5% 37 D2-A 2 SEL_eDP_MUX SEL_DP_MUX 2 D2-A 37 DPA_TXP2 C3841 2 0.1U_0402_16V7K MB_DPA_TXP2 [39] 36 D2+A GPU_SEL 3 3 GPU_SEL D2+A 36 DPA_TXN3 C3881 2 0.1U_0402_16V7K EDP_SW_D0N [22] [35] MXM_SYS_LANE_N0 MB_DPA_TXN3 [39] 35 D3-A D0- 4 4 D0- D3-A 35 DPA_TXP3 C3871 2 0.1U_0402_16V7K M/B DP EDP_SW_D0P [22] [35] MXM_SYS_LANE_P0 MB_DPA_TXP3 [39] EDP_CPU_AUX# 24 D3+A D0+ 6 6 D0+ D3+A 24 [7] EDP_CPU_AUX# EDP_SW_D1N [22] [35] MXM_SYS_LANE_N1 MB_DPA_AUX# [39] EDP_CPU_AUX 23 AUX-A D1- 7 7 D1- AUX-A 23 [7] EDP_CPU_AUX EDP_SW_D1P [22] [35] MXM_SYS_LANE_P1 MB_DPA_AUX [39] CPU_EDP_HPD# 16 AUX+A D1+ 8 8 D1+ AUX+A 16 [7] CPU_EDP_HPD# EDP_SW_D2N [22] [35] MXM_SYS_LANE_N2 MB_DP_HPD [39] HPD_A D2- 9 9 D2- HPD_A EDP_SW_D2P [22] [35] MXM_SYS_LANE_P2 MXM_eDP_LANE_N0 33 D2+ 10 10 D2+ 33 [35] MXM_eDP_LANE_N0 EDP_SW_D3N [22] [35] MXM_SYS_LANE_N3 DPB_TXN0 [33] MXM_eDP_LANE_P0 32 D0-B D3- 11 11 D3- D0-B 32 [35] MXM_eDP_LANE_P0 EDP_SW_D3P [22] [35] MXM_SYS_LANE_P3 DPB_TXP0 [33] MXM_eDP_LANE_N1 31 D0+B D3+ D3+ D0+B 31 From GPU [35] MXM_eDP_LANE_N1 DPB_TXN1 [33] MXM_eDP_LANE_P1 30 D1-B D1-B 30 [35] MXM_eDP_LANE_P1 DPB_TXP1 [33] MXM_eDP_LANE_N2 29 D1+B 13 13 D1+B 29 [35] MXM_eDP_LANE_N2 EDC_SW_AUX# [22] [35] MXM_SYS_AUX# DPB_TXN2 [33] MXM_eDP_LANE_P2 28 D2-B AUX- 14 07/19 Delete CC70, CC71, CC75, CC76, 14 AUX- D2-B 28 [35] MXM_eDP_LANE_P2 CC77, CC78, CC79, CC80, CC81,EDC_SW_AUX CC82 [22] [35] MXM_SYS_AUX DPB_TXP2 [33] MXM_eDP_LANE_N3 27 D2+B AUX+ 5 SEL_eDP_MUX SEL_DP_MUX 5 AUX+ D2+B 27 [35] MXM_eDP_LANE_N3 DPB_TXN3 [33] MXM_eDP_LANE_P3 26 D3-B AUX_HPD_SEL 18 18 AUX_HPD_SEL D3-B 26 [35] MXM_eDP_LANE_P3 EDP_SW_HPD [22] [35] DCK1_SYS_HPD DPB_TXP3 [33] GPU_AUX# 19 D3+B HPD HPD D3+B 19 Docking [35] GPU_AUX# DPB_AUX# [33] GPU_AUX 20 AUX-B 1 1 AUX-B 20 [35] GPU_AUX DPB_AUX [33] GPU_HPD 15 AUX+B GND 17 17 GND AUX+B 15 [35] GPU_HPD DPB_HPD [33] HPD_B GND 22 22 GND HPD_B R505 2 1 25 GND 43 43 GND 25 R5441 2 10K_0402_5% +3VS OE HGND HGND OE +3VS 10K_0402_5% PI3VDP12412ZHEX_TQFN42_9X3P5 PI3VDP12412ZHEX_TQFN42_9X3P5 1

100K_0402_5% 07/23 Delete R516 and CC84 R504

2 +3VS +3VS 07/23 Delete R545 and C371 07/23 Modify net name B B 2

R462 1 10K_0402_5% R535 10K_0402_5% 1 SEL_eDP_MUX 2N7002KDW_SOT363-6 07/23 Change to dual channel Q76BMOS Q76 2 2N7002KDW_SOT363-6 3 SEL_DP_MUX Q76A [14,35] DGPU_SELECT# 5 6

4 07/23 Change dual channel MOS Q76 2 ISO_PREP# [13,33] 1

09/07 Add JVGA2 circuit

9/21 Correct netname. +5VS F1 +RCRT_VCC +CRTVDD

1.1A_8VDC_FUSE D46 0.1U_0402_10V6K 1 2 2 1 C468 G 3 W=40mils G

+5VS RB491D_SOT23-3 1 1 1 1 1 1 1 09/07 Delete VGA_RED, VGA_GRN, VGA_BLU, JVGA2 C VGA_DDCCLK, VGA_DDCDATA, CRT_HSYNC, and 6 C CRT_VSYNC off page symbol CC60 CC61 CC62 CC63 CC64 CC65 11 2 U28 +3VS 2 2 2 2 2 2 VGA_RED L321 2 39NH_CS0805-39NJ-S_5% DAC_RE L291 2 110NH_CS0805-R11J-S_5% DAC_RED R573 1 2 VGA_RE R5761 2 0_0805_5% VGA_R 1 10U_0603_6.3V6M 10U_0603_6.3V6M 0.1U_0402_16V4Z 0_0805_5% 7 16 [14] PCH_CRT_RED 7 29 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 12 17 17 REDAMAX14885E VCC VGA_GRN L331 2 39NH_CS0805-39NJ-S_5% DAC_GR L301 2 110NH_CS0805-R11J-S_5% DAC_GRN R574 1 2 VGA_GR R5771 2 0_0805_5% VGA_G 2 [35] RED_R 18P_0402_50V8J C459 18P_0402_50V8J C460 18P_0402_50V8J C461 REDB 21 0_0805_5% 8 1 18P_0402_50V8J C462 18P_0402_50V8J C463 18P_0402_50V8J C464 10P_0402_50V8J C465 10P_0402_50V8J C466 10P_0402_50V8J C467 8 VCC 10/25 Delete R570, R571, 13 [14] PCH_CRT_GRN GRNA R572. Add RP19 [35] GREEN_R 18 11 CC66 VGA_BLU L341 2 39NH_CS0805-39NJ-S_5% DAC_BL L311 2 110NH_CS0805-R11J-S_5% DAC_BLU R575 1 2 VGA_BL R5781 2 0_0805_5% VGA_B 3 GRNB VL 12/20 Change RP19 to 150ohms 0_0805_5% 9 09/12 Modify JVGA2 footprint 0.1U_0402_16V4Z 10/31 Modify JVGA2 footprint 9 2 14 [14] PCH_CRT_BLU BLUA [35] BLUE_R 19 4

BLUB 1 2 3 4 33 VGA_RED 1 1 1 1 1 1 1 1 1 10 5 RED1 24 R_DOCK_RED RP19 15 [14] PCH_CRT_DDC_CLK SCLA RED2 R_DOCK_RED [33] [35] GPU_VGA_DDC_CLK 15 150_0804_8P4R_5% @ @ @ 5 SCLB 32 VGA_GRN 6 GRN1 23 R_DOCK_GRN 2 2 2 2 2 2 2 2 2 C-H_13-12201572CP [14] PCH_CRT_DDC_DAT R_DOCK_GRN [33] 16 SDAA GRN2 8 7 6 5 [35] GPU_VGA_DDC_DAT SDAB 31 VGA_BLU CONN@ R3501 2 10K_0402_5% 2 BLU1 22 R_DOCK_BLU +5VS EN BLU2 R_DOCK_BLU [33] [14] PCH_CRT_HSYNC 3 35 VGA_DDCCLK 13 SHA SCL1 26 D_DDCCLK CRT_HSYNC R5791 2 0_0402_5% CRT_HSYNC_R [35] GPU_VGA_HSYNC SHB SCL2 D_DDCCLK [33] [14] PCH_CRT_VSYNC 4 34 VGA_DDCDATA CRT_VSYNC R5801 2 0_0402_5% CRT_VSYNC_R 14 SVA SDA1 25 D_DDCDATA [35] GPU_VGA_VSYNC D_DDCDATA [33] SVB SDA2 VGA_DDCCLK +5VS R3481 2 10K_0402_5% 1 37 R_CRT_HSYNC R3851 2 33_0402_1% CRT_HSYNC R3491 2 10K_0402_5% 40 S00 SH1 28 R_D_HSYNC R3861 2 33_0402_1% VGA_DDCDATA 07/25 Combine+5VS Q56 and Q57 to Q79 D_HSYNC [33] 39 S01 SH2 38 S10 36 R_CRT_VSYNC R3871 2 33_0402_1% CRT_VSYNC S11 SV1 27 R_D_VSYNC R3881 2 33_0402_1% D_VSYNC [33]

6 SV2 Q78A 30 GND 2N7002KDW_SOT363-6 3 20 12 D47 @ D48 @ D49 @ DGPU_SELECT# 2 Q78B 10 GND NC VGA_R 2 VGA_B 2 CRT_HSYNC 2 2N7002KDW_SOT363-6 GND 1 1 1 +3VS D [33] DOCK_ID 5 41 VGA_G 3 3 CRT_VSYNC 3 D

1 GPAD MAX14885EETL+T_TQFN40_5X5~D YSLC05CH_SOT23-3 YSLC05CH_SOT23-3 YSLC05CH_SOT23-3 LA-9241P

4 VGA_DDCCLK R5011 2 10K_0402_5% VGA_DDCDATA R5021 2 10K_0402_5%

Security Classification 2012/03/23 Deciphered Date 2009/12/31

Issued Date Title Compal Electronics, Inc. Size Document Number Rev Compal Secret Data Custom 0.5

Date: Switch/MUX/VGAThursday, December 20, 2012 Sheet 36of 56 1 2 3 4 5

+VCC_SM 1 R391 09/03 Change U30 P/N 4.7K_0402_5% 11/01 Change U30 to AU9560-GBS-GR

U30 D 2 SCardC8 XTAL_OUT D SCardC6 1 28 XTAL_IN SCardFcb PWRSV_SEL# 2 SCard0C8 XO 27 PWRSV_SEL# [14] +5VS 3 SCard0C6 XI 26 07/06 Correct netname to follow GPIO table SCardRst SCard0Fcb PWRSV_SEL SCardclk R395 0_0402_5% 4 25 5 SMIO_5VPWR LEDCRD 24 PLT_RST# [13,14,25,28,29,30,35,39,5] SCardData R396 470_0402_5% SCard0Rst LEDPWR SSDA T93 PAD~D @ 2 1 6 23 SSCL T94 PAD~D @ +3VS_SM [17] USBP7- SCard0Clk RESET 1 2 7 22 EEPWP T95 PAD~D @ [17] USBP7+ SCard0Data EEPDATA C252 8 21 ICCInsertN 1 +3VS_SM DM EEPCLK 09/20 Delete R393, CC67, and connector U30.23 to PLT_RST# 0.1U_0402_16V7K +VCC_SM 9 20 C253 10 DP P1(6) 19 C254 AV33 ICCInsertN +1.8VS_SM CC68 +5VS 11 18 2 12 SCPWR0 VDDH 17 +3VS_SM 5VGND VDDP 1 13 16 1 CC69 C257 C25814 5VInputC259 AU9560-GBS-GR_SSOP28VDD 15 C255 2 V33OUT V18OUT C256 0.1U_0402_16V7K 0.1U_0402_16V7K

2 1U_0402_6.3V6K 2 1 1 1 1 1 1 1 1U_0402_6.3V6K 0.1U_0402_16V7K 1U_0402_6.3V6K 0.1U_0402_16V7K 1U_0402_6.3V6K

2 2 2 2 20.1U_0402_16V7K 2

07/20 Vendor's suggestion 07/20 Vendor's suggestion

07/20 Vendor's suggestion 11/05 Uninstall Y3, CV33, CV34

CV33 18P_0402_50V8J C @ XTAL_OUT C

Y3 @ J3 @ RH225 12MHZ_12PF_5YEA12000122IFA2Q311/01 Change Y3 to small package 1 1M_0402_5%3 2 +VCC_SM

SCardRst 12 SCardclk C260 C261 2 GND 11 SCardFcb 4 1 GND @ XTAL_IN 10 SCardC6 @ 10 9 SCardData CV34 18P_0402_50V8J 9 8 SCardC8 8 ICCInsertN 7 1 1 7 6 6 5 ACES_51524-0100N-0015 4 C264 C265 C263 CONN@4 3 2 2 3 2 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 1 07/12 Modify J3 pin define 07/10 Modify J3 footprint @ @ @ 07/16 Modify J3 pin define 09/12 Modify J3 pin define

1 1 1

0.1U_0402_16V7K 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K 2

B B

A A

Title

Size Document Number Rev C Compal Electronics, Inc. 0.5 Date: Thursday, December 20, 2012 Sheet 37of 56

Issued Date Compal Secret Data Security Classification 2012/03/23 Deciphered Date 2011/06/29 Smart Card 5 4 www.vinafix.vn3 2 1

Power Board Conn 11/01 Add R626 JKB1 2 1 [26] REC_MUTE_CTRL_KB 4 2 1 3 R400 360_0402_5%4 3 +3VDS +5VDS [30] 8051RX_CAPLED# 1 2 6 5 +3VDS R626 0_0402_5%6 5 JPWR1 1 2 8 7 KSO12 C420 @ 100P_0402_50V8J [30] 8051_RECOVER#/_NUM_LOCK_LED# 8 7 ON/OFFBTN_KBC# +5VDS 10KSO13 9 1 KSI_D_92 C421 @ 100P_0402_50V8J 1 2 12 10 9 11 1 2 +3VDS 1 2 KSO1212 11 KSI_D_13 C422 @ 100P_0402_50V8J LID_SW# 3 4 14KSO9 13 1 KSI_D_62 C423 @ 100P_0402_50V8J [22,30,39] LID_SW# 5 3 4 6 [30] KSI[0..7] 16 14 13 15 1 2 2 [30,33,39] 8051TX_STBYLED# 8051TX_STBYLED#5 6 KSI7 KSI_D_916 15 C270 ON/OFFBTN_KBC#7 8 KSI6 18KSI_D_11 17 [30,33] ON/OFFBTN_KBC# 7 8 18 17 D 0.1U_0402_16V7K 9 10 KSI5 20KSI_D_13 19 KSO1 C424 @ 100P_0402_50V8JD 11 9 10 12 KSI4 22KSI720 19 21 1 KSO62 C425 @ 100P_0402_50V8J 1 11ACES_85203-0602N-1012 KSI3 24KSI_D_622 21 23 1 KSO42 C426 @ 100P_0402_50V8J CONN@ KSI2 26KSI_D_524 23 25 1 KSO32 C427 @ 100P_0402_50V8J 09/12 Modify JPWR1 connector pin define. KSI1 28KSO126 25 27 1 2 09/12 Modify JPWR1 connector footprint and pin define. KSI0 30KSO1028 27 29 10/26 Modify JPWR1 connector footprint and pin define. 30 29 C428 [30] KSO[0..13] 32KSO6 31 KSI_D_1 @ 100P_0402_50V8J 34KSO732 31 33 1 KSI_D_42 C429 @ 100P_0402_50V8J 36KSO434 33 35 1 KSI_D_102 C430 @ 100P_0402_50V8J C431 KSO13 38KSO836 35 37 1 KSI_D_82 @ 100P_0402_50V8J KSO12 40KSO338 37 39 1 2 KSO11 KSI_D_3 42 40 39 41 KSO10 KSI_D_1 44 42 41 43 KSO9 KSI_D_244 43 KSO13 C432 @ 100P_0402_50V8J KSO8 46KSI_D_4 45 KSO9 C433 @ 100P_0402_50V8J 48 46 45 47 1 2 TP/B Conn KSO7 KSI_D_048 47 KSI_D_11 C434 @ 100P_0402_50V8J KSO6 50KSI_D_10 49 1 KSI72 C435 @ 100P_0402_50V8J 07/12 Modify KB connector pin define. 50 49 KSO5 52KSI_D_12 51 1 2 07/20 Modify KB connector pin define. 52 51 KSO4 54KSI_D_8 53 1 2 08/07 Change JKB1 footprint 54 53 KSO3 56KSI_D_14 55 09/12 Modify JTP1 pin define and footprint 09/12 Change JKB1 footprint 56 55 KSO2 09/13 Change JKB1 pin define, 58KSO5 57 KSO1 60KSO258 57 59 10/31 Change JKB1 footprint and pin define,60 59 KSO0 11/05 Modify JKB1 pin define to follow62KSO0 ME request.61 JTP1 64KSO1162 61 63 KSI_D_5 C436 @ 100P_0402_50V8J 66 64 63 65 KSO10 C437 @ 100P_0402_50V8J 68 66 65 67 1 KSO72 C438 @ 100P_0402_50V8J SP_LEFT 1 2 68 67 1 KSO82 C439 @ 100P_0402_50V8J SP_MID 3 1 2 4 70 HB_A823461-SBVR0269 1 2 SP_RIGHT 5 3 4 6 GNDGND CONN@ 1 2 DDR_XDP_WAN_SMBCLK 5 6 KSI_D_3 C440 @ 100P_0402_50V8J [11,12,13,16,28,5] DDR_XDP_WAN_SMBCLK 7 8 DDR_XDP_WAN_SMBDAT KSI_D_2 C441 @ 100P_0402_50V8J [11,12,13,16,28,5] DDR_XDP_WAN_SMBDAT 9 7 8 10 TP_DATA KSI_D_0 C442 @ 100P_0402_50V8J [30] TP_DATA 11 9 10 12 1 2 TP_CLK D39 KSI_D_12 C443 @ 100P_0402_50V8J [30] TP_CLK 13 11 12 14 D33 D36 1 2 KSI_D_0 KSI_D_3 KSI_D_6 C +3VS 15 13 14 16 KSI_D_0 [39] 1 2 C KSI0 KSI3 KSI6 17 15 16 18 1 2 17 E-T_6900K-Q10N-00R18 KSI_D_8 KSI_D_11 KSI_D_14 KSI_D_14 C444 @ 100P_0402_50V8J C297 C298 19 20 2 2 2 KSO2 C445 @ 100P_0402_50V8J 1907/09CONN@20 Change by follow spec 1 1 1 DAP202UGT106_SOT323-3 KSO11 C446 @ 100P_0402_50V8J 08/10 Modify JTP1 pin define. DAP202UGT106_SOT323-3 DAP202UGT106_SOT323-3 3 3 3 1 KSO02 C447 @ 100P_0402_50V8J D34 D37 1 KSO52 C448 @ 100P_0402_50V8J 1 2 2 3 KSI_D_1 KSI_D_4 1 1 KSI_D_1 [39] 07/24 Add for EMI request KSI1 KSI4 1 2 2 3 100P_0402_50V8J +3VS KSI_D_9 KSI_D_12 1 2 D32 YSDA0502C C/A SOT-23 100P_0402_50V8J 07/16 Change P/N for ESD's request 2 2 2 2 07/20 Change P/N for ESD's request 1 DAP202UGT106_SOT323-3 1 DAP202UGT106_SOT323-3 1 10/11 Install D32 3 3

1 D35 D38 KSI_D_2 KSI_D_5 KSI2 KSI5 C296 KSI_D_10 KSI_D_13 2 2 DAP202UGT106_SOT323-3 DAP202UGT106_SOT323-3 1 0.1U_0402_16V7K 1 1 3 3

2 +5VS +5VDS

S R407 1 100K_0402_5% +5VS_KBL Q47 G JP13 D 09/27 Change R408 to 200k R408 200K_0402_5% Stick Point+5VS CONN 3 JP9 2 KB backlight Conn B AO3413L_SOT23-32 1 2 6 B 1 12 KBD_PWM_LED [30] G4 11 G3 10 8 7 @ G2 8 ACES_50611-0040N-0017 9 6 CONN@5 [30] SP_DATA G1 09/26 Modify4 6 JP9 pin5 3define to follow ME request 2

1 1 [30] SP_CLK 8 2 4 3 1 SP_LEFT 8 8 2 1 SP_MID 7 0.047U_0402_16V7K 7 Q10A SP_RIGHT 6 5 6 6 2 5 4 CONN@ KBL_DET# [18]

4 4 C295 3ACES_50554-0080N-001 2 3 1 2 2 1

07/09 Change by follow spec 09/12 Delete JTP2 connector 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6

A A

Title Compal Electronics, Inc.

Size Document Number Rev Custom 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 38of 56 Issued Date 2012/03/23 Deciphered Date 2011/11/02

KB/TP/LED 5 4 3 2 1

VGA+Function Board Thunderbolt

+5VDS +5VDS

JTB1 1 2 3 1 2 4 5 3 4 6 CLK_TB_REFCLK# [15] [17] USBP5- 7 5 6 8 CLK_TB_REFCLK [15] [17] USBP5+ 9 7 8 10 D MXM_TB_LANE_N3D [35] 11 9 10 12 [17] USB3TN6 11 12 MXM_TB_LANE_P3 [35] [17] USB3TP6 13 14 9/07 Remove JVGA1 BTB connector 13 14 15 16 MXM_TB_LANE_N2 [35] 17 15 16 18 [17] USB3RN6 17 18 MXM_TB_LANE_P2 [35] [17] USB3RP6 19 20 21 19 20 22 21 22 MXM_TB_LANE_N1 [35] [36] MB_DPA_TXP3 23 24 MXM_TB_LANE_P1 [35] [36] MB_DPA_TXN3 25 23 24 26 27 25 26 28 MXM_TB_LANE_N0 [35] [36] MB_DPA_TXP2 29 27 28 30 MXM_TB_LANE_P0 [35] [36] MB_DPA_TXN2 31 29 30 32 33 31 32 34 PCIE_PRX_DTX_N4 [17] [36] MB_DPA_TXP1 35 33 34 36 PCIE_PRX_DTX_P4 [17] [36] MB_DPA_TXN1 37 35 36 38 39 37 38 40 PCIE_PTX_C_DRX_N4 [17] [36] MB_DPA_TXP0 41 39 40 42 PCIE_PTX_C_DRX_P4 [17] [36] MB_DPA_TXN0 43 41 42 44 45 43 44 46 PCIE_PRX_DTX_N3 [17] [17] PCIE_PTX_EXPRX_N5 45 46 PCIE_PRX_DTX_P3 [17] [17] PCIE_PTX_EXPRX_P5 47 48 49 47 48 50 PCIE_PTX_C_DRX_N3 [17] 51 49 50 52 [17] PCIE_PRX_EXPTX_N5 51 52 PCIE_PTX_C_DRX_P3 [17] [17] PCIE_PRX_EXPTX_P5 53 54 55 53 54 56 55 56 PCIE_PRX_DTX_N2 [17] [30] iSCT_LED# [15] CLK_PCIE_EXP# 57 58 57 58 PCIE_PRX_DTX_P2 [17] Q80 [15] CLK_PCIE_EXP 59 60 2N7002KW_SOT323-3 59 60 [15] CLKREQ_EXP# 61 62 PCIE_PTX_C_DRX_N2 [17] 2 61 62 +5VDS [17] USBP6- 63 64 PCIE_PTX_C_DRX_P2 [17] [13,33] SATA_ACT# [17] USBP6+ 65 63 64 66 +1.5VS 67 65 66 68 PCIE_PRX_DTX_N1 [17] USB20JUB1 Function Board+5VS 10/23 Add Q80 for iSCT_LED# circuit. 3 1 [36] MB_DPA_AUX# 69 67 68 70 PCIE_PRX_DTX_P1 [17] JFUN1 69 70 +1.5VS [36] MB_DPA_AUX 71 72 G [36] MB_DP_HPD 73 71 72 74 PCIE_PTX_C_DRX_N1 [17] 1 2 75 73 74 76 PCIE_PTX_C_DRX_P1 [17] 1 2 [38] KSI_D_0 KSI_D_0 WL/BT_LED# 75 76 EN_P1V5 3 4 KSI_D_1 20 19 R623 1K_0402_5% Q81 77 78 C 3 4 [38] KSI_D_1 20 19 [13,14,25,28,29,30,35,37,5] PLT_RST# 77 78 MXM_TB_AUX# [35]C 5 6 KSO17 18 17 S D BSS138W-7-F_SOT323-3 79 80 [17] USBP9- 5 6 [30] KSO17 18 17 [30,33,38] 8051TX_STBYLED# 79 80 MXM_TB_AUX [35] 7 8 MUTE_LED_CNTR16 15 1 2 10/24 Change Q803 to 1 10/16 Change JTB1.91 net 81 82 [17] USBP9+ [26] MUTE_LED_CNTR single MOS, Add R623, Q81 name to iSCT_LED#[30] AMBER_BATLED# TB_HPD [35] 9 7 8 10 WL/BT_LED# 14 16 15 13 iSCT_LED# 83 81 82 84 9 10 [25] WL/BT_LED# 14 13 10/23 Change [13,30]netname BAT_GRNLED# 83 84 EN_P1V5 [30,33,40,44,45]

11 12 LID_SW# 12 11 2 85 86 [22,30,38] LID_SW# to TBT_RR_GPIO# [14] TBT_RR_GPIO# CPPWR_EN [30] 13 11 12 14 10 12 11 9 87 85 86 88 [17] TB_HOT_PLUG#07/18 Add PWR_GD signal TB_CLKREQ#07/18 Remove [15] B+ and change to HDD_HALTLED 15 13 14 16 8 10 9 7 89 87 88 90

S D 07/31 Change JTB1.95+3VDS to +3VDS HDD_HALTLED [13] 17 15 16 18 6 8 7 5 91 89 90 92 19 17 18 20 4 6 E-T_6900K-Q10N-00R5 3 93 91 92 94 19 20 4 3 +3VDS 93 94 +3VDS 21 ACES_50611-0120N-00122 9/07 Add JFUN1 connector 2 CONN@1 95 96 21CONN@22 2 1 EN_P1V5 95 96 07/10 Modify JUB1 footprint and pin23 define. 24 9/12 Modify JFUN1 pin define and footprint G 97 98 07/24 Modify JUB1 pin define. 23 24 09/26 Modify JFUN1 pin define to follow ME request 99 97 98 100 99 100

ACES_50019-10001-001 07/10 Modify JTB1 footprint101 and pin define. 102 C339 GND1 CONN@GND2 0.01U_0402_16V7K_X7R 07/17 Modify JTB1 pin define. 1 09/13 Modify JTB1 footprint

B B

07/06 Add NFC connector 07/09 Modify Pin define 07/19 Modify pin define 07/30 Modify Pin define. for better return path 08/07 Modify JNFC1 footprint and pin define JCR1 08/08 Modify JNFC1 pin define +5VDS +3VS 09/21 Delete R557, Non-install R358, C374 +3V_PCH Card Reader Board +3VS JNFC1 R358 [17] USBP4- CLK_PCIE_CR [15] +3VS @ 10K_0402_5%

[17] USBP4+ 45 46 CLK_PCIE_CR# [15] 1 43 GND GND 44 NFC CONN [17] USB3RN5 41 GND GND 42 PCIE_PRX_DTX_P8 [17] 08/10 Change JCR1.21[17] connectionUSB3RP5 to +3VS GND GND PCIE_PRX_DTX_N8 [17] NFC_RST# [16] NFC_SEL_R 08/10 Change JCR1.21 connection to +3VDS 39 40 [16] NFC_3S_SMBDAT 16 15 NFC_3S_SMBCLK [16] 07/19 Modify pin define 39 40 GND GND NFC_SEL_R C374 [17] USB3TN5 PCIE_PTX_C_DRX_P8 [17] [18] NFC_INT 2 37 38 NFC_SW14 13 @ [17]for betterUSB3TP5 return path 37 38 PCIE_PTX_C_DRX_N8 [17] [25] UIM_VPP @ GND GND 35 36 R558 0_0402_5% 0.1U_0402_16V4Z 35 36 [30] NFC_TX NFC_RX [30] 33 34 12 11 R556 +3VS 33 34 12 11 31 32 10 ACES_50559-01201-0019 @ +3VS 31 32 10 9 10K_0402_5% 08/01 JCR1.35 connection to PCH_PCIE_WAKE# 29 30 PLT_RST# R538 8 CONN@7 1 29 30 8 7 1 10/16 Delete R602, connection JCR1.5 to +5VDS 27 28 100K_0402_5% 6 5 27 28 CR_CLK_REQ# [15] 6 5 25 26 1 2 1 4 3 25 26 4 3 23 24 EXT_MIC_L2 [27] 2 1 21 23 24 22 2 1 2 09/19 Add R602, and noninstall. 19 21 22 20 7/13 Modify pin net name 2 19 20 HP_OUT_R [26] +5VDS 17 18

EN_P1V5 17 18 2 15 16 HP_OUT_L [26] [27] HP_SENSE# 13 15 16 14 11 13 14 12 ACES_50103-04071-001 07/30 Modify JCR1 pin define and footprint. A 9 11 12 10 A 9 CONN@10 08/07 Change JCR1 footprint 7 8 08/08 Change JCR1 pin define 5 7 8 6 5 6 3 4 Title LA-9241P 1 3 4 2 1 2 Size Document Number Rev 0.5 Security Classification Compal Secret Data Date: Thursday, December 20, 2012 Sheet 39of 56 Issued Date 2012/03/23 Deciphered Date 2010/03/31 I/O CONN Compal Electronics, Inc. 5 4 www.vinafix.vn3 2 1

09/24 Change power rail to +3VS 9/07 Add USB3.0 repeater and connector 09/24 Change power rail to +3VS Programmable output pre-emphasis level setting for channel A Equalizer control and program for channel B 次 3.3V +3VStolerant. Internally pulled down at +3VS 3.3V tolerant. Internally pulled down at ~150K 次 [A_EQ1, A_EQ0] == ~150K USB Power Switch [B_EQ1, B_EQ0] == A_DE0 R590@ 4.7K_0402_5% LL: 3.5dB de-emphasis B_EQ0 R594@ 4.7K_0402_5% 1 2 LH: No de-emphasis 1 2 LL: adaptive EQ enable LH: program EQ at 3.5dB A_DE1 R591@ 4.7K_0402_5% HL: 5dB de-emphasis B_EQ1 R589@ 4.7K_0402_5% +5VDS 1 2 HH: Reserved 1 2 HL: program EQ at 6dB +USB_CS HH: program EQ at 10dB A_EQ0 R596@ 4.7K_0402_5% B_DE0 R593@ 4.7K_0402_5% U43 1 2 1 2 W=100mils W=100mils A_EQ1 R595@ 4.7K_0402_5% Equalizer control and program for channel A B_DE1 R597@ 4.7K_0402_5% 1 8 1 2 3.3V tolerant. Internally pulled down at 1 2 GND VOUT 2 7 C479 C475 C484 C480 ~150K次 VIN VOUT 1 EN_P1V5 3 6 [A_EQ1, A_EQ0] == Programmable output pre-emphasis level setting for channel B 1 [30,33,39,44,45] EN_P1V5 VIN VOUT 4 5 + LL: adaptive EQ enable 3.3V tolerant. Internally pulled down at ~150K次 C481 C476 C483 EN FLG 1

G547I1P81U_MSOP8 1 150U_B2_6.3VM_R45M 1000P_0402_50V7K 1 0.1U_0402_16V4Z 1 680P_0603_50V7K LH: program EQ at 3.5dB [B_EQ1, B_EQ0] ==

1 1 1 HL: program EQ at 6dB LL: 3.5dB de-emphasis HH: program EQ at 10dB LH: No de-emphasis 680P_0603_50V7K 1000P_0402_50V7K 2

0.1U_0402_16V4Z HL: 5dB de-emphasis 09/24 Change power rail to +3VS 2 2 2 2 HH: Reserved 2 2

+3VS +3VS

change power switch to high active parts C502 C482 C469 20120803 1 1 2 10U_0603_6.3V6M USB3.0 Repeater 2 2 1 09/26 Add C502

VDD : 1.5V for PS8713A U44 09/24 ChangeVDD power : +3VS3.3V rail for PS8713B to +3VS 1 13 VDD A_EQ1 VDD B_EQ1 0.1U_0402_25V6K 0.1U_0402_25V6K

0.01U_0402_50V7K 0.01U_0402_50V7K A_DE0 B_DE0 A_EQ0 15 4 B_EQ0 A_DE1 B_DE1 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 C473 0.1U_0402_25V6K USB3_C_TP2 17 2 USB3_C_TP2_RE C470 0.1U_0402_25V6K USB3_TP2_RE 2 [17] USB3TP2 18 A_EQ0/NC B_EQ0/NC 6 2 [17] USB3TN2FORM CPU C471 0.1U_0402_25V6K USB3_C_TN2 A_DE1/NC B_DE1/NC USB3_C_TN2_RE C474 0.1U_0402_25V6K USB3_TN2_RE 1 2 19 12 1 2 A_INp A_OUTp TO USB CONNECTOR 09/24 Delete Q79, Q80, C475, C477, C478, R588, R587. 1 2 USB3_RP2_RE20 11 USB3_C_RP21 2 C486 0.1U_0402_25V6K A_INn A_OUTn USB3RP2 [17] USB3_RN2_RE USB3_C_RN2 C472 0.1U_0402_25V6K 09/24 Change power rail to +3VS USB3RN2 [17] FORM USB CONNECTOR 9 22 1 2 8 B_INp B_OUTp 23 1 2 B_INn B_OUTn TO CPU TEST +3VS TEST R592 4.7K_0402_5% 5 R598 1 PD# @ 7 10 1 2 14 REXT PS8713BTQFN24GTR2_TQFN24_4X4GND 21 24 TEST GND 25 I2C_EN GPAD 2

Chip test mode enable. 3.3V tolerant. Internally pulled down at ~150K次. TEST == L: Normal operation (default) H: Test mode enable Folow ESD team recommeend change ESD diode D5 D6 Add DC to DC interface 4.99K_0402_1% 4.99K_0402_1% 20120713 2012/8/3 D50 9/17 Swap L35, L36, L37 for layout smoothly USB3RXDN2_R USB3RXDN2_R

USB3RXDP2_R USB3RXDP2_R 3 3 USB3TXDN2_R1 9 USB3TXDN2_R USB3TXDP2_R USB3TXDP2_R 2 8 R583@ 0_0402_5% USB3.0 Connector USB3_TN2_RE USB3TXDN2_R 4 7 +USB_CS L36 5 6 TVWDF1004AD0_DFN9 1 2 JUSB1

3 2.5A USB20_N1_R 4 WCM-2012-900T_4P3 USB20_P1_R USB3_TP2_RE 4 3 USB3TXDP2_R TO USB connector TX R586@ 0_0402_5% USB20_N1_R USB3RXDN2_R 1 R584@ 0_0402_5%2 USB20_P1_R USB3RXDP2_R1 USB3_RN2_RE 1 2 USB3RXDN2_R 2 VBUS USB3TXDN2_R3 D- 1 L37 2 USB3TXDP2_R4 D+ @ GND 5 9/13 Modify JUSB1 footprint and pin define D51 6 SSRX- LOTES_AUSB0041-P002A10 YSLC05CH_SOT23-3 SSRX+ GND CONN@

1 2 3 2 7 11 8 GND GND 12 9 SSTX- GND 13 WCM-2012-900T_4P 4 3 SSTX+ GND USB3_RP2_RE 4 3 USB3RXDP2_R R582@ 0_0402_5% 1 2 TO USB connector RX 1 R585@2 0_0402_5% USB20_N1_R [17] USBP1-

1 L35 2 1

4 4

1 2 Title WCM-2012-900T_4P USB20_P1_R [17] USBP1+ 4 3 4 R5813@ 0_0402_5% Size Document Number Rev CustomCompal Electronics, Inc. 0.5 1 2 Security Classification 1 2 Compal Secret Data Date: Thursday, December 20, 2012 Sheet 40of 56 Issued Date 2012/05/11 Deciphered Date 2013/05/11 1 2 LA-9241P USB3.0 CONN/Repeater A B C D E

ADP_EN ACDRV

B+ +3VS DC IN ACFET RBFET D D

Jumper RT8243AZQW +3VDSP +3VDS SY8032 +1.5VSP +1.5VS

Jumper Main +5VDSP +5VDS BATT B++ EN +3VS EN ACDRV

BATT Battery RBFET Selector +1.35VP +1.35V Jumper RT8207M +1.5VP +1.5V 2nd BATT +0.675VSP +0.675VS Jumper EN_P1V5 +0.75VSP +0.75VS Charger SLP_S3# EN 7/19 C BQ24736 C

Jumper TPS51212 +1.05VMP +1.05VM

SIO_SLP_A# EN

TPS51631 +CPU_CORE

B B

VR_ON EN

A A

5 4 www.vinafix.vn3 2 1 5 4 3 2 1

PD11 PD10 AZC099-04S.R7G SOT23 ESD L30ESD24VC3-2_SOT23-3 +3VDS 4 3 2 V I/O V I/O 1 ADP_SIGNAL PJP2 Zero force Footprint: 5 2 3 V BUS Ground FOX_BP0208C-B24B1-9HQ_8P-T 6 1 V I/O V I/O 1 PL1 PJP2 7/11 PC2 VMB_A PL4 BATT_A PJP1 HCB2012KF-121T50_0805 @ FOXCONN BP0208C-B24B1-9H 8P BATT 0.1U_0603_50V7K HCB2012KF-121T50_0805 2 1 2 VIN 1 1 2 1 2 PL2 1 2 1 2 HCB2012KF-121T50_0805 2 I2C_MAIN_DAT-1 D 3 1 2 D 3 4 ADPIN 1 2 3 4 I2C_MAIN_CLK-1 PL5 1 3 4 PL3 4 5 HCB2012KF-121T50_0805 1 5 6 HCB2012KF-121T50_0805 5 6 PC7 5 6 6 PC3 0.01U_0402_50V7K

1 2 7 2 1 7 1000P_0402_50V7K

7 8 8 2 7 8 1 1 1 1 @ PR1 8 2 3 9 10 15K_0402_5% 9 10 PC1 PC1 PC4 PC4 PC5 PC5 PC6 PC6 2 2 2 2

@ ACES_59012-0100N-002 2 1 1 1 1 1 1 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K 1000P_0402_50V7K PC10 100P_0402_50V8J PR3 PR3 PC8 PC8 PR4 PR4 PC9 PC9 PR5 PR5 2 2 2

1 PD1 2 2 2 L30ESD24VC3-2_SOT23-3 1K_0402_5% 1K_0402_5% 100_0402_5% 100_0402_5% 100_0402_5% 100_0402_5% 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

I2C_MAIN_DAT [30,43]

I2C_MAIN_CLK [30,43] VIN [30] MAIN_BAT_DET# 1 C VIN C 1 PR13 PR13 PR14 300K_0402_5% 2

1 2 3.9K_0402_5% 3.9K_0402_5% SD028680380 3 PR10 PR10 2 +3VDS PQ1B 680K_0402_5% 680K_0402_5%

5 1 4 6 PQ1A 2 PR11 PR11 2 10K_0402_5% 10K_0402_5% 1 1 PD13 PD12 AZC099-04S.R7G SOT23 ESD L30ESD24VC3-2_SOT23-3 2

PR12 PR12 +3VDS

ME2N7002DKW-G 2N SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G 4 3 2 V I/O V I/O 1 SB00000SA00 30K_0402_5% 30K_0402_5% 5 2 3 V BUS Ground 6 1

V I/O V I/O 1 B SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G +3VDS PC11 B 0.1U_0603_50V7K VMB_B PL6 BATT_B 2 1 PJP3 7/11 HCB2012KF-121T50_0805

1 1 2 1 I2C_BAY_DAT-1 2 I2C_BAY_CLK-1 PL7 2 3 1 2 2 SD028300080 3 1 HCB2012KF-121T50_0805 1

PR15 PR15 4 4 5 PC12 PC13 300_0402_5% 300_0402_5% 5 6 2 1000P_0402_50V7K 2 0.01U_0402_50V7K 6 7 7 8 4 FOX_BR0208C-Z71H1-9H8 CONN@ 5

PQ2B 1 1 1 1 1 1

3 PC16 100P_0402_50V8J 2 2 2 6

PQ2A 2 2 2 PR7 PR7 PR8 PR8 PR9 PR9 PC14 PC14 PC15 PC15 1K_0402_5% 1K_0402_5% SB00000SA00 100_0402_5% 100_0402_5% 100_0402_5% 100_0402_5% 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J

1 I2C_BAY_DAT [30] 1

A I2C_BAY_CLK [30]A [30] TRAVEL_BAT_DET# 2 ME2N7002DKW-G 2N SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G

PR16 PR16 Security Classification Title DC Conn/BATT Conn

100K_0402_5% 100K_0402_5% Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of ME2N7002DKW-G 2N SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

VIN P1 P2 B+

PQ102 PQ101 AO4423L 1P SO8 MDU1512RH 1N POWERDFN56-8 PR102 PL101 1 8 1 0.005_1206_1% 1UH_PCMB053T-1R0MS_7A_20% 2 7 2 3 6 3 5 1 4 1 2 5 D 1 1 2 3 D 4 4 1 1 1 1 1 1 1 1 PC102 2

PR101PR101 PC101PC101 PR103PR103 0.1U_0402_25V6 2 2 2 2 2 2 2 2 2 2 1 1 PC103PC103 @ PC104PC104 PC105PC105 PC106PC106 PC107PC107 @ @ 220K_0402_5%220K_0402_5% 220K_0402_5%220K_0402_5% 1 2 PC108PC108 PC138PC138

0.1U_0402_25V60.1U_0402_25V6 ACFET_CHG 0.1U_0402_25V60.1U_0402_25V6 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K 68P_0402_50V8J68P_0402_50V8J 2200P_0402_50V7K2200P_0402_50V7K 6

@ PR104PR104 PR105PR105 1 2 2 1 1 PD101PD101 82P 50V J NPO 04020402NPONPO82P82P50V50V JJ PQ103A ME2N7002DKW-G 2N SOT363-6 4.12K_0603_1%4.12K_0603_1% 4.12K_0603_1%4.12K_0603_1% for RF request, 8/6 2 2 PC109PC109 PC110PC110 2 1 BAT54WS-7-F_SOD323-2~DBAT54WS-7-F_SOD323-2~D 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 PQ105 5 AO4409L 1P SO8 3 1

SB00000SA00 ACDRV_CHG CMSRC_CHG ACP_CHG ACN_CHG B+ PQ104 P2 +3VDS CHRG_ADP_DET AON7408L_DFN8-5 1 8 PR108 2 7 2 1 3 P1 6 PR107PR107 4 5 4 2.2_0402_1% 5

PQ103BPQ103B PU102 2 21 3 5 1 4

100K_0402_5%100K_0402_5% 1 2 4 BQ24736RGRR_QFN20_3P5X3P5 PR109

10_1206_1% 3 2 1 2 ACP PAD ACN PC111 ACDRV CMSRC VCC_CHG BATT ADP_EN [30] ACPRES 1U_0603_25V6K PR110

ME2N7002DKW-GME2N7002DKW-G2N2NSOT363-6SOT363-6 0.02_1206_1% PL102 ICS C 6 20 1 2 4.7U 20% VMPI0703AR-4R7M-Z01 5.5A C PR127 ACDET VCC LX_CHG CHG 10_0402_1% 1 [30,42] I2C_MAIN_DAT 7 19 DH_CHG 1 2 1 4 IOUT PHASE PR112 2.2_0402_1% 2 3 BST_CHG-1PC112 [30,42] I2C_MAIN_CLK 1 2 8 18 0.047U_0402_25V7K 5 2 PR128 SDA HIDRV 1 CSOP1 CSON1 BST_CHG PR111PR111

10_0402_1% 1 1 1 1 1 1 1 1

REGN_CHG 4.7_1206_5%4.7_1206_5% 4/12 1 2 9 17 1 2 1 2 +3VDS SCL BTST 2 2 2 2 2 2 2 2 1 [50] SRSET 2 DLIM SRN SRP GND LODRV PC115PC115 PC116PC116 PC117PC117 PC113PC113 PC114PC114 PC154PC154 PC155PC155 4/11 10 16 PD103 PC118PC118 1 ILIM REGN RB751V-40_SOD323-2 1 1 11 12 13 14 15 PD102PD102 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 3 2 1 2 PR113 2 4 SNB_CHG 2 +5VS VIN 22K_0402_1% 2 2 1 PC119PC119

1 1 1 PC120 RB551V-30_SOD323-2RB551V-30_SOD323-2 PQ106PQ106

1U_0603_25V6K PC121PC121 CHRG_ADP_DET [30] AON7406L_DFN8-5AON7406L_DFN8-5 10U_0805_25V6K10U_0805_25V6K

PR117 1U_0603_25V6K1U_0603_25V6K @ @

4/12 0.1U_0402_25V60.1U_0402_25V6 0.01U_0402_50V7K0.01U_0402_50V7K 10U_0805_25V6K10U_0805_25V6K

PR114 PR115 10K_0402_5% DL_CHG 0.01U_0402_50V7K0.01U_0402_50V7K 2200P_0402_50V7K2200P_0402_50V7K 2 18.2K_0402_1%PD104 2 127K_0402_1% 2 PR116 LL4148_LL34-2

1M_0402_5% 680P_0402_50V7K680P_0402_50V7K

[50] V_3.9K SRN_CHG SRP_CHG

1 1 1 2 1 1

2 1 2 PR120 2 0_0402_5% 1 2 2 B PR118 PR119 D PC123PC123 B

10K_0402_1% 20K_0402_1% PC122PC122 2 G 1 PR1212 PC124 S 0.01U_0402_50V7K0.01U_0402_50V7K 100P_0402_50V8J100P_0402_50V8J 0_0402_5% 0.1U_0603_25V7K 1

PQ108 PR122 1 2

3 0_0402_5%

2N7002KW 1N SOT323-3 1 1 CURRENT_ADC [30] CHRG_RST [30] 2 12 2 @2

PC126

PC125PC125 0.22U_0402_6.3V6K

B+ 100P_0402_50V8J100P_0402_50V8J 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VIN Remove 6 *2200pF MLCC for RF request, 11/6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PR124 PR125 @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ @ 49.9K_0402_1% 576K_0402_1% 1 1 1 PC134PC134 PC136PC136 PC137PC137 PC143PC143 PC144PC144 PC147PC147 PC148PC148 PC151PC151 PC152PC152 PC130PC130 PC131PC131 PC133PC133 VOLTAGE_ADC [30] 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 2 2 6.8P_0402_50V8C6.8P_0402_50V8C 6.8P_0402_50V8C6.8P_0402_50V8C 6.8P_0402_50V8C6.8P_0402_50V8C 6.8P_0402_50V8C6.8P_0402_50V8C 6.8P_0402_50V8C6.8P_0402_50V8C SD034576380 6.8P_0402_50V8C6.8P_0402_50V8C

A PC139PC139 PC140PC140 PC141PC141 PC145PC145 PC149PC149 PC153PC153 A 1 2 1 2 2 PR126 PC128

PC127PC127 49.9K_0402_1% 0.22U_0402_6.3V6K for RF request, 8/6 82P 50V J NPO 04020402NPONPO82P82P50V50V JJ 04020402NPONPO82P82P50V50V JJ 04020402NPONPO82P82P50V50V JJ 04020402NPONPO82P82P50V50V JJ 04020402NPONPO82P82P50V50V JJ 04020402NPONPO82P82P50V50V JJ Title 100P_0402_50V8J100P_0402_50V8J CHARGER

Size Document15W Number Rev Issued Date Security Classification Date: Thursday, December 20, 2012 Sheet of Compal SecretDeciphered Data Date Compal Electronics, Inc. 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1 0.3

PQ306 D 2N7002KW 1N SOT323-3 1 PR316 @ 0_0402_5% 2 EN_P1V5G [30,33,39,40,45] +5VLP S 1 2 3

+3VDS 1 PQ305A 6 PR326PR326 2 D D PQ305B 100K_0402_1%100K_0402_1% 2 1 3

PC320 100P_0402_50V8J <1>5V=283KHz 3V=330KHz (Vin=6.5 ~ 12v) 5 1 2 <2>5V=321KHz 3V=375KHz (Vin=12 ~ 25v) 4 SB00000SA00 PR304 PR305 (By Rton= 68K ohm) [30,34] KBC_PWR_ON 13.7K_0402_1% 30K_0402_1% +5VDSP

ME2N7002DKW-GME2N7002DKW-G2N2NSOT363-6SOT363-6 +3VDSP 1 2 2 1 PR306 PR307 B+ 20K_0402_1% 20K_0402_1% B++ 1 2 1 B++

ME2N7002DKW-GME2N7002DKW-G2N2NSOT363-6SOT363-6 2 1 1 2 For RF request, 11/5 2 1 2

1 2 1 1 1 1 1 1 @ PJP301 1 1 1 1 1 1 PAD-OPEN 1x3m 1 PR308PR308 124K_0402_1% 124K_0402_1% PR310PR310 68K_0603_5% 68K_0603_5% PR309PR309 115K_0402_1% 115K_0402_1% 2 2 2 2 PQ301 PC321 2 2 5

2 2 2 2 2 2 1U_0402_10V6K @ @ @ 5

@ @ @ 2 @ PR311 PQ302PC306PC306 PC307PC307 PC308PC308 PC309PC309 PC323PC323 PC325PC325 4 2 5 1 3 FB_3V ENTRIP2 ENTRIP1 FB_5V PC324PC324 PC322PC322 PC305PC305 PC304PC304 PC303PC303 PC334PC334 0_0402_5% PU301 0.1U_0402_25V60.1U_0402_25V6 68P_0402_50V8J68P_0402_50V8J

For HP request, 11/5 2200P_0402_50V7K2200P_0402_50V7K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K 100P_0402_50V8J100P_0402_50V8J 100P_0402_50V8J100P_0402_50V8J 0.1U_0402_25V60.1U_0402_25V6 FB2 FB1 68P_0402_50V8J68P_0402_50V8J 2200P_0402_50V7K2200P_0402_50V7K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K 3VDS_PG PG_3V_5V TON C PC3101 2 PR313 C ENTRIP2 ENTRIP1 4 0.1U_0603_25V7K 2.2_0603_5% 21 PR312 PC311 PAD 3 1 2 BST_3V-1 6BST_3V 2.2_0603_5% 0.1U_0603_25V7K4 For RF request,for RF request, 11/5 8/6 PGOOD for RF request, 8/6 20 BST_5V BST_5V-1 3 2 1 SIS412DN-T1-GE3_POWERPAK8-5 RT8243AZQW BYP1WQFN 20P PL303 2 1 1 2 7UG_3V 4.7U 20% VMPI0703AR-4R7M-Z01 5.5A BOOT2 UG_5V PL302 SIS412DN-T1-GE3_POWERPAK8-5SIS412DN-T1-GE3_POWERPAK8-5 19 1 2 1 2 BOOT1 2.2UH +-20% ETQP3W2R2WFN 8.5A SH00000PH00 LX_3V 8 1 1 5 LX_5V +5VDSP +3VDSP UGATE2 18 1 2 UGATE1 + PQ303 LG_3V 5 + 9 LG_5V 1 2 PHASE2 17 PQ304 PHASE1 2 2 VIN ENLDO ENM LDO5 LDO3 1 1 1 1 1 1 1 1 10 LGATE2 1 1 16 11 12 13 14 15 PR315PR315 PR314PR314 LGATE1 2 2 2 2 2 2 2 2 4.7_1206_5%4.7_1206_5% 1 4.7_1206_5%4.7_1206_5% 1 2 @ @ @ 2 1 2 4 3 AON7406L_DFN8-5 @ @ @ PC330PC330 PC331PC331 PC332PC332 PC326PC326 PC327PC327 PC328PC328 3 2 1

PR321 1 +3VLP 4 PC315PC315 PC333PC333 PC329PC329 PC314PC314 499K_0402_1% 0.1U_0402_25V60.1U_0402_25V6 0.1U_0402_25V60.1U_0402_25V6 6.8P_0402_50V8C6.8P_0402_50V8C 6.8P_0402_50V8C6.8P_0402_50V8C 1 220U_6.3V_M220U_6.3V_M 220U_6.3V_M220U_6.3V_M 2 PC313PC313 ENLDO_3V_5V PC302 2 2200P_0402_50V7K2200P_0402_50V7K Typ: 175mA 2200P_0402_50V7K2200P_0402_50V7K 2

4.7U_0805_10V6K PC312PC312 1 100P_0402_50V8J100P_0402_50V8J 100P_0402_50V8J100P_0402_50V8J

B++ 1 1

1 2 2 680P_0402_50V7K680P_0402_50V7K 680P_0402_50V7K680P_0402_50V7K for RF request, 8/6 2 2 2 1 +5VLP MDV1526URH_PDFN33-8-5MDV1526URH_PDFN33-8-5 for RF request, 8/6 B PC317 B 2 4.7U_0805_10V6KTyp: 225mA PC319PC319 PC316PC316 PR325PR325 PR324PR324 100K_0402_1%100K_0402_1% 1U_0402_10V6K1U_0402_10V6K 0.1U_0603_25V7K0.1U_0603_25V7K PJP302 JUMP_43X118 +3VLP +5VDSP +5VDS 10K_0402_1%10K_0402_1% PJP303 JUMP_43X118 1 2 +3VDSP 1 2 +3VDS

1 2 1 2 PJP306 JUMP_43X39

+5VLP +5VL

1 2 A 1 2 A

Title

Size Document Number Rev Issued Date Custom 0.3 Security Classification Date: 3VDSP/5VDSPSheet 44of 52 2011/06/13 Compal SecretDeciphered Data Date 2014/12/31 Compal Electronics,15W Inc. 5 4 www.vinafix.vn3 2 1

PL401 HCB1608KF-121T30_0603 For RF request, 11/5 PC402 PR418 B+ 1 2 B+_1.35V 0.22U_0402_10V6K 2.2_0603_5% 1 2 1 2

PR402 1 1 1 1 1 1 0_0402_5% 1 2 PC419 PC419 PC401 PC401 PC403 PC403 PC404 PC404 PC405 PC405 PC406 PC406 2 2 2 2 2 2 +1.35VP @ @ @ @ 0.1U_0402_25V6 0.1U_0402_25V6 68P_0402_50V8J 68P_0402_50V8J 10U_0805_25V6K 10U_0805_25V6K +0.675VSP 4.7U_0805_25V6-K 4.7U_0805_25V6-K 2200P_0402_50V7K 2200P_0402_50V7K 82P 50V J NPO 0402 0402 NPO NPO J J 50V 50V 82P 82P

D 5 D PQ401 for RF request, 8/6 1 1 LX_1.35V DH_1.35V BST_1.35V +1.35VP +0.675VSP 2 2 18 16 19 17 20 4 PU401 PC407 PC407 PC408 PC408

VTT 21 PL402 PAD 10U_0805_6.3V6K 10U_0805_6.3V6K 10U_0805_6.3V6K 10U_0805_6.3V6K BOOT PHASE 2.2UH_VMPI0703AR-2R2M-Z01_8A_20% SIS412DN-T1-GE3_POWERPAK8-5 DL_1.35V UGATE VLDOIN

1 2 3 15 1 LGATE VTTGND 1 2

1 5 14 2 +1.35VP PR403 PGND VTTSNS PQ402 15.8K_0402_1% PR404 CS_1.35V 1 2 13 3 + 4.7_1206_5% CS RT8207MZQW_WQFN20_3X3GND

1 2 VTTREF_0.675V 4 12 4 PR405 VDDP VTTREF 5.1_0603_5% +5VDS VDD_1.35V +1.35VP 1 2 11 5 +1.35VP

PC409 PC409 330U_2.5V_M 330U_2.5V_M VDD VDDQ 2 1 2 3 MDV1526URH_PDFN33-8-5+5VDS 1 1 1

1 PC411 PC412 PC413 SNB_1.35V 1U_0603_10V6K 1U_0603_10V6K PGOOD TON S5 S3 FB 0.033U_0402_16V7K 2 2 2 9 8 7 6 2 10 PC410 PC410 C PR419@ C +3VS 100K_0402_5%

680P_0603_50V7K 680P_0603_50V7K 1 2 1.35V_PG PR406 10.2K_0402_1%

PR407 TON_1.35V S3_1.35V FB_1.35V 1 2 +1.35VP 7/11 887K_0402_1% B+_1.35V 1 2 PR408 42.2K_0402_1%

1 2 1 PC415 .1U_0402_16V7K 2

D 1 [30,33,39,40,44] EN_P1V5 PC418 PR411 0.22U_0402_16V7K G 10.2K_0402_1% S PR412 PQ403 2 1 1 1 0_0402_5% 2N7002KW 1N SOT323-3 1 PR416 1 2 DDR3_SET [14]8/1 [14,30,31,34] SLP_S3# 2 B 4.7K_0402_5% 2 B 3 2 2 1 1

PR417 PR417 @ PC416 @ PC417

100_0402_5% 100_0402_5% 0.1U_0402_10V7K 0.1U_0402_10V7K 2 2 1 1

1 PR420 PR415 PD401 42.2K_0402_1% 10K_0402_5% BAT54CW_SOT323-3 2 2 2 3

PJP401 JUMP_43X118 [14] SLP_S4# KBC_DS3_EN [30,5]

1 2 +1.35VP PJP402 +1.35V JUMP_43X39

1 2 1 2 A +0.675VSP +0.675VS A

Security Classification Title DDR Power Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

PL501 HCB2012KF-121T50_0805 B+_1.05V 1 2 B+ D D 1 1 1 1 1 1 2 2 2 2 2 2 PC504 PC504 PC505 PC505 PC502 PC502 @ PC503 PC503 @ PC512 PC512 @PC513 PC513

+3VS 0.1U_0402_25V6 0.1U_0402_25V6 68P_0402_50V8J 68P_0402_50V8J 4.7U_0805_25V6-K 4.7U_0805_25V6-K 4.7U_0805_25V6-K 4.7U_0805_25V6-K 2200P_0402_50V7K 2200P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 5 PQ501 1 @ PR502 PC506 for RF request, 8/6 PR511 2.2_0603_5% 0.22U_0603_16V7K 100K_0402_5% BST_1.05V-1 [31] 1.05VM_PG 1 2 1 2 4 2 PU501 7/17 PR503 BST_1.05V SIS412DN-T1-GE3_POWERPAK8-5

1 10 3 2 1 86.6K_0402_1% PGOOD VBST PR504 TRIP_1.05V DH_1.05V PL502 1 2 2 9 100_0402_5% TRIP DRVH 2.2UH +-20% ETQP3W2R2WFN 8.5A EN_1.05V LX_1.05V 1 2 3 8 1 2 [14,30,31] SIO_SLP_A# EN SW FB_1.05V +1.05VMP

4 7 1 VFB V5IN RF_1.05V DL_1.05V +5VDS 4/11 5 6 PR505 + RF DRVL 1 4.7_1206_5%

1 11 PC507 5

TP 2 C 1 TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M PQ502 1 C PR506 2 PC510 470K_0402_1% 330U_2.5V_M 2 @ 2 PC508 PC508 4 2 .1U_0402_16V7K .1U_0402_16V7K 1

SNB_1.05V PC511 1 3 2 680P_0603_50V7K 2 AON7406L_DFN8-5 AON7406L_DFN8-5 PR508 5.11K_0402_1% D 2 1 G S PQ503

2N7002KW 1N SOT323-3 2 1 PR510 10K_0402_1% 2 [34] KBC_PWR_ON# 3 1 PJP501 +1.05VMP +1.05VM B 2 1 B 2 @ JUMP_43X791

4/11

A A

Security Classification Title 1.05VMP Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

CPU_VREF PR244 2.1K_0402_1% phase3 2 1 37W pop, 47W up unpop 1 1 1 1 1 1

@ PR201 1 1 CSP3 1 PH202PH202 10K_0402_1% PH201PH201 EMI Part (47.1)RF Part (47.3) EMI Part (47.1) 1 PC201PC201 PR204PR204 PR208PR208 PR210PR210 2 2 2

PR206PR206 CPU_B+ 255K_0402_1%255K_0402_1% 2 2 2 2 88.7K_0402_1%88.7K_0402_1% 36.5K_0402_1%36.5K_0402_1% 1 PR214PR214 PC209PC209 @@ EMI@ PC260 EMI@ PR243 4700P_0402_16V7K4700P_0402_16V7K 100K_0402_1%100K_0402_1% 2 2 470P_0402_50V7K 4.7_1206_5% CSN3 1 1 2 1 2 1 2 63.4K_0402_1%63.4K_0402_1% 100K_0402_1%_TSM0B104F4251RZ100K_0402_1%_TSM0B104F4251RZ PR216PR216 1 1 1 1 1 1 10K_0402_1%_TSM0A103F34D1RZ10K_0402_1%_TSM0A103F34D1RZ 0.15U_0402_10V6K0.15U_0402_10V6K 1 1 1 1 3.01K_0402_1%3.01K_0402_1% 2 PC232PC232 PC238PC238 PC265PC265 PC268PC268 PC229PC229 PC230PC230 1 2 3 2 2 2 2 2 2 1 0.1U_0402_25V60.1U_0402_25V6 PR205PR205 PR207PR207 PR209PR209 PR211PR211 1 9

68P_0402_50V8J68P_0402_50V8J 5 4 1 4 2200P_0402_50V7K2200P_0402_50V7K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K EMI@ EMI@ EMI@ EMI@

PR202 PR203PR203 PC202PC202 @RF@@RF@ @RF@@RF@ PGND2 VIN VSW +VCC_CORE 2 2 2 2 2 82P 50V J NPO 04020402NPONPO82P82P50V50V JJ 39K_0402_1%39K_0402_1% 20K_0402_1%20K_0402_1% 39K_0402_1% 10K_0402_1%10K_0402_1% PR2181 2.2_0402_5%2 6 3 100K_0402_1%100K_0402_1% 150K_0402_1%150K_0402_1% 2 .1U_0402_16V7K.1U_0402_16V7K BOOT_R PGND1 1 2 7 2 0.15UH +-20% ETQP4LR15AFM 29A

2 PL203 BOOT VDD PC248 .1U_0402_16V7K 8 1 1 2 F-IMAX PWM3 SKIP PWM SKIP# PR212 SLEWA OCP-I B-RAM PR217 EMI Part (47.1) 10K_0402_1%2 1 O-USR PU204 0_0402_5% CSD97374CQ4M_SON8_3P5X4P5 CPU_B+ PJP201 1 2 PC210 PU201 1U_0402_6.3V6K2 1 15 10 9 16 11 13 12 14 CPU_B+ PAD-OPEN 1x3m B+ PR227 +5VDS 17 8 0_0402_5%1 2 + 1 2 + + CSP1 VR_ON 1 1 1

CSP1 IMON VBAT OCP-I

O-USR PWR_GD [30,31,5]

18 F-IMAX 7 SLEWA THERM @EMI@ PL201 CSN1 B-RAMP SKIP# 37W pop, 47W up unpop CSN1 SKIP FBMA-L11-453215-800LMA90T_1812 19 6 CSN2 PWM1 2 2 2 PC234PC234 PC235PC235 @ PR242 CSN2 PWM1 PC233PC233 1 2 20 5 0_0402_5% CSP2 PWM2 100U_25V_M100U_25V_M 100U_25V_M100U_25V_M CSP2 PWM2 100U_25V_M100U_25V_M 21 4 Acoustic (37.2) +3VS CSP3 PWM3 @ CSP3 TPS51631RSMR_QFN32_4X4 PWM3 22 3 2 CSN3 PGOOD 2 CSN3 PR241 23 2 VGATE [31] GFB VDD 2 1 GFB 1 PR221 2 24 1 2.1K_0402_1% 0_0402_5% VFB VDIO VFB SDIO [10,9] VSSSENSE 1 2 2 2 1 [9] VCCSENSE EMI Part (47.1)RF Part (47.3) EMI Part (47.1) CSP1 PH203PH203 PR252PR252 PR253PR253

PR224 1 0_0402_5% DROOP COMP VREF V5A GND VR_HOT# VCLK ALERT# PAD PC250 CPU_B+ 1 10_0402_1%10_0402_1% PR225PR225 PC213PC213

1U_0603_10V6K 47K_0402_1%47K_0402_1% EMI@ PC259 EMI@ PR240 1 1 2 1 2 25 26 27 28 29 30 31 32 33 CSN1 2 1 1 470P_0402_50V7K 4.7_1206_5% 63.4K_0402_1%63.4K_0402_1%

PC246 @ 2

1 2 1 2.2P_0402_50V8C 2 2 0.15U_0402_10V6K0.15U_0402_10V6K PR229PR229 1PR219 2 2 3 10K_0402_1%_TSM0A103F34D1RZ10K_0402_1%_TSM0A103F34D1RZ 1 1 +3VS 1 1 1 1 PC211PC211 PC212PC212 2.94K_0402_1% PC214PC214 PC215PC215 PC264PC264 PC267PC267

1PR220 2 5 4 1 4 3.01K_0402_1%3.01K_0402_1% 0.1U_0402_25V60.1U_0402_25V6

10K_0402_1% VR_HOT# SCLK ALERT# 2 2 2 2 2 2 2 68P_0402_50V8J68P_0402_50V8J 2200P_0402_50V7K2200P_0402_50V7K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K EMI@ EMI@

EMI@ EMI@ 1 2 6PGND2 3 @RF@@RF@ @RF@@RF@ VIN9 VSW +VCC_CORE CPU_VREF 04020402NPONPO82P82P50V50V JJ PR223 2.2_0402_5% 1PR215 2 PC2451 2 1 2 7 2 10K_0402_1% 330P_0402_50V7K BOOT_R PGND1 0.15UH +-20% ETQP4LR15AFM 29A 8 1 1 2 PL204 BOOT VDD PC257PC257 PC203 PC253 .1U_0402_16V7K PC258PC258 1 1 1 PWM1 SKIP 0.33U_0402_10V6K PWM SKIP# PR233 PU202 0_0402_5% @RF@@RF@ @RF@@RF@ 68P_0402_50V8J68P_0402_50V8J 2 2 2

CSD97374CQ4M_SON8_3P5X4P5 220P_0402_25V8K220P_0402_25V8K 1PR226 2 10_0603_1% RF Part (47.3) PC216 2 1 3 3 +5VDS 1U_0402_6.3V6K

PC254 +5VDS

1U_0603_10V6K1 2 1 PR250 2.1K_0402_1% 2

EMI Part (47.1)RF Part (47.3) EMI Part (47.1) 1 CSP2 PH204PH204 CPU_B+ 1 2 1 2 1

EMI@ PC263 EMI@ PR249 PR235PR235 PC217PC217 1 +VCCIO_OUT 470P_0402_50V7K 4.7_1206_5% CSN2 63.4K_0402_1%63.4K_0402_1% 2

2 3 2 1 0.15U_0402_10V6K0.15U_0402_10V6K PR239PR239 10K_0402_1%_TSM0A103F34D1RZ10K_0402_1%_TSM0A103F34D1RZ 2

PC207PC207 PC208PC208 PC266PC266 PC269PC269 PC204PC204 PC205PC205 5 4 1 4 1 1 1 1 1 1

PC256 3.01K_0402_1%3.01K_0402_1% 0.1U_0402_25V60.1U_0402_25V6 .1U_0402_16V7K 1 2 6 3 2 2 2 2 68P_0402_50V8J68P_0402_50V8J 2200P_0402_50V7K2200P_0402_50V7K 10U_0805_25V6K10U_0805_25V6K 10U_0805_25V6K10U_0805_25V6K EMI@ EMI@ EMI@ EMI@

PR230PR230 PR231PR231 PR232PR232 PGND2 @RF@@RF@ @RF@@RF@ 2 2 2 2 2 2 2 VIN VSW

1 2 100_0402_5%100_0402_5% 100_0402_5%100_0402_5% 100_0402_5%100_0402_5% PR2451 2.2_0402_5%2 7 2 +VCC_CORE 82P 50V J NPO 04020402NPONPO82P82P50V50V JJ 9

1 BOOT_R8 PGND1 1 1 2 0.15UH +-20% ETQP4LR15AFM 29A 1 2 SDIO PL202

1 1 1 BOOT [9] VR_SVID_DAT PR236 PC261 .1U_0402_16V7K VDD PWM2 SKIP 22_0402_5% PWM 1 2 ALERT# SKIP# PR247 [9] VR_SVID_ALRT# PR237 PU203 0_0402_5% 22_0402_5% CSD97374CQ4M_SON8_3P5X4P5 4 1 2 SCLK 4 [9] VR_SVID_CLK PR238 2 1 22_0402_5% PC262 [24,5] KBC_PROC_HOT_R VR_HOT# 1U_0402_6.3V6K PR228 Compal Electronics, Inc. 0_0402_5% +5VDS @ PC206 47P_0402_50V8J

1 Issued Date Title Security Classification

2 2011/06/24 2014/12/31 Size DocumentPWR-CPU_CORE Number Rev Deciphered Date Custom 0.3 Compal Secret Data Date: Sheet 47of 52 A www.vinafix.vnB C D

2 X 470u/4m +VCC_CORE 30 X 22u/0805

+VCC_CORE

D D

+ + 1 1

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 PC2001 PC2001 PC2002 PC2002 PC2005 PC2005 PC2006 PC2006 PC2007 PC2007 PC2008 PC2008 PC2009 PC2009 PC2010 PC2010 PC2011 PC2011 PC2012 PC2012 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M @@ 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 470U_D2_2VM_R4.5M 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 PC2019 PC2019 PC2020 PC2020 PC2021 PC2021 PC2022 PC2022 PC2023 PC2023 PC2013 PC2013 PC2014 PC2014 PC2015 PC2015 PC2016 PC2016 PC2017 PC2017 PC2018 PC2018 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 1 1 1 1 1 1 1 1 1 1 1 C C 2 2 2 2 2 2 2 2 2 2 2 PC2024 PC2024 PC2025 PC2025 PC2026 PC2026 PC2027 PC2027 PC2028 PC2028 PC2029 PC2029 PC2030 PC2030 PC2031 PC2031 PC2032 PC2032 PC2033 PC2033 PC2034 PC2034 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

B B

A A

Security Classification Title PROCESSOR DECOUPLING Deciphered Date Issued Date Size DocumentLA-9371P Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

1 1

2 PC602 +3VS 680P_0402_50V7K 1 SNUB_+1.5V

7/17 1 PJP602 1 JUMP_43X39 2 @ 2 PU601 4X4 2 SY8032ABC_SOT23-6 PL602 PR601 PR601 1 0.47UH +-20% PCMC042T-R47MN 6A PJP601 LX_1.5V4.7_0402_1% 4.7_0402_1% 4 3 1 2 2 1 IN LX 2 1 PR602 +1.5VSP +1.5VSP @ JUMP_43X39 +1.5VS 5 2 PG GND 10K_0402_5% EN_1.5V 1

6 1 1 2 1 FB EN 1 @ PC603 +3VS 1 1

1 0.1U_0402_10V7K 2 2 2 2 2 2 PR603 PR603 2 2 PC604 PC604 +1.5V_PCIEP 150K_0402_1% 150K_0402_1% PC605 PC605 PC606 PC606 PC601 PC601

22P_0402_50V8J 22P_0402_50V8J TDC=0.46A 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM

22U_0805_6.3VAM 22U_0805_6.3VAM Peak Current=0.66A 1 1.5VS_PG [31] PR604 100K_0402_1% D

1 7/17 @ G 2 PR605 PQ601 S 100K_0402_5% 2N7002KW 1N SOT323-3 1 2 2 [34,9] SLP_S3

+3VS 3

3 3

4 4

Security Classification Title 1.5VSP Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 A www.vinafix.vnB C D

D D

PQ1101 +3VDS PR1108 NDS0610_NL_SOT23-3 100_0402_5% ADP_SIGNAL 1 1 2 3 1 PR1109 [43] V_3.9K 100K_0402_5% 1 1

+3VDS 2 C S D PR1125 PR1110 2 SRSET [43] 13K_0402_1% 8.06K_0402_1% B

C 2 PR1112 E C 2 2 1 G 100K_0402_5% VIN PQ1103 3 PQ11021 1 2 2 MMBT3904WH_SOT323-3 MMBT3906H_SOT23-3 3 1 1 1 B PR1114 PR1115 D PR1113 220K_0402_5% 619_0402_1% 8.66K_0402_1%E

G C E

2 2 2 E

PQ504 S 1 B

2N7002KW 1N SOT323-3 B

ADP_A_ID [30] 1 OCP_A_IN [30]

1 PR1116 @ PC1103 C

3.9K_0402_5% 3900P_0402_50V7K C +3VDS 2 1 1 1 1 2

[30] ADP_ID_CHK 3 PR1117 PR1118 2 3 45.3K_0402_1% 130K_0402_1% PR1119 PQ1104 PD1102@ 3.24K_0402_1% 2 MMBT3906H_SOT23-3 GLZ4.7B_LL34-2 1 2 2 2 2

PR1120 470K_0402_1% P1

B 1 2 +3VDS B

1 +5VL PR1121 1 200K_0402_1% PR1122 47K_0402_5% 8 2 P 2 3 ADP_PRES [30] 1 + PU1102A1 PR1123 2 G O 86.6K_0402_1% - LM393DR2G SO8 4 2 1 1

PR1126 1 100K_0402_1% PR1124 @ PC1104 47K_0402_5% 0.01U_0402_16V7K 2 2 2

+5VL

A A

Security Classification Title ADP_OCP Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

PD1201 BAV99WT1G_SC70-3 PR1202 10K_0402_5% 2 3 MFET_B 1 2 1 PR1201 10K_0402_5%

2 BATT_A D D 1

1 SB00000SA00 PR1204 PD1202 PR1203 470K_0402_5% 6 3 1 2 MFET_A 10K_0402_5%

SX34H_SMA2 2 2 LATCHED_ALARM 2 5 PQ1201A PQ1201A PQ1201B PQ1201B 1 4 +3VDS 6 1 1 PR1205 PR1206 470K_0402_5% 220K_0402_5%

4 4 2 SB00000SA00 PQ1202A PQ1202A 2 1 2 5 5 3 6 6 3 BATT_A 2 7 7 2

ME2N7002DKW-G 2N SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G [30] FET_A 1 8 8 1 BATT PQ1203 PQ1204 AO4409L 1P SO8 AO4409L 1P SO8 PQ1205 PQ1206 SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G AO4409L_SO8 AO4409L 1P SO8

1 8 8 1 BATT_B 2 7 7 2 3 6 6 3

1 5 5 1 C PR1207 PR1208 C 470K_0402_5% 4 4 220K_0402_5% 2 2 1 PD1203 PR1209 MFET_B 10K_0402_5% 1 2 SX34H_SMA2 2

BATT_B 1

PR1210 1 10K_0402_5% PR1211

3 6 470K_0402_5% MFET_A SB00000SA00 1 2 2 2 10K_0402_5% 2 3 LATCHED_ALARM PR1212 5 2 4 1 PD1204 +3VDS 3 BAV99WT1G_SC70-3 PQ1207B PQ1207B PQ1207A PQ1207A 1

B B 5 SB00000SA00 4 PQ1202B PQ1202B PR1213 1M_0402_5% [30] FET_B

1 2 SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G +3VDS +5VL +3VDS SOT363-6 SOT363-6 2N 2N ME2N7002DKW-G ME2N7002DKW-G 4/11 1 4/11 4/11 BATT 1

PR1214 1

1 10K_0402_5% PC1201 PR1215 0.1U_0603_25V7M 100K_0402_5% PR1216 2 2 8

200K_0402_1% 2

D P LATCHED_ALARM

2 5 + PU1102B7 G G OLM393DR2G SO8 LATCHED_ALARM [30]

1 6 S -

PR1217 4 64.9K_0402_1% 1 PR1218

137K_0402_1% 2 1

A A 2 PQ12092

3 2N7002KW 1N SOT323-3

Security Classification Title Battery selector Deciphered Date Issued Date Size Document15W Number Rev Compal Electronics, Inc. 0.3 Compal Secret Data Date: Thursday, December 20, 2012 Sheet of 2012/04/03 2014/12/31 5 4 www.vinafix.vn3 2 1

D D 2012/08/06 1 43 Reserve PC130,129,131,139,133,132,134,140,136,135,137,141,143,142,144,145,146,147,148,149,151,150,152,153,138 RF solution 244 Reserve PC324,322,323,325326,327,328,329,330,331,32012/08/0632,333 RF solution 3 44 Add PC305,304,308,309 2012/08/06 RF solution 4 45 Reserve PC419,401 2012/08/06 RF solution 5 45 Add PC403,404,405 2012/08/06 RF solution 6 46 Reserve PC512,513 2012/08/06 RF solution 7 46 Add PC502,503 2012/08/06 RF solution 8 48 Reserve PC264,267,266,269,265,268 2012/08/06 RF solution 9 48 Add PC214,215,207,203,232,236 2012/08/06 RF solution 10 48 Change PC233,234 from SF000001280 to SF000004M00 2012/08/09 Change the hieght to 6mm 11 47 Change PR234 from 19.1K to 62K 2012/08/10 HP suggestion 1248 Change PQ203,204,211 from SB00000K300 to SB00000U3002012/09/11 Design change 1348 Change PQ201,205,209 from SB00000SJ00 to SB00000WX002012/09/13 Design change 14 44 Change PQ301,302 from SB00000JM00 to SB00000IA00 2012/09/17 Design change 15 44 Change PQ303 from SB00000CT00 to SB00000H700 2012/09/17 Design change C C 16 44 Change PQ304 from SB00000N800 to SB00000TZ00 2012/09/17 Design change 17 45 Change PQ401 from SB00000H800 to SB00000IA00 2012/09/17 Design change 18 45 Change PQ402 from SB00000N800 to SB00000TZ00 2012/09/17 Design change 19 46 Change PQ501 from SB00000H800 to SB00000IA00 2012/09/17 Design change 20 46 Change PQ502 from SB00000N800 to SB00000H700 2012/09/17 Design change 21 51 Reserve PR1101,1102,1103,1104,1105,1106,1107,PC1101,1102,PU1101,PD11012012/09/25 HP suggestion 22 45 Change PD401 from SC600000D00 to SCS00006400 2012/10/2 HP suggestion 23 45 Change PR416 from SD034100380 to SD028470180 2012/10/2 HP suggestion 24 43 Change PL101 from SH00000MR00 to SH00000NW00 2012/10/2 Design change 25 23 Change PR240,243,249 from SD001470B80 to SD0000102802012/10/2 Design change 26 23 Reserve PL201 2012/10/2 Design change 27 25 Reserve PL301 2012/10/2 Design change

B B

A LA-9241P A

Security Classification 2011/10/03 Deciphered Date 2014/12/31 Issued Date Compal Secret Data Title

Size Document Number Rev CompalPWR Electronics, - PIR Inc. 0.3 Date: Thursday, December 20, 2012 Sheet 52of 52 5 4 www.vinafix.vn3 2 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 1 VBL20 from DB0 to DB1 LA-9241P REV:0.1 -> 0.2 Modify <2012.07.04.~2012.08.07. > Rev. ItemDate Impact Page Change Cause Modify Description 0.2 1 7/6 CKT 13 -Follow HP GPIO table -Change UH1.B17 to HDD_HALTLED 0.2 2 7/6 CKT 14,37 -Follow HP GPIO table -Change UH1.G17 and U30.26 to PWRSV_SEL#. 0.2 3 7/6 CKT 15 -Follow HP GPIO table -Change UH1.U4 to WLAN_TRAMSIT_OFF# 0.2 4 7/6 CKT, LAYOUT 16 -For NFC function -Change UH1.H6 to NFC_RST#, and add QH10, RH238, RH239 for NFC SMBUS level shift 0.2 5 7/6 CKT, LAYOUT 18,23 -Follow HP GPIO table -Change UH1.C16 to ODD_EN. Change Q25.1 netname to ODD_EN and Q25.2 netname to ODD_EN# 0.2 6 7/6CKT, LAYOUT 18 -Follow HP GPIO table -Change UH1.U12 and RH185.1 to NFC_INT 0.2 7 7/6CKT, LAYOUT 19 -Add PU resistor to avoid issue. -Add RH240 and RH241PU resistor of THERM_SCI# and WWAN_TRANSMIT_OFF# D 0.2 8 7/6 CKT, LAYOUT 22 -eDP MUX -Modify eDP connector signal source from eDP MUX. D 0.2 9 7/6 CKT 23 -Power driving -Change R1316 from 100K to 10K ohms 0.2 10 7/6 CKT, LAYOUT 25 -Change WWAN connector to NFCC -Modify JMINI3 connector type and pin define 0.2 11 7/6 CKT, LAYOUT 26 -Move Mute circuit to S/B -Move QA2 and R95 to S/B 0.2 12 7/6CKT, LAYOUT 26 -Audio Combo Jack -Delete MIC_SENSE# circuit. 0.2 13 7/6 CKT, LAYOUT 27 -Follow reference design -Change C91 and C94 to 2.2uF as spec 0.2 14 7/6 CKT, LAYOUT 28 -No ACCELEROMETER LED -Delete LED1 0.2 15 7/6CKT, LAYOUT 29 -NIC yellow ban issue -Add C350 and C373 to +1.05VM_LAN 0.2 16 7/6 CKT, LAYOUT 30 -Follow HP KBC pin define. -Modify U17 pin define. 0.2 17 7/6 CKT, LAYOUT 34 -Avoid leakage issue -Swap Q40 drain and source 0.2 18 7/6 CKT, LAYOUT 35 -MXM no display out issue -Swap JMXM1 PEG TX and RX bus 0.2 19 7/6 CKT, LAYOUT 36 -Avoid eDP signal quality fail issue -Change U42 to PS8321 which had include repeater function 0.2 20 7/6 CKT, LAYOUT 36 -To support DP1.2a -Change U26 to PS8338 to support DP1.2a spec. 0.2 21 7/6 CKT, LAYOUT 39 -Add NFC function -Add JNFC1 circuit. 0.2 22 7/9 CKT, LAYOUT 13 -HP request -Delete PCH XDP circuit 0.2 23 7/9 CKT, LAYOUT 13 -HP request -Add QH11 0.2 24 7/9 CKT, LAYOUT 16 -HP request -Delete U39, U40, RH232 0.2 25 7/9 CKT, LAYOUT 30 -HP request -Delete 16pin SPI ROM socket 0.2 26 7/9 CKT, LAYOUT 30 -HP request -Add R537,Q73 C C 0.2 27 7/9 CKT, LAYOUT 35 -HP request -Swap MXM port A and port C for layout smoothly 0.2 28 7/9 CKT, LAYOUT 38 -Follow spec pin define -Modify JTP1 and JTP2 pin define 0.2 29 7/9 CKT, LAYOUT 39 -Follow spec pin define -Modify JNFC1 pin define 0.2 30 7/10 CKT, LAYOUT 6,11,12 -Following Intel CRB by HP request -Modify JCPU1 pin AM3,F16,F13 netname. Delete RC73,RC76,C13,C75. Add QD3,RD27,RD28 0.2 31 7/10 CKT, LAYOUT 8 -HP request -Delete RC106, RC107 0.2 32 7/10 CKT, LAYOUT 30 -HP request -Modify R537 to 10K ohms 0.2 33 7/10 CKT, LAYOUT 34 -HP request -Modify R363 to 4.7K ohms 0.2 34 7/11 CKT, LAYOUT 36 -Follow vendor request -Add CC75,CC76,CC77,CC78,CC79,CC80,CC81,CC82. Modify U26 circuit 0.2 35 7/11 CKT, LAYOUT 29 -HP request -Delete R135, R139, R151, R152, R140, R142 for layout. 0.2 36 7/12 CKT, LAYOUT 22 -HP request -Delete C6 0.2 37 7/12 CKT, LAYOUT 23 -HP request -Delete C54. Add R539. 0.2 38 7/12 CKT, LAYOUT 24 -HP request -Change U3 to TC7SET00 0.2 39 7/12 CKT, LAYOUT 24 -FAN module pin define wrong. -Modify JFAN1 pin define by follow latest spec. 0.2 40 7/12 CKT, LAYOUT 37 -Follow latest Smart card module pin define. -Modify J3 pin define. 0.2 41 7/12 CKT, LAYOUT 38 -Follow latest KB connector pin 1 location. -Modify JKB1 pin define. 0.2 42 7/13 CKT, LAYOUT 27,39 -Reduce layout spacing -Move R494,R495,LA5,LA9,CA37,CA38,DA4 to sub board 0.2 43 7/13 CKT, LAYOUT 30 -Correct KBC circuit -Change U17.68, C179.1, C188.1 to +RTCVCC. -Delete R224, R460, R220, R223, R496, R497, R498, R499, R244, R269, R236, RH220. -Change RH222.1, RH223.1, RH224.1, CH97.1, CH98.1, UH5.8 to +3VDS B -Reserve R541, R542 for NFC TX/RX B 0.2 44 7/13 CKT, LAYOUT 39 -Follow ME connector list -Modify JVGA1 footprint and pin define. 0.2 45 7/13 CKT, LAYOUT 39 -Follow ME connector list -Modify JTB1 pin define, add WL/BT_LED# signal. 0.2 46 7/16 CKT, LAYOUT 14 -ESD request -Reserve CH107 0.2 47 7/16 CKT, LAYOUT 25 -ESD request -Reserve C375 0.2 48 7/16CKT, LAYOUT 27 -ESD request -Change DA2 and DA3 P/N. 0.2 49 7/16 CKT, LAYOUT 27 -ESD request -Delete DA1 0.2 50 7/16 CKT, LAYOUT 28 -ESD request -Change D11 P/N 0.2 51 7/16 CKT, LAYOUT 29 -ESD request -Change D12 and D13 P/N 0.2 52 7/16 CKT, LAYOUT 33 -ESD request -Add D42 0.2 53 7/16 CKT, LAYOUT 37 -Follow HP latest generation smart card connector pin define. -Modify J3 pin define. 0.2 54 7/16 CKT, LAYOUT 38 -ESD request -Change D32 P/N. 0.2 55 7/17 CKT 11 -Correct connector name -Change JP3 to JDIMM1 0.2 56 7/17 CKT, LAYOUT 36 -Change DP and eDP MUX to passive solution -Modify U26 and U42 to PI3VDP12412ZHEX and releate circuit. 0.2 57 7/17CKT, LAYOUT 17,39 -Follow HP request -Modify JTB1 pin define. Add CH108, CH109, CH110, CH111. Connect PCIE port 1 and port 2 to JTB1. 0.2 58 7/18 CKT, LAYOUT 14 -Follow HP request -Delete RH186, and add QH12 to invertion PCH_GPIO56 signal for CR_SX_WARN# 0.2 59 7/18 CKT, LAYOUT 17 -Follow HP request -Change RH165.2 net name to TB_HOT_PLUG# for TBT function. 0.2 60 7/18 CKT, LAYOUT 30,32 -Follow HP request -Change JP6.13 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#) -Change Q35.2 connection to 8051TX_STBYLED# (instead of 8051TX_STBLED#) A -Add a 100K pullup resistor between signal PVT_CS# and +3VDS power rail. A -Make these resistors as non-install (from Install): R219,R266,R258,R253,R216,R264 -Make R215 install Compal Electronics, Inc. -Change R436 to 1K (from 10 ohm) -Make these resistors as install (from un-install): R242,R254,R500,R277,R269,R262,R218 C HW_PIR1 0.5 -Make U18 as install. Thursday, DecemberLA-9241P 20, 2012 53 56 Security Classification Compal Secret Data Issued Date Deciphered Date Title

0.2 71 7/20 CKT,LAYOUT 14 -Follow HP request -Add ME debug connector JME1 0.2 72 7/20 CKT,LAYOUT 16 -Follow latest ME drawing. -Correct screw hole size. 0.2 73 7/20 CKT,LAYOUT 19,20 -Follow HP request. -Delete CH60, CH62, CH63, CH102 0.2 74 7/20 CKT,LAYOUT 19,21,38 -Follow HP request. -Add RA28 and Q75 for REC_MUTE_CTRL_KB signal. Modify JKB1 pin define. 0.2 75 7/20 CKT 27,38 -Follow ESD request. -Change DA2, DA3, D32 P/N 0.2 76 7/20 CKT,LAYOUT 29,34 -Follow HP request. -Change C110 to 22uF, Delete C231. Change Q170A lcation to Q7A 0.2 77 7/20 CKT,LAYOUT 30 -Layout smooth -Modify RP1 pin define. 0.2 78 7/20 CKT,LAYOUT 30 -Follow HP request. -Add D44 and D45 0.2 79 7/20 CKT,LAYOUT 31 -Follow HP request. -Modify PWR_GD circuit. 0.2 80 7/20 CKT 37 -Vendor's suggestion -Change C258 and C255 to 1uF. Non install RH225. 0.2 81 7/20 CKT 38 -Modify for 2 DIMM and 4 DIMM SKU. -Reserve SIO_GPIO44 PD R554, and modify R328, R329, R330 value to 4.7K. Modify R482, R483 value to 10K 0.2 82 7/23 CKT,LAYOUT 14 -Schematic wrong. -Connection RH55.2 to power rail +RTCVCC 0.2 83 7/23 CKT,LAYOUT14 -Follow HP request. -Move QH12 to sub board. Add CR_SX_WARN# PU 10K ohms RH244 0.2 84 7/23 CKT,LAYOUT 15,17,18 -No connection to other page. -Delete FN14, FN15, USB_OC0#_R, USB_OC1#_R, USB_OC2#, USB_OC3#, USB_OC4#_R, PCH_GPIO24, FN_CLK2, PCH_GPIO37 off page symbol. C C 0.2 85 7/23 CKT,LAYOUT 16 -Follow latest ME drawing. -Modify screw hole size. 0.2 86 7/23 CKT,LAYOUT 17 -Correct net name -Change RH171.1 connection to ODD_EN 0.2 87 7/23 CKT,LAYOUT 18,29,30,34 -Follow VBK10 -Non install RH184 and RH185. Add C389, C390, C391, C392. Change C121 to 1000pF. Change C322 to 100pF. Delete Q37, R366, R361. 0.2 88 7/23 CKT,LAYOUT 22,30 -Follow RF request. -Reserve C393, C394, CH112 0.2 89 7/23CKT,LAYOUT 26 -MIC_SENSE circuit had been removed. -Delete RA7. 0.2 90 7/23 CKT,LAYOUT 27 -Reduce layout spacing -Combine QA2B with QA1A. 0.2 91 7/23 CKT,LAYOUT 31 -Follow HP request. -Change R286 to 10K 0.2 92 7/23 CKT,LAYOUT 36 -Follow HP request. -Combine Q63 and Q72 to Dual channel Q76. Delete R516, R545, CC84, C371. 0.2 93 7/23 CKT,LAYOUT 36 -Modify netname to more clear. -Change SEL to SEL_eDP_MUX. Change SEL_DP to SEL_DP_MUX 0.2 94 7/23 CKT,LAYOUT 17 -Layout smooth -Modify RPH1 and RPH2 pin define 0.2 95 7/24 CKT,LAYOUT 25 -Follow latest NGFF pin define. -Modify JMINI3 pin define. 0.2 96 7/24 CKT,LAYOUT 28 -Follow latest FP spec. -Modify JFP1 pin define. 0.2 97 7/24 CKT,LAYOUT 30,38 -Follow EMI request -Add C420, C421, C422, C422, C423, C424, C425, C426, C427, C428, C429, C430, C431, C432, C433, C434, C435, C436, C437, C438, C439, C440, C441, C442, C443, C444, C445, C446, C447, C448, R555 and C419. Change R437.2 netname to PCH_SPI_CLK_EC. 0.2 98 7/24 CKT,LAYOUT 39 -Follow HP request -Modify JUB1 pin define. 0.2 99 7/25 CKT,LAYOUT 5,9,20 -Follow HP request -Delete RC24, RC96. Change UH1 pin AJ12 and AJ14 connection to +1.05VS 0.2 100 7/25 CKT,LAYOUT 30 -Follow HP request -Change U18 to socket and add &UH2 for KBC ROM 0.2 101 7/25 CKT,LAYOUT 30 -Follow HP request -Connect JP6.13, U17.115, and R255.1 to TX_STBY_LED. Add R559, R560, and Q77

B 0.2 102 7/25 CKT,LAYOUT 36 -Reduce layout spacing -Combine Q56 and Q57 to dual channel Q79 B 0.2 103 7/25 CKT,LAYOUT 25 -Follow latest NGFF spec -Modify JMINI3 and JSIM1 pin define. 0.2 104 7/26 CKT,LAYOUT16,30 -Follow HP request -Install RH242, RH244. Add R561, R562. Noninstall R541, R542 0.2 105 7/26 CKT,LAYOUT 28 -Follow RFQ spec -Change U11 to SLB9656 0.2 106 7/27 CKT,LAYOUT 36 -Follow HP request -Add R563, R564 0.2 107 7/30 CKT,LAYOUT 5 -Follow Intel reference schematic -Non install QC1 0.2 108 7/30 CKT,LAYOUT 16 -Follow RF request -PCH_SPI_CLK reserve CH113 to GND 0.2 109 7/30 CKT,LAYOUT 22,39 -Follow HP request -Change R10.1 to +5VDS and Q20.3 to +3VDS for layout easy. Modify JVGA1 and JCR1 pin define. 0.2 110 7/30 CKT,LAYOUT 23 -Follow latest connector list -Modify JHDD1, JODD1 and JCR1 footprint. 0.2 111 7/30 CKT,LAYOUT 39 -Correct JNFC1 pin define -Modify JNFC1 pin define. 0.2 112 7/31 CKT,LAYOUT 25,39 -Follow HP request -Modify Q4A circuit. Change JTB1.95 connection to +3VDS. 0.2 113 7/31 CKT 25 -Wireless LED fail issue. -Install Q29 and Q31 0.2 114 7/31 CKT,LAYOUT 26 -No LOGO KBL function -Delete Q21,Q22,R454,R14. Delete JEDP1.35 signal 0.2 115 7/31 CKT,LAYOUT 14 -Correct netname -Change RH62.2 netname to PWRSV_SEL# 0.2 116 8/01CKT,LAYOUT 23,33,39 -HP request -Swap SATA bus port 2 and port 5. JCR1.35 connection to PCH_PCIE_WAKE# 0.2 117 8/01 CKT,LAYOUT 18,23,25 -HP request -Uninstall Q68, R459. Change PCH.AT3 and RH198.2 netname to Sec_HDD_DET. Change PCH.AP1 and RH180.2 to mSATA_DET#. Delete Q48. Add R565. 0.2 118 8/01 CKT,LAYOUT 24 -PWR request -Change R492.2 connection to KBC_PWR_ON 0.2 119 8/01 CKT 30 -Follow RFQ spec -Change KBC symbol to SMC1322 0.2 120 8/03 CKT,LAYOUT6,11,13,18 -HP request -Add CC84, CC85, CC86. Change RD6 to 33ohms. RH33.1 connection to GND. Delete RH201, RH202. Q4.2 connection to BT_ON A 0.2 121 8/03 CKT,LAYOUT 22 -Layout smooth -Swap L3 pin define for layout smooth A 0.2 122 8/03 LAYOUT 23 -Follow ME connector list -Modify JODD1, JMINI3 footprint Compal Electronics, Inc. 0.2 123 8/03CKT,LAYOUT 25,30,39 -HP request -Q4.2 connection to BT_ON. Change R437 to 33 ohms. Change R540 to 4.7K. Change JVGA1 pin 39 and 40 connection to +3VDS

0.2 124 8/03 CKT,LAYOUT 30 -RF request -Add CH114 C HW_PIR2 0.5 0.2 125 8/06 CKT,LAYOUT 9,15 -HP request -Reserve CC87. Change JCPU1 pin AM43 and pin AL44 ball name Thursday, DecemberLA-9241P 20, 2012 54 56 Security Classification Compal Secret Data Issued Date Deciphered Date Title

C 15,17,20, RPH1.3 to TB_HOT_PLUG# directly. Delete RH226 and connect pin AD12 of PCH to +3V_PCH power rail. Delete RC106 and connect UC1.1 to VR_ON. Noninstall C 31,32, 33 RC36,RC38,RC40,RC43,RC45,RC47. Delete RC66. Connect CPU.AT26 pin to CPU_PLTRST#. Delete RC30. Connect CPU.AL34 pin to H_CPUPWRGD. Change RC55.1 connection to H_CPUPWRGD. Delete RC27. Connect CPU.AM35 pin to PCH_THERMTRIP#_R. Delete RC93 and connect SLP_S3# to QC5.5. Delete R351. Connect EN_P1V5 to JDOCK1.140. Change C299 to 0.01uF. Delete R336 and connect C299.1 to ON/OFFBTN_KBC# . Connect ON/OFFBTN_KBC# to JDOCK1.49. Delete R287. Connect joint point of R286.1 and U18.1 to VR_ON. Add R601 4.7K PU to +3VS on signal SIO_GPIO42. Noninstall R601. Delete RH92, RH93, RH221, RH94, RH95, RH107, RH103, RH203, RH114, RH116, RH205, RH122, RH124, RH126, RH127, RH128, RH130

0.3 8 9/12 CKT, LAYOUT 30 -Follow HP request -Delete R543, R561, R562. Delete signal ADP_ID_CHK connection to KBC.86 pin. Delete R249 and connect signal OCP_PWM_OUT to KBC.59 pin. Delete R251 and connect signal PM_PWROK to KBC.60 pin. Delete R256 and connect signal EN_P1V5 to KBC.38 pin. Delete R277 and connect signal VR_ON to KBC.72. Change RP1 and RP2 to 100K. 0.3 9 9/12 CKT, LAYOUT 38, -ME move LID SW from Power board to Function baord. -Modify JPWR1 and JFUNC1 connector pin defein. 0.3 10 9/12 CKT, LAYOUT37 -ME rotate Smart connector 90 degree. -Modify J3 pin define. 0.3 11 9/13 CKT, LAYOUT 16 -Follow latest ME drawing -Delete H4, H32, H34, H41, JP2. Add H42, H43, H44, H45, H46. Modify JEDP1, JSIM1, JFP1, JVGA2, J3, JKB1, JTP1. JFUN1 pin define and footprint. 0.3 12 9/14 CKT, LAYOUT 14,31 -Follow HP request -Delete UH7, RH235. Move RH236, CH106 to page 31. Modify POWER OK circuit 0.3 13 9/14 CKT, LAYOUT 22,30,38,39,40 -Follow ME and DFX request -Modify JEDP1, UH5, JTB1, JUSB1 and JKB1 pin define and footprint. 0.3 14 9/17 CKT, LAYOUT 40 -Layout request -Swap L35, L36, L37 for layout smoothly. 0.3 15 9/17 CKT, LAYOUT 38 -Follow ME connector list -Change JPWR1 footprint and pin define. 0.3 16 9/17 CKT, LAYOUT 38 -Follow Keyboard spec -Modify JKB1 pin define. 0.3 17 9/18 CKT, LAYOUT 28 -Follow ME drawing -Modify JFP1 pin define. 0.3 18 9/19 CKT, LAYOUT 13,39 -Follow HP request -Add a 0ohm resistor between JCR1.5 and signal PCH_PCIE_WAKE#. Then make this resistor open. Change QH11 to P MOS. Change RH30 to 2.2K ohms 0.3 19 9/19 CKT, LAYOUT 34 -Layout smooth -Delete J2 0.3 20 9/20 CKT, LAYOUT 14,26,30,37 -Follow HP request -Change RH74 to 100K. Change RH147.1 power rail to +3VS. Delete RA13, CA20. Change R227 to 3K. Delete R393, CC67, and connector U30.23 to PLT_RST#. B 0.3 21 9/20 CKT, LAYOUT 22 -Correct circuit short issue -Modify JEDP1 connector circuit. Add one more +3VS power pin for power consumption B 0.3 22 9/20 CKT, LAYOUT 22,26 -Change to common part. -Change D3 and DH1 to RB751V-40_SOD323-2 0.3 23 9/21 CKT, LAYOUT 8,13,30,39 -Follow HP request -Reserve CFG9 PD resistance RC106. Non-install RH39, RH40, RH41, RH44, RH48, RH47, RH46. Change R436 to 100K and connection R436.2 to GND. Delete R557, Non-install R358, C374 0.3 24 9/21 CKT, LAYOUT 36 -Netname issue. -Change L29.2 netname to DAC_RED. L30.2 netname to DAC_GRN. L31.2 netname to DAC_BLU 0.3 25 9/23CKT, LAYOUT 5,30,31,47 -Follow HP request -Change netname VR_ON to PWR_GD, change netname PWR_GOOD_3 to VGATE 0.3 26 9/24 CKT, LAYOUT 20,30 -Follow HP request -Non install D21. Delete RH213, RH216, and change netname 0.3 27 9/24CKT, LAYOUT 40 -No need another DC/DC circuit to provide +3VDS_P to U44. -Delete Q79, Q80, C475, C477, C478, R588, R587. Change +3VDS_P power rail to +3VS. 0.3 28 9/25 CKT, LAYOUT 22 -Change +3VS, +5VS and +LCDVDD power rail soultion -Delete R9, R10, R11, Q12, Q20, C1, C7, C8, U24, C226, C221, C222, U25, C218, C223, C219, C227, R354, R356, R357, Q9. Add U47, C497, C498, C499, U45, R603, C489, C490, C491, C492, U46, R604, C493, C494, C495, C496, Uninstall R370, R373, Q43, Q44, R490 0.3 29 9/25 CKT, LAYOUT 30 -Follow HP request -Install R237, R235, R234, R233, R231 0.3 30 9/25 CKT, LAYOUT 31 -Reserve for EC CLK issue -Reserve R605 and connect R605.1 to SUSCLK_KBC 0.3 31 9/26 CKT, LAYOUT5,22,34,40 -Follow HP request -Change JXDP1.47 connection to PM_PWROK via a 0ohm resistor. Add a C502 (10uF cap) for +3VS decoupling. Change C489 and C492 value to 10uF or 4.7uF. Change C494 and C496 to 10uF or 4.7uF. Change C499 value to 4.7uF and make R480 as install. Change C493 and C490 to 0.01uF 0.3 32 9/26CKT, LAYOUT 34 -Correct Netname -Change R375.1 connection netname to SLP_S3# 0.3 33 9/26 CKT, LAYOUT38,39 -Follow ME request -Modify JP9 and JFUN1 pin define. 0.3 34 9/26CKT, LAYOUT 34 -Follow HP request. -Modify +1.05VS power circuit. 0.3 35 9/27 CKT, LAYOUT33,35,38 -Follow HP request. -Delete R339, R340, R341, R342. Add R606, R607, R608 PU to +3VS. Change R408 to 200K ohms. Uninstall C295. 0.3 36 9/27CKT, LAYOUT 29 -Material shortage issue -Change Y2 to smaller (32x25 mm) package. 0.3 37 9/28 CKT, LAYOUT 34 -Follow HP request. -Add C503 0.3 38 10/09ckT 16 -Follow HP request. -Change RH152, RH153 to 499ohms. A A

Compal Electronics, Inc.

C HW_PIR3 0.5 Thursday, DecemberLA-9241P 20, 2012 55 56 Security Classification Compal Secret Data Issued Date Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED2011/11/5 TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL2010/12/01 ELECTRONICS, INC. Date: Sheet of 5 4 www.vinafix.vn3 2 1 5 4 3 2 1 VBL20 from DB1R to SI1 LA-9241P REV:0.3 -> 0.4 Modify <2012.10.11.~ 2012.11.09> Rev. ItemDate Impact Page Change Cause Modify Description 0.4 1 10/11CKT, LAYOUT 26,27 -Follow IDT request -Change RA14 to 0 ohm. Change C91, C94 to 150u. Change R97, R98, R102, R104 to 1%. Non-install R106, R107. Change C95 to 0.47u X5R. Change QA1.4, R110.2, Q6.1, R111.2, Q6.4 to AGND. 0.4 2 10/11 CKT, 33 -Follow ESD request. -Non-install D42. Install D32. 0.4 3 10/11CKT, LAYOUT 35 -Follow HP request -Re-arrange MXM DP port. Port A for Thunder Bolt. Port B for Dock. Port C for EDP. Port D for SWITCH 0.4 4 10/12 CKT, LAYOUT 5,14,30,34 -Follow HP request -Reserve RC108, UH6, CH116, R610. Change U17.85 and R276.1 connection netname to RSMRST#_EC. Change R455 to 47K. Add Q18A, C504, R609. Modify +3V_PCH power circuit 0.4 5 10/16 CKT, LAYOUT 9,14,25,29, -Follow HP request -Install R567, D21. Add R612, R616, Q80, R614, Q79. Delete R602, C504, R609, R456, Q67B, R218, R239, R240, R540, Q74, R247, C322, C186, R230, R64. Change R568.1, R569.1 and 30,34,39 R245.1 connection to KBC_WAKE#. Remove current VCC1_PWRGD connection to JP6.16. Then add a 4.7 K resistor between JP6.16 and new signal VCC1_PWRGD_SUS#. Change R215.2 to GND. Change R227 to 3.3K. Add a R615 PD for U7.102. Change U7.102 connection to PLT_DET. Change R248 to 200k ohms. Change R248.1, U17.77 connection to D VCC1_PWRGD_SUS#. Change R243.1 and U7.125 connection to CHRG_RST. Change R243 to 100K. Change R243.2 connection to GND. change R436.2 connection to +3VDS. Change D JTB1.91, U17.41 and R436.1 connection to iSCT_LED#. Change D21.2 connection to PM_APWROK. Modify +3V_PCH power circuit. Change JCR1.5 connection to +5VDS. 0.4 6 10/17 CKT, LAYOUT 14,30 -Follow HP request -Change R614.1 connection to +3V_PCH. Correct R227 to 10K. 0.4 7 10/18 CKT, LAYOUT 5,9,14,16 -Follow HP request -Change R615 to 470K, R610 to 470 ohm, R614 to 10K ohms, R612, R137, R606, R607 and R608 to 4.7K ohms, RC108 to 10K ohms . Delete Q67A, QC1, RC12, Q80, R461, Q2, RC90. 20,24,25 Install RH209, R492, RC108, R613, CH116 and UH6. Uninstall QC3, RH148, RH67, RH208. Change R492.2 connection to PCH_THERMTRIP#_R Connection R614.1 to PM_RSMRST#. Modify 30,34,35 +1.35VS power circuit 0.4 8 10/23 CKT, LAYOUT 14,20,30 -Follow HP request -Delete R612. Reserve R616 between KBC. 124 pin and signal SIO_SLP_SUS#. Uninstall RH209, Q79, R614, R613, CH116 and UH6. Install RH67, RH208. Change PCH.AL6, JTB1.91 34,39 and RH244.2 connection to TBT_RR_GPIO#. Add Q80 for iSCT_LED# circuit 0.4 9 10/24CKT, LAYOUT 18,25,28 -Follow HP request -Add R618, R619, R620, R621. Delete R567, and connect JMINI3.15 to WLAN_WAKE# directly. Change ACCEL_INT# connection to U9.11. Change RH176.2 connection to GND and make RH176 install. Change RH185 as install 0.4 10 10/25 CKT, LAYOUT14,18,25 -Follow HP request -Add R247, Q63. Change RH70 to 200k ohms. Add LANWAKE# PU RH248 to +3VDS. Delete R618, R89. Change R455 to 200k. Add PD R622. Change Q61 and Q62 to dual channel 7002 29,34,35 0.4 11 10/25CKT, LAYOUT 30 -Solve KBC external crystal can not work issue. -Reserve R624 and connection to SUSCLK_KBC 0.4 12 10/26 CKT, LAYOUT13,14,15 -Follow Compal HW request -Delete RH56, RH57, RH59, RH60, RH66, RH69, RH71, RH98, RH99, RH100, RH141, RH234, RH139, RH108, RH110, RH111, RH112, R160, R161, R162, R163, R320, R477, R478, R464, 29,32,36 R465, R466, R467, R472, R473, R474, R475, R468, R469, R470, R471, R479, R484, R485, R486, R318, R319, R321, R322, R570, R571, R572. Add RP7, RP8, RP9, RP10, RP11, RP12, RP13, RP14, RP15, RP16, RP17, RP18, RP19. 0.4 13 10/26 CKT, LAYOUT13,14,15 -For layout smoothly. -Rearrange RP11, RP8, RP17, RP13, RP14, RP15, RP16, RP12, RP10, RP7 pin assignment for layout smoothly. 29,32,36 0.4 14 10/26 CKT, LAYOUT 38 -Move LID switch to PWR board by ME reqesut. -Change JPWR1 to 6 pin, and modify the JPWR1 pin define. 0.4 15 10/26 CKT, LAYOUT 13,14,17 -Follow HP request. -Delete R153, R481, R565. Swap QH11A.2 and QH11B.5 connection. Change RH75.2 and PCH.K7 connect to BATLOW#. Change PCH.U7 connect to BT_OFF. Change PCH.P3 and RPH2.4 18,23,29 connect to WWAN_DET#_PCH. Delete A20GATE and VCC1_PWRGD_SUS# off page symbol. Change RH180.2 and UH1.AP1 connect to PCH_GPIO_35. Change RH198.1 and UH1.AT3 30,32,34 connect to PCH_GPIO_36. Change R376 to 10k. Change R376.1 connect to +3VDS. Connect Q34.3 to LED_LINK_LAN_DOCK# with R625, and delete LED_LINK_LAN_DOCK# connection to 38, Q34.1. Delete R157 and connect Q34.1 and signal LED_LINK_LAN#_R. Connect U22.26 pin to signal mSATA_DET#. Change R455.2 connection to B+. Change Q36 to AO3413. C C 0.4 16 10/29 CKT, LAYOUT 18,35 -Follow HP request. -Change RH179 to 100ohms. Delete R137, Q82.B. Add D52 0.4 17 10/31 CKT, LAYOUT 18,36 -Follow ME request. -Change JODD1, JVGA2, JKB1 footprint 0.4 18 10/31CKT, LAYOUT 18,37 -Follow HP request. -Change R291.1 connection to +5VL. Change R291 to 105K_1% 0.4 19 11/01 CKT, LAYOUT 31 -Follow HP request. -Change R304.1 connection to +5VL. Change R304 to 88.7k +-1%. Uninstall R306. 0.4 20 11/01CKT, LAYOUT 13,15,37 -Material shortage issue -Change Y3, YH1, YH2 to small package 0.4 21 11/01 CKT, LAYOUT 22,30,37,38 -Follow HW request -Uninstall Y4, C487, C488. Delete C23, C80, C82, C111. Change U30 to AU9560-GBS-GR. Add R626 0.4 22 11/02 CKT, LAYOUT 29 -Follow HP request. -Reserve C504. Add C505 0.4 23 11/05 CKT, LAYOUT27 -Audio Jack change to normal open type -Delete R174, QA1B. HP_SENSE# connection to R167.1 0.4 24 11/05 CKT, LAYOUT 38 -Follow ME request -Modify JKB1 pin define to follow ME request. 0.4 25 11/05 CKT, LAYOUT39 -Smart Card Reader AU9560-GBS-GR no need external crystal -Uninstall Y3, CV33, CV34 0.4 26 11/06 CKT, LAYOUT 9,14,22, 25 -Follow HP request -Change QC5A.2 and QC5B.5 connection to SLP_S3. Change PCH.D2 pin connection to DDR3_SET. Delete Q68, R459. Change R458 to 0ohm. Change JMINI3.13 connection to signal WWAN_DET#_PCH. Change JMINI3.65 connection to GND. Change C498 to 4700pF 0.4 27 11/06CKT, LAYOUT 12 -Follow RF request -Add C506, C507, C508, C509, C510, C511 0.4 28 11/07 CKT, LAYOUT 5 -Follow ESD request -Delete RC36, RC38, RC40, RC43, RC45, RC47 by ESD request. Add T144, T145, T146, T147, T148, T149 0.4 29 11/07 CKT, LAYOUT 23,32 -Follow RF request -Change C48 and C58 to 68pF. Change R332 to 33 ohms, C205 to 82pF and install R332 and C205 0.4 30 11/08 CKT, LAYOUT 23,33 -Follow HP request -Delete D52. Add Q83, R627 0.4 31 11/09 CKT 16,34,35 -Follow HP request -Change RH152 and RH153 value to 2.2K. Change C491 and C495 to 4700pF. Change R627 to 4.7K.

VBL20 from SI1 to SI2 LA-9241P REV:0.4 -> 0.5 Modify <2012.12.12.~ > B B Rev. ItemDate Impact Page Change Cause Modify Description 0.5 1 12/12CKT, LAYOUT 9,14,28,30 -Follow HP request -Uninstall QC4, RC92, CC39, RC89, QC5 and RC88. Add J4, Q84, Q85. Delete Q79, R615, UH6, R613, R617, R227 , CH116, R605. Change RH222, RH223, RH224, R615, R248 to 100K. 31 Remove R611. Connect JP6.16 to VCC1_PWRGD_SUS#. Install R624. Change CH115 to 0.22uF 0.5 2 12/12 CKT, LAYOUT 35 -Material shortage issue. -Change U34, U35, U36 to small package 0.5 3 12/13 CKT9,28 -Follow HP request -Install RC88. Change JFP1.11 netname to FPR_OFF_C 0.5 4 12/20 CKT 35,36 -Solve CRT switch issue -Uninstall R91,R92,R93. Change RP19 to150 ohms

A A

Compal Electronics, Inc.

C HW_PIR3 0.5 Thursday, DecemberLA-9241P 20, 2012 56 56 Security Classification Compal Secret Data Issued Date Deciphered Date Title