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Circuit Designer's Notebook

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Circuit Designer's Notebook CIRCUIT DESIGNER’S NOTEBOOK Capacitors in Bypass Applications Capacitors used in bypass applications are Impedance: (Z)The magnitude of a capacitor’s For example a switched pulse with a rise and fall implemented as shunt elements and serve to carry impedance is equal to . As time of 1.5 ns will yield spurious spectral ͌ʲ(ESRʲ) 2 +ʲ (X Lʲ– Xcʲ ) 2 RF energy from a specific point in the circuit to seen by this relationship a capacitor’s impedance is components up to 233 MHz. ground. Proper selection of a bypass capacitor will significantly influenced by its net reactance (X L-X C). provide a very low impedance path to ground. In Drain Bias Network: theory the ideal impedance is zero ohms; however As illustrated in figure 3, the FET’s drain bias network a real capacitor will exhibit some impedance due consists of series inductive elements having an to its reactance and inherent parasitic elements. impedance of ␻L and shunt capacitive elements with Ω Satisfying capacitive bypass application an impedance of 1/ ␻C. Proper selection of bypass requirements entails careful analysis of various capacitors in the bias network is essential as they will frequency dependent capacitor parameters such as serve to de-couple RF energy from the V DD supply line to ground over a wide range of frequencies. series resonant frequency (F SR ), equivalent series resistance (ESR), and the magnitude of the Since capacitors exhibit a small parasitic impedance. The ESR and impedance should inductance there is an associated series (sel f) always be evaluated at the operating frequency. resonant frequency where F SR = 1/2 ⌸͌ʲLs Cʲ o . At FSR the magnitude of the inductive and capacitive Figure 1 is a block diagram illustrating a capacitor Figure 2: Impedance vs. Frequency for bypass application. Capacitor C in this figure is reactances are equal and hence the net impedance 0 ATC100A101 (100pF) 2 2 represented with its equivalent series resistance ͌ʲ(ESRʲ) +ʲ (X Lʲ– Xcʲ ) is equal to a small ESR It is important to evaluate the magnitude of the value. Accordingly the designer will ideally select denoted as R S, equivalent series inductance (ESL) impedance throughout the desired frequency a capacitor that has an F SR at or close to the denoted as L S and parasitic parallel capacitance C P, associated with the parallel resonant frequency (F ). range. A properly selected bypass capacitor will desired “bypass frequency”. This preference is PR exhibit suitably low impedance over this range. As based on establishing a low impedance path with seen in Figure 2 the net impedance below F SR is minimal or zero net reactance thereby making it RF to be capacitive and is dominated by 1/ ␻C, yielding a ideal for bypassing applications. bypassed hyperbolic curve for frequencies less than F SR . CO FPR usually occurs at more than twice F SR for most Conversely, the net impedance above F SR is multi-layer ceramic capacitors. At the capacitor’s C L inductive and is dominated by ␻L yielding a linear P S FPR , the impedance is likely to be high and line segment for frequencies greater than F SR . inductive (R+j ␻L) and may not provide an RS Figure 1: Bypass Application Example adequate RF path to ground. To alleviate this, CFaigpuacrieto 1r :C Bonypfigaussra tion Bypassing is a critical design matter that requires several capacitors are selected such that their self- Capacitor Configuration careful consideration. Figure 3 shows a 1.9 GHz resonant frequencies are staggered in order to cellular FET amplifier with emphasis on the drain cover a wide range of frequencies with reasonably Terminology: bias network. low loss. The number of required capacitive Equivalent Series Resistance (ESR): Is the summation elements depends on the loss and impedance of all losses resulting from the dielectric (R SD ) and characteristics of each element over the intended metal elements (R SM ) of a capacitor (R SD + R SM ) and frequency band segments. is typically expressed as milli-ohms. R SD is the The inductors are in series with the drain and are dielectric loss tangent and is dependent upon specific not directly connected to reference RF ground. characteristics of the dielectric formulation and Accordingly they rely on bypass capacitors, C 1 processing. Metal losses are dependent on resistive through C 4 to achieve a low impedance path to characteristics of the electrode and termination ground. The combination of L 1 and C 1 will greatly materials, as well as the losses of the electrodes due suppress the in-band 1.9 GHz carrier frequency to skin effect. ESR is a key parameter to consider energy from appearing on the V DD supply line. when utilizing capacitors in RF bypass applications. Inductor L 1 will act as a block at this frequency Quality factor (Q): A capacitor’s Q is numerically while capacitor C 1 will serve to further suppress in- equal to the ratio of its net reactance (X - X ) to its Figure 3: Bypass Capacitors in a 1.9GHz FET band RF energy by bypassing it to ground. L C , C L Broadband Bias Network 2 2 equivalent series resistance (ESR) or Q = |X C - X L| / C3 and C 4 will suppress RF energy at frequencies ESR. From this expression it can be seen that the The circuit elements depicted in this figure will below the 1.9 GHz carrier frequency where the capacitor’s Q varies inversely to its ESR and serve to suppress RF energy from getting onto the gain of the amplifier may be much higher. C 1’s directly with its net reactance. VDD supply line while providing high impedance at capacitance value is selected such that its FSR is Series Resonant Frequency (F ): A resonance that the drain in order to maintain optimum in-band RF close to the amplifiers operating frequency. Since SR gain. It also functions to keep noise generated by occurs at F =1/2 ⌸͌ʲLs Cʲ o. At this frequency the C1 is a shunt element, and the impedance is low at SR the power supply from appearing on the drain of capacitor’s net reactance is zero and the its FSR , the RF energy at the operating frequency the FET. High-speed switching environments impedance is equal to the ESR. The capacitor will will be bypassed to ground. Capacitor elements C 2, created by switch mode power supplies (SMPS) will provide its lowest impedance path required for C3 and C 4 are staggered in value and selected so optimal bypassing at this frequency. generate noise on V DD supply lines. Instantaneous that the impedance of each will be low at current generated by fast rising and falling switch successive frequency segments in order to offer Parallel Resonant Frequency (F ): A resonance PR pulse edges can easily cause the V DD supply line to continuous bypassing of frequencies below the occurring at approximately twice the F SR for a ring. The resultant noise can include frequencies of amplifier’s operating band. parallel plate capacitor. In contrast to F SR the up to several hundred megahertz. RF noise impedance of a capacitor at its F PR can be generated by SMPS switching is continuous and Richard Fiore precipitously high. This is readily observed by will generally occur up to frequencies equal to Director, RF Applications Engineering assessing the magnitude of the insertion loss at F . PR 0.35 / P E, where P E = pulse rise or fall time (sec). American Technical Ceramics Corp. Excerpt from complete Circuit Designers’ Notebook, Document #001-927, Rev. E, 1/05 American Technical Ceramics • www.atceramics.com.
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