Post-K Computer Development

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Post-K Computer Development In collaboration with RIKEN, Fujitsu is developing the world’s top-level supercomputer, capable of realizing high effective performance for a broad range of application software. Advanced Technology Fujitsu Contributions to the Post-K Computer National Project Post-K Development ・System Characteristics We are aiming to achieve the development goals of having an effective application performance that is up to 100 times greater than that of the K computer and power consumption of 30-40 MW (the K computer’s power consumption is 12.7MW), and to create the world’s top-performing general-purpose supercomputer. To be more precise, our aim is to balance various factors, such as i) power consumption, ii) computational performance, iii) user convenience, and iv) ability to produce ground-breaking results, characterized by its all-around capabilities, compared to any other system in the world. ・Fujitsu’s Efforts Fujitsu, through efficient use of not only cutting-edge technology, but also the cultivation of know-how and performance experience with the K computer and the Supercomputer PRIMEHPC Series, is developing the entire system; from the processor to the software. In particular, in regards to the processor, Fujitsu chose the Arm instruction set architecture with supercomputing extensions co-created with Arm, and is working hard to extract the potential maximum performance from it. 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 K Computer K Computer Development Operation Basic Mass Install./ Prototype・Detailed Design Operation Post-K Design Product. Tuning K computer The K computer is used in various fields PRIMEHPC FX100 from advanced research to manufacturing. Post-K © RIKEN RIKEN and Fujitsu are developing with the PRIMEHPC FX10 goal of beginning full operations around 2021. This leaflet has been translated from a Japanese local version. Some content referenced is for Japan only. If you need further information, please contact the sales representative in your region. http://www.fujitsu.com/global/solutions/business-technology/tc/ Copyright 2018 FUJITSU LIMITED 2019.2.

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Supercomputer Fugaku
Supercomputer Fugaku Toshiyuki Shimizu Feb. 18th, 2020 FUJITSU LIMITED Copyright 2020 FUJITSU LIMITED Outline ◼ Fugaku project overview ◼ Co-design ◼ Approach ◼ Design results ◼ Performance & energy consumption evaluation ◼ Green500 ◼ OSS apps ◼ Fugaku priority issues ◼ Summary 1 Copyright 2020 FUJITSU LIMITED Supercomputer “Fugaku”, formerly known as Post-K Focus Approach Application performance Co-design w/ application developers and Fujitsu-designed CPU core w/ high memory bandwidth utilizing HBM2 Leading-edge Si-technology, Fujitsu's proven low power & high Power efficiency performance logic design, and power-controlling knobs Arm®v8-A ISA with Scalable Vector Extension (“SVE”), and Arm standard Usability Linux 2 Copyright 2020 FUJITSU LIMITED Fugaku project schedule 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 Fugaku development & delivery Manufacturing, Apps Basic Detailed design & General Feasibility study Installation review design Implementation operation and Tuning Select Architecture & Co-Design w/ apps groups apps sizing 3 Copyright 2020 FUJITSU LIMITED Fugaku co-design ◼ Co-design goals ◼ Obtain the best performance, 100x apps performance than K computer, within power budget, 30-40MW • Design applications, compilers, libraries, and hardware ◼ Approach ◼ Estimate perf & power using apps info, performance counts of Fujitsu FX100, and cycle base simulator • Computation time: brief & precise estimation • Communication time: bandwidth and latency for communication w/ some attributes for communication patterns • I/O time: ◼ Then, optimize apps/compilers etc. and resolve bottlenecks ◼ Estimation of performance and power ◼ Precise performance estimation for primary kernels • Make & run Fugaku objects on the Fugaku cycle base simulator ◼ Brief performance estimation for other sections • Replace performance counts of FX100 w/ Fugaku params: # of inst. commit/cycle, wait cycles of barrier, inst.
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