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An Overview of Formal Hardware Specification Languages

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An Overview of Formal Hardware Specification Languages An Overview of Formal Hardware Specification Languages Annette Bunker∗ Sally A. McKee Ganesh Gopalakrishnan School of Computing School of Electrical and Computer Engineering School of Computing University of Utah Cornell University University of Utah Salt Lake City, Utah 84112 Ithaca, New York 14853 Salt Lake City, Utah 84112 [email protected] [email protected] [email protected] Abstract standard compliance verification. As in any engineering ef- fort, the tools chosen for a verification project can greatly Verification is widely recognized as one of the most affect its eventual success or failure. One of the most impor- difficult aspects of computer hardware design. The gap tant tools of a formal verification engineer is the language between design and verification capabilities grows, as does used to specify the design. Having a broad view of the spec- the cost of missed flaws. Many researchers investigate ification languages available allows the practitioner to refine ways to formally verify processor designs, interconnects, the candidate language set to those most appropriate to the and protocols, but creating verification methods and tools problem to be solved. will remain a central problem for computer scientists for at To that end, we present a taxonomy of the specification least the next decade. We introduce this field by surveying language space, and we use this taxonomy to structure our formal specification languages. We construct a taxonomy of discussion of the relative merits of each approach. We clas- languages and discuss the applicability of each to standard sify specification languages first according to their form, i.e., compliance verification, or demonstrating that a hardware textual versus graphical or visual. We make finer classifica- design complies to an interconnect standard. tions according to origins: HDLs versus traditional software programming languages in the textual case, and software en- gineering versus hardware engineering versus system engi- 1. Introduction neering in the visual case. This short survey is not intended to be comprehensive, but instead serves to familiarize the Verification is one of the most difficult aspects of com- reader with the variety of languages used in practice and puter hardware design. The cost of missing even a single bug their applicability in our domain. can be staggering. For instance, the floating point division The ideal language for our purposes possesses four char- bug in the Intel R Pentium R processor cost the company acteristics, as outlined below. While we realize it is unlikely $475 million [4]. Validation efforts for modern micropro- that an existing language exactly matches our application, cessor designs can consume months of CPU time on large we prefer to make adjustments to a language that already server farms, yet the total “runtime” for the simulated de- exists rather than developing a new language. sign during this period is equivalent to only a few minutes • Precise semantics. A formal specification provides a of wall-clock time on a 1 GHz CPU [2]. Furthermore, the precise baseline for many implementations developed by gap between industrial design capabilities and verification different organizations. capabilities is growing, rather than shrinking, as is the po- • Short learning curve. The specification is likely to be tential cost of bugs that escape verification teams. used by hardware engineers of all specialties, and thus the In response to this problem, researchers and practitioners language must be easy to learn and understand, even by alike strive to create methods and technologies that can help those not highly trained in formal verification techniques. close the design/verification gap. Current formal verifica- • Connections with automatic verification techniques. tion techniques target many aspects of computer systems, in- Because the same verification may be performed by mul- cluding microprocessor design [12, 15, 26], interconnect de- tiple organizations (the intellectual property designer and sign, protocol design [11, 14], and specification validation. integrator, for example), the verification effort must be However, none of the techniques nor tools yet addresses the significantly less than the total design effort. Languages problem of verifying that register transfer language (RTL) that lend themselves to automatic verification techniques designs comply with interconnect standards. help mitigate verification effort. This paper surveys several formal specification languages • Integration with existing design practice. The transfer that are candidates for our application of interest, interface of formal methods technologies to industrial practice de- pends on their ability to fit neatly into existing or emerg- ∗This work was supported by National Science Foundation Grant CCR- 9987516, and was conducted while the second author was at Utah. ing design practices. 2. Textual Languages Objective VHDL. Objective VHDL (OVHDL) raises the abstraction level at which design activities occur, enhancing Textual languages constitute the majority of current spec- design reuse [23]. This object-oriented version of VHDL ification languages. They resemble hardware description adds type classes for data abstraction and entity classes for languages and conventional programming languages, and structural abstraction. Type classes allow the user to create therefore lend themselves to automated analysis. We divide class data types, such as arrays or records, with inheritance such approaches broadly into those inspired by hardware de- and data hiding. Since VHDL entity-architecture pairs al- scription languages, which tend to describe designs in low- ready implement data hiding, OVHDL developers only add level detail, and those arising from programming languages, inheritance to complete the implementation of entity classes. which tend to specify behavior at a higher abstraction level. Allara, et al., point out that designers require only mini- mal training in using the additional OVHDL syntax [1], and 2.1. Hardware Description Languages automatic formal verification tools exist for which VHDL is the modeling language. The OVHDL tool suite translates We first focus on two HDL approaches, hardware mon- models into VHDL that can be simulated by off-the-shelf itors and Objective VHDL. Hardware monitors have been tools, facilitating integration with existing design practice. used to specify the PCI 2.2 standard and the Intel ItaniumTM As with hardware monitor specifications, the semantics of bus protocol. Objective VHDL was developed to support OVHDL models depend on the chosen VHDL simulators. abstraction and reuse in hardware modeling. Figure 1(a) shows how a hypothetical counter module Hardware Monitors. The use of monitor modules as aids might be specified using OVHDL. The inputs inc and re- for simulation-based verification was proposed as early as set increment and reset the counter’s value, respectively. In 1996 [19]. Shimizu, et al., retarget monitors for formally Figure 1(a), the counter class is declared with a single data specifying hardware designs [25], showing that even the attribute, count, of type integer. Procedures are then de- most complicated hardware protocols can be described in clared to handle the two inputs and implemented to handle this manner [24]. Such a specification consists of a series the inc input and the reset input. of small monitor modules written in the same hardware de- scription language as the implementation, where each mon- 2.2. Programming Languages itor describes one requirement in the specification. Moni- tors used for hardware specification tend to be of two types: Next we consider SpecC and JavaTMfor hardware speci- a small counter machine for an event which must happen fication. SpecC encourages design reuse by providing a sin- within a certain number of cycles of a trigger event; or a flag gle, executable language in which to document many design machine that remembers one piece of information, such as activities. Java, a high-level, object-oriented programming whether the transaction is a read or a write. language, developed at Sun Microsystems R , enables hard- Monitors possess capabilities especially useful for proto- ware/software codesign by providing a single simulation en- col design and verification. First, they can be checked for vironment for the entire system. internal consistency using standard model checking tools, SpecC. SpecC is a formal, executable modeling lan- without the aid of a completed implementation. Second, guage with an accompanying tool suite intended to facili- they can be reused for many verification purposes. Fi- tate hardware-software codesign [8]. The language retains nally, monitor-style specifications can be proven to be im- much of the syntax of the C programming language. At plementable, as demonstrated by Shimizu and colleagues. each stage in the SpecC design cycle, tools generate models Monitor specifications do not require the designer to learn that can be analyzed by typical simulation and debugging a new language to create the specification, since they are tools. Other SpecC tools provide static analysis and esti- written in hardware description languages. Furthermore, mation to ensure that design metrics remain within specified writing the specification in the same HDL as the imple- bounds. SpecC’s formal semantics and familiar syntax com- mentation means that the specification is already fully in- bined with the complete design methodology surrounding tegrated into the design cycle and is supported by appropri- the
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