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A linear-logarithmic CMOS pixel for behavior with fixed-pattern- correction and tunable responsivity

Monica Vatteroni, Daniele Covi and Alvise Sartori Neuricam s.p.A. Via Grazioli 71, I-38100 Trento, Italy {vatteroni,covi,sartori}@neuricam.com

Abstract—A CMOS with programmable dynamic are the simplicity of the architecture and the wide obtainable range linear-logarithmic response through tunable transition dynamic range. Disadvantages are the pure response at low point and fixed pattern noise correction is presented. Each 2 and the high residual FPN. 9.4x9.4μm pixel cell integrates a 5T active pixel structure with a An alternative and more recent technique to obtain intra- hard reset and an active load for the high light logarithmic frame high dynamic range is the so called time-to-saturation behavior. A chip with a 100x100 pixel array and 12- digital approach [7]; in this case, two are combined to obtain output has been fabricated in a 0.35um, 3.3V standard CMOS an enhanced dynamic image: a standard linear output and a technology. The dynamic range of the sensor can be changed from 45dB to over 120dB with decreasing pixel resolution, the related to the time needed to reach a saturation temporal noise is lower than 0.22% over the full range and the threshold. The range depends on the function used to map the fixed patter of 0.83% (1.39%) in the linear (logarithmic) region. saturation time into the read-out voltage signal and is theoretically extendable to over 120dB. Keywords: dynamic range, image sensor, CMOS active pixel, A detailed reference list with a comparative theoretical study . of main high dynamic (HDR) architectures can be found in [8]. This work proposes an architecture which aims to take I. INTRODUCTION advantage of the simplicity and wide dynamic range of the High Dynamic Range (HDR) is the capability to map a wide logarithmic technique, overcoming his disadvantages. Starting range of light in the same picture. Techniques to obtain high from this basic idea, a novel image sensor with linear- dynamic range have been widely studied in the past and can logarithmic response has been developed. In this contribute be classified in two major groups: intra-frame and inter-frame we present the design and characterization of a 100×100 pixel techniques. In the first case the whole light dynamic is image sensor, fabricated in a standard 0.35μm, 3.3V CMOS mapped in the same image, in the second one, the high technology. The sensor is capable of high dynamic range dynamic range image is a result of the combination of more imaging (over 120dB), with a complete pixel level fixed than one image [1-3]. Nowadays the simplicity of the multi- pattern noise (FPN) subtraction in the linear region as well integration technique makes it the most used at industrial partially in the logarithmic one. Moreover, the power level. In a technique that can be considered an evolution of responsivity curve of the proposed sensor can be easily the multiple capture one, pixels are progressively reset to a adjusted, through a tunable analog reference, to obtain a wide decreasing reference value [4]. The result is that only pixels dynamic range rather than a high pixel resolution. which, at every commutation, have reached a voltage lower The pixel operating principle is described in Section II, the than the new reference value will be reset while the other will imager architecture is discussed in Section III and continue to discharge. This leads to an intra-frame image with measurement results are presented in section IV. enhanced noise performance. Within intra-frame techniques, the simplest is the logarithmic one [5-6]. The array is continuously read-out and the photo-detector output is II. PIXEL OPERATION PRINCIPLE compressed by means of a dynamic MOS load. The result is a The proposed linear-logarithmic pixel is shown in Figure logarithmic compressed light response that covers over 6 1. The pixel is covered by patent [9] and operates as follows. decades of irradiance. The main advantages of this technique The image acquisition starts by resetting the integration

1-4244-2581-5/08/$20.00 ©2008 IEEE 930 IEEE SENSORS 2008 Conference capacitance through the reset switch. In this phase the input of Correlated Double Sampling (CDS) Column , a node is set to the reset voltage Vres. After that the integration Data Double Sampling (DDS) block [10], a pre-amplifier, a starts by switching RES off. During the integration the photo- 12-bit ADC, and several other support blocks (Figure 2). generated current Iph is integrated onto the parasitic When a row-decoder selects a row, every pixel of the selected capacitance at the input node (In). In low-medium light line transfers simultaneously its output value to a Column conditions, the pixel operates as a standard active pixel sensor Amplifier which stores the information. Then the pixels of the (APS) and the light intensity is linearly related to the voltage selected row are reset and their reset values are transferred to at the photosensitive node Vin. Nevertheless, in a standard the associated bit-line Column Amplifier. The Column APS, increasing the light intensity, the input node quickly subtracts this value from the stored one and makes saturates and no information is associated to light the result available at the output. This subtraction allows to corresponding to voltage over the saturation value. In the eliminate pixel Fixed Pattern Noise. This correction is linear-logarithmic pixel, the voltage at the photosensitive node complete in the case of linear response and partial in case of increase linearly with the light intensity up to voltage value logarithmic response because the contribution of the MOS depending on the commutation voltage VLOG. Above this active load is not cancelled. The Column Amplifiers are threshold an active MOS pixel load becomes active and the selected by a column decoder and the output value of each one response of the pixel is logarithmicly compressed, been is sequentially transferred to a DDS that performs a double potentially able to see images in a range over 120 dB. The reading of each Column Amplifier, signal and reset value, a VLOG voltage is tunable by the user in order to modify the subtraction between them and an addition of a threshold power response to enhance the light dynamic range rather than voltage (VREF). The DDS output is differential, following the the pixel responsivity. At different value of the VLOG voltage, law: between 1.0V and 3.3V, the light dynamic of the sensor VOutDDS± = VCM ± GAIN × (VREF - (VResCDSOut - VSigCDSOut)) changes from 50dB to over 120dB, progressively reducing the linear region. where VOutDDS± are the DDS Outputs, VResCDSOut is the Column It has also to be noted that the hard reset implemented at pixel Amplifier Reset Output, VSigCDSOut is the Column Amplifier level allows a fixed patter noise (FPN) correction not only in Signal Output, VREF is a reference voltage, VCM is the common the linear region, but also partially in the logarithmic one with mode voltage and GAIN is the DDS variable gain ( between 1 a significant improvement of the raw image quality also in the and 4). high light range. The DDS differential output signals are sent to a 12-bit The simplicity of this architecture permits a compact pixel ADC and digitized into 4096 levels. Each pixel is therefore design according to the used CMOS technology. described by a 12-bit word following the law: + − − V V 11 ADCOUT = OutDDS OutDDS * 2 VREFP −VREFN

where VOutDDS± are the DDS differential output, VREFP and VREFN are the ADC reference voltages and ADCOUT is the ADC digital output word.

Figure 1. Schematic diagram of the proposed pixel.

III. CHIP ARCHITECTURE Figure 2. Sempified block diagram of the camera. The linear-logarithmic technique presented in this work has been implemented in a monolithic active-pixel IV. EXPERIMENTAL RESULTS grey level camera-on-a-chip sensor. The photo-sensitive The image sensor has been realized in a standard 0.35μm matrix consists of 100×100 pixel array based on a CMOS technology. The chip layout is shown in Figure 3. nwell/psubstrate photodiode, with a pixel pitch of 9.4μm×9.4μm. The sensor integrates a pixel array, a number

931 The die size is about 6.36mm×3.68mm, including test is clearly valuable that the light response resolution is structures not described in this work. Electro-optical tests were significantly higher in the linear region than in the logarithmic carried out on a dedicated electro-optical bench to characterize one but, changing the VLOG value from 1.8V to 2.2V the loss, the imager sensor performance. For this purpose, a custom in terms of dynamic range, in the linear region is insignificant board has been developed (Figure 4). The overall integration if compared to the overall gain of one decade. It has to be time has been set to 30ms and the VLOG reference has been set noted that the limitation to 110dB of the power response is to different values to prove the power responsivity due to the measurement set-up and can theoretically go over modulation. the 120dB. Nevertheless, the sensitivity of the pixel can be improved increasing the integration time, like in a standard linear APS. The measured Signal to Noise Ratio (SNR) is also reported in Figure 5, showing the possibility to obtain a maximum DR over the 120dB, in fact it can be noted that there is no appreciable decrease in the SNR curve for strong incident light. Examples of HDR images acquired with the described chip are shown in Figure 6. The full image has been shown compressed in 8 and in 10 bits divided in 4 slices of 8 bit, to better appreciate the high dynamic range capability. No processing has been applied to the images. The most appreciable aspect is the quantity of residual fixed pattern noise in the high light region; compared to a pure logarithmic response, it is significantly reduced (1.37% over the whole range). Finally, the main performance of the developed image sensor Figure 3. Complete imager layout are summarized in Table I.

3.00

VLOG=1.8V VLOG=2.0V VLOG=2.2V

2.00 Output code (LSB)

1.00

0.00 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 Irradiance (W/m2)

60.00

50.00 Figure 4. Customized test board

40.00 VLOG=1.8V VLOG=2.0V VLOG=2.2V As can be seen in Figure 5, over an of 30.00 11.6 (DR=110dB ) the main part of the power response in dedicated to the linear region that covers 2.2 decades of S/Nmedio (dB) 20.00 irradiance with high resolution (11.2bits – DR=45dB), while the residual 3.3 decades (DR=65dB) are logarithmically 10.00 compressed with a significantly lower resolution. To test the 0.00 modulation capability of the power responsivity the VLOG reference voltage has been set at three different value: 1.8V, -10.00 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 2.0V and 2.2V. The result is a shift of the transition point from Irradiance (W/m2) linear to logarithmic region in the power responsivity curve. It

932 Figure 5. Power responsivity and SNR at different VLOG values. V. CONCLUSIONS AND FUTURE PERSPECTIVES

A novel linear-logarithmic technique for intra-frame high dynamic range imager sensor has been implemented in a 100×100 pixel device. The imager achieves over 120 dB of DR with good temporal noise (0.22% rms) and fixed pattern noise (0.83-1.37%) performance, also in the logarithmic region. The developed sensor produces a 12-bit digital output mapping the whole dynamic range and featuring a high SNR even at high illuminations. Furthermore, the dynamic range and, accordingly, the resolution of the power responsivity curve can be simply adjusted by the used tuning the transition from linear to logarithmic domain through an analog reference signal setting.

Figure 6. Example of HDR images – rescaled to 8bits and divided in 4 slices in a different light range. REFERENCES [1] D. Yang, A. El Gamal, B. Fowel and H. Tian, “A 640x512 CMOS image sensor with ultrawide dynamic range floating-point pixel-level ADC,” IEEE J. Solid State Circuits, vol.34, pp.1821-1834, Dec.1999. [2] T. Lulé, B. Schneider and M. Bohm, “Design and fabrication of a high TABLE I. PERFORMANCE OF THE DEVELOPED IMAGE SENSOR dynamic-range image sensor in TFA technology,” IEEE J. Solid-State Circuits, vol. 34, pp. 704–711, May 1999. Technology 0.35μm, 3.3V CMOS (2P-4M) [3] B. J. Hosticka, W. Brockherde, A. Bussmann, T. Heimann, R. Jeremias, A. Kemma, C. Nitta and O. Schrey, “CMOS imaging for automotive Pixel pitch 9.4 μm×9.4 μm applications“, IEEE Trans. On Electron Devices, vol. 50, no.1, pp. 173- 182, Jan. 2003. Array size 100×100 pixels [4] H. Seung, C.G. Sodini, K.G. Fife, SMaL Camera Tech., U.S. Patent Application US6,600,471, 2003. Chip size 6.36mm×3.68mm [5] M. Loose, K. Meier and J. Schemmel, “A self-calibrating single-chip CMOS camera with logarithmic response,” IEEE J. Solid State 4mA (Digital part @ 30fps) Circuits, vol. 36, pp. 586-596, Apr. 2001. Operating supply current [6] S. Kavadias, B. Dierickx, D. Scheffer, A. Alaerts, D. Uwaerts and J. 32mA (Analog part @ 30fps) Boagaerts, “A logarithmic response CMOS image sensor with on-chip calibration”, IEEE J. Solid-State Circuits, vol. 35, pp. 1146-1152, Aug. Fill factor 30% 2000. [7] D. Stoppa, M. Vatteroni, A. Baschirotto, A. Sartori, A. Simoni, “A 120- Sensor output 12 bit digital output dB dynamic range CMOS image sensor with programmable power responsivity,” IEEE J. Solid state Circuits, vol. 42, pp.1555-1563, Jul. FNP(linear, logarithmic reg.) 0.83%, 1.37% 2007. [8] S. Kavusi, et al., “Quantitative study of high dynamic range image PN(linear, logarithmic reg.) < 0.22% sensor architectures”, Proc. of SPIE vol. 5301, pp. 264- 275, Apr. 2004. Dynamic range 112dB [9] A. Sartori, M. Vatteroni, NeuriCam S.p.A., U.S. Patent Application US6,600,471, 2003. 0.22% (Of saturation signal at [10] S. K. Mendis, S. E. Kemeny, R. C. Gee, B. Pain, C. O. Staller, Q. Kim Dark Signal room temperature) and E. R. Fossum, “CMOS active pixel image sensors for highly integrated imaging systems”, IEEE J. Solid-State Circuits, vol. 32, pp. 187-197, Feb. 1997.

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