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Timing Products Update Timing Products Update J U N E 2 0 2 0 Complete Timing Portfolio ▪ Leader in high performance clocks and oscillators ▪ Frequency flexibility + ultra-low jitter ▪ Best-in-class integration → single IC clock trees ▪ Highly programmable with quick-turn samples XO/VCXO Clock Generators Clock Buffers Synchronization Jitter Attenuating Clocks Wireless Clocks 2 3 Focus Markets COMMUNICATIONS DATA CENTER WIRELESS INDUSTRIAL/AUTOMOTIVE Optical line cards Top of rack switches RRU/BBU/Massive MIMO Autonomous driving Optical modules Servers / storage Small cells/DAS Broadcast video Core switches & routers Acceleration cards Fronthaul/backhaul Audio/video processing Broadband access SmartNICs Test/measurement Timing Portfolio Overview Wireless/ Si5348/83 Oscillators Clock Gens JA Clocks Coherent JAs Buffers 3-DSPLL SyncE + GPS Clock <100 fs RMS Si545-9 Si5391 Si539x Si537x Si5388/89 3-DSPLL SyncE + GPS + 1588 SW SyncE Si540-4 100-200 fs Si5341/0 Si534x Si538x Si533xx Modules RMS Si56x IEEE 1588/SyncE 1588/ IEEE 1588 SW 200-500 fs Si53x Si5332 Si532x RMS Servo+Stack Si59x Si522xx 500-800 fs Si5338 Clock Gens RMS Si51x Si532xx >1 ps RMS Si5351/7 Clock Buffers (LVCMOS only) Si531xx Automotive temperature grade available Zero Delay Buffers PCIe Gen1/2/3/4/5 Differentiated Technology MULTISYNTH DSPLL INTEGRATED REFERENCE XO Phase Loop DCO VCO Detector Filter OUT MultiSynth Frac-N Divider MCM Frac-N Phase Divider Adjust DSPLL Inner Loop fVCO fDIV fOUT Reference Phase Error e Cancellation Divider Select Si5332 (DIV1, DIV2) Phase Digital fIN Loop DCO Detector fOUT Si539x & ADC Filter Frac-N Divider DSPLL Outer Loop Any-Frequency clock synthesis Eliminates VCXO & loop filter Improved system reliability, low-jitter performance Better stability during Zero ppm error temperature ramp tests Smaller PCB area 5 Reference Design Partnerships ▪ FPGAs ▪ Network processors ▪ Ethernet switch SoCs and fabrics ▪ Optical transceivers ▪ Server processors ▪ GPUs ▪ 5G wireless infrastructure IC’s ▪ Automotive processors and switches Oscillators/VCXOs Si54x/56x Ultra SeriesTM Oscillators Frequency Flexible, Ultra Low Jitter XO/VCXO ▪ Ultra low jitter: 80 fs RMS ▪ Ideal for 28G / 56G / 112G SerDes ▪ Any frequency from 200 kHz to 3.0 GHz, <1ppb steps ▪ Single/Dual/Quad/I2C, XO and VCXO options ▪ Better stability and aging than SAW oscillators ▪ Built-in power supply noise rejection ▪ Linear Kv ensures constant loop bandwidth ▪ Adjustable VCXO gain simplifies development ▪ 1~2 week sample lead time: 5x7, 3.2x5, 2.5x3.2mm Fixed Frequency XTAL DSPLL IC High Performance XO Portfolio Launching 3Q, Sampling Now Frequency TYP Total Performance Part Number of Voltage Temp Size Range Jitter Stability Number CML Option Frequencies LVDS (V) (°C) (mm) HCSL (MHz) (fs RMS) (±ppm) LVPECL LVCMOS Dual CMOS Si545 Single 5 x 7 Si546 Dual 0.2 to 1500 80 20, 25, 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si547 Quad NEW! 2.5 x 3.2 Si549 Any (I2C) Si540 Single Ultra 5 x 7 Si541 Dual Low 0.2 to 1500 125 20, 25, 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si542 Quad Jitter 2.5 x 3.2 Si544 Any (I2C) Si560 Single 5 x 7 Si561 Dual 0.2 to 3000 90 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si562 Quad 2.5 x 3.2 Si564 Any (I2C) Si530/1 Single Low Si532/3 Dual 20, 31.5, 10 to 1417 300 l l l l 1.8, 2.5, 3.3 -40 to 85 5 x 7 Jitter Si534 Quad 61.5 Si570 Any (I2C) Si590/1 Single 20, 30, 5 x 7 10 to 810 500 l l l 1.8, 2.5, 3.3 -40 to 85 Si598 Any (I2C) 50, 100 3.2 x 5 General Purpose Si510/1 Single 5 x 7 30, 50, Si512/3 Dual 0.1 to 250 800 l l l l l 1.8, 2.5, 3.3 -40 to 85 3.2 x 5 100 Si514 Any (I2C) 2.5 x 3.2 High Performance VCXO Portfolio Launching 3Q, Sampling Now Frequency TYP Min Performance Part Number of Voltage Temp Size Range Jitter APR Number CML Option Frequencies LVDS (V) (°C) (mm) HCSL (MHz) (fs RMS) (±ppm) LVPECL LVCMOS Dual CMOS Si565 Single NEW! 5 x 7 Si566 Dual Ultra 0.2 to 3000 100 20 - 190 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si567 Quad Low Jitter 2.5 x 3.2 Si569 Any (I2C) Si550 Single Low Si552 Dual 10 to 1417 500 12 - 375 l l l l 1.8, 2.5, 3.3 -40 to 85 5 x 7 Jitter Si554 Quad Si571 Any (I2C) Si595 Single Si596 Dual 5 x 7 10 to 810 700 10 - 370 l l l l 1.8, 2.5, 3.3 -40 to 85 Si597 Quad 3.2 x 5 General Si599 Any (I2C) Purpose 5 x 7 Si515 Single 0.1 to 250 1000 30 - 100 l l l l l 1.8, 2.5, 3.3 -40 to 85 3.2 x 5 Si516 Dual 2.5 x 3.2 Si54x/56x Provides Ultra Low Jitter 75 fs RMS 12kHz-20MHz Si545-Si549: Consistent, Ultra Low Jitter for Any Frequency Typ Jitter > 200MHz = 80 fs! Si56x: Consistent, Ultra Low Jitter up to 3GHz Typ Jitter > 200MHz = 90 fs High Noise Rejection Ensures Reliable Operation VDD < 50 fs of additive jitter ▪ On-chip regulation ensures low jitter operation in noisy systems ▪ Eliminates or simplifies power supply filtering ▪ Simplifies layout and design Si56x DSPLL Provides High Control Voltage Linearity Conventional VCSO Si56x VCXO ▪ Digital control provides more linear response versus varactor-based solutions ▪ Keeps loop bandwidth constant over entire Vc pull range ▪ Adjustable VCXO gain (Kv) via I2C simplifies development Online XO Phase Noise Look-Up Tool ▪ Instant, real-world XO phase noise plots! ▪ All plots are screen shots directly from phase noise analyzer ▪ Over 1000 combinations available - product family, output format, and output frequency ▪ Also works on mobile devices ▪ Available for free on the Silicon Labs oscillator webpage ▪ www.silabs.com/oscillators Clock Generators Any-Frequency Clock Generators Si5391 Si5340/1 Si5332 Si5335/8 Si5350/7/Si5121x RMS Phase Jitter 69 fs 100 fs 230 fs 800 fs 1ps # Outputs 12 4, 10 6, 8, 12 4 2, 3, 8, 12 Out Frequency Range 0.1 – 1028 MHz 0.1 – 1028 MHz 5 – 333.33 MHz 0.16 – 710 MHz 0.25 – 200 MHz Spread Spectrum No No Yes Yes Yes HW Input Pins No No Yes Yes Yes Output Format LVDS, LVPECL, LVDS, LVPECL, HCSL, LVDS, LVPECL, HCSL, LVDS, LVPECL, LVCMOS HCSL, LVCMOS HCSL, LVCMOS LVCMOS LVCMOS Embedded Xtal No No Yes (Q4) No No ClockBuilder Pro Yes Yes Yes Yes Yes Target Markets Communications, Communications, Data center, Data center, Consumer, Industrial Data Center, OTN Industrial Industrial Industrial Data Center Target Applications 100/200/400G 100/200/400G 25/40/50/100G 10G 1G and below 56G PAM4 SerDes 28G SerDes 10/28G SerDes, PCIe 10G SerDes, PCIe Si534x/91 Any-Frequency Clock Generators for 100/200/400G Phase Clock Inputs/ Output Part Number Jitter PLL Bandwidth Package Outputs Frequency (fs RMS) 69 INT Si5391 4 / 12 1 MHz 64-QFN 4/10/12 130 FRAC MultiSynth Outputs 0.001 MHz to OSC Si5341 4/10 64-QFN Crystal 1028MHz 100 INT MultiSynth Output PLL 140 FRAC Clock Si5340 4/4 44-QFN Input ... Clocks MultiSynth Format & MultiSynth Dividers ▪ Generates any mix of output frequencies SPI/ Status & MultiSynth I2C Control Program & ▪ 69 fs RMS phase jitter (12 kHz -20 MHz) Control NVM ▪ Configurable outputs: LVPECL, LVDS, LVCMOS, HCSL, CML ▪ Glitchless, dynamic on-the-fly frequency switching ▪ Customizable using ClockBuilder Pro ▪ -40 to +85 ⁰C operation 25 Precision Calibration Grade Performance Clock Outputs: ▪ 156.25MHz ▪ 312.5MHz ▪ 100MHz ▪ 50MHz ▪ 25MHz Si5332 Any Frequency Clock Generators for 10/25/50/100G Part Clock Output RMS Phase # Control Pins Package Number Outputs Frequency Jitter Si5332 32-QFN, 10 MHz to Multi Si5332 6 / 8 / 12 230 fs 5 / 7 / 7 40-QFN 333.33 MHz OSC Synth 48-QFN Crystal Low Multi ÷ INT Jitter Synth 6/8/12 Input PLL ÷ INT Output ▪ Generates any mix of output frequencies Clocks ÷ INT Clocks ÷ INT ÷ ▪ User-defined HW input pins GPI Status / ÷ INT INT Pins Control n ÷ INT ▪ Two independent SSCG domains ▪ Embedded reference crystal option ▪ Low phase jitter ▪ 175 fs RMS (integer) ▪ 250 fs RMS (fractional) ▪ Multi-profile selection via HW input pins ▪ Excellent PSNR simplifies external filtering ▪ 1.8V – 3.3V operation 26 On-Chip Noise Regulation Ensures Low Jitter Operation Si5332 PSNR total jitter, 3.3 V , 156.25 MHz, LVDS, 100 mV sine wave noise 1.8V-3.3V Si5332 300 0 250 -20 VDD or VDDO pin 200 -40 1uF 0.1uF 150 -60 Spur (dBc) RMS (fs) Jitter 100 -80 50 -100 ▪ Extensive on-chip power supply regulation 0 -120 25 50 100 250 500 1000 ▪ Ensures low jitter operation in noisy systems Power supply noise freq (KHz) ▪ Simplifies power supply filtering RMS jitter (fs) Power of spurious tone (dBC) ▪ Only 2 external caps on each VDD/VDDO ▪ IDT requires up to 30 passives for power filtering ▪ TI requires an external LDO and passives 22 Jitter Attenuator Clocks Si539x Si534x Si532x RMS Phase Jitter 69 fs 100 fs 230 fs # Outputs 12 4, 10 6, 8, 12 Output Frequency Range 0.1 – 1028 MHz 0.1 – 1028 MHz 5 – 312.5 MHz Spread Spectrum No No Yes HW Input Pins No No Yes LVDS, LVPECL, LVDS, LVPECL, HCSL, LVDS, LVPECL, Output Format HCSL, LVCMOS HCSL, LVCMOS LVCMOS Embedded Xtal Yes No Yes ClockBuilder Pro Yes Yes Yes Communications, Communications, Target Markets Data center, Industrial Data Center, OTN Industrial 100/200/400G 100/200/400G 25/40/50/100G Target Applications 56G PAM4 SerDes 28G SerDes 10/28G SerDes, PCIe Si539x Jitter Attenuators for 200/400G Clock Input Output Phase Part Inputs/ Frequency Frequency Jitter Package Number Outputs (MHz) (MHz) (fs RMS) Si5395 4/12 64QFN 9x9mm 0.008 to 0.001 to 4/4 80 44QFN 7x7mm Si5394 750 MHz 1028 MHz Si5392 4/2 44QFN 7x7mm ▪ Up to 12 outputs - ANY combination of output frequencies ▪ 69 fs (int); 150 fs (frac) RMS phase jitter [12kHz -20MHz] ▪ Jitter/wander attenuation (down to 0.1 Hz) ▪ Enhanced input clock hitless switching: 0.2 ns ▪ Status monitoring: LOL, LOS, OOF ▪ 0.1Hz to 4 kHz PLL bandwidth 24 Si5397/96: High Performance Multi-DSPLL Jitter Attenuating Clocks
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