Timing Products Update
J U N E 2 0 2 0 Complete Timing Portfolio
▪ Leader in high performance clocks and oscillators ▪ Frequency flexibility + ultra-low jitter ▪ Best-in-class integration → single IC clock trees ▪ Highly programmable with quick-turn samples
XO/VCXO Clock Generators Clock Buffers
Synchronization Jitter Attenuating Clocks Wireless Clocks
2 3 Focus Markets
COMMUNICATIONS DATA CENTER WIRELESS INDUSTRIAL/AUTOMOTIVE
Optical line cards Top of rack switches RRU/BBU/Massive MIMO Autonomous driving Optical modules Servers / storage Small cells/DAS Broadcast video Core switches & routers Acceleration cards Fronthaul/backhaul Audio/video processing Broadband access SmartNICs Test/measurement Timing Portfolio Overview
Wireless/ Si5348/83 Oscillators Clock Gens JA Clocks Coherent JAs Buffers 3-DSPLL SyncE + GPS Clock <100 fs RMS Si545-9 Si5391 Si539x Si537x Si5388/89 3-DSPLL SyncE +
GPS + 1588 SW SyncE Si540-4 100-200 fs Si5341/0 Si534x Si538x Si533xx Modules
RMS Si56x IEEE 1588/SyncE 1588/ IEEE 1588 SW 200-500 fs Si53x Si5332 Si532x RMS Servo+Stack
Si59x Si522xx 500-800 fs Si5338 Clock Gens RMS Si51x Si532xx >1 ps RMS Si5351/7 Clock Buffers (LVCMOS only) Si531xx
Automotive temperature grade available Zero Delay Buffers PCIe Gen1/2/3/4/5 PCIe Differentiated Technology
MULTISYNTH DSPLL INTEGRATED REFERENCE
XO Phase Loop DCO VCO Detector Filter OUT MultiSynth
Frac-N Divider MCM Frac-N Phase Divider Adjust DSPLL Inner Loop fVCO fDIV fOUT Reference
Phase Error e Cancellation
Divider Select Si5332 (DIV1, DIV2) Phase Digital fIN Loop DCO Detector fOUT Si539x & ADC Filter
Frac-N Divider DSPLL Outer Loop
Any-Frequency clock synthesis Eliminates VCXO & loop filter Improved system reliability, low-jitter performance Better stability during Zero ppm error temperature ramp tests Smaller PCB area
5 Reference Design Partnerships
▪ FPGAs ▪ Network processors ▪ Ethernet switch SoCs and fabrics ▪ Optical transceivers ▪ Server processors ▪ GPUs ▪ 5G wireless infrastructure IC’s ▪ Automotive processors and switches Oscillators/VCXOs Si54x/56x Ultra SeriesTM Oscillators
Frequency Flexible, Ultra Low Jitter XO/VCXO ▪ Ultra low jitter: 80 fs RMS ▪ Ideal for 28G / 56G / 112G SerDes ▪ Any frequency from 200 kHz to 3.0 GHz, <1ppb steps ▪ Single/Dual/Quad/I2C, XO and VCXO options ▪ Better stability and aging than SAW oscillators ▪ Built-in power supply noise rejection ▪ Linear Kv ensures constant loop bandwidth ▪ Adjustable VCXO gain simplifies development ▪ 1~2 week sample lead time: 5x7, 3.2x5, 2.5x3.2mm Fixed Frequency XTAL
DSPLL IC High Performance XO Portfolio Launching 3Q, Sampling Now
Frequency TYP Total Performance Part Number of Voltage Temp Size Range Jitter Stability
Number CML
Option Frequencies LVDS (V) (°C) (mm) HCSL
(MHz) (fs RMS) (±ppm) LVPECL
LVCMOS Dual Dual CMOS Si545 Single 5 x 7 Si546 Dual 0.2 to 1500 80 20, 25, 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si547 Quad NEW! 2.5 x 3.2 Si549 Any (I2C) Si540 Single Ultra 5 x 7 Si541 Dual Low 0.2 to 1500 125 20, 25, 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si542 Quad Jitter 2.5 x 3.2 Si544 Any (I2C) Si560 Single 5 x 7 Si561 Dual 0.2 to 3000 90 50 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si562 Quad 2.5 x 3.2 Si564 Any (I2C) Si530/1 Single Low Si532/3 Dual 20, 31.5, 10 to 1417 300 l l l l 1.8, 2.5, 3.3 -40 to 85 5 x 7 Jitter Si534 Quad 61.5 Si570 Any (I2C)
Si590/1 Single 20, 30, 5 x 7 10 to 810 500 l l l 1.8, 2.5, 3.3 -40 to 85 Si598 Any (I2C) 50, 100 3.2 x 5 General Purpose Si510/1 Single 5 x 7 30, 50, Si512/3 Dual 0.1 to 250 800 l l l l l 1.8, 2.5, 3.3 -40 to 85 3.2 x 5 100 Si514 Any (I2C) 2.5 x 3.2 High Performance VCXO Portfolio Launching 3Q, Sampling Now
Frequency TYP Min Performance Part Number of Voltage Temp Size Range Jitter APR
Number CML
Option Frequencies LVDS (V) (°C) (mm) HCSL
(MHz) (fs RMS) (±ppm) LVPECL
LVCMOS Dual Dual CMOS
Si565 Single NEW! 5 x 7 Si566 Dual Ultra 0.2 to 3000 100 20 - 190 l l l l l l 1.8 - 3.3 -40 to 85 3.2 x 5 Si567 Quad Low Jitter 2.5 x 3.2 Si569 Any (I2C) Si550 Single Low Si552 Dual 10 to 1417 500 12 - 375 l l l l 1.8, 2.5, 3.3 -40 to 85 5 x 7 Jitter Si554 Quad Si571 Any (I2C) Si595 Single Si596 Dual 5 x 7 10 to 810 700 10 - 370 l l l l 1.8, 2.5, 3.3 -40 to 85 Si597 Quad 3.2 x 5 General Si599 Any (I2C) Purpose 5 x 7 Si515 Single 0.1 to 250 1000 30 - 100 l l l l l 1.8, 2.5, 3.3 -40 to 85 3.2 x 5 Si516 Dual 2.5 x 3.2 Si54x/56x Provides Ultra Low Jitter
75 fs RMS 12kHz-20MHz Si545-Si549: Consistent, Ultra Low Jitter for Any Frequency
Typ Jitter > 200MHz = 80 fs! Si56x: Consistent, Ultra Low Jitter up to 3GHz
Typ Jitter > 200MHz = 90 fs High Noise Rejection Ensures Reliable Operation
VDD
< 50 fs of additive jitter
▪ On-chip regulation ensures low jitter operation in noisy systems ▪ Eliminates or simplifies power supply filtering ▪ Simplifies layout and design Si56x DSPLL Provides High Control Voltage Linearity
Conventional VCSO Si56x VCXO
▪ Digital control provides more linear response versus varactor-based solutions ▪ Keeps loop bandwidth constant over entire Vc pull range ▪ Adjustable VCXO gain (Kv) via I2C simplifies development Online XO Phase Noise Look-Up Tool
▪ Instant, real-world XO phase noise plots! ▪ All plots are screen shots directly from phase noise analyzer ▪ Over 1000 combinations available - product family, output format, and output frequency ▪ Also works on mobile devices ▪ Available for free on the Silicon Labs oscillator webpage ▪ www.silabs.com/oscillators Clock Generators Any-Frequency Clock Generators
Si5391 Si5340/1 Si5332 Si5335/8 Si5350/7/Si5121x RMS Phase Jitter 69 fs 100 fs 230 fs 800 fs 1ps # Outputs 12 4, 10 6, 8, 12 4 2, 3, 8, 12 Out Frequency Range 0.1 – 1028 MHz 0.1 – 1028 MHz 5 – 333.33 MHz 0.16 – 710 MHz 0.25 – 200 MHz Spread Spectrum No No Yes Yes Yes HW Input Pins No No Yes Yes Yes Output Format LVDS, LVPECL, LVDS, LVPECL, HCSL, LVDS, LVPECL, HCSL, LVDS, LVPECL, LVCMOS HCSL, LVCMOS HCSL, LVCMOS LVCMOS LVCMOS Embedded Xtal No No Yes (Q4) No No ClockBuilder Pro Yes Yes Yes Yes Yes Target Markets Communications, Communications, Data center, Data center, Consumer, Industrial Data Center, OTN Industrial Industrial Industrial Data Center Target Applications 100/200/400G 100/200/400G 25/40/50/100G 10G 1G and below 56G PAM4 SerDes 28G SerDes 10/28G SerDes, PCIe 10G SerDes, PCIe Si534x/91 Any-Frequency Clock Generators for 100/200/400G
Phase Clock Inputs/ Output Part Number Jitter PLL Bandwidth Package Outputs Frequency (fs RMS) 69 INT Si5391 4 / 12 1 MHz 64-QFN 4/10/12 130 FRAC MultiSynth Outputs 0.001 MHz to OSC Si5341 4/10 64-QFN Crystal 1028MHz 100 INT MultiSynth Output PLL 140 FRAC Clock Si5340 4/4 44-QFN Input ... Clocks MultiSynth Format & MultiSynth Dividers ▪ Generates any mix of output frequencies SPI/ Status & MultiSynth I2C Control Program & ▪ 69 fs RMS phase jitter (12 kHz -20 MHz) Control NVM ▪ Configurable outputs: LVPECL, LVDS, LVCMOS, HCSL, CML ▪ Glitchless, dynamic on-the-fly frequency switching ▪ Customizable using ClockBuilder Pro ▪ -40 to +85 ⁰C operation
25 Precision Calibration Grade Performance
Clock Outputs: ▪ 156.25MHz ▪ 312.5MHz ▪ 100MHz ▪ 50MHz ▪ 25MHz Si5332 Any Frequency Clock Generators for 10/25/50/100G
Part Clock Output RMS Phase # Control Pins Package Number Outputs Frequency Jitter Si5332 32-QFN, 10 MHz to Multi Si5332 6 / 8 / 12 230 fs 5 / 7 / 7 40-QFN 333.33 MHz OSC Synth 48-QFN Crystal Low Multi ÷ INT Jitter Synth 6/8/12 Input PLL ÷ INT Output ▪ Generates any mix of output frequencies Clocks ÷ INT Clocks ÷ INT ÷ ▪ User-defined HW input pins GPI Status / ÷ INT INT Pins Control n ÷ INT ▪ Two independent SSCG domains ▪ Embedded reference crystal option ▪ Low phase jitter ▪ 175 fs RMS (integer) ▪ 250 fs RMS (fractional) ▪ Multi-profile selection via HW input pins ▪ Excellent PSNR simplifies external filtering ▪ 1.8V – 3.3V operation 26 On-Chip Noise Regulation Ensures Low Jitter Operation
Si5332 PSNR total jitter, 3.3 V , 156.25 MHz, LVDS, 100 mV sine wave noise 1.8V-3.3V Si5332 300 0
250 -20 VDD or VDDO pin 200 -40 1uF 0.1uF
150 -60 Spur (dBc)
RMS RMS (fs) Jitter 100 -80
50 -100 ▪ Extensive on-chip power supply regulation
0 -120 25 50 100 250 500 1000 ▪ Ensures low jitter operation in noisy systems Power supply noise freq (KHz) ▪ Simplifies power supply filtering RMS jitter (fs) Power of spurious tone (dBC) ▪ Only 2 external caps on each VDD/VDDO ▪ IDT requires up to 30 passives for power filtering ▪ TI requires an external LDO and passives
22 Jitter Attenuator Clocks
Si539x Si534x Si532x
RMS Phase Jitter 69 fs 100 fs 230 fs
# Outputs 12 4, 10 6, 8, 12
Output Frequency Range 0.1 – 1028 MHz 0.1 – 1028 MHz 5 – 312.5 MHz
Spread Spectrum No No Yes
HW Input Pins No No Yes LVDS, LVPECL, LVDS, LVPECL, HCSL, LVDS, LVPECL, Output Format HCSL, LVCMOS HCSL, LVCMOS LVCMOS Embedded Xtal Yes No Yes
ClockBuilder Pro Yes Yes Yes Communications, Communications, Target Markets Data center, Industrial Data Center, OTN Industrial 100/200/400G 100/200/400G 25/40/50/100G Target Applications 56G PAM4 SerDes 28G SerDes 10/28G SerDes, PCIe Si539x Jitter Attenuators for 200/400G
Clock Input Output Phase Part Inputs/ Frequency Frequency Jitter Package Number Outputs (MHz) (MHz) (fs RMS) Si5395 4/12 64QFN 9x9mm 0.008 to 0.001 to 4/4 80 44QFN 7x7mm Si5394 750 MHz 1028 MHz Si5392 4/2 44QFN 7x7mm ▪ Up to 12 outputs - ANY combination of output frequencies ▪ 69 fs (int); 150 fs (frac) RMS phase jitter [12kHz -20MHz] ▪ Jitter/wander attenuation (down to 0.1 Hz) ▪ Enhanced input clock hitless switching: 0.2 ns ▪ Status monitoring: LOL, LOS, OOF ▪ 0.1Hz to 4 kHz PLL bandwidth
24 Si5397/96: High Performance Multi-DSPLL Jitter Attenuating Clocks
XTAL/ Clock Input Output Phase REFCLK Part # PLL Inputs/ Frequency Frequency Jitter Package Number DSPLLs Bandwidth Outputs (MHz) (MHz) (fs RMS) XA XB 44QFN Si5396 2 4 / 4 0.008 0.001 0.1 Hz 7x7mm OSC to to 90 to 64QFN Si5397 4 4 / 8 or 4 750 1028 4 kHz 9x9mm
÷INT OUT0 ▪ Two or four independent timing paths ÷INT DSPLL OUT1 ▪ ANY input frequency to ANY output frequency per DSPLL IN0 ÷FRAC A ÷INT OUT2 Si ▪ Ultra-low 90fs RMS phase jitter [12kHz -20MHz] DSPLL 5396 IN1 ÷FRAC B ÷INT OUT3 ▪ Enhanced hitless switching: 0.2 ns phase transient
÷INT ▪ Frequency-on-the-fly IN2 ÷FRAC DSPLL OUT4 C ▪ Change DSPLL input/output frequency or loop bandwidth ÷INT OUT5 IN3 ÷FRAC DSPLL ▪ Does not impact other DSPLLs D ÷INT OUT6
Si ▪ Holdover operation with user-defined input clock history NVM 5397 ÷INT OUT7 ▪ Free-run, locked, holdover, definable status monitoring: LOL, LOS,
I2C/SPI OOF ▪ Control/ Drop-in compatible with Si5347/46 Status Universal and Standard Format Buffers Si533xx Universal Clock Buffers
Universal Clock Buffer Features Bank A ▪ ANY format in/out translation DIV ▪ Ultra-low additive jitter Input Output Clocks Bank B Clocks ▪ Integrated muxes, dividers, level shifters DIV ▪ Simplified clock distribution
Multi-Format Pin Drivers
Applications Communications Audio/Video Industrial Ethernet Embedded Mil/Aero
41 Universal Format Translation
Any Input Clock Format Any Output Clock Format (1.8, 2.5, 3.3 V) (1.8, 2.5, 3.3 V) LVPECL LVPECL LVDS LVDS CML CML HCSL HCSL LVCMOS LVCMOS
Universal format translation Pin configurability benefits ▪ Two independent output banks with individual format ▪ Single device reusable across multiple designs selection ▪ Replaces multiple fixed-format buffers ▪ On-chip voltage translation (independent core VDD and ▪ Easily accommodates PCB design changes output bank VDDO)
42 High Performance Si533xx Clock Buffers
Universal LVPECL LVDS Inputs Outputs Package Inputs Outputs Package Inputs Outputs Package Buffer Buffer Buffer Si53301-B-GM 2 6 Diff / 12 SE Q32FN Si53320-B-GT 2 5 Diff 20TSSOP Si53340-B-GM 2 4 Diff 16QFN Si53302-B-GM 2 10 Diff / 20 SE Q44FN Si53321-B-GM 2 10 Diff Q32FN Si53341-B-GM 2 4 Diff 16QFN Si53303-B-GM 1 5 Diff / 10 SE Q44FN Si53321-B-GQ 2 10 Diff 32LQFP Si53342-B-GM 2 6 Diff Q24FN Si53304-B-GM 2 6 Diff / 12 SE Q32FN Si53322-B-GM 1 2 Diff 16QFN Si53343-B-GM 2 6 Diff Q24FN Si53305-B-GM 2 10 Diff / 20 SE Q44FN Si53323-B-GM 2 4 Diff 16QFN Si53344-B-GM 2 10 Diff Q32FN Si53306-B-GM 1 4 Diff / 8 SE 16QFN Si53325-B-GM 1 5 Diff Q32FN Si53345-B-GM 2 10 Diff Q32FN Si53307-B-GM 2 2 Diff / 4 SE 16QFN Si53325-B-GQ 1 5 Diff 32LQFP LVCMOS Si53308-B-GM 1 3 Diff / 6 SE Q32FN Si53326-B-GM 2 10 Diff Q32FN Inputs Outputs Package Si53311-B-GM 2 6 Diff / 12 SE Q32FN Si53327-B-GM 2 6 Diff Q24FN Buffer Si53312-B-GM 2 10 Diff / 20 SE Q44FN Si53328-B-GM 2 6 Diff Q24FN Si53360-B-GT 2 8 SE 16TSSOP Si53313-B-GM 1 5 Diff / 10 SE Q44FN Si53361-B-GM 2 8 SE 16QFN Si53314-B-GM 2 6 Diff / 12 SE Q32FN Si53362-B-GM 2 12 SE Q24FN Si53315-B-GM 2 10 Diff / 20 SE Q44FN Si53365-B-GT 1 8 SE 16TSSOP
44 PCI-Express Clocks and Buffers 31 PCIe Clocks and Buffers
Clock Gens Clock Buffers Si522xx Si5332 Si5214x Si5211x Si532xx Si5315x Si5311x Si53102 PCIe Gen 4/5 Gen 4/5 Gen1/2/3 Gen1/2/3 Gen 4/5 Gen1/2/3/4 Gen1/2/3 Gen1/2/3 Compliance VDD 1.5 – 1.8 V 1.8 – 3.3 V 2.5 – 3.3 V 2.5 – 3.3 V 1.5 – 1.8 V 2.5 – 3.3 V 2.5 – 3.3 V 2.5 – 3.3 V
# Outputs 2, 4, 8, 12 6, 8, 12 2, 5, 4, 6, 9 1, 2 4, 8, 12 2, 4, 6, 9 6, 8, 15, 19 2
Internal 85, 100 Ω 85, 100 Ω 100 Ω 100 Ω 85, 100 Ω 100 Ω 85, 100 Ω 100 Ω Output Impedance Individual OE Yes Yes Selected No Yes Selected No No Pin Control I2C Control Yes Yes Yes No Yes Yes Yes No
Smallest 3 x 3 mm 5 x 5 mm 4 x 4 mm 1.4 x 1.6 mm 5 x 5 mm 4 x 4 mm 5 x 5 mm 1.4 x 1.6 mm package Target Servers, Servers, Datacenters, Tbolt2/3, Servers, Datacenters, Servers – Storage, Applications Datacenters, Datacenters, Storage, Digital Datacenters, Storage, DB800, Access NIC, Add-on Storage Tbolt2/3, MFP camera/video, NIC, Add-on Tbolt2/3, MFP DB1x00 Points, MFP Cards, DSC Add-on cards, Cards, DSC NIC 3 2 PCIe Gen1/2/3/4/5 Clock Generators
PCIe PCIe Si522xx Clock Output Family Gen4 Gen5 Power Package Outputs Frequency Jitter Jitter OSC REF 20-QFN 100, 133, Si522xx 2/4/8/12 241 fs 110 fs 1.5 - 1.8V 32-QFN 200 MHz OEbn 40-QFN PLL SSCG ON Control Outputs 32-QFN (w/SSC) VDD_IO Si5332 6/8/12 100MHz 48 fs 48 fs 1.8 - 3.3V 40-QFN 48-QFN
▪ Fully compliant with PCIe Gen 1/2/3/4/5 Si5332 ▪ <300fs RMS phase jitter, >60% margin to max spec ▪ HCSL drivers with integrated termination
OSC PLL OEbn (w/SSC) ▪ Spread spectrum for EMI reduction Outputs VDD_IO CLKIN ▪ Individual output enable
SSCG ON Control ▪ Mux Input option SEL 3 3 PCIe Gen1/2/3/4/5 Clock Buffers
Si532xx Clock Input/Output Additive Family Power Package OE0 Outputs Frequency Jitter 32-QFN OUT0 Si532xx 4/8/12 100 MHz 40 fs 1.5 – 1.8V 40-QFN OE1 32-QFN OUT1 Si5332 6/8/12 100 MHz 36 fs 1.8 – 3.3V 40-QFN CLKIN OE2 48-QFN OUT2 OE3 OUT3 ▪ Fully compliant with PCIe Gen 1/2/3/4/5 ▪ <100fs RMS additive phase jitter Si5332 OE0 ▪ HCSL drivers with integrated termination OUT0 ▪ Spread spectrum pass through OE1 CLKIN OUT1 ▪ Individual output enable OE2 CLKIN OUT2 ▪ Mux input option OE3 SEL OUT3 PCIe Clock Jitter Tool
▪ Greatly simplifies PCIe clock jitter measurements ▪ Simply upload a waveform file ▪ Easy to read results summary ▪ Includes Gen4/5 filters specified by PCI-SIG ▪ Download here: PCIe Learning Center
34 Automotive Grade Timing 36 AEC-Q100 Qualified Timing Product Family
CLOCK GENERATORS CLOCK BUFFERS PCIE CLOCKS PCIE BUFFERS
6/8/12-Output Options 2/4/8/10-Output Options 4/8-Output Options 4/8-Output Options 230fs RMS Phase Jitter 120fs RMS Additive Jitter Gen1/2/3/4/5 PCIe Gen1/2/3/4/5 Custom Programmable Custom Programmable
Clock Tree Consolidation Loss of Signal (LOS) Monitor 85/100Ω Internal Termination 85/100Ω Internal Termination Functional Safety Features Level/Format Translation Spread Spectrum Modulation Loss of Signal (LOS) Monitor Applications
NETWORKING ADAS / AUTONOMOUS VEHICLE IVI / INTEGRATED COCKPIT
• SoC/Processor • SoC/FPGA/CPU • Audio sampling • Ethernet PHY • PCIe Gen3/4/5 and/or NVLink • SoC/DSP • Ethernet PHY • PCIe Gen3/4 • System functions • USB/connectivity
37 Reduce Points Of Failure, Increase Reliability
▪ Quartz crystals and oscillators are susceptible to shock and vibration effects ▪ Each quartz component is a potential point of failure ▪ Migrating to a silicon timing solution reduces points of failure, decreases DPPM, and provides numerous other features and benefits Existing Solution Silicon Labs ▪ Clock tree example: Crystal FIT rate 4 x 1.43 = 5.72 1 x 1.43 = 1.43 ▪ 4 crystals Oscillator FIT rate 4 x 4.77 = 19.08 ▪ 2 LVCMOS oscillators IC FIT rate 1 x 1.6 = 1.6 1 x 1.6 = 1.6 ▪ 2 differential oscillators ▪ 1 differential fanout buffer Total FIT rate 26.4 3.03 DPPM/yr 23.1 2.6
38 Si5332-AM Any-Frequency Clock Generators
No. of Clock Input Output Phase # Control Package Outputs Frequency Frequency Jitter Pins 32-QFN 10 to 10 to 333 6 / 8 / 12 230 5 / 7 / 7 40-QFN 170 MHz MHz 48-QFN ▪ Generates any mix of output frequencies/formats ▪ Low phase jitter ▪ 190 fs RMS (integer)→60% lower than competing solutions ▪ 250 fs RMS (fractional) ▪ HCSL, LVDS, LVPECL, LVCMOS formats ▪ PCIe Gen1/2/3/4/5 compliant ▪ Best-in-class PSNR simplifies external power filtering ▪ User-configurable HW input pins ▪ Frequency select, SSC, OE control, Loss of Signal (LOS) ▪ Two independent SSCG domains (down/center) PCIe Gen1/2/3/4/5 Clock Generators & Buffers
PCIe Clock Input Output PCIe Device Voltage Package Outputs Frequency Frequency Gen4 Jitter
Si5225x 100, 133, 32-QFN 4/8 25 MHz 200 fs 1.8-3.3 V Clocks 200 MHz 40-QFN
Si5325x 36 fs 32-QFN 4/8 100 MHz 100 MHz 1.8-3.3 V Buffers Additive 40-QFN
▪ Fully compliant with PCIe Gen 1/2/3/4/5 ▪ Clocks: <200 fs Gen4 RMS phase jitter ▪ Buffers: <40 fs Gen4 Additive RMS phase jitter ▪ HCSL drivers with integrated termination ▪ Selectable 85/100 Ω impedance ▪ Spread spectrum for EMI reduction ▪ Individual output enable pins ▪ Dual input option for redundancy
40 Si5335x Clock Buffers
# of Clock Frequency Output Additive Family Type Voltage Package Outputs Range Format Jitter
Si5335xA Fixed LVCMOS, 32-QFN 10 to LVPECL 4 / 8 /10 110 fs 1.8-3.3 V 40-QFN 333 MHz LVDS Custom 48-QFN Si5335xB HCSL (CBPro)
▪ Single-ended and differential input/outputs ▪ Ultra-low additive jitter (120 fs RMS) ▪ Individual output enable pins ▪ Customize through ClockBuilder Pro ▪ Voltage translation ▪ Individually programmable output drivers (format translation) ▪ Output dividers (1-63) ▪ Loss of Signal (LOS)
41 Network Synchronizers IEEE 1588 Silicon Labs Acquires Qulsar’s IEEE 1588 Modules and Software
▪ Accelerates Silicon Labs’ vision of simplifying customer design and adoption of IEEE 1588 ▪ Expands net sync portfolio w/plug-and-play IEEE 1588 modules and software ▪ Enables us to address more opportunities in wireless, communications, data center, industrial
43 Silicon Labs IEEE 1588 / SyncE Solutions
Si5348/83/84 ▪ Highly integrated SyncE/IEEE 1588 clock IC for customers with their own IEEE 1588 software Network ▪ Up to 3 independent DSPLLs supporting SyncE, IEEE 1588 and general-purpose clocking Synchronization Clocks ▪ Any DSPLL can operate as PTP DCO w/1 ppt tuning resolution
Si5388/89 Network ▪ Highly integrated SyncE/IEEE 1588 clock IC and software solution for compact switches/routers Synchronization ▪ Supports T-BC & T-TSC modes; fully ITU G.8262/8262.1/8261/8272.3 standards compliant Clocks with ▪ Embedded MCU runs PTP servo software, PTP stack runs on system host processor AccuTime Software
M6x/M8x ▪ Complete SyncE/IEEE 1588 hardware and software solution IEEE 1588 ▪ Plug-and-play solution for fast time to market Modules ▪ Directly connects to 1G Ethernet PHY on system board
AccuTime ▪ Software-only solutions for 4G small cells IEEE 1588 ▪ Targeted at Intel and Qualcomm SoC-based systems adhering to vendor reference design Software
44 IEEE 1588 Standards-Compliant Solutions
▪ IEEE 1588-2008 PTP equipment clock specification support ▪ ITU-T G.8273.2 T-BC, T-BC-P, T-TSC ▪ ITU-T G.8262 (SyncE) EEC Options 1 & 2 ▪ ITU-T G.8262.1 (Enhanced SyncE) eEEC ▪ ITU-T G.8261 ▪ ITU-T G.812 Type III, IV ▪ ITU-T G.813 Option 1 ▪ Telcordia GR-1244, GR-253 (Stratum-3/3E) ▪ PTP profile support ▪ ITU-T G.8275.1 – Telecom profile for phase with full timing support networks ▪ ITU-T G.8275.2 – Telecom profile for phase with partial timing support networks ▪ ITU-T G.8265.1 Telecom profile for frequency synchronization ▪ Compliance reports available upon request
45 High Performance IEEE 1588 Servo Mitigates PDV Effects
▪ ITU.G.8261 used to test IEEE 1588 under network load conditions ▪ Simulates network congestion load ▪ Time Deviation (TDEV) measures network wander noise ▪ AccuTimeTM servo algorithm supports statistical packet selection ▪ Dynamically adjusts to changing network load conditions to mitigate PDV effects ▪ Open-source LinuxPTP4L servo uses simple PI controller ▪ No added intelligence for varying network conditions, only the PI K-constants can be adjusted
Full suite of Calnex equipment for compliance testing >$1M investment for compliance test
46 Silicon Labs vs LinuxPTP 1PPS TDEV Performance Comparison
Silicon Labs Servo LinuxPTP Servo Passes G.8261 Fails G.8261 Requirements Requirements
Margin to Spec Limit
Exceeds Spec Limit
Full compliance reports available upon request
47 Si5348/83 Low Jitter Network Synchronizers
Clock Input Output Phase Part # PLL Inputs/ Frequency Frequency Jitter Package Number DSPLLs Bandwidth APPLICATIONS Outputs (MHz) (MHz) (fs RMS) 8 kHz to 750 64-QFN Si5348 ▪ IEEE 1588 ▪ Switches and routers 3 DIFF + 2 MHz 1 PPS to 1 mHz – 9x9mm 3 150 SE / 7 DIFF 1 PPS, 8 kHz 718.5 MHz 4 kHz 56-LGA Si5383 ▪ Synchronous Ethernet ▪ 5G wireless to 750 MHz 8x8mm
XTAL OCXO/ TCXO FEATURES XB XA REF
OSC Si5348/83 ▪ Usable in conjunction with customers own IEEE 1588 software ▪ 3 independent, fully flexible any-rate DSPLLs ▪ Any DSPLL can operate as DCO w/1 ppt tuning resolution ÷ OUT DSPLL* ▪ Low jitter: 150 fs RMS 12kHz – 20MHz IN* ÷ DCO ÷ OUT
IN* ÷ ÷ OUT ▪ Hitless reference switching: <0.2 ns (typ) DSPLL ÷ OUT ▪ Short-term holdover operation with user-defined input clock history IN ÷ DCO ÷ OUT ▪ Programmable start-up configuration IN ÷ ÷ OUT IN DSPLL ▪ Si5383 supports 1 PPS for GPS ÷ DSPLL A ÷ OUT DCO ▪ TCXO/OCXO reference input with embedded jitter cleaning ▪ Comprehensive alarm/status monitors: LOL, LOS, OOF I2C/ Control/ SPI Status ▪ Programmable format per output: LVPECL, LVDS, HCSL, LVCMOS ▪ Standards-compliant: G.8262, G.8262.1, G.812, G.813 DSPLL* selects from IN* or IN DSPLL selects from IN only
48 Si5388/89 Network Synchronizers w/IEEE 1588 AccuTime Software
Clock Input Output Phase Part # PLL Inputs/ Frequency Frequency Jitter Package Number DSPLLs Bandwidth APPLICATIONS Outputs (MHz) (MHz) (fs RMS) Si5388 2 3 DIFF + 1 PPS, 8 ▪ ▪ 1 PPS to 1 mHz – 64-QFN Pizza box switches/routers 5G RAN 2 SE / 8 kHz to 750 120 718.5 MHz 4 kHz 9x9mm Si5389 3 DIFF MHz ▪ Synchronous Ethernet ▪ Small cells
XTAL OCXO/ TCXO FEATURES XB XA REF ▪ Silicon Labs IEEE 1588 AccuTime Software OSC Si5388/89 ▪ Embedded MCU running IEEE 1588 servo software ▪ 1588 Stack runs on customer’s host processor ▪ Software API for initialization, control and debug ÷ OUT DSPLL* ▪ 2 or 3 independent, fully flexible any-rate DSPLLs IN* ÷ DCO ÷ OUT ▪ Each DSPLL can operate as DCO w/1 ppt tuning resolution IN* ÷ ÷ OUT DSPLL ▪ Low jitter: 120 fs RMS, 12kHz – 20MHz ÷ OUT IN ÷ DCO ▪ Synchronizes to 1PPS or SyncE input ÷ OUT IN ÷ Si5388 ▪ Hitless reference switching: 0.2 ns (typ) ÷ OUT IN DSPLL ÷ DSPLL OUT ▪ Short-term holdover operation with user-defined input clock history DCOA ÷ ▪ Programmable start-up configuration ÷ OUT Si5389 ▪ TCXO/OCXO reference input with embedded jitter cleaning MCU I2C/ Control/ 1588 ▪ Comprehensive alarm/status monitors: LOL, LOS, OOF SPI Status Servo Loop ▪ Standards-compliant: G.8262, G.8262.1, G.8261, G.8273, G.812, G.813 DSPLL* selects from IN* or IN DSPLL selects from IN only ▪ T-BC, T-BC-P, and T-TSC operating modes
49 Application Example: “Pizza Box” Switch/Router & 5G T-BC/T-TSC
▪ Si5388/89 is a single IC IEEE 1588 + SyncE solution
Ethernet PHY (10G, 25G) Si5388/89 Network Sync Clock ▪ One DSPLL operates as IEEE 1588 DCO to steer 1588 System Reference Clock the time stamp clocks IEEE 1588 Time Stamp Unit DSPLL DCO 1588 1PPS ▪ One DSPLL operates as G.8262 SyncE jitter attenuator Host Processor ▪ Locks to RX SyncE clock SGMII IEEE 1588 DCO MAC Commands ▪ Supports hitless switching, holdover, jitter filtering 1588 Packets ▪ Generates ultra-low jitter reference for TX SyncE clock 1588 Time Silicon Labs Stamp Data Silicon Labs IEEE 1588 Servo IEEE 1588 Stack ▪ Servo controller communicates with IEEE 1588
Algorithm Si5388-SW stack SyncE Jitter cleaned RX Jitter cleaned Clock SyncE
SyncE Filtered TX Clock XMT G.8262 SyncE DSPLL CDR “Pizza Box” Switch/Router SyncE Filtered RX Clock “Pizza Box” 5G T-BC/T-TSC T-BC: Telecom Boundary Clock T-TSC: Telecom Time Slave Clock
50 Si5388/89 Xilinx Zynq Ultrascale+ MPSoC/RFSoC 1588 Reference Design
Xilinx® Zynq® Ultrascale+ ▪ Clock solution is optimized for entire Zynq family MPSoC ▪ Si5389 Network Synchronizer ZCU102 TCXO or ARM ® ▪ OCXO XTAL Processor Provides all IEEE 1588 and PHY clocks XTAL TM Silicon Labs ▪ AccuTime 1588 servo SW internal to Si5389 1588 SW 26MHz LVDS CLK SPI Silicon Labs Stack GTR_REF_CLK_USB3 1588 SW TM 27MHz LVDS CLK ▪ AccuTime IEEE 1588 Software Stack Servo GTR_REF_CLK_DP 33.33MHz LVCMOS CLK TM 390.625MHz → 25G GTH – MPSoC PS_REF_CLK ▪ AccuTime stack sw runs on host processor 156.25MHz → 10G GTY – RFSoC Clean_SyncE_CLK Si5389 Master PHY 100MHz LVDS CLK Si5341 ▪ Easily portable to any Xilinx Zynq family member GTR_REF_CLK_PCIe Clock Network 125MHz LVDS CLK Synchronizer GTH – MPSoC GTR_REF_CLK_SATA Generator ▪ Si5386 Wireless Clock (RFSoC-only) 390.625MHz → 25G GTY – RFSoC 125MHz LVDS CLK Clock 156.25MHz → 10G CLK_125 Recovered_SyncE_CLK Slave PHY Optional ▪ Provides clocks for RF ADCs and DACs
156.25MHz LVDS CLK CLK_156 ▪ Supports up to 5 independent clock domains 500MHz PTP_SYS_CLK 300MHz LVDS CLK TOD GTR_REF_CLK_DDR4 ▪ 1PPS Eliminates discrete VCXO and loop filter ▪ Si5341 Clock Generator (both MPSoC & RFSoC) 500MHz RFSoC PTP_REF_CLK ▪ Provides all general purpose clocks XO ZCU111 PL_SYSREF_FPGA LVDS Air Interface ▪ Multiple product options to meet customer needs PL_FPGA_REFCLK_OUT LVDS Si5386 RF SYSREF_RFSOC ADCs/DACs ® LVDS Wireless (RFSoC Only) ADC_RF_CLK Clock LVDS DAC_RF_CLK LVDS
51 IEEE 1588 Reference Design Loaner Program
▪ Turnkey solution simplifies evaluation ▪ Easy to follow instructions Silicon Labs Solution • Si5389 FMC w integrated 1588 servo SW ▪ Configurable solution for all Xilinx Zynq Ultrascale+ MPSoC and RFSoC • 4x 10Gbe optical transceivers devices • SD Memory card w SW + 1588 Stack SW Xilinx Zynq UltraScale+ MPSoC • Fiber and SMA Cables ZCU102 Evaluation Kit • Documentation ▪ Silicon Labs 1588 servo algorithm supports statistical packet selection • Tech support to get solution running ▪ Dynamically adjusts to changing network load conditions to mitigate PDV
ZCU102 effects need to pass ITU-T G.8261 test case and remain standards compliant. ▪ LinuxPTP will not pass all G.8261 standards compliance tests ▪ 1588 Class C compliant solution (+/-10ns) ▪ Targeting Pizza Box Designs ▪ Telecom Boundary Clock (T-BC) Si5389 FMC ▪ Telecom Time Slave Clock (T-TSC) ▪ Configurable using CBPro and CLI software ▪ Frequency Plan ▪ Features and Settings
Silicon Labs + Xilinx Loaner Solution
52 IEEE 1588 / SyncE Modules
M88 ▪ M68 + SyncE support ▪ Frequency assist mode ▪ HW-accelerated PTP master M68 ▪ M64 + Boundary Clock ▪ 32, 128 or 256 unicast slaves ▪ GNSS and PTP input M64 ▪ IEEE 1588-only ▪ 29x29mm LGA-144 ▪ G.8273.4 APTS support ▪ Master/Slave operation ▪ Drop-in compatible w/M64 ▪ Up to 10 unicast slaves ▪ 29x29mm LGA-84
Common Features ▪ Turnkey solution – reduces time to market ▪ Standards-compliant ▪ All real-time 1588 processing on module ▪ Phase sync better than ±1 µs* ▪ Wire-speed GbE passthrough eliminates ▪ Frequency accuracy better than ±10 ppb* dedicated switch port ▪ Field-upgradable
* 10-switch Carrier Ethernet network (G.8261). Limits: ±1.1 µs and ±16 ppb.
53 IEEE 1588 Module Selection Guide
PTP & Clock Functions Network Interfaces Reference Standards Operating # Unicast 10Base-T Frequency Physical Performance Boundary Slaves Clock Clock 100Base-TX Ethernet Compliance Temp Master Slave Assist Layer RGMII Oscillator Type Clock (16, 128 Inputs Outputs 1000Base-T Passthrough1 Mode Clocking pkts/sec) PHY
Voltage ±1 usec3 M64 ✓ ✓ - - - 10, 1 - - 1 1 ✓ G.8265.1 -40C - 85C Controlled ±10 ppb3
PPS,TOD GNSS Voltage ±1 usec3 M68 ✓ ✓ ✓ - - 10, 1 5/10/20 1 1 ✓ G.8265.1 -40C - 85C PTP Controlled ±10 ppb3 /25MHz
PPS,TOD G.8265.1 GNSS SyncE 5 low G.8275.1 32, 128, PTP Fixed ±1 usec3 M88 ✓ ✓ ✓ ✓ PDH jitter - 2 ✓ G.8275.2 draft -40C - 85C 256 SyncE Frequency2 ±10 ppb3 HW SDH prog. G.8273.2 BITS accelerated outputs G.8262
1. Wire-speed Ethernet passthrough enables bump-on-a-wire operation, eliminating need for dedicated switch port 2. Contact Qulsar for availability of voltage-controlled oscillator support for M88 3. Phase/frequency performance measured on a 10-switch Carrier Ethernet network using G.8261 PTP-only test conditions. Application target limits are ±1.1 usec and ±16 ppb. IEEE 1588 Software for Small Cells
FSM9016 Silicon Labs SyncMgr Software Qualcomm Software ▪ For Intel Transcede T2xxx / T3xxx & Qualcomm FSM9016 / FSM9955 platforms Hardware MAC IEEE 1588 Ethernet Timestamping Software ▪ Enables RF reference frequency & ToD to be sourced from remote Grandmaster Unit TFCS Server ▪ No need for local GNSS receiver – reduces cost & installation expenses
Disciplined ▪ Enhanced failover & resilient performance when combined with GNSS Clock to RF Stage ▪ Compatible with vendor reference designs IEEE 1588 Servo ▪ Superior performance with real-world networks User Space ▪ Better than 5 ppb frequency accuracy and 1.5 µs time alignment with low-cost TCXO IEEE 1588 Stack ▪ Unicast and multicast operation with one and two-step masters ▪ Compatible with boundary clock, transparent clock and non-PTP aware networks OpenWRT Kernel Kernel Space ▪ Full support of telecom G.8265, G.8275.1 & G.8275.2 profiles Transcede Silicon Labs DAC T21xx BSP Updates interface
▪ Supports ARM-based CPUs running Linux DAC, Hardware Ethernet MAC & PHY filter & ▪ With option for other architectures and OSes VCTCXO
Silicon Labs Software Components Software will be ported to new high-volume SoCs in the future
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