Reducing Development Risks in Communications Applications with High-Performance Oscillators. by James Wilson

Next wave in timing innovation Reducing development risks in communications applications with high-performance oscillators. By James Wilson.

s optical networks, hyperscale In addition, 56G PAM4 PHYs, offer any-frequency synthesis, ultra-low data centres and mobile 100G/200G/400G Ethernet, and jitter of 80fs rms and are available in A fronthaul/backhaul networks 100G/400G OTN require a more standard, small form factor oscillator move to higher data rates to support diverse mix of frequencies, increasing footprints. By providing best-in-class rapidly increasing Internet traffic timing complexity. jitter margin and frequency flexibility, demands, SerDes reference clock The Si54x Ultra Series of oscillator the Ultra series is intended to make it performance is becoming increasingly products from Silicon Labs is easy for hardware designers to de-risk important. purpose-built to address the needs product development. If reference clock jitter is too high, of these demanding high-speed The device can be programmed it results in unacceptably high system communications and data centre and customised to meet the target bit-error rate (BER), lost traffic or loss applications. frequency during outgoing test and, of system communication. These high-performance oscillators by using this approach, the Si54x can be mass customised in order to meet High-speed communications and data centre timing requirements each customer’s requirements. The Si54x Ultra series supports Target Reference clock any frequency from 200kHz to 1.5GHz, Standard Data Rate frequencies max phase jitter* enabling a single product family to support both standard and custom CEI-28G 28Gbit/s 106.25MHz 150fs frequency applications. CEI-56G PAM4 56Gbit/s 125.00MHz 150fs Designed in 55nm CMOS technology, the fourth generation 100G Ethernet 4x25.8Gbit/s 156.25MHz 180fs DSPLL leverages a highly digital CAUI-4 4x25.8Gbit/s 161.13281MHz 240fs architecture to deliver improved 16G Fibre Channel 14.0Gbit/s 175MHz 240fs frequency flexibility and jitter performance. 32G Fibre Channel 25.6Gbit/s 200MHz 130fs The input to the DSPLL’s phase Infiniband EDR 25.8Gbit/s 322.265625MHz 180fs Author profile: detector is converted from analogue to James Wilson digital, enabling the DSPLL to operate Rapid IO-4 25.3125Gbit/s 644.53125MHz 290fs is marketing entirely in the digital domain and SONET OC-192 9.953Gbit/s 240fs director, timing this all-digital approach has multiple products, with benefits for the design engineer. *Note: Calculated directly from reference clock or transmitter eye closure specifications budgeting eye closure 50/50 deterministic/rms and 33%/67% clock/transmitter per raw (pre-FEC) BER requirements. Adobestock Silicon Labs First, the digitally controlled

www.newelectronics.co.uk 9 January 2018 25 SYSTEM DESIGN FREQUENCY MANAGEMENT

oscillator (DCO) can be precisely To further simplify device • Support multi-protocol SerDes with steered with a step size as small evaluation, Silicon Labs also offers single device as 1ppb to track out phase delay an XO phase noise lookup utility that • Simplified set up/hold time testing between the reference and feedback can be used to retrieve more than • Frequency margining (for example, clocks. The DCO gain is small, making 1000 measured phase noise plots 156.25MHz +50 ppm, 156.25MHz, the circuit less susceptible to noise of oscillators across a wide range of 156.25MHz -50 ppm) than conventional analogue PLLs. popular frequencies. • Simplified prototyping. Testing new Secondly, the DSPLL supports an SerDes and ASICs with a variety innovative phase error cancellation Integrated power supply noise of reference clocks using a multi circuit that uses advanced digital regulation frequency oscillator. Transition to a signal processing to remove PLL The DSPLL also comes with an fixed, single frequency oscillator once noise due to delay, non-linearity, and extensive network of on-chip low drop the final frequency is selected. temperature effects. out regulators to provide power supply These architectural features ensure noise rejection, ensuring consistently Wide range of format options consistent device performance across low jitter operation even in noisy Silicon Labs’ Ultra Series oscillators process, voltage and temperature system environments. have a flexible output driver that can and, as a result, Silicon Labs’ fourth Another benefit of integrated power be factory customised to support any generation DSPLL architecture delivers supply noise regulation is simplified common signalling format, including ultra low jitter across the entire power supply filtering, PCB design and LVDS, LVPECL, HCSL, CML, CMOS operating range. layout. and dual CMOS. When it comes to jitter In addition, the output driver performance versus operating Multi-frequency support supports a wide supply voltage range. frequency and temperature, the Ultra In addition to standard single A single Si54x device can support series comes with two performance frequency oscillators, dual and quad 1.8V to 3.3V operation, enabling a grades. Si545/6/7 devices provide frequency oscillators leveraging single part number to replace multiple a typical phase jitter performance of Silicon Labs’ DSPLL architecture are fixed voltage 1.8V, 2.5V and 3.3V 80fs rms (12kHz to 20MHz), whereas available. These devices can replace oscillators. Si540/1/2 devices provide a typical two or more discrete oscillators with As the demand for oscillators jitter performance of 125fs rms a single IC, helping to minimise both grows so manufacturers are looking (12kHz to 20MHz). Given their jitter Below: The Ultra BOM cost and complexity. to offer a one-stop shop for high performance, the Si54x has been series DSPLL Multiple benefits are offered by multi- performance oscillators to meet the designed to maximise jitter margin. architecture frequency oscillators, including: needs of design engineers.

Fixed frequency frequency crystal flexible DSPLL Low noise DCO driver OSC digital phase error digital phase cancellation loop filter detector

fractional Flexible formats, divider 1.8 to 3.3V NVM operation

control power supply regulation

Frequency select Built-in power supply (pin control) noise rejection

26 9 January 2018 www.newelectronics.co.uk