Chapter 3 Digital Logic Structures

Transistor: Building Block of Computers Microprocessors contain millions of transistors • Intel Pentium 4 (2000): 48 million • IBM PowerPC 750FX (2002): 38 million Chapter 3 • IBM/Apple PowerPC G5 (2003): 58 million Digital Logic Logically, each transistor acts as a switch Combined to implement logic functions Structures • AND, OR, NOT Combined to build higher-level structures • Adder, multiplexer, decoder, register, … Based on slides © McGraw-Hill Additional material © 2004/2005 Lewis/Martin Combined to build processor • LC-3 CSE 240 3-2 How do we represent data in a computer? A Transistor Analogy: Computing with Air At the lowest level, a computer has electronic “plumbing” Use air pressure to encode values • Operates by controlling the flow of electrons • High pressure represents a “1” (blow) • Low pressure represents a “0” (suck) Easy to recognize two conditions: Valve can allow or disallow the flow of air 1. Presence of a voltage – we’ll call this state “1” • Two types of valves 2. Absence of a voltage – we’ll call this state “0” N-Valve P-Valve Low (Off) Low (On) Computer use transistors as switches to manipulate bits • Before transistors: tubes, electro-mechanical relays (pre 1950s) hole • Mechanical adders (punch cards, gears) as far back as mid-1600s Before describing transistors, we present an analogy… High (On) High (Off) CSE 240 3-3 CSE 240 3-4 1 Pressure Inverter Pressure Inverter (Low to High) High High P-Valve P-Valve In Out Low High N-Valve N-Valve Low Low CSE 240 3-5 CSE 240 3-6 Pressure Inverter Pressure Inverter (High to Low) High High P-Valve P-Valve High Low N-Valve N-Valve Low Low CSE 240 3-7 CSE 240 3-8 2 Analogy Explained Transistors as Switches Pressure differential → electrical potential (voltage) • Air molecules → electrons Two types N-Valve N-MOSFET • High pressure → high voltage • N-type • Low pressure → low voltage • P-type Air flow → electrical current Properties • Pipes → wires • Solid state (no moving parts) P-Valve P-MOSFET • Air only flows from high to low pressure • Reliable (low failure rate) • Electrons only flow from high to low voltage • Small (90nm channel length) • Flow only occurs when changing from 1 to 0 or 0 to 1 • Fast (<0.1ns switch latency) Valve → transistor • The transistor: one of the century’s most important inventions CSE 240 3-9 CSE 240 3-10 MOS + FET N-type MOS Transistor gate insulator • When Gate has positive voltage, source drain short circuit between #1 and #2 channel (switch closed) (cross-section view of a MOSFET) • When Gate has zero voltage, MOS: three materials needed to make a transistor open circuit between #1 and #2 (switch open) • Metal (Al, W, Cu): conductor • Oxide (SiO ): insulator 2 Gate = 1 • Semiconductor (doped Si): conducts under certain conditions FET: field effect (the mechanism) transistor • Voltage on gate: current flows source to drain (transistor on) • No voltage on gate: no current (transistor off) Gate = 0 Terminal #2 connected Recall, two types of MOSFET: n and p to GROUND (0V). CSE 240 3-11 CSE 240 3-12 3 P-type MOS Transistor Inverter (NOT Gate) P-type is complementary to n-type Power • When Gate has positive voltage, open circuit between #1 and #2 (switch open) • When Gate has zero voltage, short circuit between #1 and #2 (switch closed) Gate = 1 Truth table Ground In Out 0 1 Terminal #1 connected Gate = 0 to POWER 1 0 (in this example, +2.9V) CSE 240 3-13 CSE 240 3-14 CMOS Circuit NAND Gate (NOT-AND) Inverter is an example of Complementary MOS (CMOS) Power Uses both n-type and p-type MOS transistors • p-type Attached to POWER (high voltage) Pulls output voltage UP when input is zero • n-type Attached to GROUND (low voltage) Pulls output voltage DOWN when input is one A B C For all inputs, make sure that output is either connected to GROUND 0 0 1 or to POWER, but not both! (why?) 0 1 1 1 0 1 Ground 1 1 0 CSE 240 3-15 CSE 240 Note: Parallel structure on top, serial on bottom. 3-16 4 AND Gate NOR Gate (NOT-OR) A B C Power 0 0 0 Power 0 1 0 1 0 0 1 1 1 A B C 0 0 1 0 1 0 Add inverter to NAND. 1 0 0 Ground Ground 1 1 0 CSE 240 3-17 CSE 240 Note: Serial structure on top, parallel on bottom. 3-18 OR Gate Basic Gates A B C Power From Now On… Gates 0 0 0 • Covered transistors mostly so that you know they exist 0 1 1 • Note: “Logic Gate” not related to “Gate” of transistors 1 0 1 Will study implementation in terms of gates 1 1 1 • Circuits that implement Boolean functions NOT/INV NAND AND NOR OR More complicated gates from transistors possible Ground Add inverter to NOR. • XOR, Multiple-input AND-OR-Invert (AOI) gates CSE 240 3-19 CSE 240 3-20 5 More than 2 Inputs? Visual Shorthand for Multi-bit Gates AND/OR can take any number of inputs Use a cross-hatch mark to group wires • AND = 1 if all inputs are 1 • Example: calculate the AND of a pair of 4-bit numbers • OR = 1 if any input is 1 • A3 is “high-order” or “most-significant” bit • Similar for NAND/NOR • If “A” is 1000, then A3 = 1, A2 = 0, A1 = 0, A0 = 0 Implementation • Multiple two-input gates or single CMOS circuit A0 Out0 B0 4 A1 4 Out1 A B1 Out B A2 4 Out2 B2 A3 Out3 B3 CSE 240 3-21 CSE 240 3-22 Shorthand for Inverting Signals Logical Completeness Invert a signal by adding either AND, OR, NOT can implement ANY truth table • A before/after a gate A B C S in A B Cin • A “bar” over letter 0 0 0 0 1. AND combinations 0 0 1 1 A that yield a "1" in the B A AND B 0 1 0 1 truth table 0 1 1 0 1 0 0 1 S A A AND B B 1 0 1 0 1 1 0 0 2. OR the results of the AND gates 1 1 1 1 A A OR B B CSE 240 3-23 CSE 240 3-24 6 Logical Completeness via PLAs DeMorgan's Law Any truth table as a Programmable Logic Array (PLA) Converting AND to OR (with some help from NOT) • Traditionally a grid of AND and OR gates Consider the following gate: To convert AND to OR • Configurable by removing wires (or vice versa), A AND B = A OR B Single-output custom PLA (as on previous slide): invert inputs and output. • One AND gate per row with “1” in output in truth table A AND B = A OR B • Maximum number of AND gates: 2n for n inputs • One OR gate A B A B A AND B A AND B 0 0 1 1 1 0 Multiple-output custom PLA: • Build multiple single-output PLAs 0 1 1 0 0 1 A AND B = A OR B • Share AND gates “in common” 1 0 0 1 0 1 • One OR gate per output column in truth table 1 1 0 0 0 1 CSE 240 3-25 CSE 240 Why might this be useful? 3-26 Summary Next Time MOS transistors are used as switches to implement Lecture logic functions • Combinational Logic Circuits • n-type: connect to GROUND, turn on (with 1) to pull down to 0 • p-type: connect to POWER, turn on (with 0) to pull up to 1 Reading • Chapter 3.3 Basic gates: NOT, NOR, NAND • Logic functions are usually expressed with AND, OR, and NOT Quiz • Universal: any truth table to simple gates (via a PLA) • Online (as always) DeMorgan's Law Upcoming • Convert AND to OR (and vice versa) by inverting inputs/output • HW2 due next Friday CSE 240 3-27 CSE 240 3-28 7 AND, OR, NOT Gates: What Good Are They? Last time: • Transistors and gates • Can implement any logical function using gates (using PLAs) Chapter 3 Today: • We’ll use gates to create some building blocks of a processor Digital Logic • One goal: automate binary arithmetic from Chapter 2 • Continuing on our bottom-up journey Structures Next time: • Storing bits (memory) Based on slides © McGraw-Hill • Circuits with “state” Additional material © 2004/2005 Lewis/Martin CSE 240 3-30 Incrementer One-bit Incrementer 16 16 Let’s create a incrementer A +1 S Implement a single-column of an incrementer • Input: A (as a 16-bit 2’s complement integer) CarryInn • Output: A+1 (also as a 16-bit 2’s complement integer) 00001011 1 1 A +00000001 n +1 Sn Approach #1 (impractical): 00001100 • Use PLA-like techniques to implement circuit CarryOutn A C • Problem: 216 or 65536 rows, 16 output columns n in • In theory, possible; in practice, intractable An Cin Sn Cout 0 0 0 0 S Approach#2 (pragmatic): 0 1 1 0 • Create a 1-bit incrementer circuit 1 0 1 0 • Replicate it 16 times 1 1 0 1 Cout CSE 240 3-31 CSE 240 3-32 8 Aside: XOR N-bit Incrementer Chain N 1-bit incrementers together An Cin Sn Cout CarryIn0 1 1 0 0 0 0 A S A0 +1 S0 0 1 1 0 CarryOut CarryIn 0 1 0 1 0 1 1 1 1 1 0 1 Cout A1 +1 S1 Cin …but how do we 4-bit CarryOut1 CarryIn2 A Cin correctly handle the example 1 1 A2 +1 S2 least-significant bit? XOR CarryOut2 A CarryIn3 S 1 1 Cin A3 +1 S3 CarryOut3 CSE 240 3-33 CSE 240 3-34 N-bit Incrementer, continued Adder How do we handle the least-significant bit? Conceptually similar to an incrementer 1 • Build a one-bit slice, replicate n times CarryIn 00001011 0 CarryInn 1 1 00001011 1 A S +00000001 0 +1 0 An 1 1 S CarryOut +00110011 Add n 0 Bn 00001100 CarryIn1 1 1 00111100 CarryOut A1 +1 S1 n 00001011 C = 1 CarryOut1 in CarryIn2 +00000000 1 1 A2 +1 S2 00001100 CarryOut No longer needed; 2 .

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