DOCSLIB.ORG

S2600WF Technical Product Specification

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
S2600WF Technical Product Specification Intel® Server Board S2600WF Product Family Technical Product Specification An overview of product features, functions, architecture, and support specifications. Rev 2.5 August 2020 Intel® Server Products and Solutions Intel® Server Board S2600WF Product Family Technical Product Specification <Blank Page> Intel® Server Board S2600WF Product Family Technical Product Specification Document Revision History Date Revision Description of Change July 2017 1.0 • Production release. • Updated all tables from Appendix B and Appendix C. • Updated Product Architecture Overview. • Updated S2600WF Architecture Block Diagram. Added Intel® QAT information: October 2017 1.1 • Server Board Product Family Feature Set • Architecture Board Diagram • Added 6.1 section Intel® QuickAssist Technology Support • Added S2600WFQ(R) Architecture Block Diagram • Updated Trusted Platform Module (China version) iPC AXXTPMCHNE8 on table Intel® Server Board S2600WF product family feature set. November 2017 1.2 • Added section: 3.3.1.12 Trusted Platform Module (TPM) on 3.3.1 Supported Technologies. • Added TPM definition on Glossary section. August 2018 1.3 • Updated Disclaimers page. Corrected wording and typos. • Added support for 2nd Gen Intel® Xeon® processor Scalable family December 2018 2.0 • Added support for memory type Intel® Optane™ DC persistent memory module December 2018 2.1 • Updated Table 18 and Table 19 • Removed Table 11 April 2019 2.2 • Updated appropriate support hyperlinks • Added Figure 14. Intel® Server S2600WF Product Family Sensor Position • Added Table 4. Intel® Server S2600WF Product Family Sensor List • Corrected section 2.4 Product Architecture Overview to include Intel® Ethernet Con- October 2019 2.3 troller X722 • Corrected Table 70. Intel® Server System R2000WF product family feature set for Riser Card Support • Updated Figures 6 and 74 – added 12V STND-BY Power LED • Added Appendix F to include Product Regulatory Information, including EU Lot 9 January 2020 2.4 product collateral support links • Replaced all references of Intel® RSTe to Intel® VROC (SATA RAID) • Updated on-board RAID support content in chapter 6 • Update Table 2 with current Trusted Platform Module 2.0 August 2020 2.5 • Updated naming conventions for Purley Refresh 1 Intel® Server Board S2600WF Product Family Technical Product Specification Disclaimers Intel technologies’ features and benefits depend on system configuration and may require enabled hard- ware, software, or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of mer- chantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by visiting www.intel.com/design/literature.htm. Intel, the Intel logo, Xeon, and Xeon Phi are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. *Other names and brands may be claimed as the property of others. © Intel Corporation 2 Intel® Server Board S2600WF Product Family Technical Product Specification Table of Contents 1. Introduction ............................................................................................................................................................... 11 1.1 Intel Server Board Use Disclaimer .......................................................................................................................... 12 1.2 Product Errata.................................................................................................................................................................. 12 2. Server Board Family Overview .............................................................................................................................. 13 2.1 Server Board Family Feature Set ............................................................................................................................. 15 2.2 Server Board Component/Feature Identification ............................................................................................. 17 2.3 Server Board Mechanical Drawings ........................................................................................................................ 21 2.4 Product Architecture Overview ................................................................................................................................ 25 2.5 System Software Stack ................................................................................................................................................ 26 2.5.1 Hot Keys Supported During POST .......................................................................................................................... 27 2.5.2 Field Replaceable Unit (FRU) and Sensor Data Record (SDR) Data ........................................................... 29 3. Processor Support .................................................................................................................................................... 32 3.1 Processor Socket and Processor Heat Sink Module (PHM) Assembly .................................................... 32 3.2 Processor Thermal Design Power (TDP) Support ............................................................................................ 34 3.3 Intel® Xeon® Processor Scalable Family Overview ........................................................................................... 35 3.3.1 Supported Technologies ............................................................................................................................................ 37 3.3.2 Intel® Xeon® Processor Scalable Family with Integrated Intel® Omni-Path Fabric ............................. 41 3.3.3 Intel®Omni-Path IFT Carrier Accessory Kits ........................................................................................................ 42 3.4 Processor Population Rules ....................................................................................................................................... 45 3.5 Processor Initialization Error Summary ................................................................................................................ 45 4. Memory Support ....................................................................................................................................................... 48 4.1 Memory Subsystem Architecture ............................................................................................................................ 48 4.1.1 Intel® Optane™ DC Persistent Memory Module Overview ............................................................................. 49 4.2 Supported Memory ....................................................................................................................................................... 50 4.3 General Support Rules for Memory ........................................................................................................................ 51 4.3.1 DIMM Population Guidelines ..................................................................................................................................... 53 4.4 Memory RAS Features .................................................................................................................................................. 55 4.4.1 DIMM Populations Rules and BIOS Setup for Memory RAS ........................................................................ 56 5. PCIe* Support ............................................................................................................................................................ 57 5.1.1 PCIe* Enumeration and Allocation ......................................................................................................................... 57 5.1.2 Non-Transparent Bridge ............................................................................................................................................. 57 6. System I/O ................................................................................................................................................................. 59 6.1 Intel® QuickAssist Technology (Intel® QAT) Support ...................................................................................... 59 6.2 PCIe* Add-in Card Support ........................................................................................................................................ 60 6.2.1 Riser Slot #1 and Riser Slot #2 Riser Card Options ........................................................................................
Load more

Recommended publications
  • Improved Cryptanalysis of the Reduced Grøstl Compression Function, ECHO Permutation and AES Block Cipher
    Improved Cryptanalysis of the Reduced Grøstl Compression Function, ECHO Permutation and AES Block Cipher Florian Mendel1, Thomas Peyrin2, Christian Rechberger1, and Martin Schl¨affer1 1 IAIK, Graz University of Technology, Austria 2 Ingenico, France [email protected],[email protected] Abstract. In this paper, we propose two new ways to mount attacks on the SHA-3 candidates Grøstl, and ECHO, and apply these attacks also to the AES. Our results improve upon and extend the rebound attack. Using the new techniques, we are able to extend the number of rounds in which available degrees of freedom can be used. As a result, we present the first attack on 7 rounds for the Grøstl-256 output transformation3 and improve the semi-free-start collision attack on 6 rounds. Further, we present an improved known-key distinguisher for 7 rounds of the AES block cipher and the internal permutation used in ECHO. Keywords: hash function, block cipher, cryptanalysis, semi-free-start collision, known-key distinguisher 1 Introduction Recently, a new wave of hash function proposals appeared, following a call for submissions to the SHA-3 contest organized by NIST [26]. In order to analyze these proposals, the toolbox which is at the cryptanalysts' disposal needs to be extended. Meet-in-the-middle and differential attacks are commonly used. A recent extension of differential cryptanalysis to hash functions is the rebound attack [22] originally applied to reduced (7.5 rounds) Whirlpool (standardized since 2000 by ISO/IEC 10118-3:2004) and a reduced version (6 rounds) of the SHA-3 candidate Grøstl-256 [14], which both have 10 rounds in total.
    [Show full text]
  • Grøstl – a SHA-3 Candidate∗
    Grøstl – a SHA-3 candidate∗ http://www.groestl.info Praveen Gauravaram1, Lars R. Knudsen1, Krystian Matusiewicz1, Florian Mendel2, Christian Rechberger2, Martin Schl¨affer2, and Søren S. Thomsen1 1Department of Mathematics, Technical University of Denmark, Matematiktorvet 303S, DK-2800 Kgs. Lyngby, Denmark 2Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Inffeldgasse 16a, A-8010 Graz, Austria January 15, 2009 Summary Grøstl is a SHA-3 candidate proposal. Grøstl is an iterated hash function with a compression function built from two fixed, large, distinct permutations. The design of Grøstl is transparent and based on principles very different from those used in the SHA-family. The two permutations are constructed using the wide trail design strategy, which makes it possible to give strong statements about the resistance of Grøstl against large classes of cryptanalytic attacks. Moreover, if these permutations are assumed to be ideal, there is a proof for the security of the hash function. Grøstl is a byte-oriented SP-network which borrows components from the AES. The S-box used is identical to the one used in the block cipher AES and the diffusion layers are constructed in a similar manner to those of the AES. As a consequence there is a very strong confusion and diffusion in Grøstl. Grøstl is a so-called wide-pipe construction where the size of the internal state is signifi- cantly larger than the size of the output. This has the effect that all known, generic attacks on the hash function are made much more difficult. Grøstl has good performance on a wide range of platforms, and counter-measures against side-channel attacks are well-understood from similar work on the AES.
    [Show full text]
  • Security Analysis for MQTT in Internet of Things
    DEGREE PROJECT IN COMPUTER SCIENCE AND ENGINEERING, SECOND CYCLE, 30 CREDITS STOCKHOLM, SWEDEN 2018 Security analysis for MQTT in Internet of Things DIEGO SALAS UGALDE KTH ROYAL INSTITUTE OF TECHNOLOGY SCHOOL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Security analysis for MQTT in Internet of Things DIEGO SALAS UGALDE Master in Network Services and Systems Date: November 22, 2018 Supervisor: Johan Gustafsson (Zyax AB) Examiner: Panos Papadimitratos (KTH) Swedish title: Säkerhet analys för MQTT i IoT School of Electrical Engineering and Computer Science iii Abstract Internet of Things, i.e. IoT, has become a very trending topic in re- search and has been investigated in recent years. There can be several different scenarios and implementations where IoT is involved. Each of them has its requirements. In these type IoT networks new com- munication protocols which are meant to be lightweight are included such as MQTT. In this thesis there are two key aspects which are under study: secu- rity and achieving a lightweight communication. We want to propose a secure and lightweight solution in an IoT scenario using MQTT as the communication protocol. We perform different experiments with different implementations over MQTT which we evaluate, compare and analyze. The results obtained help to answer our research questions and show that the proposed solution fulfills the goals we proposed in the beginning of this work. iv Sammanfattning "Internet of Things", dvs IoT, har blivit ett mycket trenderande ämne inom forskning och har undersökts de senaste åren. Det kan finnas flera olika scenarier och implementeringar där IoT är involverad. Var och en av dem har sina krav.
    [Show full text]
  • A (Second) Preimage Attack on the GOST Hash Function
    A (Second) Preimage Attack on the GOST Hash Function Florian Mendel, Norbert Pramstaller, and Christian Rechberger Institute for Applied Information Processing and Communications (IAIK), Graz University of Technology, Inffeldgasse 16a, A-8010 Graz, Austria [email protected] Abstract. In this article, we analyze the security of the GOST hash function with respect to (second) preimage resistance. The GOST hash function, defined in the Russian standard GOST-R 34.11-94, is an iter- ated hash function producing a 256-bit hash value. As opposed to most commonly used hash functions such as MD5 and SHA-1, the GOST hash function defines, in addition to the common iterated structure, a check- sum computed over all input message blocks. This checksum is then part of the final hash value computation. For this hash function, we show how to construct second preimages and preimages with a complexity of about 2225 compression function evaluations and a memory requirement of about 238 bytes. First, we show how to construct a pseudo-preimage for the compression function of GOST based on its structural properties. Second, this pseudo- preimage attack on the compression function is extended to a (second) preimage attack on the GOST hash function. The extension is possible by combining a multicollision attack and a meet-in-the-middle attack on the checksum. Keywords: cryptanalysis, hash functions, preimage attack 1 Introduction A cryptographic hash function H maps a message M of arbitrary length to a fixed-length hash value h. A cryptographic hash function has to fulfill the following security requirements: – Collision resistance: it is practically infeasible to find two messages M and M ∗, with M ∗ 6= M, such that H(M) = H(M ∗).
    [Show full text]
  • Improved Cryptanalysis of the Reduced Grøstl Compression Function, ECHO Permutation and AES Block Cipher
    Improved Cryptanalysis of the Reduced Grøstl Compression Function, ECHO Permutation and AES Block Cipher Florian Mendel1,ThomasPeyrin2,ChristianRechberger1, and Martin Schl¨affer1 1 IAIK, Graz University of Technology, Austria 2 Ingenico, France [email protected], [email protected] Abstract. In this paper, we propose two new ways to mount attacks on the SHA-3 candidates Grøstl,andECHO, and apply these attacks also to the AES. Our results improve upon and extend the rebound attack. Using the new techniques, we are able to extend the number of rounds in which available degrees of freedom can be used. As a result, we present the first attack on 7 rounds for the Grøstl-256 output transformation1 and improve the semi-free-start collision attack on 6 rounds. Further, we present an improved known-key distinguisher for 7 rounds of the AES block cipher and the internal permutation used in ECHO. Keywords: hash function, block cipher, cryptanalysis, semi-free-start collision, known-key distinguisher. 1 Introduction Recently, a new wave of hash function proposals appeared, following a call for submissions to the SHA-3 contest organized by NIST [26]. In order to analyze these proposals, the toolbox which is at the cryptanalysts’ disposal needs to be extended. Meet-in-the-middle and differential attacks are commonly used. A recent extension of differential cryptanalysis to hash functions is the rebound attack [22] originally applied to reduced (7.5 rounds) Whirlpool (standardized since 2000 by ISO/IEC 10118-3:2004) and a reduced version (6 rounds) of the SHA-3 candidate Grøstl-256 [14], which both have 10 rounds in total.
    [Show full text]
  • Advanced Meet-In-The-Middle Preimage Attacks: First Results on Full Tiger, and Improved Results on MD4 and SHA-2
    Advanced Meet-in-the-Middle Preimage Attacks: First Results on Full Tiger, and Improved Results on MD4 and SHA-2 Jian Guo1, San Ling1, Christian Rechberger2, and Huaxiong Wang1 1 Division of Mathematical Sciences, School of Physical and Mathematical Sciences, Nanyang Technological University, Singapore 2 Dept. of Electrical Engineering ESAT/COSIC, K.U.Leuven, and Interdisciplinary Institute for BroadBand Technology (IBBT), Kasteelpark Arenberg 10, B–3001 Heverlee, Belgium. [email protected] Abstract. We revisit narrow-pipe designs that are in practical use, and their security against preimage attacks. Our results are the best known preimage attacks on Tiger, MD4, and reduced SHA-2, with the result on Tiger being the first cryptanalytic shortcut attack on the full hash function. Our attacks runs in time 2188.8 for finding preimages, and 2188.2 for second-preimages. Both have memory requirement of order 28, which is much less than in any other recent preimage attacks on reduced Tiger. Using pre-computation techniques, the time complexity for finding a new preimage or second-preimage for MD4 can now be as low as 278.4 and 269.4 MD4 computations, respectively. The second-preimage attack works for all messages longer than 2 blocks. To obtain these results, we extend the meet-in-the-middle framework recently developed by Aoki and Sasaki in a series of papers. In addition to various algorithm-specific techniques, we use a number of conceptually new ideas that are applicable to a larger class of constructions. Among them are (1) incorporating multi-target scenarios into the MITM framework, leading to faster preimages from pseudo-preimages, (2) a simple precomputation technique that allows for finding new preimages at the cost of a single pseudo-preimage, and (3) probabilistic initial structures, to reduce the attack time complexity.
    [Show full text]
  • Research Intuitions of Hashing Crypto System
    Published by : International Journal of Engineering Research & Technology (IJERT) http://www.ijert.org ISSN: 2278-0181 Vol. 9 Issue 12, December-2020 Research Intuitions of Hashing Crypto System 1Rojasree. V, 2Gnana Jayanthi. J, 3Christy Sujatha. D PG & Research Department of Computer Science, Rajah Serfoji Govt. College(A), (Affiliated to Bharathidasan University), Thanjavur-613005, Tamilnadu, India. Abstract—Data transition over the internet has become there is no correlation between input and output bits; and no inevitable. Most data transmitted in the form of multimedia. correlation between output bits, etc. The data transmission must be less complex and user friendly To ensure about the originator of the message, Message at the same time with more security. Message authentication Authentication Code (MAC) is used which can be and integrity is one of the major issues in security data implemented using either symmetric Stream cipher Transmission. There are plenty of methods used to ensure the integrity of data when it is send from the receiver and before it cryptography or Hashing cryptography techniques. reaches the corresponding receiver. If these messages are However, MAC is limited with (i) Establishment of Shared tampered in the midst, it should be intimated to the receiver Secret and (ii) Inability to Provide Non-Repudiation. Even and discarded. Hash algorithms are supposed to provide the some kind of attacks is found like Content modification, integrity but almost all the algorithms have confirmed Sequence modification, Timing modification etc. breakable or less secure. In this review, the performances of This paper is aimed to discuss the several security various hash functions are studied with an analysis from the algorithms based on hash functions in cryptography to point of view of various researchers.
    [Show full text]
  • Avalanche Handbook
    AGRICULTURE HANDBOOK 489 U.S. DEPARTMENT OF AGRICULTURE FOREST SERVICE U.S. DEPARTMENT OF AGRICULTURE FOREST SERVICE July 1976 USDA, National Agricultural Library NALBIdg ^ 10301 Baltimore Bivd Beltsville, MD 20705-2351 Avalanche Handbook RONALD I. PERLA and M. MARTINELLI, Jr. Alpine Snow and Avalanche Research Project Rocky Mountain Forest and Range Experiment Station USDA Forest Service Fort Collins, Colorado (Dr. Perla is now with the Glacioiogy Division, Environment Canada, Calgary, Alberta) Agriculture Handbook 489 Acknowledgments We wish to thank André Roch and Hans Frutiger of Switzerland and many persons in the United States who furnished photographs. Special mention is due the instructors at the 1972 and 1973 National Avalanche Schools, who used and improved early versions of much of the material presented here, and Alexis Keiner, who did the art and graphic work. Substantial help was also received from numerous reviewers in the Forest Service and from: WILLIAM HOTCHKISS National Ski Patrol and U.S. Geological Survey Helena, Montana DR. E. R. LACHAPELLE University of Washington Seattle, Washington DR. JOHN MONTAGNE Montana State University Bozeman, Montana PETER SCHAERER National Research Council of Canada Vancouver, British Columbia. Cover photos: Wingle (front), Keiner (back), Standley (inside). Perla, Ronald I., and M. Martinelli, Jr. 1975. Avalanche Handbook. U.S. Dep. Agrie, Agrie. Handb. 489, 238 p. Avalanches seldom touch man or his works, but when they do they can be disas- trous. This illustrated handbook sets forth procedures for avoiding such disasters in ski areas, near roads and settlements, and in the back country. New snowfall and old snow redeposited by winds are the major causes of ava- lanches.
    [Show full text]
  • Preimages for Reduced SHA-0 and SHA-1
    Preimages for Reduced SHA-0 and SHA-1 Christophe De Canni`ere1,2 and Christian Rechberger3 1 D´epartement d’Informatique Ecole´ Normale Sup´erieure, [email protected] 2 Katholieke Universiteit Leuven, Dept. ESAT/SCD-COSIC, and IBBT 3 Graz University of Technology Institute for Applied Information Processing and Communications (IAIK) [email protected] Abstract. In this paper, we examine the resistance of the popular hash function SHA-1 and its predecessor SHA-0 against dedicated preimage attacks. In order to assess the security margin of these hash functions against these attacks, two new cryptanalytic techniques are developed: – Reversing the inversion problem: the idea is to start with an impossible expanded message that would lead to the required di- gest, and then to correct this message until it becomes valid without destroying the preimage property. – P3graphs: an algorithm based on the theory of random graphs that allows the conversion of preimage attacks on the compression func- tion to attacks on the hash function with less effort than traditional meet-in-the-middle approaches. Combining these techniques, we obtain preimage-style shortcuts attacks for up to 45 steps of SHA-1, and up to 50 steps of SHA-0 (out of 80). Keywords: hash function, cryptanalysis, preimages, SHA-0, SHA-1, di- rected random graph 1 Introduction Until recently, most of the cryptanalytic research on popular dedicated hash functions has focused on collisions resistance, as can be seen from the successful attempts to violate the collision resistance property of MD4 [10], MD5 [32, 34], SHA-0 [6] and SHA-1 [13, 21, 33] using the basic ideas of differential cryptanaly- sis [2].
    [Show full text]
  • SMASH Implementation Requirements
    1 2 Document Number: DSP0217 3 Date: 2014-12-07 4 Version: 2.1.0 5 SMASH Implementation Requirements 6 Document Type: Specification 7 Document Status: DMTF Standard 8 Document Language: en-US 9 SMASH Implementation Requirements DSP0217 10 Copyright Notice 11 Copyright © 2009, 2014 Distributed Management Task Force, Inc. (DMTF). All rights reserved. 12 DMTF is a not-for-profit association of industry members dedicated to promoting enterprise and systems 13 management and interoperability. Members and non-members may reproduce DMTF specifications and 14 documents, provided that correct attribution is given. As DMTF specifications may be revised from time to 15 time, the particular version and release date should always be noted. 16 Implementation of certain elements of this standard or proposed standard may be subject to third party 17 patent rights, including provisional patent rights (herein "patent rights"). DMTF makes no representations 18 to users of the standard as to the existence of such rights, and is not responsible to recognize, disclose, 19 or identify any or all such third party patent right, owners or claimants, nor for any incomplete or 20 inaccurate identification or disclosure of such rights, owners or claimants. DMTF shall have no liability to 21 any party, in any manner or circumstance, under any legal theory whatsoever, for failure to recognize, 22 disclose, or identify any such third party patent rights, or for such party’s reliance on the standard or 23 incorporation thereof in its product, protocols or testing procedures. DMTF shall have no liability to any 24 party implementing such standard, whether such implementation is foreseeable or not, nor to any patent 25 owner or claimant, and shall have no liability or responsibility for costs or losses incurred if a standard is 26 withdrawn or modified after publication, and shall be indemnified and held harmless by any party 27 implementing the standard from any and all claims of infringement by a patent owner for such 28 implementations.
    [Show full text]
  • Randomness Analysis in Authenticated Encryption Systems
    Masarykova univerzita Fakulta}w¡¢£¤¥¦§¨ informatiky !"#$%&'()+,-./012345<yA| Randomness analysis in authenticated encryption systems Master thesis Martin Ukrop Brno, autumn 2015 Declaration Hereby I declare, that this paper is my original authorial work, which I have worked out by my own. All sources, references and literature used or excerpted during elaboration of this work are properly cited and listed in complete reference to the due source. Martin Ukrop Advisor: RNDr. Petr Švenda, Ph.D. ii Acknowledgement Many thanks to you all. There would be much less algebra, board gaming, curiosity, drama, experience, functional programmig, geekiness, honesty, inspiration, joy, knowledge, learning, magic, nighttime walks, OpenLabs, puzzle hunts, quiet, respect, surprises, trust, unpredictability, vigilance, Wachumba, xylophone, yummies and zeal in the world for me without you. Access to computing and storage facilities owned by parties and projects contributing to the National Grid Infrastructure MetaCentrum, provided under the programme „Projects of Large Infrastructure for Research, Development, and Innovations“ (LM2010005), is greatly appreciated. iii Abstract This thesis explores the randomness of outputs created by authenticated encryption schemes submitted to the CAESAR competition. Tested scenarios included three different modes of public message numbers. For the assessment, four different software tools were used: three common statistical batteries (NIST STS, Dieharder, TestU01) and a novel genetically in- spired framework (EACirc). The
    [Show full text]
  • Evaluation of Cryptographic Packages
    Institutionen för systemteknik Department of Electrical Engineering Examensarbete Title: Evaluation of Cryptographic Packages Master thesis performed in ISY Linköping Institute of Technology Linkoping University By Muhammad Raheem Report number LITH-ISY-EX--09/4159 Linköping Date March 6, 2009 TEKNISKA HÖGSKOLAN LINKÖPINGS UNIVERSITET Department of Electrical Engineering Linköpings tekniska högskola Linköping University Institutionen för systemteknik S-581 83 Linköping, Sweden 581 83 Linköping Title Evaluation of Cryptographic Packages Master thesis in Information Theory division at ISY, Linköping Institute of Technology By Muhammad Raheem LITH-ISY-EX--09/4159 (master level) Supervisor: Dr. Viiveke Fåk Examiner: Dr. Viiveke Fåk Linköping, 6 March 2009 II III Abstract The widespread use of computer technology for information handling resulted in the need for higher data protection whether stored in memory or communicated over the network. Particularly with the advent of Internet, more and more companies tend to bring their businesses over this global public network. This results in high exposure to threats such as theft of identities, unauthorized and unauthenticated access to valuable information. The need for protecting the communicating parties is evident not just from third parties but also from each other. Therefore high security requirements are important. The usage of high profile cryptographic protocols and algorithms do not always necessarily guarantee high security. They are needed to be used according to the needs of the organization depending upon certain characteristics and available resources. The effective assessment of security needs of an organization largely depends upon evaluation of various security algorithms and protocols. In addition, the role of choosing security products, tools and policies can’t be ignored.
    [Show full text]