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EMC and Signal Integrity in High-Speed Electronics

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EMC and Signal Integrity in High-Speed Electronics EMCEMC andand SignalSignal IntegrityIntegrity inin HighHigh--speedspeed ElectronicsElectronics Li Er-Ping , PhD, IEEE Fellow Advanced Electromagnetics and Electronic Systems Lab. A*STAR , Institute of High Performance Computing (IHPC) National University of Singapore [email protected] IEEE EMC DL Talk Missouri Uni of ST Aug. 15, 2008 AboutAbout SingaporeSingapore IEEE Region 10 AboutAbout SingaporeSingapore Physical • Land area: 699 sq km • Limited natural resources • Geographical position • Natural harbour Population • 1960: 1.60 million • 2006: 4.7 million (including Economy (GDP) 800K expatriates and migrant • 1960: $1.5 billion workers) • 2006: $134 billion • Per capita:$35,000 Foreign Reserves Political Landmarks • 1963: S$1.2 billion • 1959: Self-government • 2005: S$193.6 billion • 1963: Merger in Federation of Malaysia • 1965: Independence (separation from Malaysia) Outline 1. Introduction 2. High-speed Electronics Key SI/EMC Issues Transmission Line effects Crosstalk Simultaneous Switching Noise (SSN) Radiated Emission Design Considerations 3. Summary Introduction Trends in IC & Package Industry More Dense Higher Frequency Complexity of Intel microprocessors 1GIGA Itanium 10GHz Pentium IV 100MEG Pentium III Pentium 4 MicroprocessorsPentium III Pentium 1GHz (Intel) PentiumII 10MEG PentiumII Pentium MPC755 80486 MPC555 80486 80386 100MHz 80386 1MEG 68HC16 80286 Microcontrolers 80286 68HC12 100K (Freescale) 10MHz 68HC08 Operating Frequency Number fo Devices 16 bits 32 bits 64 bits 10K 8086 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010 1980 1985 1990 1995 2000 2005 Year Year Source: INTEL Packaging and System Integration -- A Roadmap -- System Integration: Vertical -Analog/Digital system -Photonic integration -Displays -MEMS -Energy 12 20 9 200 2006 Introduction Complex System-on-Package (SOP) Structure Reference: Georgia Institute of Technology , Packaging Research Center. 3 ”I” SI (Signal Integrity) PI (Power Integrity) EMI (Electromagnetic Interference) is a very important issue for IC & package design Emission Digital IC RF IC Susceptibility Digital IC Crosstalk Simultaneous Switching Noise (SNN) High-Speed Design Challenges Slow Driver Fast Driver Driver Receiver Driver Receiver Both Simulations are the Same 15 cm Line! • Signal Integrity • Timing – Reflections, ringing, overshoot, monotonicity – Meet setup/hold requirements – Crosstalk – Path level delay management – Simultaneous switching noise – Clock distribution and skew Transmission Lines • 10ns Driver 100ps Driver – Both driving the same load 15 cm away – Impedance discontinuity at the Receiver (open) EMC design becomes more and more important If not properly take EMC-Design – One circuit will disturb another • Causing the output signal distortion • Causing signal delay • Mulfunction – One board works properly, but the assembly may not work properly – One device works properly at lab, but may work properly after installed on real environment SI/EMI Design Objectives Signal Integrity EMI • Make it work reliably • Make it comply EMI requirements • Signal quality • Shielding • Timing • Grounding • Crosswalk • Filtering • Power/ground noise • Noise isolation • … • …. Key SI Issues Propagation Delay Electrically long interconnect: finite length of the transmission line comparable to the operating wavelength Key SI Issues Attenuation of Signal Attenuation of signal due to Ohmic loss --- finite conductivity, skin/proximity effect Conductance loss – lossy substrate Key SI Issues Attenuation of Signal Skin effects: At high frequencies, current concentrated at the surface of the conductor Resistance increases as square root of frequency! Key SI Issues Ringing & Reflection due to Discontinuity in characteristic impedance of transmission lines RjL+ ω L ZZ= ======= = 00GjC+ ω lossless C # Structure related: bend, stub, etc. # Transitions in transmission lines: Microstrip to stripline transition; vias Discontinuity Reflection Ringing High-order Harmonics Key SI Issues Ringing & Reflection due to Impedance Mismatch Circuits’ Impedance 2 Transmission Line’s Impedance (Mismatching) ÆMultireflectionÆRinging Key SI Issues Crosstalk Coupling path: Common-impedance (ground impedance) H Electric field coupling (capacitive) Magnetic field coupling (inductive) Crosstalk CM – The coupling of two conductors via the Mutual Capacitance --- CM electric field. dV & IC= driver noise, Cm m dt Mutual Inductance --- LM LM – The current in one loop affects the second loop by means of the magnetic field. di VL= driver noise, Lm m dt Key SI/EMC Issues Crosstalk Induced Delay The worst scenario for delay is when the victim and the aggressor signals switch in opposite directions Key EMC Issues Simultaneous Switching Noise (SSN) Also known as ground bounce, power bounce or delta-I noise. Voltage noise appears when circuit draws currents from the power distribution network. These effects cause unwanted switching and slow performance. The problem is amplified when many circuits switch at the same time. Key EMC Issues Simultaneous Switching Noise Propagation along Power Distribution Network Aggressor Victim SSN coupling to other signal traces Produce emission from package Key EMC Issues Emission from Package Emission sources …… heat sink wire connected to edge/gap of power- PCB ground plane For low frequency, can be simplified to be a dipole antenna. For high frequency&complex structures, emission analysis is more complex than SI analysis. Design Considerations Balance between all EMC issues Every control method is frequency dependent. Design Considerations Return Vias/Shorting Vias/Decoupling cap Return Vias Provide return current for active via, reduce SSN Prevent propagation of EM wave from noise Isolate the noise source But introduce resonance for higher frequency Design Consideration Minimizing Cross-talk ■ Cross-talk (Near and Far End Cross-talk) ■ Example: Near End Cross-talk w s t V ⎛⎞CL NEXT===b K 1 * ML + ML V b 4 ⎜⎟ a ⎝⎠CLLL h where Vba== Max imumvoltage on quiet line, V M ax imumvoltage on active line KbML== Backward coefficient,t C Mutual capacian ce per length CL == Capacitan ce per length of signal trace, LML Mutual inducceptan e LL = Inductan ce per length of signal trace ■ Use 2D Field Solver to Extract L and C Matrices ■ L and C matrices contain all information about coupling of traces, from which all aspects of cross-talk can be analysed (e.g., SPICE equivalent circuit model can be built,…) Minimizing Cross-talk ■ Cross-talk (Near and Far End Cross-talk) ■ Example: Near End Cross Talk – Comparison between FR4, Thin and Thick Film Substrates Organic Thickfilm Thinfilm 0,12 Substrate Substrate Substrate 0,1 Er=10.2 Al2O3 Ceramic Al2O3 Ceramic FR4 (96%) (99%) 0,08 Er=9.2 εr 4.20 9.2 10.2 0,06 Kb tanδ 0.007 0.0023 0.0023 Er=4.2 0,04 5 % of noise margin allocated to cross-talk 0,02 0 123456 Space in W Use substrate with lower dielectric constant FR4 Thick film (Er_9.2) Thin film (Er=10.2) Space btw conductors must be at least 2W to keep Kb less than or equal 2% Minimizing Cross-talk Via-to-via crosstalk Provide adjacent return/shorting via. [H. Johnson, et al, High speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003] Minimizing Cross-talk-vias ■ Use Interplane Vias to Shield Sensitive Signal Paths a) 1 interplane via beside each signal b) 1 interplane via beside each signal c) 3 interplane vias beside each via and no interplane via between via and 1 interplane via between signal via and 1 interplane via signal vias signal vias between signal vias Interplane Via Interplane Interplane Via Via Signal Signal Via Via Signal Via ■Cancellation of magnetic field leads to a reduction in cross-talk between the signal vias Vias I. Nidp, EPTC, 2005, Singapore Minimizing Cross-talk-Vias S1.3 Simulated Mutual Inductance -30 -40 For the 3 Structures -50 -60 (a) (b) (c ) (a) Mag. [dB] -70 (a) -80 -90 9pH 4pH 2pH -100 1e+08 1e+09 10e+9 31e+9 f [Hz] S1.4 -30 (b) -40 Cross-talk is reduced if three -50 interplane vias are used to shield -60 aggressor and one interplane via is Mag. [dB] -70 placed between aggressor and -80 victim -90 1e+08 1e+09 10e+9 31e+9 (c) f [Hz] Design Considerations Impedance Matching z Match discontinuities: Microstrip<->Stripline Wire bond<->Signal Trace PCB Trace<->Cable zIn general, Use blind and buried vias to cause less reflection comparing to the through-hole vias (But some time is not true, depends on the structures, let’s examine ) Minimizing Reflections ■ Comparison of Buried and Through-Hole Vias (ECPWG- ECPWG transition) ■ Both vias were used to connect two 50 Ω traces in layers 2 and 3 Reference plane Signal path Signal path Via hole Via hole Reference plane Buried via Through-hole via L/H C/F Z/Ω Buried via 1.0E-10 1.7E-13 24.9 Through-hole via 1.5E-10 1.1E-13 36.5 Buried via Via hole Through –hole via impedance is Through-hole via more close to the load 50 Ω , impedance match is better than buried via Ref: I. Nidp, EPTC, 2004, Singapore Minimizing Reflections To adjust the Pad/Hole Ratio for Capacitive Vias , also could minimize the reflections Reference plane Signal path Via hole Via hole Via pad d Reference plane (e.g., beneath Reference plane blind via) Buried Via 4:1 ¼ of via 3:1 pad dia 2:1 Same as 1.5:1 via pad dia Smaller pad/hole ratio (smaller annular ring) leads Larger distance btw via and reference , less to an increase in Zvia, thus reducing the reflection reflections Minimizing Reflections ■ Effects of bends when no other discontinuity is present along signal path Chamfered 90° bend 45° bend 90° bend Uniform trace 45° bend 90° bend 800 µm long trace Chamfered 90° bend Minimizing Reflections ■ Effects of bends when other discontinuities are present along signal path ■ Example: 2.4 mm long signal path within the substrate 90° 45° One bend Through-hole via Four bends 2.4 mm long signal path (reference) ■ Above 10 GHz use less than four 90° bends to keep reflection < 10% ■ Use only 45° whenever possible. Up to 15 GHz, six 45° bends can be used and <10% of signal will be reflected.
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