• Abstract and Figures
• Public Full-text

Analog Applications Journal Automotive Reduce buck-converter EMI and voltage stress by minimizing inductive parasitics By Timothy Hegarty Systems Engineer, Non-Isolated Power Solutions Introduction Consider the turn-on of the high-side MOSFET, Q1, in High-frequency conducted and radiated emissions from the synchronous buck converter of Figure 1. Current synchronous buck converters occur based on the transient flowing originally from source to drain of the synchronous voltage (dv/dt) and transient current (di/dt) generated MOSFET, Q2, ramps to zero, and the current in Q1 during hard switching. Such electromagnetic interference increases to the inductor current level. Hence, the loop (EMI) is an increasingly vexing issue in the design and shaded in red and labeled “1” in Figure 1 is designated as qualification cycle, especially given the increased switch- the high-frequency switching power loop (or “hot” loop). ing speed of power MOSFETs. This article identifies the In contrast, the current flowing in the inductor, LF, is significant role of power-stage inductive parasitics in EMI largely DC with superimposed triangular ripple. The rate generation and offers suggestions for their minimization to of change of the current is inherently limited by the induc- reduce the broadband EMI signature. tor and any parasitic inductance contributed by the series connections is essentially benign. Critical converter loops with high Loops 2 and 3 in Figure 1 are classified as gate loops for slew-rate currents the power MOSFETs. Specifically, loop 2 represents the A compact, optimized layout of a power stage lowers EMI high-side MOSFET’s gate driver supplied by bootstrap for easier regulatory compliance. In translating a converter capacitor, CBOOT. Likewise, loop 3 corresponds to the low- schematic to a board layout, one essential step is to side MOSFET’s gate driver supplied by VCC. The gate pinpoint the high slew-rate current loops, with an eye to turn-on and turn-off current paths are delineated in each recognizing the layout-induced parasitic or stray induc- case by solid and dashed lines, respectively. tances that cause excessive noise, overshoot, ringing and ground bounce.[1] Figure 1. Critical high-frequency AC loops with high slew-rate currents are the power loop and gate-drive loops VCC VIN PWM Controller DBOOT RBOOT CIN HB 1 CBOOT Q High-Side HO 1 Gate Driver 2 LF SW VOUT VCC CVCC COUT LO Q Low-Side 2 Gate Driver 3 PGND GND Texas Instruments 1 AAJ 3Q 2016 Analog Applications Journal Automotive Parasitic inductances expected, the power-loop inductance is highly related to In general, the behavior of MOSFET switching and the the layout geometry of the input capacitor-MOSFET loop consequences for waveform ringing, power dissipation, denoted by the red-shaded area in Figure 1. device stress, and EMI are correlated with the parasitic Meanwhile, the gate-loop self-inductance, LG, includes inductances of the power-loop and gate-drive circuits. lumped contributions from the MOSFET package and PCB Figure 2 provides a comprehensive illustration of the para- trace routing. An inspection of Figure 2 reveals that the sitic elements arising from component placement, device common-source inductance of Q1 exists mutually in both package, and printed circuit board (PCB) layout routing the power and gate loops. It increases switching loss that affect switching performance and EMI of the synchro- because the di/dt of the power loop creates a negative nous buck converter. feedback voltage that impedes rise and fall times of the The effective high-frequency power-loop inductance, gate-source voltage. Another factor that leads to increased component stress is the common-source inductance of Q2, LLOOP, is the sum of the total drain inductance, LD, and the which contributes to spurious turn-on of the low-side common-source inductance, LS, that results from the [2] series inductance of the input capacitor and PCB traces, MOSFET during body-diode reverse recovery. and the package inductances of the power MOSFETs. As Figure 2. MOSFET and gate-driver stage with inductive and capacitive parasitic elements L VIN PCB1 D VCC Q1 DBOOT High-Side LD1_INT Driver Gate current charges C & GS1 dv /dt BOOT d ds1 CGD1 at turn on CGD1 D CDS1 L B1 HI G_EXT1 g R SRCE1 G L =Σ L = RG_INT1 LG_INT1 C D C GS1 BOOT s LPCB1 + L PCB2 + L D1_INT + + LD2_EXT +L D2_INT +L S2_INT + SW did1 /dt induced voltage L + L di /dt S2_EXT CIN LS1_INT d1 CBOOT refresh current opposes applied gate drive voltage flows in Q2⇒ LS = L S1_INT + L S1_EXT parasitic inductances S limit min TOFF of Q 1 Kelvin connection to source LS1_EXT C IN – SW node To C Inductor 1 C LD2_EXT SW-CM D Chassis GND LCIN Q2 L Low-Side D2_INT VCC dvds2 /dt induced R Driver CIN current spikes d up gate voltage CDS2 CGD2 DB2 + LG_EXT2 LO RSINK2 g dv /dt – ds2 G RG_INT2 LG_INT2 C CGS2 VCC s – PGND did2 /dt induced voltage did2 /dt during diode RR spikes LS2_INT down source voltage S Kelvin connection to source L S2_EXT Power Loop Current GND + Gate Drive Currents High dv/dt Node LPCB2 Texas Instruments 2 AAJ 3Q 2016 Analog Applications Journal Automotive EMI frequencies and coupling modes times (Figure 3). Using Fourier analysis, it is shown that Delineated in Table 1 are the three loosely-defined the harmonic-amplitude envelope is a double-sinc function frequency ranges over which a synchronous buck with corner frequencies of f1 and f2, depending on the pulse width and rise/fall time of the time-domain converter excites and propagates EMI. During MOSFET [3] switching, where the slew rate of the commutating current waveform. A similar analysis applies for the instanta- may exceed 5 A/ns, just 2 nH of parasitic inductance neous current in the power loop. results in a voltage overshoot of 10 V. Furthermore, the Three dominant noise-coupling paths are identified as: current waveforms in the power loop with fast switching (1) conducted noise through the DC input lines; edges and leading-edge resonant ringing are rich in (2) magnetic field coupling from the power loop; and (3) electric field coupling from the SW-node copper harmonic content, posing a severe threat of magnetic field [4] coupling and radiated EMI. surface. Power-loop inductance, LLOOP, increases MOSFET Table 1. Converter EMI frequency classification switching loss and the peak drain-to-source voltage spike. Conducted/ Converter Dominant Noise Frequency It also exacerbates SW-voltage ringing, affecting broad- Radiated Noise Type Source Range band EMI in the 50- to 200-MHz range. Clearly, it is vital to Emissions minimize the effective loop length and enclosed area of Low- Switching-frequency 150 kHz to the power loop. This reduces parasitic inductance and 1 frequency Conducted harmonics 50 MHz magnetic field self-cancellation, and makes it possible to noise reduce the magnetically-coupled radiated energy emanat- MOSFET voltage ing from what effectively is a loop antenna structure.[3, 4, 5] Broadband and current rise/ 50 MHz to 2 Both Conducted noise coupling is most likely on the noise fall times, resonant 200 MHz ringing converter input side as the ratio of loop inductance and input-capacitor series inductance (ESL) determines the High- Body-diode reverse Above 3 frequency Radiated filtering. Reducing LLOOP increases the input-filter attenu- recovery 200 MHz noise ation requirement. Fortunately, the noise conducted to the output is minimal if the filter inductor has a high self- To get an idea of the harmonic frequency amplitudes of resonant frequency (SRF) and also provides high transfer the switch (SW) voltage waveform, consider an input impedance from the SW to VOUT nets. The output noise is having a periodic trapezoidal pulse with finite rise and fall additionally filtered by low-impedance output capacitor(s). Figure 3. The switch-voltage waveform and spectral envelope that depends on pulse width and rise/fall times tR tF VIN 0 dB/dec –20 dB/dec Maximum k Envelope Fourier t ds 1 Analysis Envelope V (t) ⇒ –40 dB/dec Spectral Amplitude, A (dBµV) Time, t tSS = 1/f Log f 1 t = Pulse width (measured at half maximum) f = 1 1 1 πt f2 = 1 πtR tS = Pulse period D = Duty cycle = t1 /t S t = Rise time, t = Fall time of edge transition sin()kπ D sin(kπ × tRS t ) R F ADVK=2 × IN × kπ D kπ × tRS t Texas Instruments 3 AAJ 3Q 2016 Analog Applications Journal Automotive Equivalent resonant circuit contributes to voltage stress of the MOSFETs and gate drivers, and it also correlates to the frequency at which Referring to the SW voltage waveform in Figure 4, a reso- [4] nance is excited by the parasitic energy stored during the broadband-radiated EMI is centered. MOSFET switching. Simplified equivalent circuits are Note that two important aspects during resonance are included on the right side of Figure 4 for analyzing the the resonant frequency and the loss or damping factor at switching behavior. The switch-voltage overshoot above that resonance. The main design goal is to push the reso- nant frequency as high as possible by minimizing the VIN and undershoot below ground (GND) are evident during the rising and falling edges, respectively. The oscil- power-loop inductance. This decreases the stored reactive lation amplitude depends on the distribution of partial energy and lowers the resonant peak voltage. Also, the inductances within the loop, and the subsequent ringing is damping factor is increased at a higher frequency due to damped by the effective loop AC resistance. This the skin effect. Figure 4. Practical SW-node voltage waveform and equivalent RLC circuits for a synchronous buck Equivalent RLC circuit after Q1 turns ON LLOOP Peak Amplitude Q1 on RLOOP High Z VSW Voltage VIN Overshoot Resonant Frequency (5 V/div) Q off C 1 2 OSS2 fres1 = = 160 MHz 2π LCLOOP OSS2 VIN Equivalent RLC circuit Damping after Q1 turns OFF RLOOP α = LLOOP 2LLOOP 1 fres2 = Q off C 2π LCLOOP OSS1 1 OSS1 RLOOP 3 High Z Voltage VSW Undershoot VIN Q2 on Time (40 ns/div) Texas Instruments 4 AAJ 3Q 2016 Analog Applications Journal Automotive EMI mitigation begins at the schematic using minimum dielectric thickness.

Load more

  8

Copy Link