Portable Test and Stimulus: the Next Level of Verification Productivity Is Here

Portable Test and Stimulus: The Next Level of Verification Productivity is Here

On behalf of the Accellera Portable Stimulus Working Group Sharon Rosenberg, Cadence Design Systems Pradeep Salla, Mentor Graphics

• Introduction: What and Why? • “Hello World”: Language Concepts • Block-to-System Example

• Design complexity continues to increase

– Outstripping verification productivity SIMULATION • System-level state space too big for STIMULUS effective UVM constrained-random EMULATION • Multiple verification platforms • Need to reuse Test Intent FPGA PROTO – Higher abstraction IP BLOCK SUBSYSTEM FULL SYSTEM – Block to system – Different design versions

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 3 The Portable Stimulus Journey

PSPWG PSWG 2014 2015 2017 2018 Portable Stimulus Working Group Participants AMD IBM OneSpin AMIQ EDA Intel Qualcomm Analog Devices Mentor Semifore Breker National Instruments Synopsys Cadence NVIDIA Texas Instruments Cisco NXP Semiconductors Vayavya Labs Cypress Semiconductor

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 4 Reuse of Test Intent Across Platforms/Users

• Single specification of test intent is critical Portable Stimulus • Constrain and randomize at the Scenario Level by capturing: – interactions – dependencies UVM C – resource contention • Abstraction lets tools IP BLOCK SUBSYSTEM FULL SYSTEM automate test generation – Multiple targets – Target-specific SIMULATION EMULATION FPGA PROTO customization

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 5 The Advantages of a Declarative Specification . Most SoC tests are directed . Declarative tests let the tool do the work . Manually determining . Explore all possible options turn-by-turn directions . Easy to optimize . Hard to account for new stops . Guided by preferences . Route limited by driver's biases . Declarative Portable Stimulus Description enables automation and analysis . Automation makes test intent portable . Enables retargeting to different environments . Automation makes test techniques portable . Bring automated constraint-driven tests to SoC TFitz, Portable Stimulus IP to SoC, DVClub-EU 6 Sept, 2018 Projected Tool Flow

DSL DSL

Compiler Gen-time or Run-time

Constraint Test Scenario model Solver Solved Model Generator + Constraints

C++ Compile / Compile Link / Run Link UVM UVM Sync C-test Sequences Sequences PSS Abstract

AXIAXI VIPVIP TB Scenario AXI CPUVIP Model DMAC DMAC

UART UART DDR UART UART DDR VIP MEM VIP MEM

UVM Testbench SoC Testbench

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 7 What Portable Stimulus Is NOT • NOT a UVM replacement • NOT a reference implementation • NOT one forced level of abstraction – Expressing intent from different perspectives is a primary goal • NOT Monolithic – Representations would typically be composed of portable parts • NOT Two standards – PSS/DSL and PSS/C++ input formats describe 1:1 semantics – Tools shall consume both formats • NOT Just stimulus – Models Verification Intent – Stimulus, checks, coverage, scenario-level constraints – Portable test realization

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 8 "HELLO WORLD": LANGUAGE CONCEPTS

© Accellera Systems Initiative 9 Hello World: Atomic Actions component groups elements for reuse and composition component pss_top { hello action hello_world_a{ action defines behavior world exec body SV = """ exec defines implementation $display("Hello World"); """; } } class hello_world_a_seq_1 extends uvm_sequence;  Reuse `uvm_object_utils(hello_world_a_seq_1)  Composition

virtual task body();  Abstract behaviors $display("Hello World");  Retargetable endtask Implementations endclass

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 10 Exec Block Types

• Specify mapping of PSS entities to their implementation test.sh Solve platform Target platform test.c header #include gcc –c test.c –DBARE_METAL

declaration void declared_func() { … pre_solve run_start file }

constraint solving void test_main() { do_run_start(); post_solve fork_threads(); do_run_end(); Runtime Runtime } scheduler scheduler void thread0() { Could be SV … body body or other language bodybody … bodybody // step N body body do_body(); … };

void thread1() { … } run_end Could be multiple threads on one core, or threads running on different cores

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 11 Hello World: Compound Actions

action hello_world_a { compound action hello_a h; hello traverses other actions world_a w; activity activity { world defines scheduling h; w; } } void hello_world_a_test_1() { } printf ("Hello\n"); printf ("World\n"); }  Behavior encapsulation  Behavior scheduling

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 12 Hello World: Data Flow Objects component pss_top { buffer defines data flow buffer msg_buf { stream and state also defined rand string s; } data may be randomized

disp input defines flow requirement action display_a { output too input msg_buf msg; "moustache" passes model exec body SV = """ elements to templates $display("{{msg.s}}"); """;  Complex data structures }  Data flow modeling  Constrained random data  Reactivity

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 13 Hello World: Data Flow Objects component pss_top { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1send } action hello_world_a { "Hello" send_a send1, send2; display_a disp1, disp2; disp1disp activity { action display_a { send1; send2 input msg_buf msg; disp1;with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2;with {msg.s == "World";}; disp2 """; bind send1.msg disp1.msg; } bind send2.msg disp2.msg; }  } Directed testing when desired }  In-line constraints

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 14 Hello World: Packages componentpackage hw_pkg pss_top{ { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } send_a send1, send2; component pss_top { display_a disp1, disp2; disp1 import hw_pkg::*; activity { action display_a { send1; send2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; bind send1.msg disp1.msg; } bind send2.msg disp2.msg; } }  Additional reuse and } encapsulation

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 15 Hello World: Inferred Actions package hw_pkg { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } send_a send1, send2; component pss_top { display_a disp1, disp2; disp1 import hw_pkg::*; activity { action display_a { send1; send2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; } } }  Abstract partial specifications }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 16 Hello World: Activity Statements package hw_pkg { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } component pss_top { display_a disp1, disp2; send1 disp1 send2 import hw_pkg::*; activity { "Hello" "World" action display_a { select { disp1 send2 disp2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; } } Randomly choose a branch }  Scenario-level randomization }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 17 Activity: Robust Expression of Critical Intent

that T F activity { Action instance traversal i==0 that; an_a do an_a; Anonymous action traversal a9 a10 parallel {a1, a2}; a1 a2 a11 sequence {a3, a4}; Subject to select {a5, a6}; flow/resource a12 schedule {a7, a8}; constraints a3 if (i == 0) {a9;} a11 else {a10;} a4 repeat (2) {a11, a12}; a12 foreach (arr[j]) { a5 a6 a13 a13 with {a13.val == arr[j];}; } a13 a7 a8 a7 a8 a13  Robust scheduling support a8 a7

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 18 Hello World: Extension & Inheritance Type extension extend component pss_top { Inheritance hello_a buffer hello_buf : msg_buf { "Hello" "Hello""Hello""Hello" constraint {msg.s in["Hello", "Hallo"];} "Hello""Hello""Hello" "Hallo" } action disp_h : display_a { disp_h override {type msg_buf with hello_buf}; } Override action hello_a { output hello_buf msg; }  Type extension (aspect- oriented programming) }  Object-oriented inheritance  Type (& instance) override

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 19 Hello World: Object Pools & Binding

extend component pss_top { hello_a hello_p buffer hello_buf : msg_buf { "Hello" "Hello""Hello""Hello" constraint {msg.s in["Hello", "Hallo"];} "Hello""Hello""Hello" "Hallo" } action disp_h : display_a { disp_h override {type msg_buf with hello_buf}; } action hello_a { output hello_buf msg; world_a world_p }

"World" pool hello_buf hello_p; "Welt" bind hello_p *; } disp_w  Constrain data paths  Preserve intent

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 20 Hello World: Scenarios

hello_a hello_a world_a action hello_world_a { activity { "Hallo" "Hello" "Hallo" "Hello" hello_a world_a sequence { do disp_h; disp_h world_a hello_a "Hello" do disp_w; "Hallo" } "Hallo" "Hello" anonymous "World" } "Welt" "World" } action world_a disp_h disp_h disp_h "Welt" traversal "Welt" "World" "Welt" "World"  Multiple scenarios from simple specification disp_w disp_w disp_w disp_w

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 21 Hello World: C++ package hw_pkg { class hw_pkg : public package { PSS_CTOR(hw_pkg, package);

buffer msg_buf { struct msg_buf : public buffer { PSS_CTOR(msg_buf, buffer); rand string s; rand_attr s {"s"}; } }; } }; type_decl hw_pkg_decl;

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 22 Hello World: C++ component pss_top { class pss_top : public component { import hw_pkg::*; PSS_CTOR(pss_top, component);

action display_a { class display_a : public action { PSS_CTOR(display_a, action); input msg_buf msg; input msg {"msg"}; exec body SV = """ exec e {exec::body, "SV", $display("{{msg.s}}"); "$display(\"{{msg.s}}\");"}; """; }; } type_decl display_a_decl;

action send_a { class send_a : public action { PSS_CTOR(send_a, action); output msg_buf msg; output msg {"msg"}; } }; type_decl send_a_decl;

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 23 Hello World: C++

pool msg_buf msg_p; pool msg_p {"msg_p"}; bind msg_p *; bind b {msg_p}; action hello_world_a { class hello_world_a : public action { PSS_CTOR(hello_world_a, action); display_a disp1, disp2; action_handle disp1 {"disp1"}, disp2 {"displ2"}; activity { activity a { select { select { disp1 with {msg.s == "Hello ";}; disp1.with (disp1->msg->s == "Hello"), disp2 with {msg.s == "World";}; disp2.with (disp2->msg->s == "World") } } } }; } }; type_decl hello_world_a_decl; }; type_decl pss_top_decl;

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 24 PSS DSL and C++ Inter-Operability • Two syntax representation of the same single domain language • PSS compliant tools may consume both formats and allow mixing Top can be either one extend component pss_top { Base class can be buffer hello_buf : msg_buf { C++ or DSL constraint {msg.s in["Hello", "Hallo"];} } Instantiating from the action disp_h : display_a { other format is allowed override {type msg_buf with hello_buf}; }  Select your favorite style action hello_a { knowing that you will not be output hello_buf msg; } blocked from integrating pool hello_buf hello_p; other models bind hello_p *; }

a ga ga ga a do_b Partial Specifications b b b b b are Flexible e e e e e

c j f c dj f c dj f c d f c d f action test_top { action test_top { buffer mbuf {…}; stream mstr {…}; do_a a; do_b b; do_b b; do_c c; do_d d; do_c c; action do_a { action do_c { do_e e; do_f f; do_f f; output mbuf m; input mstr s; …}; …}; activity { activity { a; action do_b { action do_d { b; b; input mbuf m; output mstr s; select { select { output mbuf o; …}; parallel { c; d; } c; …}; {e; f;} f; action do_j { } } action do_g { output mstr m; } } output mbuf m; …}; } } …}; DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 26 Resolving a Partial Specificationa

action test_top { abg a activity { b; select { c; a b d e f; } } What combination of known } actions will produce a buf of a buf the correct type? buf b buf What set of actions is needed to b support downstream requirements? str c buf d str What set of actions will str e buf produce a stream of the correct type? buf f Are there any resource g buf c f conflicts that constrain the str j str possible scheduling?

p buf

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 27 A Quick Recap: PSS Gives You…  Reuse  In-line constraints  Composition  Additional reuse and encapsulation  Abstract behaviors  Abstract partial specifications  Retargetable Implementations  Scenario-level randomization  Behavior encapsulation  Robust scheduling support  Behavior scheduling  Type extension  Complex data structures  Object-oriented inheritance  Data flow modeling  Type (& instance) override  Constrained random data  Constrain data paths  Reactivity  Preserve intent  Directed testing when desired  Multiple scenarios from simple specification

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 28 The PSS LRM 1.0

• We highly recommend reading the PSS LRM • Can be downloaded for free on Accellera website: – http://www.accellera.org/images/downloads/standards/pss/Portable_Test_Stim ulus_Standard_v1.0.pdf • Lots of modeling content is provided to leverage the standard strengths

 Not in the LRM? Not PSS!

Verification goal #2: low-power DMA DRAM Flash Power Bus IF Bus IF Bus IF Bus IF Bus IF LTE Bus IF Ext. Modem GPS VIP

Bus IF CPU CPU Bus IF CDMA Modem Bluetooth PHY CPU CPU Bus IF LTE Bus IF Modem WiFi Bus IF NFC Bus IF Modem

Bus IF Bus IF Bus IF Bus IF Int. Display Audio Touchpad Camera VIP Processor Codec The Rest of Verification goal #3: the System performance and stress

Block Decomposing the scenarios into actions System allows reusable library of building blocks DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 31 The LTE Modem Component

Ext. VIP lte_c component lte_c { PHY pktStr pktStr action rx { LTE Modem input pktStr pStr; Bus IF rx↓ tx ↑ output datBuf dBuf; constraint {pStr.size < 200;} Int. datBuf datBuf VIP } action tx { For modeling actions read the input datBuf dBuf; output pktStr pStr; spec and identify key behaviors constraint {pStr.size < 200;} } } Inputs and output should not assume the provider of Rules of correct inputs and the information outputs should be captured in constraints

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 32 Define Data Flow Objects PSS provides packages for package data_flow_pkg{ code reuse enum dir_e {inb=0, outb}; buffer requires sequential producer-consumer execution enum kind_e {video, text, msg}; buffer datBuf { rand fields are randomized rand dir_e dir; rand bit [7:0] length; Ext. stream requires parallel rand bit [31:0] addr; VIP rand kind_e kind; producer-consumer execution PHY } LTE Modem stream pktStr { Bus IF rand dir_e dir; rand bit [15:0] size; Int. bit [47:0] MAC_src; VIP prod_a pktStr cons_a bit [47:0] MAC_dst; rand kind_ecomponentkind; lte_c { } import data_flow_pkg::datBuf; } … }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 33 The VIP Components

extvip_c invip_c

pktStr send ↑ datBuf store↑

rcv↓ pktStr rtrv↓ datBuf

Ext. VIP component extvip_c { component intvip_c { action send { action store { PHY LTE output pktStr pStr; output datBuf dBuf; Modem constraint {pStr.size > 100;} } Bus IF } action rtrv { Int. action receive { input datBuf dBuf; VIP input pktStr pStr; } constraint {pStr.size > 100;} } } }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 34 PSS Model Instantiation Connection of new components pss_top predefined component pss_top is simple – just instantiate them extvip_c component pss_top { send ↓ receive ↑ import data_flow_pkg::*;

pStr_p Ext. pool pktStr pStr_p; VIP pktStr bind pStr_p {xvip.*, lte.*}; lte_c pool datBuf dBuf_p; PHY bind dBuf_p *; LTE Modem rx ↓ tx ↑ Bus IF extvip_c xvip; dBuf_p lte_c lte; Int. VIP datBuf intvip_c ivip; intvip_c } • Now we are ready to create portable scenarios! store ↓ rtrv ↑ These two actions can be used for coherency, stress, • Endless number of scenarios can be performance and more randomized on this model

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 35 Portable Scenario Example action my_scenario { activity { datBuf store ↓ schedule { do lte_c::rx; send ↓ pktStr rx ↓ do lte_c::tx; tx ↑ pktStr receive ↓ } } datBuf }

tx ↑ pktStr receive ↓ • The scenarios are Ext. send ↓ pktStr rx ↓ focus on the intent VIP

PHY store ↓ datBuf LTE Modem datBuf Bus IF • The algebraic constraints of Int. pktStr pktStr the input and the output are tx ↑ receive ↑ send ↓ rx ↓ VIP resolved datBuf • Size < 200 && size > 100

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 36 The Modem Component + Resources What if the Modem is half-duplex? i.e it is illegal to run rx & tx actions at the same time

resource defines a component lte_c { resource object import data_flow_pkg::*; import modem_funcs::*; defaults to size == 1 pool resource mchan_r {…/* struct */}; Ext. declares pool[1] mchan_r mchan_p; VIP lock bind mchan_p *; exclusive access PHY LTE action rx { action tx { Modem input pktStr pStr; Bus IF modem_c mchan_p input datBuf dBuf; output datBuf dBuf; output pktStr dBuf; mchan Int. lock mchan_r mchan; lock mchan_r mchan; VIP constraint {…} constraint {…} rx↓ tx ↑ } } … }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 37 action my_scenario { activity { Portable Scenario Example schedule { do lte_c::rx; datBuf store ↓ do lte_c::tx; } send ↓ pktStr rx ↓ } tx ↑ pktStr receive ↓ }

datBuf Ext. VIP

tx ↑ pktStr receive ↓ PHY pktStr datBuf LTE send ↓ rx ↓ Modem Bus IF store ↓ This is illegal due to lack Int. datBuf VIP of resources

tx ↑ pktStr receive ↑ send ↓ pktStr rx ↓ datBuf

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 38 Parallel Scenario

action my_scenario { activity { parallel { do lte_c::rx; do lte_c::tx; } Solve time error message } } PSS saves you a lot of debug by identifying incorrect scenario early before execution Upfront guarantees with respect to resource, configuration and more

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 39 A Block-to-System Example The key thing is that the scenarios are portable extvip_c The same actions that are defined pktStr send ↑ for IP verification are reusable DMA DRAM Flash Power Bus IF Bus IF Bus IF Bus IF rcv↓ pktStr Bus IF LTE Bus IF Ext. Modem GPS VIP

Bus IF CPU CPU Bus IF lte_c CDMA pktStr pktStr pktStr PHY Modem Bluetooth CPU CPU Bus IF

LTE Bus IF rx↓ tx ↑ Modem WiFi Bus IF NFC Bus IF Modem datBuf datBuf Bus IF Bus IF Bus IF Bus IF Int. Display Audio VIP Touchpad Camera invip_c Processor Codec

datBuf rtrv ↑ The Rest of

store↓ datBuf the System The internal VIP is not needed anymore but a real IP will Block provide the needed input System

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 40 The CDMA Modem Component: more of the same … package modem_funcs { more function imports function bit [47:0] CDMA_MAC_src(); function bit [47:0] CDMA_MAC_dst(); cdma_c function bit [31:0] CDMA_data_buf(); pktStr pktStr } component cdma_c { rx↓ tx ↑ import data_flow_pkg::*; extend component pss_top { Ext. VIP import modem_funcs::*; ... datBuf datBuf cdma_c cdma; PHY action rx { }; CDMA prepost-solve-solve blockblock runs Modem execexec input pktStr pStr; PSS Connectivity is seamless.Bus IF runsbefore after randomization randomization output datBuf dBuf; This component is now connected

extvip_c

pktStr Int. send ↑ constraint {pStr.size < 400}to all other sub-systems DMA DRAM Flash Power ↓ rcv pktStr VIP lte_c Bus IF Bus IF Bus IF Bus IF pktStr pktStr Bus IF rx↓LTE tx ↑ Bus IF ModemdatBuf datBuf GPS Bus IF CPU CPU Bus IF exec pre_solve { cdma_c CDMA exec post_solve { pktStr pktStr Modem Bluetooth rx↓ tx ↑ CPU CPU Bus IF Bus IF

datBuf datBuf pkt.MAC_src = CDMA_MAC_src(); WiFi Bus IF NFC pStr.addr = CDMA_data_buf(); Modem Bus IF Bus IF Bus IF Bus IF } pkt.MAC_dst = CDMA_MAC_dst(); Display Audio Touchpad Camera Processor Codec } …

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 41 SW Operations Modeling

component cpu_c { every operation locks the core cpu_c abstract action sw_operation { lock core_s core;

datBuf }; For multi-threading PSS also allows resources to be shared read action mem_read : sw_operation { input datBuf src_data; component pss_top { write }; ... PSS Connectivity done!

datBuf action mem_write : sw_operation { pool [4] core_s chan; output datBuf dst_data; bind core_s *; datBuf };

}; extvip_c pktStr copy ↑ send DMA DRAM Flash Power ↓ action mem_copy : sw_operation { rcv pktStr lte_c Bus IF Bus IF Bus IF Bus IF pktStr pktStr Bus IF

cpu_c datBuf rx↓LTE tx ↑ Bus IF input datBuf src; ModemdatBuf datBuf datBuf GPS read Bus IF CPU CPU Bus IF cdma_c CDMA write pktStr pktStr output datBuf dst; Modem datBuf Bluetooth

rx↓ tx ↑ CPU datBuf CPU Bus IF Bus IF copy datBuf WiFi datBuf Bus IF datBuf NFC constraint c1 {src.size == dst.size;} Modem constraint c2 {src.kind == dst.kind;} Bus IF Bus IF Bus IF Bus IF Display Audio Touchpad Camera }; Processor Codec };

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 42 The Display Component C++ input format provides the same constructs with the exact PSS_ENUMclass screen (kind_e : public, videoresource, photo);{…}; same powerful semantic class : public buffer { DMA DRAM Flash Power PSS_CTOR (, buffer); declare randomizable enum Bus IF Bus IF Bus IF Bus IF Bus IF

rand_attr kind {"kind"}; Bus IF LTE …}; constructor macro Modem GPS

Bus IF CPU random attribute CPU Bus IF CDMA class display_c : public component { Modem Bluetooth CPU CPU Bus IF PSS_CTOR(display_c, component); Bus IF WiFi Bus IF NFC Modem class play : public actionconstraint{ PSS_CTOR(play, action); display_cBus IF Bus IF Bus IF Bus IF Display Audio Touchpad Camera input <> data{"data"}; ProcessordatBuf Codec constraint c {data->kind == video}; play↓ lock lk {"lk"}; …}; declare type type_decl play_d; Note that screen can only System }; accept a video type_decl display_d; DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 43 Example #1: Text Message with Photo Test requirement: in parallel 1. Capture a video and upload via the modem 2. Send a message to from the keyboard 3. Stress the interconnect/DDR with traffic DMA DRAM Flash Power action my_example1 { Bus IF Bus IF Bus IF Bus IF Bus IF

activity { Bus IF LTE parallel { Modem GPS

Bus IF CPU sequence { CPU Bus IF CDMA do capture; Modem Bluetooth CPU CPU

do tx; Bus IF Bus IF bind capture.dbuf tx.dbuf; WiFi Bus IF NFC } Modem do txt_msg; Bus IF Bus IF Bus IF Bus IF Display Audio repeat (10) { Touchpad Camera schedule { Processor Codec do dma_c::xfer; do dma_c::xfer; do cpu_c::mem_copy; } } System }} DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 44 Example #2: Partially Specified Scenario action my_example2 { Test requirement: activity { 1. Display long video while parallel { decoding a long video tb_c do play with {play.dBuff.size > 300;} do decode with {decode.dBuff.size > 300;} bdload But wait, why not send the }} datBuf same cdma rx output to both? Introducing a DMA copy cdma_c lte_c dmatb_c_c pktStr pktStr datBuf may solve the issue rx↓ rx↓ copybdload↓ Can the TB backdoor write datBuf datBuf datBuf into an area that the play can read from? PSS allows tools to make dataBuf dataBuf easy or hard inferences of LTE constraint that it is solutions that users did smaller than 200 not think of decode play

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 45 Example #3

action my_example3 { activity { DMA DRAM Flash Power repeat (10) { Bus IF Bus IF Bus IF Bus IF

schedule { Bus IF

play_a Bus IF do audio_c::play_a; LTE Modem GPS do extvip_c::receive;

Bus IF CPU extvip_a CPU Bus IF do diplay_c::play_a; CDMA Modem Bluetooth doplay_atxt_msg_aextvip_a ; play_a txt_msg_a CPU CPU Bus IF play_a } Bus IF WiFi Bus IF NFC } Modem } txt_msg_a Bus IF Bus IF Bus IF Bus IF } Display Audio 10 Touchpad Camera Processor Codec or any parallel or serial combination

System

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 46 Remember This Scenario?

This is our sub-system/IP scenario

that can run on full system! DMA DRAM Flash Power Bus IF Bus IF Bus IF Bus IF Bus IF action my_scenario { LTE Bus IF activity { Modem GPS

Bus IF CPU schedule { CPU Bus IF CDMA do lte_c::rx; Modem Bluetooth CPU CPU Bus IF do lte_c::tx; Bus IF WiFi Bus IF NFC } Modem } } Bus IF Bus IF Bus IF Bus IF Display Audio Touchpad Camera Processor Codec We can realize/implement the same scenario on full system

System

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 47 Layering in Power Scenarios extend component pss_top { outputs a radioState action radio_on_aradio_off {{ output radioState out_s; flow object LTE CDMA VIP VIP may only run if previous constraint was out_s.prev.rstate == offon;; PHY PHY rstate off BFM/ LTE CDMA constraint CPU Modem Modem set next rstate to on out_s.rstate == onoff;; Bus IF Bus IF Bus IF

exec body { turn on the radio radio_onradio_off();(); Bus IF Bus IF } MEM Audio } Codec } }

Subsystem

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 48 Layering in Power Scenarios extend component pss_top { rstate==on radio_on action radio_idle { input radioState in_s; on lte. constraint in_s.rstate == off; LTE CDMA radioState VIP VIP rx ↓ } PHY PHY on cdma. action test { BFM/ LTE CDMA CPU Modem Modem tx ↑ activity { Bus IF Bus IF Bus IF select { do radio_idle; rstate==off radio_off schedule { Bus IF Bus IF do audio_c::play; MEM Audio off do lte_c::tx; Codec radio_idle } } } } Subsystem }

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 49 Portable Stimulus Coverage

• PSS provides full functional coverage on top of the concise behavioral model – Allows capturing coverage goals that are impractical in any other way Actions model captures the – Due to the declarative nature of PSS the coverage goal infinite legal scenario space can direct the randomization • Coverage constructs style derived from SV – Support cross, illegal, ignore and others == – Keyword is change from covergroup -> coverspec Coverage capture the • Supported coverage verification intent – Data structure coverage – Action coverage – Scenario (compound action) coverage – Resource coverage

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 50 Coverage Example action my_example1 { dma_C::xfer xfer1; dma_C::xfer xfer2; camera_c::capture capture1; extend action my_example1 { activity { coverspec my_example1_goals parallel { (my_example1 t) { sequence { xfer1_chan: coverpoint capture1; t.xfer1.channel.instance_id; do tx; xfer2_chan: coverpoint bind capture.dbuf tx.dbuf; t.xfer2.channel.instance_id; } chan_cross: cross xfer1_chan, do txt_msg; xfer2_chan; repeat(10){ video_format: coverpoint schedule { t.capture1.dBuf.video_format; xfer1; } xfer2; } do cpu_c::copy; } } }} DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 51 Coverage Maximization

• Lots of coverage maximization can be achieved on top of UVM – No need to adopt PSS for config class or packets’ attributes • However, the PSS allows further maximization – Involves also use-cases and flows – Of internal behaviors and usage of resources – Enables static decisions that allows coverage review before launching simulations – Powerful ability to modify timing to fulfil coverage goals • This is enabled via the PSS rule based approach

• In the tutorial examples we called either C firmware or UVM register sequences to program the DUT • Considering a set of constructs for capturing device drivers in an abstract way – Obviously, programing registers and setting up descriptors – But also, interrupt properties and synchronization, control flow and more • This is not part of the PSS 1.0 release – Will be added in future releases Scenarios/Use Cases

Driver API Interface

HW/SW Interface

53 Advantages of Portable Stimulus

• Declarative language/library enables automation – Partial specification expands to multiple scenarios – Constrained-randomization at the scenario level • Easily composable, reusable and portable • Maps to implementations on multiple platforms – Leverage existing infrastructure, sequences, methods – Apply scenario randomization and coverage to system-level tests (in C, too!)

• Established Communications – Main PSWG Site http://www.accellera.org/community/portable-stimulus • Central site to access standards, draft and tutorial for PSS – Public forum for 1.0 feedback http://forums.accellera.org/forum/44-portable-stimulus-10 • Please review the standard and provide feedback. We truly appreciate your feedback! • 1.1 Activities – 1.0 Errata release planned – PSWG pioneering requirements management tool deployment at Accellera – Moving to rigorous tracking based on requirements (not only Mantis)

DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 55