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Portable Test and Stimulus: the Next Level of Verification Productivity Is Here

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Portable Test and Stimulus: the Next Level of Verification Productivity Is Here Portable Test and Stimulus: The Next Level of Verification Productivity is Here On behalf of the Accellera Portable Stimulus Working Group Sharon Rosenberg, Cadence Design Systems Pradeep Salla, Mentor Graphics © Accellera Systems Initiative 1 Agenda • Introduction: What and Why? • “Hello World”: Language Concepts • Block-to-System Example © Accellera Systems Initiative 2 It's an SOC World • Design complexity continues to increase – Outstripping verification productivity SIMULATION • System-level state space too big for STIMULUS effective UVM constrained-random EMULATION • Multiple verification platforms • Need to reuse Test Intent FPGA PROTO – Higher abstraction IP BLOCK SUBSYSTEM FULL SYSTEM – Block to system – Different design versions DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 3 The Portable Stimulus Journey PSPWG PSWG 2014 2015 2017 2018 Portable Stimulus Working Group Participants AMD IBM OneSpin AMIQ EDA Intel Qualcomm Analog Devices Mentor Semifore Breker National Instruments Synopsys Cadence NVIDIA Texas Instruments Cisco NXP Semiconductors Vayavya Labs Cypress Semiconductor DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 4 Reuse of Test Intent Across Platforms/Users • Single specification of test intent is critical Portable Stimulus • Constrain and randomize at the Scenario Level by capturing: – interactions – dependencies UVM C – resource contention • Abstraction lets tools IP BLOCK SUBSYSTEM FULL SYSTEM automate test generation – Multiple targets – Target-specific SIMULATION EMULATION FPGA PROTO customization DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 5 The Advantages of a Declarative Specification . Most SoC tests are directed . Declarative tests let the tool do the work . Manually determining . Explore all possible options turn-by-turn directions . Easy to optimize . Hard to account for new stops . Guided by preferences . Route limited by driver's biases . Declarative Portable Stimulus Description enables automation and analysis . Automation makes test intent portable . Enables retargeting to different environments . Automation makes test techniques portable . Bring automated constraint-driven tests to SoC TFitz, Portable Stimulus IP to SoC, DVClub-EU 6 Sept, 2018 Projected Tool Flow DSL DSL Compiler Gen-time or Run-time Constraint Test Scenario model Solver Solved Model Generator + Constraints C++ Compile / Compile Link / Run Link UVM UVM Sync C-test Sequences Sequences PSS Abstract AXIAXI VIPVIP TB Scenario AXI CPUVIP Model DMAC DMAC UART UART DDR UART UART DDR VIP MEM VIP MEM UVM Testbench SoC Testbench DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 7 What Portable Stimulus Is NOT • NOT a UVM replacement • NOT a reference implementation • NOT one forced level of abstraction – Expressing intent from different perspectives is a primary goal • NOT Monolithic – Representations would typically be composed of portable parts • NOT Two standards – PSS/DSL and PSS/C++ input formats describe 1:1 semantics – Tools shall consume both formats • NOT Just stimulus – Models Verification Intent – Stimulus, checks, coverage, scenario-level constraints – Portable test realization DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 8 "HELLO WORLD": LANGUAGE CONCEPTS © Accellera Systems Initiative 9 Hello World: Atomic Actions component groups elements for reuse and composition component pss_top { hello action hello_world_a{ action defines behavior world exec body SV = """ exec defines implementation $display("Hello World"); """; } } class hello_world_a_seq_1 extends uvm_sequence; Reuse `uvm_object_utils(hello_world_a_seq_1) Composition virtual task body(); Abstract behaviors $display("Hello World"); Retargetable endtask Implementations endclass DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 10 Exec Block Types • Specify mapping of PSS entities to their implementation test.sh Solve platform Target platform test.c header #include <stdint.h> gcc –c test.c –DBARE_METAL declaration void declared_func() { … pre_solve run_start file } constraint solving void test_main() { do_run_start(); post_solve fork_threads(); do_run_end(); Runtime Runtime } scheduler scheduler void thread0() { Could be SV … body body or other language bodybody … bodybody // step N body body do_body(); … }; void thread1() { … } run_end Could be multiple threads on one core, or threads running on different cores DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 11 Hello World: Compound Actions action hello_world_a { compound action hello_a h; hello traverses other actions world_a w; activity activity { world defines scheduling h; w; } } void hello_world_a_test_1() { } printf ("Hello\n"); printf ("World\n"); } Behavior encapsulation Behavior scheduling DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 12 Hello World: Data Flow Objects component pss_top { buffer defines data flow buffer msg_buf { stream and state also defined rand string s; } data may be randomized disp input defines flow requirement action display_a { output too input msg_buf msg; "moustache" passes model exec body SV = """ elements to templates $display("{{msg.s}}"); """; Complex data structures } Data flow modeling Constrained random data Reactivity DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 13 Hello World: Data Flow Objects component pss_top { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1send } action hello_world_a { "Hello" send_a send1, send2; display_a disp1, disp2; disp1disp activity { action display_a { send1; send2 input msg_buf msg; disp1;with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2;with {msg.s == "World";}; disp2 """; bind send1.msg disp1.msg; } bind send2.msg disp2.msg; } } Directed testing when desired } In-line constraints DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 14 Hello World: Packages componentpackage hw_pkg pss_top{ { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } send_a send1, send2; component pss_top { display_a disp1, disp2; disp1 import hw_pkg::*; activity { action display_a { send1; send2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; bind send1.msg disp1.msg; } bind send2.msg disp2.msg; } } Additional reuse and } encapsulation DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 15 Hello World: Inferred Actions package hw_pkg { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } send_a send1, send2; component pss_top { display_a disp1, disp2; disp1 import hw_pkg::*; activity { action display_a { send1; send2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ send2; "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; } } } Abstract partial specifications } DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 16 Hello World: Activity Statements package hw_pkg { action send_a { buffer msg_buf { output msg_buf msg; rand string s; } send1 } action hello_world_a { "Hello" } component pss_top { display_a disp1, disp2; send1 disp1 send2 import hw_pkg::*; activity { "Hello" "World" action display_a { select { disp1 send2 disp2 input msg_buf msg; disp1 with {msg.s == "Hello ";}; exec body SV = """ "World" $display("{{msg.s}}"); disp2 with {msg.s == "World";}; disp2 """; } } Randomly choose a branch } Scenario-level randomization } DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 17 Activity: Robust Expression of Critical Intent that T F activity { Action instance traversal i==0 that; an_a do an_a; Anonymous action traversal a9 a10 parallel {a1, a2}; a1 a2 a11 sequence {a3, a4}; Subject to select {a5, a6}; flow/resource a12 schedule {a7, a8}; constraints a3 if (i == 0) {a9;} a11 else {a10;} a4 repeat (2) {a11, a12}; a12 foreach (arr[j]) { a5 a6 a13 a13 with {a13.val == arr[j];}; } a13 a7 a8 a7 a8 a13 Robust scheduling support a8 a7 DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 18 Hello World: Extension & Inheritance Type extension extend component pss_top { Inheritance hello_a buffer hello_buf : msg_buf { "Hello" "Hello""Hello""Hello" constraint {msg.s in["Hello", "Hallo"];} "Hello""Hello""Hello" "Hallo" } action disp_h : display_a { disp_h override {type msg_buf with hello_buf}; } Override action hello_a { output hello_buf msg; } Type extension (aspect- oriented programming) } Object-oriented inheritance Type (& instance) override DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 19 Hello World: Object Pools & Binding extend component pss_top { hello_a hello_p buffer hello_buf : msg_buf { "Hello" "Hello""Hello""Hello" constraint {msg.s in["Hello", "Hallo"];} "Hello""Hello""Hello" "Hallo" } action disp_h : display_a { disp_h override {type msg_buf with hello_buf}; } action hello_a { output hello_buf msg; world_a world_p } "World" pool hello_buf hello_p; "Welt" bind hello_p *; } disp_w Constrain data paths Preserve intent DVCon Europe 2018 Portable Stimulus Tutorial, Accellera PSWG 20 Hello World: Scenarios hello_a hello_a world_a action hello_world_a { activity { "Hallo" "Hello" "Hallo" "Hello" hello_a world_a sequence { do disp_h; disp_h world_a hello_a "Hello" do disp_w; "Hallo" } "Hallo" "Hello" anonymous "World" } "Welt" "World" } action world_a disp_h disp_h disp_h "Welt" traversal "Welt" "World" "Welt" "World" Multiple
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