Single port to dual port conversion for an LSI memory
Item Type text; Thesis-Reproduction (electronic)
Authors Adams, Dennis Lee, 1948-
Publisher The University of Arizona.
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Download date 24/09/2021 02:57:46
Link to Item http://hdl.handle.net/10150/554945 SINGLE PORT TO DUAL PORT CONVERSION FOR
AN LSI MEMORY
by
Dennis Lee Adams
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL ENGINEERING
In Partial Fulfillment of the Requirements For the Degree of
MASTER OF SCIENCE
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 7 5 STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of re quirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers mder rules of the Library.
Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the najor department or the Dean of the Graduate College when.in his judg- nent the proposed use of the material is in the interests of scholar ship. In all other instances, however, permission must be obtained from the author.
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
Professor of EMetrical Engineering TABLE OF CONTENTS
Page
LIST OF ILLUSTRATIONS ...... iv
LIST OF TABLE S ...... V
ABSTRACT ...... vi
CHAPTER
1. INTRODUCTION ...... I
2. DPM OPERATION ...... 7
Port One Electrical Characteristics ...... 7 Port One Write Operation ...... -V 9 Port One Read Operation ...... 10 Port Two Electrical Characteristics ...... 11 Port Two Write Operation ...... 11 Port Two Read Operation ...... 12 Port Three Electrical Characteristics 12 Port Three Write Operation ...... 13 Port Three Read Operation ...... 14 DPM Access Priority ...... 15
3. CONTROL SEQUENCER ...... 16
4. PHYSICAL ASSEMBLY ...... 27
Construction ...... 27 Operation ...... 29
5. OPERATIONAL CHECKOUT ...... 32
6. CONCLUSION ...... 35
APPENDIX A: WIRING LIST ...... „ ,. „ . 37
APPENDIX B: ELECTRICAL DRAWINGS ...... „ 53
LIST OF REFERENCES ...... 60 LIST OF ILLUSTRATIONS
Figure Page
1. CDC Architecture 2
2, Computer Laboratory Architecture , „ „ „ . „ „ „ „ „ „ „ „ „ 4
3. DEM Communication Connections 6
4. Data, Address and Control Signal Flow 8
5. Control Sequencer from AHPL Description o 25
6„ Pin Side View of IC Bars and Slot Locations 28
7. Power Control Panel 31
iv LIST OF TABLES
Table Page
1. Signal Mnemonics and Their Definitions Used in AHPL „ , „ 18
2. Complete AHPL Sequence ...... 23
v ABSTRACT
This thesis will discuss, design and report on the construction of an interface unit that will convert a standard LSI solid state memory into a dual-port memory. The interface unit will have three communica tion ports. The first port will connect to a PDP-11/40 UNIBUS, the second to a 16-bit microprocessor, and the third to an Electronic
Memories Microram 30Q0N 8K x 20^-bit memory. The design is such that the interface unit will appear as an 8K block of memory to the PDP-11/40 and microprocessor ports and as a single user requesting memory service to the Microram memory port. CHAPTER 1
INTRODUCTION
Digital computers usually have only one central processing unit
(CPU) which must perform all operations. This single CPU executes all instructions, whether they are directly related to some user program or housekeeping duties of the computer. While considerable effort has been directed towards the efficient utilization of CPU time 5 one stumbling block remains; all operations must be performed sequentially. It is therefore reasonable to assume, that if a system had more than one CPU, it would be able to perform some instructions or operations simultaneous ly. This assumption requires the operations be independent. Several manufacturers have capitalized on this idea and have produced computing systems that produce a high rate of throughput. The Control Data 6000 series is a classic example.
Control Data computers employ one or two fast central processing units connected to a large memory (see Figure 1). Also connected to the memory are ten smaller and slower processors which are called Peripheral
Processors. In this scheme, the Peripheral Processors perform all I/O operations, allowing the main CPU to perform the arithmetic and logical operations. As the I/O operations are usually very slow, the main CPU can be executing several programs sequentially while the Peripheral
Processors are executing the I/O operations in parallel. The central
1 TEN I/O CPU(S) MEMORY PERIPHERAL DEVICES
< TV PROCESSORS V
Figure 1. CDC Architecture.
N> communications point in this system is the multiport memory, A memory,
such as this allows many devices to read or store data at selected memory locations. This in itself is not significant until the concept of
interprocessor communications is realized. The memory is no longer a
storage device, but a communications device. The memory is now a means
for passing data from one processor to another or programming one
processor with another. Variations of this scheme are presented in
Reference 1.
Dr. Korn*s paper entitled, HA Comparison of Interprocessor Com munication Schemes,11 discusses methods in which one processor may
communicate with another. After discussion of various schemes and their advantages and disadvantages, it was concluded that dual-port memories are the most economical and efficient method for interprocessor communi
cations ,
Reference 2 proposes a computer laboratory that would employ a
DEC PDP-11/40, two dual-port memories, two microprocessors, and assorted
I/O and storage devices as shown in Figure 2. Under this scheme, the
PDP-11/40 would place an object program into the dual-port memory along with any data the program would require. The microprocessor would then execute the program. These programs would be similar to large sub routines, such as integration routines or fast fourier transforms.
When the microprocessor had finished executing the program, it would place the answer or results into a specified location in the dual port memory and signal the PDP-11/40 that the computation was completed.
The signaling could be accomplished by the microprocessor placing an yp yP
0 0
I/O Other DPM DPM Devices Memory
7 Y / /X
PDP-11/40
Figure 2. Computer Laboratory Architecture. indicator in a "mail box" memory location that the PDP-11/40 would
periodically interrogate. A microprocessor to PDP-11/40 interrupt
routine could also be employed. Using this computer structure, many
programs could be executed in significantly less time than would be the case in computers with only one CPU0 The key to this system is the dual-port memory (DPM).
The DPM will consist of a LSI single-port memory and an inter face control unit with three ports, as shown in Figure 3. The DPM will permit the microprocessor or the PDP-11/40 to read or write into any location in the LSI memory. In this manner the computers may use the
DPM as a storage device or a communications medium. It is a DPM such as this that is discussed and designed in this thesis. MICROPROCESSOR INTERFACE CONTROL PDP-11/1+0 yX UNIT
LSI MEMORY
Figure 3. DPM Communication Connections. CHAPTER 2
DPM OPERATION
The dual-port memory (DPM) interface unit will have three ports.
Connected to these three ports will be the UNIBUS of a PDP-11/40, a 16- bit microprocessor and an Electronic Memory, Microram 3QQ0N, 8K x 20 bit
LSI memory. Although this memory has 20-bit words, only 16 bits will be used.
Ports one and two will appear as an 8K block of memory to the microprocessor and PDP-11/40 while port three will act as a single memory user to the LSI memory. Only 16-bit read or write operations will be used, making it unnecessary to take advantage of byte or split cycle operations. The functional layout with address, data, control and signal lines of the DPM is shown in Figure 4.
Port One Electrical Characteristics
Port one must be electrically and operationally compatible with the DEC PDP-11/40 UNIBUS. The control, data and address lines that will be used in port one communications are as follows:
MSYN--master sync from PDP-11/40
SSYN-"slave sync to PDP-11/40
A01-A13--address lines from PDP-11/40
D0-D15--bidirectional data lines
Cl— read/write control line h / V 1
R W Cl DA2 U DT2 DPM CONTROL SEQUEN MSYN CER AND DATA/ADD SSYN N MICROPROCESSOR DAE Port RESS BUS LOGIC Port AI2 Two One All I DUBUS DI2 B .MDO U < = S Port Three
vjA a n H o H on I / J < S g s & BCL g A \ N - vt v
MICRORAM 3000N MEMORY
Figure 4. Data, Address and Control Signal Flow. 9
The DIM will only accept read or write operations from the
PDP-11/40, Therefore3 the DFM control logic will decode only the Cl
UNIBUS control line. The C0 UNIBUS control line indicates whether the operation is to be a Read-Pause-Write (split-cycle) operation which will not be employed. Address line A00 is also ignored because only 16-bit word transfers are required, (Line A00 indicates whether the high or low 8-bit byte will be transferred, but this operation is also excluded from this design,)
The PDF-11/40 uses a master-slave bus signaling scheme. That is, when one device wishes to communicate with another it must sense whether the bus busy line (BBSY) on the UNIBUS is high, indicating the bus is currently being used. If the bus is not in use, the device may raise the bus busy line of the UNIBUS, thus becoming master of the bus. The bus master now places the memory address on the UNIBUS along with the proper command code. If it is a write operation, data is placed on the bus at this time. When these signals have settled and have been decoded by the devices on the bus, the bus master asserts the master sync line
(MSYN), The slave device, which has recognized the address as its own and has decoded the command, may now begin executing the command, This is a very abbreviated explanation of UNIBUS theory and operation, A complete explanation may be found in Reference 3,
Port One Write Operation
If the bus master wishes the slave to store data (a write opera tion) , it will cause the Cl line to be high. The slave will decode this and clock in the data from the data lines. The slave will indicate to 10
the master that the bus may be cleared by causing the SSYN line to go
high. During this time the data will be stored, at the indicated address0
The bus master removes the address9 data, command and MSYN signals from
the bus when it senses SSYN being high. The slaves remove the SSYN
signal when the bus master has removed the MSYN signal from the bus.
When the slave has removed the SSYN signal, the bus master removes the bus busy signal allowing other devices to become bus masters and use
the bus.
Port One Read Operation
If a master device wishes to perform a read operation, it gains control of the bus as previously stated. Data lines will not be asserted during this portion of the read operation but the bus master will cause the Cl line to be low indicating a read operation. When the slave has recognized the command and decoded the address, it must remove the data from the addressed memory, location and place it on the UNIBUS, When the slave device has placed the data on the UNIBUS, it must raise the
SSYN line indicating the data is on the bus. The bus master will then clock in the data from the UNIBUS and ranove the MSYN signal indicating to the slave device that it may remove the data from the UNIBUS. The bus master also removes the address and command signals at this time.
When the slave device senses the MSYN line has gone low, it removes the data and SSYN signals from their respective lines. When the bus master senses the SSYN signal has gone low, it removes the bus busy signal allowing other devices to use the bus. Port Two Electrical Characteristics
Port two will connect to a microprocessor that has a 100 nano second instruction cycle time. The exact signaling and data transfer requirements of the microprocessor are unknown at this time. Therefore a universal signaling scheme will be provided at port two. If required, input or output buffer registers may easily be added at a later date.
The control, data, and address lines that will be used in port two com munications are as follows:
A-«read request from p,p
W — write request from pp .
DA2— data available to p,p
DT2--data taken to (j,p
DAE--data/address enable to ^p
AI2--address lines from p,p
DI2--data lines from p,p
MD0--data lines to p,p
Port Two Write Operation
A write operation begins with the microprocessor causing the write request line (W) to go high. The DPM control logic will cause the data/address enable (DAE) line to go high when the request for service has been recognized. This signal may be used to enable the data and address lines if the microprocessor has tri-state outputs.
When the DPM has stored the data, a positive data-taken pulse
(DT2) will be sent to the microprocessor indicating the data has been removed from the data-in lines. The microprocessor must lower the write 12 request line when the data-taken pulse is received* If the W line stays high, another write cycle will be performed by the DPM*
Port Two Read Operation
A read cycle begins with the microprocessor raising the read- request line (R)* The DPM control will return a DAE signal to the micro processor when the request for service has been recognized* DPM control will send a long positive data available (DA) pulse to the microprocessor when the requested data is on the data-out lines (MDO)« This data will
/ be valid for the duration of the DA pulse (approximately 200 nanoseconds)«
The raising of the DA line means the microprocessor must lower the R line or another memory read cycle will be performed*
Port Three Electrical Characteristics
Port three will interface with an Electronic Memories Microram
3000N NMOS semiconductor memory* The memory contains 8K of 20-bit words with a 300 nanosecond memory cycle time and 180 nanoseconds data access time*
Because both the PDP-11/40 and microprocessor are 16-bit machines, only 16 bits of each 20-bit memory word will be used* No connections will be made to the four most significant bits* The extra features available with this memory will not be used because they are not part of the DPM requirements* The wiring list will indicate if the controlling pins are to be connected to a high or low state to inhibit these fea tures* A complete description of the memory and its operation is con tained in Reference 4* The data, address and control lines for port three are as follows: 13
MBI--Data lines to memory
MDO--Data lines from memory
MAI--Address lines to memory
RP--Initiate line to memory
BCL~~Read/write line
MB--Memory busy line
DA3--Data available line
Port Three Write Operation
A memory write operation must begin with both the memory busy line (MB) and the initiate line (RP) in a high state, MB low indicates the memory is currently in a memory cycle and cannot accept a request for service, RP must be high for a minimum of 50 nanoseconds before a request for service is made. The data is placed on the data-in lines
(DI00-DI15), the address is placed on the address lines (A00-A12) and the byte control line (BCL) is held low enabling a write cycle to be executed. When the data, address and BCL lines have stabilized, the initiate line (RP) goes low starting the memory write cycle. This line and the data and address lines must be stable for a minimum of 50 nanoseconds. In Chapter 3, the DPM control sequencer will be designed to hold the RP line low for 125 nanoseconds, then return to its high rest state. The data-in lines and address lines may change to any state after this 50 nanosecond period. When the memory senses RP going low, it strobes the address and data lines and causes its memory busy line to go low indicating a busy state. When memory busy is low, all requests for service are ignored. 14
The memory will store the data at the specified address and
change the MB line to a high state (non-busy) approximately 300 nano
seconds after it receives the request pulse. The memory is now ready
to accept another request for service. During this memory cycle, the
data available line (DA) will be in a high state,indicating the data on
the data-out lines (D000-D015) are invalid.
Port Three Read Operation
The read operation must begin with the initiate line and the memory busy line in a high state. The address of the desired memory lo
cation is placed on the address lines and the byte control line is held
high enabling a read operation. The states of the data-in lines are
immaterial during a read operation. When the lines have settled, the
initiate line (RP) goes low causing the memory to begin its read cycle.
As before, all input lines must be held stable for 50 nanoseconds. The memory will cause its memory busy line to go low indicating another re
quest for service will not be accepted, and the data available line (DA) will go high indicating the data-out lines (D000-D015) are invalid.
Approximately 180 nanoseconds after the initiate pulse is received, the memory will cause its data-available line to go low indicating the data
on the data-out lines are the true contents of the requested memory
location. The data will remain valid for approximately 120 nanoseconds.
The data-available line will return to a high state when the output data
are no longer valid. 15
PPM Access Priority
The PPM will service each port upon request<, but there must be a priority arbitration circuit for the case of a simultaneous request.
The microprocessor will be performing functions as directed by the
PPP-11/40, therefore, the PPM usage priority will be given to the micro processor. If a decision is made later that the usage priority should alternate between the ports, the simple addition of a flip-flop to the priority logic would be required. The priority circuit consists of a simple logic decoder with the appropriate synchronization procedures.
The requests for service from ports one and two must be synchro nized before they enter the priority logic. Failure to do this may cause the PPM to start servicing port one then stop and begin servicing port two. Such actions may cause the PPM to go into undefined states or produce invalid data. Several circuits are available for synchroniza tion of external signals but probably the simplest is the P flip-flop.
This method, along with the 8 MHZ system clock, will be used in the PPM to synchronize the external signals. CHAPTER 3
CONTROL SEQUENCER
The heart of any digital system is the control sequencer. This array of decision-making logic is truly what makes a complex digital machine work properly and execute commands as the designers intended.
For this reason, considerable concern and forethought should be expended on the control sequencer.
There are basically two types of control sequencers: hard wired and microprogramable.
Microprogramming is currently the most popular for systems where versatility and emulation are a must; however, microprogramming falls 1 short when high clock rates are necessary, ROMS that can support micro instruction clock rates of 8 MHZ do exist, but are very expensive. On the other hand, hardwired control sequencers can easily employ very high clock rates at very little expense. With future changes, of microinstruc tions being of little concern and high clock rates being mandatory, a hardwired control sequencer is easily justified for the DPM.
If the operations that a digital machine is required to perform are known, a control sequencer may be described in A Hardware Programming
Language (see References 5 and 6) from which a complete circuit.diagram may be drawn.
16 17
By recalling the operational characteristics of the devices involved as described in Chapter 2 and defining the data, address, and control signals, the control sequencer may be described briefly in AHPL.
The abbreviation for signals that will be used are listed in Table 1.
AHPL can describe the synchronization of external signals into a system with the synchronization function, SYN(f). This is translated into hardware as a D-type flip-flop. The unsynchronized signal is con nected to the D input and the synchronized signal or its complement will appear at the Q or Q outputs respectively. Using this, two func tions are defined which are used in the priority arbitration circuit:
SYN (PDF) = SYN(SSYN A MB A MSYN A Al)
SYN (pP) = SYN(MB A (R V W))
These functions are used in control state one of the AHPL sequence which determines which operation will be performed.
1. -((Cl A SYN(PDP) A SYN(p,P)), (Cl A SYN(PDP)/\ SYN(^P)),
(SYN(p,P) A W), (SYN(^P)A R), ((CIA SYN(PDP) A SYN(M,P))V
(Cl A SYN(PDP) A SYN(p,P)) V (SYN^P) A W) V (SYN(^P) A R)))/
(2,6,9,12,1)
State 1 decodes as.
Go to State: 2 for a port one read operation
6 for a port one write operation
9 for a port two write operation
12 for a port two read operation or stay in state 1 to honor a request for service if none of the previous conditionals are satisfied. 18
Table 1, Signal Mnemonics and Their Definitions Used in AHPL,
Signal Definitions
D01(16) Output buffer register to port one
Cl Read or write command from UNIBUS
All Address lines from port one
DUBUS . Bi-directional data lines at port one
MSYN Master Sync from port one
R Read request from port two
W Write request from port two
AI2 Address lines from port two
DI2 Data input lines from port two
MDO Data output lines from memory
MB Memory busy signal from memory
DAS Data Available from memory
SSYN Slave sync to port one
DAE Data address enable
DA2 Data available to port two
DT2 Data taken to port two
MAI Address lines to memory
MDI Data input lines to memory
RP Initiate line to memory
A1 Output of device address selector 19
The port one read operation is described as follows;
. 2. MAI = All; RP = 0; BCL = 1
-(1;3>
3. D0UMD0
' • . ■ - 1 - . 4. DUBUS = D01; SSYN = 1
-»(MSYN)/ (4)
5. DEAD END
State 2 gates the address from port one to the memory, makes BCL high indicating a read operation, and makes RP low causing the memory to per form a read operation. The unconditional branch causes control to trans fer to two states, state 1 and state 3. States 3 through 5 control the asynchronous communication with the PDP-11/40. Because asynchronous hand-shaking signals are sometimes time consuming, it is possible that this procedure could take longer than the 300 nanoseconds cycle time of the Microram memory. To utilize the high speed of the memory, control is transferred to state one, but cannot leave that state until the memory is not busy (indicated by MB being high). The data requested by this read operation will be transferred by state 3 into an output buffer register so it will be available for later use.
It is possible that the data would be valid at the Microram memory outputs for the duration) of the asynchronous communications but worst-case conditions (a memory request from port two when the memory becomes not busy) would make the data available for about 120 nano seconds. This is sufficient time for transfer into a buffer register but not for asynchronus communications. By using the above scheme it 20 is possible for the DEM to appear to be executing two memory operations simultaneously.
State 4 places the buffer register on the data lines of the
UNIBUS and indicates to the PDP-11/40 that the data is available by causing SSYN to be high. Control will stay in this state until MSYN goes low. When MSYN goes low, control passes to state 5 which is a dead end. This Is possible because the control that would begin a new
DPM cycle was transferred to state 1 during state 2.
The port one write operation is described as follows:
6. MAI = All; MDI = DUBUS; RP = 0
- d s7)
7. SSYN = 1
-»(MSYN)/ (7)
8. DEAD END
State 6 gates the address and data to the memory and causes RP to go low indicating a request for service. BCL is low at its rest state, there fore it need not be changed to indicate a write operation. Control then branches to state 1, to await another request for service, andto state
7. State 7 causes SSYN to go high, indicating to the PDP-11/40 that the data has been strobed from the data lines and stored in memory.
Control will stay in this state until MSYN goes low. At that time control continues on to step 8 which is a dead end, ending the write cycle. 21
The port two write operation is described as follows;
9, DAE = 1; MDI = DI2;
MAI = AI2; RP = 0
-(1,10)
10. DT2 = 1
11. DEAD END
• '
State 9 sends a data/address enable (DAE) level to the microprocessor, gates the address and data to the memory and causes RP to go low indicat ing a request for service. As before, BCL is already low indicating a write operation. Control is then transferred to states 1 and 10. State
10 sends a data-taken (DT2) level to the microprocessor. Control then passes to state 11, a dead end, ending the write cycle.
The port two read operation is described as follows;
12. DAE. = 1; MAI = AI2
BCL = 1; RP = 0
-(1,13)
13. DA2 = 1 * DAS
14. DA2 = 1 * DAS
15. DEAD END
State 12 sends a DAE level to the microprocessor, gates the address to the memory, causes BCL to go high and causes RP to go low, indicating a request for service. Control is then transferred to sta-tres
1 and 13. States 13 and 14 cause DA2 to be high upon the condition tlcst
DA3 is high. This is done for only two clock periods so the DAS signal 22
from another memory cycle is not gated to port two erroneously,, DA3 is
gated for more than one clock period because it is desirable to have DA2
high for as long as possible. Control then passes to state 15 ending
the read cycle. The complete AHPL sequence suitable for a hardware
compiler is given in Table 2.
One assumptio'n in the preceding design is that the memory data- out lines will be connected directly to the port two data-out connec
tions. This will delete the requirement for gating logic or output buffers. This savings in logic will require the microprocessor to ignore the data-out lines until DA3 is high; indicating that the MDO lines are valid. If a microprocessor is used that must have the MDO lines at known states between memory requests, an output buffer register can be added with minimum effort. The DA2 would then be used to clock the data
from the memory into the buffer and to set a data-ready flip-flop. The
data could then be removed from the buffer by the microprocessor under
its own clock and transfer scheme. This was not done however, because
the microprocessor will be capable of connecting to port two without any output buffer register. With the completion of the AHPL description of
the control sequencer, the control logic may be drawn.
Converting AHPL directly to hardware, the control sequencer was
constructed as shown in Figure 5. This is the schematic of the control
sequencer that was used to build the DPM. IC numbers, pin connections and various other details have been deleted for clarity. A minor differ ence in the control sequencer as shown in Figure 5 is the deletion of
MDI = DI2 from control state 9. This was possible because data 23
Table 2, Complete AHPL Sequence.
REGISTERS: D01 (16)
INPUTS: Cl, AI1(13), MSYN, R, W, Al, AI2(13)
DI2(16), MDO(16), MB, DA3
OUTPUTS: SSYN, DAE, DA2, DT2, MAI(13)
MDI(16), RP, BCL
BUS: DUBUS(16)
FUNCTIONS: SYN(PDP) = DYN (SSYN A MB A MSYN/\ Al)
SYN(^P) = SYN (MB A (R V W))
1. -((CIA SYN(PDP) A SYN(|i,P)) , (Cl A SYN(PDP) A SY N (^P)),
(SYN(pP)A W), (SYN^P) A R), ((Cl A SYN(PDP) A SYN(M,P))V
(Cl A SYN(PDP) A SYN(p,?)) V (SYN(^P) A W)V(SYN(p,P)/\ R))/
(2,6,9,12,1)
2. MAI = All; RP = 0; BCL = 1
-»(i;3)
3. DOlfMDO
4. DUBUS = DOl; SSYN = 1
-(MSYN)/(4)
5. DEAD END
6. MAI = Mil; MDI = DUBUS; RP = 0
-(1,7)
7. SSYN = 1
-(MSYN)/(7) Table 2,— continued.
8. DEAD END
9. DAE = 1; MDI = DI2;
MAI = AI2; RP = 0
■-(1,10)
10. DE2 = 1
11. DEAD END
12. DAE = 1; MAI = Al2
BCL = 1; RP = 0
-(1,13)
13. DA2 = 1 * DA3
14. DA2 = 1 * DA3
15. DEAD END X
PV
Figure 5. Control Sequencer from AHPL Description; 26 multiplexers were used for the memory data input instead of the usual
and/or gate bus configuration. The AHPL can reflect this change by
dropping this term from the control state. Changes of this type are
common unless the actual IC's and their operation are known beforehand.
AHPL designs will always work but may not represent the most economical
design. If the extra features provided by some IC’s are known, AHPL may use them and will provide a minimal state sequencer. Final design of
the DPM is now a matter of drawing IC's and pin connections. CHAPTER 4
PHYSICAL ASSEMBLY
The equipment for this project was mounted in a six-foot cabinet on rollers. Student accessability to the equipment was of major concern, thus liberal usage of space was employed. Power and space were reserved for the microprocessor so it may be mounted in the cabinet at a later date.
Construction
The 36 IC's used in this project were low power Schottky TIL in either 14 or 16 DIP1 s, All but W o are mounted, on seven, 88 pin sockets.
Two DEC connection blocks are used as recepticals for bus cabling and circuit cards. The sockets and recepticals are mounted in a standard
6 inch x 19 inch rack panel with wire-wrapped pins outward to facilitate future modification. Their relative location is shown in Figure 6, The connector-block slots are assigned as follows:
51--PDP-11/40 UNIBUS
52— Clock/Address selector card
53--Microprocessor connection cable
54— Memory connection cable
55— Bus terminator card
56--Unassigned
27 a ?
^ ^ 5/ SZ 53 54 SS 56 57 S3
Figure 6. Pin Side View of IC Bars and Slot Locations.
N> 00 29
S7— Unassigned
S 8— Una s signed
.The memory card is mounted in the interior of the cabinet and plugs into
two 44-pin connectorse Power supplies of +5 volts DC, and +15 volts DC
are mounted in the bottom of the cabinet. Sufficient DC and AC power is
available to operate the microprocessor. With few exceptions, wire wrap
techniques are used throughout. There is liberal labeling of power
connections, cabling and connectors to ease user identification and
operation, A detailed wiring list is provided in Appendix A, The draw
ings here listed are provided for maintenance and circuit modification
and may be found in Appendix B,
Drawing 1--Control Sequencer
Drawing 2"-Address Multiplexing Logic
Drawing 3--Address Selector Circuit and UNIBUS Control Signals
Drawing 4--Clock Circuit
Drawing 5--DPM Data-in Circuit
Drawing 6--DPM Data-out Circuit
Operation
The DEM may be operated either as a one- or two-port memory.
For two-port operation, the UNIBUS cable is plugged into socket one
(SI), the clock/address selector card into S2, the microprocessor
connecting cable into S3, the memory connecting cable into S4, and the
UNIBUS termination card into S5, The clock/address selector card must be programmed to accept the desired address on the UNIBUS, This is accomplished by eight SPST switches mounted on a 16-pin DIP. The four
most significant address bit may be programmed to either be high or low
in order to cause the address selector output, Al, to be highe The
address selector may only be programmed in 8K increments.
After proper address programming and all the connections are made,
the power may be turned on. The relative locations of the power switches
and indicator lights are as shown in Figure 7, The AC power for the DPM
is controlled by a single switch, marked 11 AC Power.” When the power is off, all red indicator lights should be off and the green "safe” light
should be on. When the power is on, the red main power switch should be on, indicating AC power is supplied to the power supplies. The green
safe light should be off when the AC power light is on. There are red panel lights for each of the power supplies. These lights should be on when the power supplies are operating properly. The DPM should now
function if the preceding conditions are satisfied.
The DPM may be operated without a microprocessor. This is done by disconnecting the microprocessor from S3 and inserting a dummy card which properly grounds the address, R, and W lines. The DPM will then
function as a normal 8K memory which is attached to the UNIBUS.
The DPM may be operated by only the microprocessor by simply disconnecting the UNIBUS and UNIBUS terminator card. The DPM will then
function as a normal 8K memory attached to a microprocessor. £ / } £ £
M £ M O f ? y O fo V 6 £
Power Control Panel. CHAPTER 5
OPERATIONAL CHECKOUT
As with all new designs, the final proof of an engineering effort is a working product. The DPM was no exception.
Initial turn on resulted in no burnt fuses or smoking IC?s, A gate-by-gate checkout of the control sequencer was made from both ports one and two, A Mgi-Designer was used to simulate the PDP-11/40 and microprocessor, A 1 HZ clock from a Digi-Designer replaced the 8 MHZ
DPM clock during this simulation so gate performance could be observed.
One faulty gate was found and subsequently replaced. The Cl connection to the UNIBUS was found miswired, A small rewiring change corrected this deficiency.
The microprocessor that will plug into port two was not available for DPM testing so Digi-Designers were used throughout the testing period to simulate the microprocessor.
The PDP-11/40 was then connected to port one and the 8 MHZ single DPM system clock restored. Read and write operations were made from the front panel of the PDP-11/40 with no errors encountered, A program was then written that would write data into and read data out of all DPM memory locations. The PDP-11/40 would print an error message when the data that was read out was different from that which was stored.
This high speed DPM testing revealed several problems,
32 33
The high speed operation of the DEM produced a high level of
noise on the ground and power buses-. This noise caused erroneous data
to be returned to the PDP-11/40 and at times would cause the Microram
3000N memory to lock up. The addition of several bypass capacitors on
the seven 88-pin IC sockets and re-routing of the ground and power buses reduced the circuit noise and error rate, x
Errors still occurred during the initial portion of the program when all zeros are written into and read from memory and then all ones written into and read from memory. The errors appeared to be one-bit errors and prevalent to particular locations. One-bit errors also occurred when certain bit patterns were encountered.
These errors were eliminated by delaying the initiate pulse (RP) to the memory by one clock period and by leaving the address and/or data on the memory input lines for two clock periods. The DPM clock rate was also reduced from 8 MHZ to a maximum of 5*2 MHZ, (A 4,33 MHZ crystal is currently used,) The slower clock and additional delay now give the DPM a memory cycle time of approximately 800 nanoseconds.
The probable cause of the high-speed errors is the cabling from the DPM control logic and buffer register to the Microram 3000N memory.
This cabling is approximately six feet in length and introduces too much delay. This should be eliminated in other DPM's that are constructed by placing the DPM control logic and Microram 3000N memory on the same backplane. It is also possible that an undetected slow gate is causing the high speed errors. Test with available resources failed to reveal 34
such a gates thus, the cabling configuration is the most likely cause of
the high-speed errors.
The DPM was exercised for six hours with the slower clock rate and encountered no errors. The DPM now provides the desired service with acceptable reliability. CHAPTER 6
CONCLUSION 1 .... . i
The preceding has been an example of the transformation of a
single-port memory into a dual-port memory^ By examination, the process
is readily divided into four distinct steps.
In step one the designer must define which memory and computers will be involved and what data transfers will be required. The inter
active signaling scheme may then be defined and analyzed.
Step two is the design of the control sequencer. The use of a
design language in this step will greatly simplify the task; AHPL was
used with this project,
AHPL enables the designer to describe exactly what he wishes to happen. He may also implement various operational modifications to
determine for the optimum circuit before any effort is put towards hardware. When the designer is satisfied that his AHPL statements
describe exactly what he wants, step three may begin.
This step is the direct translation of the AHPL statements into
a hardware control sequencer. Each AHPL step may be interpreted as a
control state flip-flop and/or a logical branch which executes the de
sired operations. Only rarely will the designer observe portions of his
circuit that may be combined for a more minimal solution. Step four is
the preparation of final detailed drawings and system construction. 36
The designing of the DPM carefully followed these steps. Con siderable effort was expended on steps two and three to insure a circuit that would work properly. As expected, final operational checkout revealed only grounding and noise bugs usually encountered with high speed circuits. Once these were corrected, the DEM performed as the design intended. APPENDIX A
WIRING LIST
37 38
IC Number and Type
I d SN74LS08 Quad 2-input positive-and gate IC2 SN74LS74 Dual D-type flip-flop IC3 SN74LS74 Dual D-type flip-flop IC4 SN74LS08 Quad 2-input positive-and gate ' IC5 SN74LS74 Dual D-type flip-flop IC6 SN74LS11 Triple 3-input positive-and gate IC7 SN74LS74 Dual D-type flip-flop ICS . SN74LS73 Dual pulse triggered J-K flip-flop rc9 SN74LS08 Quad 2-input positive-and gate IC10 SN74LS32 Quad 2-input positive-or gate IC11 SN74LS04 Hex inverter IC12 SN74LS32 Quad 2-input positive-or gate IC13 SN74LS21 Dual 4-input positive-and gate IC14 SN74LS32 Quad 2-input positive-br gate IC15 DM8837 Hex unified bus receiver IC16 DM8838 Quad unified bus transceiver IC17 SN74LS32 Quad 2-input positive-or gate IC18 SN74LS32 Quad 2-input positive-or gate ' IC19 SN74LS32 Quad 2-input positive-or gate IC20 SN74LS157 Quad 2-line-to-1-line data selector/multiplexer IC21 SN74LS157 Quad 2-line-to-l-line data selector/multiplexer IC22 SN74LS157 Quad 2-line-to-1-line data selector/multiplexer IC23 SN74LS157 Quad 2-line-to-l-line data selector/multiplexer IC24 DM8837 Hex unified bus receiver IC25 SN74LS75 4-bit bistable latch IC26 SN74LS75 4-bit bistable latch IC27 SN74LS75 4-bit bistable latch IC28 SN74LS75 4-bit bistable latch \ IC29 DM8837 Hex unified bus receiver IC30 DM8838 Quad unified bus transceiver IC31 DM8838 Quad unified bus transceiver IC32 DM8838 Quad unified bus transceiver IC33 DM8838 Quad unified bus transceiver IC34 DM8837 Hex unified bus receiver IC35 SN74LS00 Quad 2-input nand gate IC36 SN74LS04 Hex inverter ■ 39
Bar 1
To To To Pin Pin To To To - Bl-8 2 'I ' 14 1 B3-U U- 2 13 ? 52-A31 32-50 B2-66 6 3 12 5 62— ?4 4 IC" 1 1 31—2 33-23 8 ? 36-8 5 1 1 0 33-2 10 9 32-27 6 9 1.2-60 i 0 33-2< GliD 14 7 8 13 32-77 32-41 +5V 16 I 14 15 + 5" B2-f 18 2 1 3 17 + 5V B l-2 1 31-36 20 3 12 10 B2-35 +57 22 21 Bl-20 S3-3FI 24 5 1 0 23 +5V 2% 6 9 25 B2-48 GMD 29 7 8 27 30 f 0 +57 32 1 1 4 31 +5V 32-12 34 2 1 3 33 +5V Bl-20 31-37 36 3 1 2 35 +57 38 4 IC 1 1 37 B2-20 Bl-36 33-82 B1-U3 4o 5 3 1 0 39 +5V U2 6 9 4l B3-84 GMD UU 7 8 43 Bl-40 46 45 48 47 50 49 52 51 54 53 56 55 58 57 6o 59 62 6l 64 63 66 65 68 67 70 69 72 71 74 73 76 75 78 77 80 79 82 81 84 83 86 85 88 87 40
Bar 2
To To To Pin Pin To To To • B2-8 2 1 14 1 +5V 2 1 3 B3-79 4" 3 Bl-18 B3-38 6 3 12 5 B2-2 B2-25 8 4 1C 1 1 7 5 4 1 0 33-77 10 9 33-86 B1-3U B3-U0 12 6 9 11 33-26 7 8 Giro 14 13 S3-BE1 r 1 4 +5V 16 15 +5V B2-81 18 2 1 3 17 + 5V 3 12 Bl-37 B2-21 20 19 32-43 ♦ 1 1 +5V 22 5 21 S2-AC1 B2-20 B2-32 24 5 1 0 23 +5V Bl-11 26 3 9 25 B2-8 S3-BD1 Giro 28 z 8 27 32-34 31-9 * 80 29 1 1 4 B2-36 B2-2U 32 31 +5V 2 1 3 B2-38 B2-27 34 33 33-19 3 12 B2-32 36 35 .31-19 33-11 4 B2-3U 38 IC 1 1 37 B3-64 5 6 1 0 33-17 40 39 33-81 6 9 B2-U'9 42 4l 31-13 7 8 Giro 44 43 32-19 +5V 46 1 14 45 +5V 2 B3-9 31-25 48 1 3 47 +5V 3 12 B2-51 31-3 50 IC 49 +5V 52 ♦ 7 1 1 51 32-50 32-62 Bl-5 32-61 54 5 1 0 53 +5V 6 56 9 55 33-85 32-74 7 8 Giro 58 57 60 59 r TT B2-70 32-51 62 61 32-54 +5V 64 2 1 3 63 37-15 31-6 66 3 12 65 32-76 +5V 68 4 IC 1 1 67 Giro 32-62 70 5 8 1 0 69 31-12 5 9 +5V 72 71 33-2 33-78 / 8 B2-55 33-34 74 73 B2-78 32-65 76 1 14 75 +5V 32-76 78 2 1 3 77 31-13 32-82 80 3 12 79 33-72 IC B2-81+ 32-80 82 4 1 1 81 32-18 9 B2-82 84 5 1 0 83 6 9 B3-76 B3-4 86 85 / 8 GND 88 87 41 r 3
To' To To Pin Pin To" To To Bl-10 B2-71 2 i ■ 1 4 1 +5V 2 1 3 Bl-U B2-86 k ’ 3 S3-BP1 • BU-27 6 3 1 2 5 B4-5 8 i* IC 1 1 S4-BP1 B3-13 i n 7 B3-87 10 5 1U 1 0 9 B2-48 33-32 B3-25 12 5 9 11 32-35 Giro 14 ; 8 13 33-8 33-39 B3-80 16 i 1 4 15 +5V B3-62 18 2 1 3 17 B7-73 32-40 3 1 2 B3-37 20 IC 19 B2-33 SU-BE1 22 ^ 11 1 1 21 B3-68 S4-BC1 24 5 1 0 23 Bl-8 B2-11 26 5 9 25 B3-12 7 8 Giro 28 27 34-15 30 29 B3-9.. 32 1 14 31 +5V B2-7U 34 2 1 3 33 33-42 B3-35 36 3 12 35 33-36 4 1C 1 1 B2-6 38 37 33-20 5 -L Bar 4 To ; To To Pin Pin To______To______To 2 1 1 6 1 +5V U 2 1 5 3 S1-BP1 3 . 14 6 5 B3-5 8 4 IC 13 7 10 5 15 12 9 12 3 1 1 11 114 7 10 13 3 9 GND 16 15 B3-27 B5-82 1 1 6 18 17 + SV 20 2 1 5 19 22 3 14 21 24 , 13 23 26 5 16 12 25 S1-BV1 28 6 1 1 27 Bh-31 GND 30 7 1 0 29 GND 32 8 9 31 B4-30 34 33 S3-BJ1 36 1 IT 35 +5V B6-81 38 2 1 3 37 S3-BH1 S14-BJ1 40 3 12 39 B6-73 S3-BK2 42 4 1C 1 1 39 S4-BH1 B6-72 44 5 17 10 43 S3-BJ2 SU-BKP 46 6 9 45 B6-77 GND 48 7 8 47 S4-BJ2 50 49 S3-BL1 52 1 14 51 +5V B5-73 54 2 1 3 53 S3-BK1. SU-BL1 56 3 12 55 B6-76 S3-BM2 58 4 ic 11 57 S4-BK1 B5-77 60 5 18 10 59 S3-BL2 SU-BM2 62 6 9 61 B6-80 7 8 GND 64 63 S4-BL2 66 65 S3-BN1 68 1 14 67 +5V B5-76 70 2 1 3 69 S3-BM1 S4-BN1 72 3 1 2 71 B5-81 S3-BP2 71* 4 1 1 73 S4-K-I1 5 1 0 B5-80 76 75 S3-BN2 Sh-BP2 78 6 9 77 B5-72 7 8 GND 80 79 S4-BM2 82 81 84 83 86 85 88 87 43 Bar 5 To ' ToTo Pin Pin ToTo To B5-13 1 6 S3-AC1 1 5 14 B7-7 S3-AE2 S14-AC1 B7-12 20 12 S3-AD2 10 SU-AE2 B7-13 12 11 11 1 0 13 B7-6 GND SU-AD1 B5-2 B5-36 1 6 + 5V S3-AE1 20 1 5 B7-23 221 4 21 S3-AH2 SU-AEl 1 3 B7-28 S3-AF2 1 2 B7-29 1 1 S3-AF1 SU-AF2 1 0 B7-22 B5-18 B5-521 6 + 5V S3-AH1 1 5 B7-141 1 4 39 53-AK2 22 13 B7-U6 12 SU-AK2S3-AJ2 1 1 S3-AJ1 SU-AJ2 1 0 B7-U0 GND SU-AJ1 B5-36 B3-87 + 9V S3-AK11 5 GND B7-57 1 4 S3-AM2 IC B7-62 S3-AL2" 1 2 SU-AM2 B7-63 11 S3-AL1 SU-AL2 1 0 GND SU-ALl S1-BN2 1 6 +5V 1 5 S1-BL1 1 4 1-BM2 S1-BP2 12 1 1 S1-BM1 B5-83 1 0 GND B6-82B5-82 44 Bar 6 To To_____ To Pin Pin To- To To - 2 1 1 6 1 37-5 2 1 5 S3-AMI It. 3 37-11 3 14 S3-AN2 6 5 B6-7 31-7 8 7 B6-8 36-24 +5V 10 ; g " 9 Giro S3-AN1 12 6 1 1 11 7 10 B3-AP2 lU 13 37-4 $ 9 16 15 B7-10 18 1 1( 17 B7-21 2 1 £ S3-AP1 20 19 37-27 S3-AR2 22 3 14 21 36-23 36-7 2h 4 IQ 13 23 36-24 Bb-42 +5V 26 5 26 12 25 Giro S3-AR1 28 6 1 1 27 S3-AS2 30 7 10 29 B7-20 8 9 32 31 B7-26 31* 33 36 1 1 6 35 37-39 S3-AS1 38 2 15 37 37-45 S3-AT2 UO 3 14 •39 .36-Ui 36-23 h2 4 j o 13 4l B6-42 B6-58 +5V hb 5 27 12 43 GND S3-AT1 46 5 11 45 S3-AU2 48 7 10 47 37-38 3 9 50 49 B7-44 52 1 1 5 51 37-55 S3-AU1 54 2 1 5 53 37-61 3 14 S3-AV2 56 55 4 IC 1 3 b6-Ui 58 36-58 36-57 , 2 8 1 2 57 +5V 6o 59 GND S3-AVI 626 11 61 S3-BA2 64 7 1 0 63 37-54 66 8 9 65 37-60 68 67 S1-BR2 70 1 1 6 69 +5V BU-Uh 72 2 1 5 71 S1-BH1 S1-BK1 74 3 14 73 34-39 B4-55 76 4 IC 13 75 S1-BJ2 S1-BL2 78 5 29 12 77 B4-45 B4-61 80 5 11 793 S1-BJ1 36-83 35-83 827 1 0 81 B4-38 3 9 GND 84 83 36-82 86 85 88 87 45 Bar 7 Td To To Pin Pin To To. To S1-AD1 1 6 +5V B6-13 1 5 S1-AC1 1 4 b6-i B5-13 IC 13 S1-AE2 B5-6 B6-15 10 1 2 SI-AD 2 1 1 B5-7 12 11 B6-3 1 0 GND B5-12 GND 16 B2-b3 B7-31 S1-AF11 6 +5V B6-29 20 1 5 S].-AE1 22 IC 14 21 56-17 S1-AH2 B5-22 1 2 B6-31 S1-AF2 1 1 B5-23 B6-19 GND 1 0 GND B7-15 B7-U9 S1-AJ1 1 G • +5V 1 5 S1-AH1 1 4 S1-AK2 1 2 S1-AJ2 B6-37 GND B5-U6 GND B7-31 57-65 S1-AL1 +5V 1 5 S1-AK1 1 4 B6-51 S1-AM2 1 3 IC 56-65 1 2 S1-A12 55-57 56-53 GND 1 0 55-62 S1-BS1 1 6 1 5 S1-BT2 S1-BS2 1 4 53-17 S2-AK2 S1-BV1 1 2 S1-BR1 53-68 S2-AH2 1 1 S1-BR2 GND 1 0 S2-AE2 GND GND 46 SI UNIBUS To To To Pin Pin To To To S5-AA1 AA1 AA2 +5V S5-AA2 S5-AB1 AB1 AB2 GND S5-AB2 S5-AC1 B7-3 AC1 AC 2 GND S5-AC2 S5-AD1 B7-2 ADI AD2 B7-9 S5-AD2 S5-AE1 B7-19 AE1 AE2 B7-8 S5-AE2 S5-AF1 B7-18 AF1 AF2 B7-25 S5-AF2 S5-AH1 B7-37 AH1 AH2 B7-2U- S5-AH2 S5-AJ1 B7-36 AJ1 AJ2 B7-U3 S5-AJ2 S5-AK1 B7-53 AK1 AX2 B7-U2 S5-AK2 S5-AL1 B7-52 AL1 AL2 B7-59 S5-AL2 S 5-AMI AMI AM 2 B7-58 S5-AM2 S5-AM1 GND AN1 AN 2 S5-AN2 S5-AP1 GND API AP2 S5-AP2 S5-AR1 GND AR1 AR2 S5-AR2 S5-AS1 GND AS1 AS2 S5-AS2 S5-AT1 GND ATI AT2 .S5-AT2 S5-AU1 AVI AV2 S5-AU2 S5-AV1 AVI AV2 GND S5-AV2 S5-BA1 BA1 BA2 +5V S5-3A2 S5-BB1 BB1 BB2 GND S5-BB2 S5-BC1 BC1 BC2 GND S5-BC2 S5-BD1 GND BD1 BD2 S5-BD2 S5-BE1 GND BE1 BE2 S5-BE2 S5-BF1 BF1 BF2 S5-BF2 S 5-Bill B6-71 BH1 BH2 S5-BH2 ' S5-BJ1 B6-79 BJ1 BJ2 B6-75 S5-BJ2 S5-BK1 b 6-7^ BK1 BK2 B6-70 S5-BK2 S5-BL1 B5-71 BL1 BL2 86-78 S5-BL2 S5-BM1 B5-79 BM1 BM2 55-75 S5-BM2 S5-BN1 B5-7k Bill BN2 B5-70 S5-BN2 S5-BP1 BU-3 BP1 BP2 E5-78 S5-3P2 S5-BR1 B7-78 BR1 BR2 37-79 S5-BR2 S5-BS1 B7-70 ESI BS2 B7-7U S5-BS2 S5-BT1 GND BT1 BT2 B7-71 S5-BT2 S5-BU1 BU-25 BUI BU2 S5-BU2 S5-BV1 B7-75 BV1 BV2 GND S5-BT2 S-2 Clock Card To To To . Pin Pin To To To M l AA2 +5V 31-3 AB1 AB2 B2-21 • AC1 AC2 Giro ADI AD 2 B3-63 AE1 AE2 B7-81 AFL AF2 B3-65 Aill AH2 37-80 AJ1 AJ2 33-69 AK1 AK2 37-76 AL1 AL2 33-71 AMI AM2 37-72 A1T1 AI{2 API AP2 AR1 AR2 AS1 AS 2 ATI AT 2 AU1 AU2 AVI AV2 BA1 BA2 BB1 BB2 BC1 BC2 BD1 BD2 BE1 BE2 BF1 BF2 BH1 BH2 * BJ1 BJ2 BK1 BK2 BL1 BL2 BM1 BM2 BIT! BN2 BP1 BP2 BR1 BR2 BS1 BS2 BT1 BT2 3V1 BV2 BV1 BV2 S3-Microprocessor To To To Pin Pin To To To AA1 AA2 GND GND AB1 AB2 (DIOO) B5-U • AC1 AC 2 • ( DI02) B 5 - H ADI AD 2 B5-10 (DI01) (DIOU) B5-20 AE1 AE2 B5-5 (DI03) (DI06) B5-2T API AF2 35-26 (DI05) (DI08) 35-38 AK1 AH 2 B5-21 (DI07) (DUO) B5-U5 AJ1 AJ2 B 5 - U (DI09) (DI12) B5-5% AK1 AK2 B5-39 (Dill) (011%) B5-61 ALT AL2 35-60 (DI13) (D000) B6-U SU-AMl AiMl AM 2 B5-55 (DI15) (D002) B6-12 SU-ANl M l AN2 SU-M2 b6-6 (D001) (DOOlj) B6-20 SU-AP1 API AP2 SU-AP2 B6-1U (D003) (D006) B6-28 SU-AB1 API AR2 Slt-AR2 36-22 (D005) (D008) B6-38 SU-AS1 AS1 AS 2 SU-AS2 B6-30 (D007) (D010) B6-^6 Sit-ATI ATI AT 2 Slt-AT2 B6-lt0 (D009) (D012) B6-5U SU-AU1 AU1 AU2 SU-AU2 B6-U8 (D011) (DOlU) B6-62 Slt-BB2 AVI AV2 SU-AV2 B6-56 (D013) • BA1 BA2 SU-BA2 B6-6U (D015) (R) ‘ B3-77 BB1 BB2 (w) B3-79 BC1 BC2 (DAE) B2-25 BD1 BD2 (DA2) B2-13 BE1 BE2 (DT2) B1-2U BF1 BF2 (A00) BU-37 BH1 BH2 (A02) Blt-36 BJ1 BJ2 BU-U3 (A01) (A04) BU-53 BK1 EK2 BU-U2 (A03) . (A06) Bli-52 BL1 BL2 BU-59 (AOS) (AOS) BU-69 BM1 BM2 Blt-58 (A07) (A10) Blt-68 BN1 BN2 BU-75 (A09) (A12) B3-3 BP1 BP2 BU-7U (All) BRL BR2 BS1 BS2 BT1 BT2 BUI BU2 BV1 BV2 49 S-4 Memory Port To To To Pin Pin To______To______To AA1 AA2 AB1 AB2 (DIOO) B5-8 AC1 AC 2 (DI02) 35-15 ADI AD2 B5-1U (d i o i ) (DIOU) B5-2U AE1 AE2 B5-9 (DI03) (DI06) B5-31 AFL AF2 35-30 (DI05) (DIOS) B 5-1*2 AH1 AH 2 35-25 (DI07) (DF10) B5-U9 AJ1 AJ2 35-18 (DI09) (DI12) 35-58 AK1 AK2 35-13 (Dill) (DIlU) 35-65 AL1 AL2 35-61 (DI13) (D000) S3-AMI AMI AM 2 35-59 (DI15) (D002) S3-AN1 M l M 2 S3-AN2 (D001) (DOOM S3-AP1 API AP2 S3-AP2 (D003) (D006) S3-AR1 API AR2 S3-AR2 (D005) (DOOS) S3-AS1 AS1 AS 2 S3-AS2 (D007) (D010) S3-ATI ATI AT2 .S3-AT2 (D009) (D010) S3-AU1 AU1 AU2 S3-AU2 (D011) AVI AV2 S3-AV2 (D013) BA1 BA2 S3-BA2 (D015) (MB) B3-6U BB1 BB2 S3-AVI (DOll) (DA) B3-2U BC1 BC2 (BCL) B3-l*3 BD1 BD2 (HP) B3-22 BE1 BE 2 BF1 BF2 (A00) BU-Ul BH1 BH2 (A02) BU-ltO BJ1 BJ2 Bl-l? (AOl) (AOU) BU-57 SKI BK2 Bl-16 (A03) (ao6 ) BU-56 BL1 BL2 Bl-63 (A05) (A08) BU-73 BM1 BM2 Bl-62 (A07) (A10) Bli-72 NB1 BN2 Bl-79 (A09) (A12) B3-7 BP1 BP2 Bl-78 (All) BR1 BR2 BS1 BS2 BT1 BT2 BUI BU2 BV1 BV2 S-5 UNIBUS Terminator Card To To To Pin Pin To To To S1-AA1 AA1 AA2 S1-AA2 +5V S1-AB1 AB1 AB2 S1-AB2 GND S1-AC1 AC1 AC 2 S1-AC2 GND S1-AD1 ADI AD2 S1-AD2 S1-AE1 AE1 AE2 S1-AE2 S1-AF1 API AF2 ' S1-AF2 S1-AH1 AH1 AH2 S1-AH2 S1-AJ1 AJ1 AJ2 S1-AJ2 S1-AK1 AK1 AX2 S1-AK2 S1-AL1 AL1 AL2 S1-AL2 S1-AM1 AMI AM 2 S1-AM2 GND S1-AN1 AN1 AN 2 SI-AN2 GND S1-AP1 API AP2 S1-AP2 GND S1-AB1 AR1 AR2 S1-AR2 GND S1-AS1 ASi AS2 SI-A32 GND S1-AT1 ATI AT 2 • S1-AT2 S1-AU1 AU1 AU2 S1-AU2 S1-AV1 AVI AV2 S1-AV2 S1-BA1 BA1 BA2 S1-BA2 +5V S1-BB1 BB1 BB2 S1-BB2 GND S1-BC1 BC1 BC2 S1-BC2 GND GND S1-BD1 BD1 BD2 S1-BD2 GND S1-BE1 BS1 EE2 S1-BE2 S1-BF1 BF1 BF2 S1-BF2 S1-BH1 BH1 BH2 S1-BH2 S1-BJ1 BJ1 BJ2 S1-BJ2 S1-BK1 BK1 BK2 S1-BK2 S1-BL1 BL1 BL2 S1-BL2 S1-BM1 BM1 BM2 S1-EM2 S1-BN1 BN1 BN2 SI-BN2 S1-BP1 BP1 BP2 S1-BP2 S1-BR1 BR1 BR2 S1-BR2 S1-BS1 BS1 BS2 S1-BS2 S1-BT1 BT1 BT2 S1-BT2 S1-BU1 BUI BU2 S1-BU2 S1-BV1 BV1 BY 2 S1-BV2 GND 51 Memory Socket Connections Pin Connector Pin Connector No. J1 J2. No. J1 J2 .1 GND GND ' 41 GND Giro 2 +5V API (DI06) 42 +5V AD2 (DI01) 3 -15V AH2 (DI07) 43 -15 AC1 (DI00) k GND AF2 (DI05) 44 Giro AH1 (DIOS) 5 +15V AE1 (DI04) 45 +15V 6 +5V AR1 (D006) 46 BMl (A08) AP2 (D003) 7 AS2 (D007) 47 BM2 (A07) 8 AR2 (D005) 48 BL1 (A06) AN2 (D001) 9 API (D004) 49 BP2 (All) AM2 (D000) 10 AE2 (DI03) 50 BN1 A10) AS1 (D008) 11 51 Giro 12 J2-06 52 BN2 (A09) ADI (DI08) 13 J2-07 53 BK2 (A03) AN1 (D002) 14 J2-08 54 Giro BA2 (D015) 15 J2-09 55 BK1 (A04) Giro 16 J2-46 56 BL2 (A05) AM2 (DI15) 17 J2-47 57 GND AL1 (DI14) • 18 J2-48 55 BH1 (A00) BB2 (D014) 19 J2-49 59 BJ2 (A01) AV2 (D013) 20 J2-50 60 GND GND 21 J2-54 61 BJ1 (A02) AL2 (DI13) 22 J2-58 62 BP1 (A12) AK1 (DI12) 23 J2-59 63 +5V AU1 (D012) 24 J2-63 64 GND 25 Jl-33 J2-72 65 GND 26 Jl-36 J2-73 66 GND Giro 27 +5V J2-69 67 GND Giro 28 +5V J2-53 68 Giro 29 +5V 69 AU2 (D011) 30 + 5V 70 AK2 (Dill) 31 Jl-35 (BCL2) 71 AJ1 (DUO) 32 GND 72 ATI (D010) 33 BB1 (MB) 73 AT2 (D009) 34 GND 74 AJ2 (DI09) 35 BD1 (BCL1) GND 75 +5V 36 BC1 (DA) +15V 76 +15V 37 GND Giro 77 Giro 38 -15V 78 -15 V 39 +5V 79 BE1 (HP) +5V 40 |GND GND 80 GND Giro Clock/Address Selector Card 12. £ Z 1 2 . /— e/-3 £&0-/i- 2 /£ 3 —t>V— /4 /.sxn. 4 /3 £ — /«? 0/-4 /Z 2 Z O A <2> // / ^ ^7^ £ Z - S II l 9 W 7 0 70, T O 5 / H Z 56-/5 TO TO_ z y y '5— fo 5 / m = 7 51/ ^7-7 Z 7 V / /4 2 7— 76 / /4 /&f Ul K> APPENDIX B ELECTRICAL DRAWINGS 53 Drawing 1— Control Sequencer C/ & /i /4 ^ = 2 _ f . /3 c/ izr / z r Ul 4> I 55 Drawing 2--Address Multiplexing Logic 1 ^1 // /f 03 S / - 3 M 6 406 3 / - 3 0 S / - 3 M Z — 5 / - 3 A / / /A/jO 3 4 // N W \ %#% % % % % Drawing 3--Address Selector Circuit and UNIBUS Control Signals c/ _ C/ /6 5 / - £ T Z // /z /3 Mf/AL. MM- // /J/4 - MW 3 0 A/6 *, / A/? K 5/-3S/ /3 -SZ-/M 5 3 - M Z ' -6L, / 3 /o /I/ _Z£. 3 / - S M / Drawing 4--Clock Circuit £ & a n AAA— & M U Z XZ41 / O f f 58 Drawing 5— PPM Data-in Circuit \ ijy 0 / 0 0 /3 /5 47-40/ P J O / /2> /2 S/-402 01 0 ? 3 / 0 7 OS <2> 4 5/-47Z 0 7 0 4 /S\ / 0 57-407 0 7 0 5 /a /2 j / x y z 0707} 3 3/ / 5/-477 0 / 0 7 <7 0 7 0 3 /3 75 I 0 / 0 9 70 7? 0 7 / 0 J / . a v & / y 077/ 6 0 7/2 /3 Z 5 - a 07/3 70 0 / 7 4 / 57-427 T a j y - x t k t r (5 ' A40J— DI/ aw x <27 Nr 1 59 Drawing 6--DPM Data-out Circuit I? /^ /VI ^*-s/-/ic/ S fjf /% / / 11 / -S/-s4£Z ZL /2L M - & ~ S /-/!£/ X 6 / / /Z> 2 ^ s z - z / z J/ — 5 /-/If! £~~ 5/-Z//Z /f U\ SM/// /% // 5 / - / U 2 9 <6 //— 5/-AJ/ $/-/?//* /f X/ /^ // S/-ZL2 f__6 -~-5/-4// X 0 0 / - - M P 0 //I 1 f c / o c x 111!! 5; % % & % ; % > >V) >V) LIST OF REFERENCES Korn, Granino A., "A Comparison of Interprocessor Communication Schemes," Computer Science Laboratory Report Number 210, November, 1974. Korn, Granino A., "Back to Parallel Computation," Simulation. Volume 9, August 1972, pp. 37-44. Digital Equipment Corporation, PDP-11 Peripherals Handbook. 1975. Electronic Memories, Technical Manual, Microram 3000N Memory Card Assembly, TM 928095, Rev. A, September, 1974. Hill, F. J., and Peterson, G. R., Digital Systems: Hardware Organization and Design, Wiley, New York, 1973. Hill, Fredrick J., "Updating AHPL," Proceedings of the Third International Symposium on Computer Hardware Description Languages, September, 1975.