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Single port to dual port conversion for an LSI memory Item Type text; Thesis-Reproduction (electronic) Authors Adams, Dennis Lee, 1948- Publisher The University of Arizona. Rights Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. Download date 24/09/2021 02:57:46 Link to Item http://hdl.handle.net/10150/554945 SINGLE PORT TO DUAL PORT CONVERSION FOR AN LSI MEMORY by Dennis Lee Adams A Thesis Submitted to the Faculty of the DEPARTMENT OF ELECTRICAL ENGINEERING In Partial Fulfillment of the Requirements For the Degree of MASTER OF SCIENCE In the Graduate College THE UNIVERSITY OF ARIZONA 19 7 5 STATEMENT BY AUTHOR This thesis has been submitted in partial fulfillment of re­ quirements for an advanced degree at The University of Arizona and is deposited in the University Library to be made available to borrowers mder rules of the Library. Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation from or reproduction of this manuscript in whole or in part may be granted by the head of the najor department or the Dean of the Graduate College when.in his judg- nent the proposed use of the material is in the interests of scholar­ ship. In all other instances, however, permission must be obtained from the author. APPROVAL BY THESIS DIRECTOR This thesis has been approved on the date shown below: Professor of EMetrical Engineering TABLE OF CONTENTS Page LIST OF ILLUSTRATIONS ...................... iv LIST OF TABLE S .......................... V ABSTRACT ............................. vi CHAPTER 1. INTRODUCTION ....................... I 2. DPM OPERATION ...................... 7 Port One Electrical Characteristics ......... 7 Port One Write Operation ............... -V 9 Port One Read Operation ............... 10 Port Two Electrical Characteristics ......... 11 Port Two Write Operation . .......... 11 Port Two Read Operation . .... 12 Port Three Electrical Characteristics 12 Port Three Write Operation .............. 13 Port Three Read Operation .............. 14 DPM Access Priority ................. 15 3. CONTROL SEQUENCER .................... 16 4. PHYSICAL ASSEMBLY ..................... 27 Construction . ........ ............... 27 Operation ...................... 29 5. OPERATIONAL CHECKOUT . .................. 32 6. CONCLUSION ........................ 35 APPENDIX A: WIRING LIST ................ „ ,. „ . 37 APPENDIX B: ELECTRICAL DRAWINGS ................ „ 53 LIST OF REFERENCES ........................ 60 LIST OF ILLUSTRATIONS Figure Page 1. CDC Architecture 2 2, Computer Laboratory Architecture , „ „ „ . „ „ „ „ „ „ „ „ „ 4 3. DEM Communication Connections 6 4. Data, Address and Control Signal Flow 8 5. Control Sequencer from AHPL Description o 25 6„ Pin Side View of IC Bars and Slot Locations 28 7. Power Control Panel 31 iv LIST OF TABLES Table Page 1. Signal Mnemonics and Their Definitions Used in AHPL „ , „ 18 2. Complete AHPL Sequence . ........... 23 v ABSTRACT This thesis will discuss, design and report on the construction of an interface unit that will convert a standard LSI solid state memory into a dual-port memory. The interface unit will have three communica­ tion ports. The first port will connect to a PDP-11/40 UNIBUS, the second to a 16-bit microprocessor, and the third to an Electronic Memories Microram 30Q0N 8K x 20^-bit memory. The design is such that the interface unit will appear as an 8K block of memory to the PDP-11/40 and microprocessor ports and as a single user requesting memory service to the Microram memory port. CHAPTER 1 INTRODUCTION Digital computers usually have only one central processing unit (CPU) which must perform all operations. This single CPU executes all instructions, whether they are directly related to some user program or housekeeping duties of the computer. While considerable effort has been directed towards the efficient utilization of CPU time 5 one stumbling block remains; all operations must be performed sequentially. It is therefore reasonable to assume, that if a system had more than one CPU, it would be able to perform some instructions or operations simultaneous­ ly. This assumption requires the operations be independent. Several manufacturers have capitalized on this idea and have produced computing systems that produce a high rate of throughput. The Control Data 6000 series is a classic example. Control Data computers employ one or two fast central processing units connected to a large memory (see Figure 1). Also connected to the memory are ten smaller and slower processors which are called Peripheral Processors. In this scheme, the Peripheral Processors perform all I/O operations, allowing the main CPU to perform the arithmetic and logical operations. As the I/O operations are usually very slow, the main CPU can be executing several programs sequentially while the Peripheral Processors are executing the I/O operations in parallel. The central 1 TEN I/O CPU(S) MEMORY PERIPHERAL DEVICES < TV PROCESSORS V Figure 1. CDC Architecture. N> communications point in this system is the multiport memory, A memory, such as this allows many devices to read or store data at selected memory locations. This in itself is not significant until the concept of interprocessor communications is realized. The memory is no longer a storage device, but a communications device. The memory is now a means for passing data from one processor to another or programming one processor with another. Variations of this scheme are presented in Reference 1. Dr. Korn*s paper entitled, HA Comparison of Interprocessor Com­ munication Schemes,11 discusses methods in which one processor may communicate with another. After discussion of various schemes and their advantages and disadvantages, it was concluded that dual-port memories are the most economical and efficient method for interprocessor communi­ cations , Reference 2 proposes a computer laboratory that would employ a DEC PDP-11/40, two dual-port memories, two microprocessors, and assorted I/O and storage devices as shown in Figure 2. Under this scheme, the PDP-11/40 would place an object program into the dual-port memory along with any data the program would require. The microprocessor would then execute the program. These programs would be similar to large sub­ routines, such as integration routines or fast fourier transforms. When the microprocessor had finished executing the program, it would place the answer or results into a specified location in the dual port memory and signal the PDP-11/40 that the computation was completed. The signaling could be accomplished by the microprocessor placing an yp yP 0 0 I/O Other DPM DPM Devices Memory 7 Y / /X PDP-11/40 Figure 2. Computer Laboratory Architecture. indicator in a "mail box" memory location that the PDP-11/40 would periodically interrogate. A microprocessor to PDP-11/40 interrupt routine could also be employed. Using this computer structure, many programs could be executed in significantly less time than would be the case in computers with only one CPU0 The key to this system is the dual-port memory (DPM). The DPM will consist of a LSI single-port memory and an inter­ face control unit with three ports, as shown in Figure 3. The DPM will permit the microprocessor or the PDP-11/40 to read or write into any location in the LSI memory. In this manner the computers may use the DPM as a storage device or a communications medium. It is a DPM such as this that is discussed and designed in this thesis. MICROPROCESSOR INTERFACE CONTROL PDP-11/1+0 yX UNIT LSI MEMORY Figure 3. DPM Communication Connections. CHAPTER 2 DPM OPERATION The dual-port memory (DPM) interface unit will have three ports. Connected to these three ports will be the UNIBUS of a PDP-11/40, a 16- bit microprocessor and an Electronic Memory, Microram 3QQ0N, 8K x 20 bit LSI memory. Although this memory has 20-bit words, only 16 bits will be used. Ports one and two will appear as an 8K block of memory to the microprocessor and PDP-11/40 while port three will act as a single memory user to the LSI memory. Only 16-bit read or write operations will be used, making it unnecessary to take advantage of byte or split cycle operations. The functional layout with address, data, control and signal lines of the DPM is shown in Figure 4. Port One Electrical Characteristics Port one must be electrically and operationally compatible with the DEC PDP-11/40 UNIBUS. The control, data and address lines that will be used in port one communications are as follows: MSYN--master sync from PDP-11/40 SSYN-"slave sync to PDP-11/40 A01-A13--address lines from PDP-11/40 D0-D15--bidirectional data lines Cl— read/write control line h / V 1 R W Cl DA2 U DT2 DPM CONTROL SEQUEN­ MSYN CER AND DATA/ADD­ SSYN N MICROPROCESSOR DAE Port RESS BUS LOGIC Port AI2 Two One All I DUBUS DI2 B .MDO U < = S Port Three vjA a n H o H on I / J < S g s & BCL g A \ N - vt v MICRORAM 3000N MEMORY Figure 4. Data, Address and Control Signal Flow. 9 The DIM will only accept read or write operations from the PDP-11/40, Therefore3 the DFM control logic will decode only the Cl UNIBUS control line. The C0 UNIBUS control line indicates whether the operation is to be a Read-Pause-Write (split-cycle) operation which will not be employed. Address line A00 is also ignored because only 16-bit word transfers are required, (Line A00 indicates whether the high or low 8-bit byte will be transferred, but this operation is also excluded from this design,) The PDF-11/40 uses a master-slave bus signaling scheme. That is, when one device wishes to communicate with another it must sense whether the bus busy line (BBSY) on the UNIBUS is high, indicating the bus is currently being used.

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