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Areliable Miniature Electronic and Optical ELECTRONIC AND OPTICAL INTERCONNECTS FOR LOW-VOLUME APPLICATIONS Reliable Miniature Electronic and Optical Interconnects for Low-Volume Applications Guy V. Clatterbaugh, Charles V. Banda, and S. John Lehtonen t some level, all integrated circuit devices, passive devices, and optoelectronic devices must be interconnected together to function as a highly integrated electronic or optoelec- tronic system. As silicon-based device technologies have continued to evolve, the number of chip-level and package-level interconnections has increased dramatically while chip sizes have remained relatively constant. This dramatic increase in inter- connection density has been enabled through the adoption of area array packages such as ball grid arrays and chip-scale packages. To accommodate these area array packages, today’s printed wiring board fabrication techniques are featuring 100-µm (2-mil) lines and spaces as well as 0.25-mm-diameter (10-mil) blind and buried vias, both of which are necessary for high interconnection densities. Although the Atechnology for wiring chips to packages and packages to boards for high-volume applications is relatively mature, it becomes increasingly ambitious to implement that technology for low-volume electronic applications. The nature of APL’s wide range of innovative, miniature electronic development activities necessitates the use of high-density interconnection methods. This article focuses on APL’s ongoing activity to develop high-density interconnection methods for use with low-volume, noncommercial electronic applications. INTRODUCTION Reliable, cost-effective miniaturized electronics sys- applications. The low volume and rapid turnaround tems are a key to APL’s future business plans as they requirements for some miniature electronic systems relate to military, homeland security, and space systems designed at APL preclude the up-front planning required JOHns HopKins APL TecHnical DIGest, Volume 28, NumBer 1 (2008) 47 G. V. CLATTERBAUGH, C. V. BANDA, AND S. J. LEHTONEN to both design and purchase devices that are manufac- and medical applications since the late 1970s.1 In recent tured specifically for ultra-miniaturized electronic sys- years, APL has fabricated COB assemblies for both tems. In addition, preparing commercially available inte- space and national defense programs. Currently, APL is grated circuits (ICs) for extreme miniaturization can be moving more toward COF assemblies for their reduced quite costly. Back-end wafer processing for high-density size as well as the ability to conform these circuits to applications such as die-thinning and solder-bumping IC three-dimensional geometries. bond pads add additional cost to the devices and typically There are two primary methods for interconnecting require that the customer purchase at least one entire unpackaged ICs to the underlying circuit board: wire wafer. For the majority of devices, these back-end services bonding and flip-chip bonding. Wire bonding is the are not even available. To meet the diverse requirements traditional method for electrically wiring ICs to either of APL sponsors, state-of-the-art techniques and innova- packages or circuit boards. In this method, the back- tive new solutions are being developed that address the side of the IC die is first solder- or epoxy-attached to need to provide cost-effective, high-density, miniature the substrate or package. In this case, a gold wire is first electronic packaging solutions. bonded to a pad on the IC and then to a pad on the underlying substrate. This is repeated for each IC bond MINIATURE ELECTRONIC PACKAGING TECHNOLOGIES pad. These wires electrically connect the device to the Currently, wafer-scale integration offers the highest metal traces on the substrate or to the package leads. available density in two-dimensional electronic packag- The wire-bonding process is depicted in Fig. 1. Flip-chip ing. In fact, an ever-increasing level of on-chip integra- bonding involves the direct attachment of the top side of tion has postponed the widespread adoption of multi- the IC die to the underlying substrate via a small bump chip packaging methods. The increased functionality contact. The substrate must have a pad layout that mir- available on a single IC chip has resulted in significant rors the pad layout for the chip so that when a die is decreases in electronic system volume without the use positioned over the substrate and brought into contact of more advanced substrate and packaging technologies. with the substrate, a bond between chip and substrate However, in many applications where highly integrated can be formed. The flip-chip interconnection technique devices are not available or packaged devices are too is illustrated in Fig. 2. large for ultra-miniature applications, direct chip attach- ment techniques are still required. Direct chip attachment assemblies involving more than one active device are often referred to either as multichip modules (MCMs) or as chip-on-board (COB) assemblies. The label MCM is typically reserved for mul- tilayer thin-film circuits on silicon, multilayer thick film on ceramic, or thick film on multilayer cofired ceramic. The label COB refers to unpackaged ICs mounted directly onto printed wiring boards (PWBs). A newer designation, chip-on-flex (COF), refers specifically to bare ICs mounted on thin, flexible polyimide PWBs. APL has been consistently fabricating MCMs for space Align chip bumps to substrate pads Pressure Heat Gold ball wire-bonding process A wire-bonded integrated circuit chip Heat Figure 1. A gold ball wire-bonding process (upper) and a wire- Apply heat and/or pressure bonded integrated circuit chip (lower). Figure 2. Flip-chip bonding process. 48 JOHns HopKins APL TecHnical DIGest, Volume 28, NumBer 1 (2008) ELECTRONIC AND OPTICAL INTERCONNECTS FOR LOW-VOLUME APPLICATIONS A small tradeoff in density for convenience can be Buried VCSEL with Flip-Chip Bumps gained with the use of chip-scale packages (CSPs) and Au/Ti contact ball grid arrays (BGAs). The CSP is typically used to package medium-scale IC devices (such as an operational Epitaxial p DBR Epitaxial regrowth regrowth amplifier and transistor arrays, etc.). CSPs are typically Active region not more than 10% larger than the IC itself and offer a n DBR slightly smaller footprint than the BGA package. The leads are typically 100-µm-diameter solder balls that are located around the periphery of the package or in an Substrate area array. Large-scale ICs with higher numbers of inputs Au/Ti contact and outputs (signal processors, gate arrays, etc.) are more likely packaged in the larger BGAs. These packages also have ≥100-µm-diameter solder balls; however, they are Ceramic Lens Ceramic arranged as an array to accommodate the increased substrate substrate number of inputs and outputs. Examples of CSPs and BGAs are shown in Fig. 3. PIN diode photodetector silicon on sapphire Figure 5. Flip-chip-mounted VCSEL used with a silicon-on- sapphire (SOS) PIN diode for motion detection. DBR, distributed Bragg reflector. The technology for interconnecting highly inte- Figure 3. Examples of BGAs, microBGAs, and CSPs. grated optoelectronic systems is at the present time relatively immature compared with that for electronic Edge-Emitting Semiconductor Laser Top metal contact systems. Traditional interconnection schemes involved Semi-insulating complex alignment of embedded optical fibers (usually barrier p+ GaAs in V-grooves etched in silicon) to edge-emitting laser Light out (EEL) devices in that same silicon. With the advent of p AlGaAs the vertical-cavity surface-emitting lasers (VCSELs), Active region n AlGaAs interconnection options have increased. The differ- n AlGaAs ences between VCSELs and EELs are illustrated in Fig. substrate 4. VCSELs, along with thin-film optoelectronic compo- nents such as waveguides and coupling gratings, have Bottom metal contact facilitated the use of both photodetectors and photo- Light out emitters that are embedded directly into the substrate. Top metal With advancements in embedded waveguide techniques, contact flip-chip attachment of VCSELs is rapidly becoming the preferred interconnection method. A flip-chip style of n InP VCSEL is depicted in Fig. 5 for a microelectromechani- substrate cal motion-sensor application fabricated at APL.2 LOW-VOLUME, HiGH-DENSITY INTERCONNECT n InP TECHNOLOGIES Active region p InP Wire Bonding SiO2 Bottom metal contact In high-volume commercial applications, the Vertical Cavity Surface-Emitting Laser principal die-level interconnection method used for high-density circuits is still the gold wire bond. There Figure 4. Differences between the EEL and VCSEL. are two types of wire bonds, the ball bond and the JOHns HopKins APL TecHnical DIGest, Volume 28, NumBer 1 (2008) 49 G. V. CLATTERBAUGH, C. V. BANDA, AND S. J. LEHTONEN wedge bond. Both the ball bond and the wedge bond are substrate into contact with the bumped chip. The con- welded to the aluminum metal bond pad on the IC by tact pressure is monitored via a pressure sensor or by a using ultrasonic energy and heat. This process is referred displacement sensor, depending on whether the bumps to as thermosonic gold wire bonding. Gold wedge bond- are to be welded or reflowed. ing typically takes up less space on a bond pad; however, Flip-chip attachment is not new. IBM was making ICs it has less flexibility than does the gold ball bond when with small solder bumps on IC bond pads as far back as bonding die with complex pad layouts or when bonding the early 1960s.3 Their process was called the controlled to substrates with irregular pad arrangements. For high collapse chip connection or C4. Essentially, the IC with input/output (I/O) density ICs, 18-µm-diameter (0.7-mil) solder-bumped pads was mounted front-side down onto gold wire is now the standard. With this thinner wire, a ceramic or silicon substrate with corresponding pads gold ball bonds can easily be used on devices with 50-µm and then heated until the solder reflowed, producing pads and 50-µm pad spacings.
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