A Hardware-Oblivious Optimizer for Data Stream Processing

Total Page:16

File Type:pdf, Size:1020Kb

A Hardware-Oblivious Optimizer for Data Stream Processing A Hardware-Oblivious Optimizer for Data Stream Processing Constantin Pohl supervised by Prof. Dr. Kai-Uwe Sattler Technische Universitat¨ Ilmenau Ilmenau, Germany [email protected] ABSTRACT properties come into play, like memory hierarchies or CPU High throughput and low latency are key requirements for core count. data stream processing. This is achieved typically through For this paper, we consider different aspects and para- different optimizations on software and hardware level, like digms of parallelization that are applicable on data stream multithreading and distributed computing. While any con- processing. In addition, first measurements on SIMD and cept can be applied to particular systems, their impact on multithreading realized on an Intel Core i7 and Intel Xeon performance and their configuration can differ greatly de- Phi Knights Landing (KNL) with our SPE PipeFabric are pending on underlying hardware. shown. Our final goal is a full optimizer on a SPE capable Our goal is an optimizer for a stream processing engine of dealing with unknown UDFs in queries as well as with ar- (SPE) that can improve performance based on given hard- bitrary hardware the system uses. Two consequential tasks ware and query operators, supporting UDFs. In this paper, arise from this. we consider different forms of parallelism and show mea- surements exemplarily with our SPE PipeFabric. We use a • Exploitation of opportunities given by modern hard- multicore and a manycore processor with Intel's AVX/ AVX- ware, like wider CPU registers on Intel's AVX-512 in- 512 instruction set, leading to performance improvements struction set, manycore processors with 60+ cores on through vectorization when some adaptations like micro- a chip or increased memory size. batching are taken into account. In addition, the increased • Analysis of performance impacts by possible UDFs and number of cores on a manycore CPU allows an intense ex- operations, like computational effort or possible paral- ploitation of multithreading effects. lelization degree in case of data dependencies. Keywords The rest of this paper is organized as follows: Next Sec- tion 2 is a short recapitulation about stream processing, Data Stream Processing, AVX, Xeon Phi, SIMD, Vectoriza- possible parallelism and opportunities given by hardware. tion, Parallelism Section 3 summarizes related work done on SIMD paral- lelism, hardware-oblivious operations and stream partition- ing in context of data stream processing. Our results are 1. INTRODUCTION presented in Section 4, followed by Section 5 with future Technological advancement leads to more and more op- work. Section 6 with conclusions tops off this work. portunities to increase application performance. For stream processing, data arrives continuously at different rates and from different sources. A stream processing engine (SPE) 2. PREREQUISITES has to execute queries fast enough that no data is lost and This section shortly summarizes requirements on stream results are gathered before the information is already out- processing and parallelization opportunities in addition to dated. A solution to achieve this is a combination of software information on used hardware, like supported instruction optimizations paired with modern hardware for maximizing sets. parallelism. It is difficult to find an optimal parametrization though, e.g. for the number of threads or load balancing 2.1 Data Stream Processing between them. It gets even worse when different hardware As already mentioned, high throughput and low latency are main requirements for stream processing. A data stream delivers continuously one tuple of data after another, possi- bly never ending. Queries on data streams have to consider that tuples can arrive at alternating rates and they get out- dated after a while, because storing all of them is impossible. Operating with windows of certain sizes are a common so- lution for this property. Proceedings of the VLDB 2017 PhD Workshop, August 28, 2017. Munich, As a consequence, a query has to be processed fast enough Germany. Copyright (c) 2017 for this paper by its authors. Copying permitted for to produce no outdated results as well as keeping up with private and academic purposes.. eventually fast tuple arrival rates. Handling multiple tuples at once through partitioning of data or operators exploiting parallelism possibilities is therefore a must. Data Stream T B Batch Op . 2.2 Parallelism Paradigms There are mainly three forms of parallelism on stream Tuple T Batch B processing that can be exploited. <A1...An> <T1.A1...Tm.A1> Partitioning. Partitioning can be used to increase speedup ... through splitting data on different instances of the same op- <T1.An...Tm.An> erator. Therefore every instance executed in parallel has to add its function on a fraction of data, increasing throughput Figure 1: Processing Model of a query. However, additional costs for assigning data to instances and merging results afterwards arise, influencing the optimal partitioning degree. Task-Parallelization. Operators of a query can execute gathered first on a batching operator with attribute group- in parallel if data dependencies allow such parallelism. A ing in memory realized by vectors until batch size is reached pipelining schema provides possibilities to achieve this, re- and then forwarded to the next operator. alized by scheduling mechanisms. Vectorization. A single instruction can be applied on mul- 2.3 Hardware Opportunities tiple data elements, called SIMD. For stream processing, There are mainly two different ways to increase compu- some preparatory work is necessary to use this form of par- tational speed on hardware, distributed and parallel com- allelism, like storing a number of tuples before processing puting. Distributed computing uses usually many high-end them at once with SIMD support. On the one hand, it in- processors connected to each other, sharing computational creases the throughput of a query while on the other hand work between them. The disadvantage comes with commu- batching up tuples worsens latency. nication costs. With requirements of low latency, we focus on parallel computing. Manycore processors like the Xeon We focus on partitioning and vectorization, because task- Phi series from Intel use simpler cores, but many of them in- parallelism is mainly a scheduling problem that is not of side their CPU. This eliminates most of the communication further interest at this point. costs, improving latency while providing wide parallelization opportunities compared to a single multicore processor. 2.2.1 Partitioning The latest Xeon Phi KNL uses up to 72 cores with 4 threads each, available through hyperthreading. In addi- A speedup through partitioning is achieved mainly with tion, the AVX-512 instruction set can be used for 512bit multithreading. Each partition that contains operators pro- wide operations (SIMD). This leads to great possibilities on cessing incoming tuples uses a thread, which leads to chal- partitioning and vectorization to reduce latency of a query. lenges on synchronization or load balancing, especially on There are more interesting improvements on KNL like clus- manycores, as shown by Yu et al. [6] for concurrency con- tering modes, huge page support or high-bandwidth memory trol mechanisms. Partitioning is a key for high performance on chip (MCDRAM) which we will address in future work. when using a manycore processor, which provides support for 200+ threads at the cost of low clock speed. To investi- gate the right partitioning degree between reduced load on 3. RELATED WORK each partition and increased overhead from threads as well For parallelism through vectorization and partitioning on as an appropriate function for forwarding tuples to parti- data streams, a lot of research has been done already, espe- tions additional observations have to be made. Statistics cially since manycore processors are getting more and more are a common solution, but can be far away from optimal common. To achieve performance benefits, those manycore performance in worst cases. CPUs rely massively on SIMD parallelism and multithread- ing for speeding up execution time. 2.2.2 Vectorization For data stream processing, the functionality of operations To use vectorization, certain requirements must be ful- like joins or aggregations to give an example, are basically filled. Without batching up tuples it is impossible to ap- the same. However, for realization the stream processing ply a vector function on a certain attribute. This leads to properties have to be taken into account. the next challenge, the cache-friendly formation of a batch. Without careful reordering, any vectorization speedup is lost Polychroniou et al. [4] take a shot on different database through expensive scattered memory accesses. A possible operators, implementing and testing vectorized approaches solution for this is provided by gather and scatter instruc- for each one. Results show a performance gain up to a mag- tions that index through masking certain memory addresses nitude higher than attempts without SIMD optimization. In for faster access. Additional requirements on vectorization addition to this, their summary of related work gives a good arise through the used operator function and data depen- review about research done with SIMD on general database dencies between tuples. The function must be supported by operations. used instruction set, while dependencies are solved through For stream partitioning, the degree in terms of numbers of rearrangements or
Recommended publications
  • Parallel Patterns for Adaptive Data Stream Processing
    Università degli Studi di Pisa Dipartimento di Informatica Dottorato di Ricerca in Informatica Ph.D. Thesis Parallel Patterns for Adaptive Data Stream Processing Tiziano De Matteis Supervisor Supervisor Marco Danelutto Marco Vanneschi Abstract In recent years our ability to produce information has been growing steadily, driven by an ever increasing computing power, communication rates, hardware and software sensors diffusion. is data is often available in the form of continuous streams and the ability to gather and analyze it to extract insights and detect patterns is a valu- able opportunity for many businesses and scientific applications. e topic of Data Stream Processing (DaSP) is a recent and highly active research area dealing with the processing of this streaming data. e development of DaSP applications poses several challenges, from efficient algorithms for the computation to programming and runtime systems to support their execution. In this thesis two main problems will be tackled: • need for high performance: high throughput and low latency are critical re- quirements for DaSP problems. Applications necessitate taking advantage of parallel hardware and distributed systems, such as multi/manycores or cluster of multicores, in an effective way; • dynamicity: due to their long running nature (24hr/7d), DaSP applications are affected by highly variable arrival rates and changes in their workload charac- teristics. Adaptivity is a fundamental feature in this context: applications must be able to autonomously scale the used resources to accommodate dynamic requirements and workload while maintaining the desired Quality of Service (QoS) in a cost-effective manner. In the current approaches to the development of DaSP applications are still miss- ing efficient exploitation of intra-operator parallelism as well as adaptations strategies with well known properties of stability, QoS assurance and cost awareness.
    [Show full text]
  • A Middleware for Efficient Stream Processing in CUDA
    Noname manuscript No. (will be inserted by the editor) A Middleware for E±cient Stream Processing in CUDA Shinta Nakagawa ¢ Fumihiko Ino ¢ Kenichi Hagihara Received: date / Accepted: date Abstract This paper presents a middleware capable of which are expressed as kernels. On the other hand, in- out-of-order execution of kernels and data transfers for put/output data is organized as streams, namely se- e±cient stream processing in the compute uni¯ed de- quences of similar data records. Input streams are then vice architecture (CUDA). Our middleware runs on the passed through the chain of kernels in a pipelined fash- CUDA-compatible graphics processing unit (GPU). Us- ion, producing output streams. One advantage of stream ing the middleware, application developers are allowed processing is that it can exploit the parallelism inherent to easily overlap kernel computation with data trans- in the pipeline. For example, the execution of the stages fer between the main memory and the video memory. can be overlapped with each other to exploit task par- To maximize the e±ciency of this overlap, our middle- allelism. Furthermore, di®erent stream elements can be ware performs out-of-order execution of commands such simultaneously processed to exploit data parallelism. as kernel invocations and data transfers. This run-time One of the stream architecture that bene¯t from capability can be used by just replacing the original the advantages mentioned above is the graphics pro- CUDA API calls with our API calls. We have applied cessing unit (GPU), originally designed for acceleration the middleware to a practical application to understand of graphics applications.
    [Show full text]
  • AMD Accelerated Parallel Processing Opencl Programming Guide
    AMD Accelerated Parallel Processing OpenCL Programming Guide November 2013 rev2.7 © 2013 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, AMD Accelerated Parallel Processing, the AMD Accelerated Parallel Processing logo, ATI, the ATI logo, Radeon, FireStream, FirePro, Catalyst, and combinations thereof are trade- marks of Advanced Micro Devices, Inc. Microsoft, Visual Studio, Windows, and Windows Vista are registered trademarks of Microsoft Corporation in the U.S. and/or other jurisdic- tions. Other names are for informational purposes only and may be trademarks of their respective owners. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or other- wise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as compo- nents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or envi- ronmental damage may occur.
    [Show full text]
  • Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated
    FineStream: Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated Architectures Feng Zhang and Lin Yang, Renmin University of China; Shuhao Zhang, Technische Universität Berlin and National University of Singapore; Bingsheng He, National University of Singapore; Wei Lu and Xiaoyong Du, Renmin University of China https://www.usenix.org/conference/atc20/presentation/zhang-feng This paper is included in the Proceedings of the 2020 USENIX Annual Technical Conference. July 15–17, 2020 978-1-939133-14-4 Open access to the Proceedings of the 2020 USENIX Annual Technical Conference is sponsored by USENIX. FineStream: Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated Architectures Feng Zhang1, Lin Yang1, Shuhao Zhang2;3, Bingsheng He3, Wei Lu1, Xiaoyong Du1 1Key Laboratory of Data Engineering and Knowledge Engineering (MOE), and School of Information, Renmin University of China 2DIMA, Technische Universität Berlin 3School of Computing, National University of Singapore [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] Abstract GPU memory via PCI-e before GPU processing, but the low Accelerating SQL queries on stream processing by utilizing bandwidth of PCI-e limits the performance of stream process- heterogeneous coprocessors, such as GPUs, has shown to be ing on GPUs. Hence, stream processing on GPUs needs to be an effective approach. Most works show that heterogeneous carefully designed to hide the PCI-e overhead. For example, coprocessors bring significant performance improvement be- prior works have explored pipelining the computation and cause of their high parallelism and computation capacity.
    [Show full text]
  • Lightsaber: Efficient Window Aggregation on Multi-Core Processors
    Research 28: Stream Processing SIGMOD ’20, June 14–19, 2020, Portland, OR, USA LightSaber: Efficient Window Aggregation on Multi-core Processors Georgios Theodorakis Alexandros Koliousis∗ Peter Pietzuch Imperial College London Graphcore Research Holger Pirk [email protected] [email protected] [email protected] [email protected] Imperial College London Abstract Invertible Aggregation (Sum) Non-Invertible Aggregation (Min) 200 Window aggregation queries are a core part of streaming ap- 140 150 Multiple TwoStacks 120 tuples/s) Multiple TwoStacks plications. To support window aggregation efficiently, stream 6 Multiple SoE 100 SlickDeque SlickDeque 80 100 SlideSide SlideSide processing engines face a trade-off between exploiting par- 60 allelism (at the instruction/multi-core levels) and incremen- 50 40 20 tal computation (across overlapping windows and queries). 0 0 Throughput (10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Existing engines implement ad-hoc aggregation and par- # Queries # Queries allelization strategies. As a result, they only achieve high Figure 1: Evaluating window aggregation queries performance for specific queries depending on the window definition and the type of aggregation function. an order of magnitude higher throughput compared to ex- We describe a general model for the design space of win- isting systems—on a 16-core server, it processes 470 million dow aggregation strategies. Based on this, we introduce records/s with 132 µs average latency. LightSaber, a new stream processing engine that balances parallelism and incremental processing when executing win- CCS Concepts dow aggregation queries on multi-core CPUs.
    [Show full text]
  • Parallel Stream Processing with MPI for Video Analytics and Data Visualization
    Parallel Stream Processing with MPI for Video Analytics and Data Visualization Adriano Vogel1 [0000−0003−3299−2641], Cassiano Rista1, Gabriel Justo1, Endrius Ewald1, Dalvan Griebler1;3[0000−0002−4690−3964], Gabriele Mencagli2, and Luiz Gustavo Fernandes1[0000−0002−7506−3685] 1 School of Technology, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre - Brazil [email protected] 2 Department of Computer Science, University of Pisa, Pisa - Italy 3 Laboratory of Advanced Research on Cloud Computing (LARCC), Tr^esde Maio Faculty (SETREM), Tr^esde Maio - Brazil Abstract. The amount of data generated is increasing exponentially. However, processing data and producing fast results is a technological challenge. Parallel stream processing can be implemented for handling high frequency and big data flows. The MPI parallel programming model offers low-level and flexible mechanisms for dealing with distributed ar- chitectures such as clusters. This paper aims to use it to accelerate video analytics and data visualization applications so that insight can be ob- tained as soon as the data arrives. Experiments were conducted with a Domain-Specific Language for Geospatial Data Visualization and a Person Recognizer video application. We applied the same stream par- allelism strategy and two task distribution strategies. The dynamic task distribution achieved better performance than the static distribution in the HPC cluster. The data visualization achieved lower throughput with respect to the video analytics due to the I/O intensive operations. Also, the MPI programming model shows promising performance outcomes for stream processing applications. Keywords: parallel programming, stream parallelism, distributed pro- cessing, cluster 1 Introduction Nowadays, we are assisting to an explosion of devices producing data in the form of unbounded data streams that must be collected, stored, and processed in real-time [12].
    [Show full text]
  • Design and Implementation of an FPGA-Based Scalable Pipelined
    Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation A dissertation submitted to the Kent State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy by Hong Wang November 2006 Dissertation written by Hong Wang B.A., Lanzhou University, 1990 M.A., Kent State University, 2002 Ph.D., Kent State University, 2006 Approved by ___Robert A. Walker ___________________, Chair, Doctoral Dissertation Committee ___Johnnie W. Baker ___________________, Members, Doctoral Dissertation Committee ___Kenneth E Batcher __________________ ___Eugene C. Gartland, Jr._______________ _____________________________________ Accepted by ___Robert A. Walker___________________, Chair, Department of Computer Science ___John R. D. Stalvey__________________, Dean, College of Arts and Sciences ii Table of Contents 1 INTRODUCTION........................................................................................................... 3 1.1 Overview of Associative Computing Research......................................................... 5 1.2 Associative Computing ............................................................................................... 7 1.2.1 Associative Search and Responder Processing......................................................... 7 1.2.2 Associative Reduction for Maximum / Minimum Value ......................................... 9 1.3 Applications of a Scalable Associative Processor..................................................
    [Show full text]
  • SABER: Window-Based Hybrid Stream Processing for Heterogeneous Architectures
    SABER: Window-Based Hybrid Stream Processing for Heterogeneous Architectures Alexandros Koliousis†, Matthias Weidlich†‡, Raul Castro Fernandez†, Alexander L. Wolf†, Paolo Costa], Peter Pietzuch† †Imperial College London ‡Humboldt-Universität zu Berlin ]Microsoft Research {akolious, mweidlic, rc3011, alw, costa, prp}@imperial.ac.uk ABSTRACT offered by heterogeneous servers: besides multi-core CPUs with Modern servers have become heterogeneous, often combining multi- dozens of processing cores, such servers also contain accelerators core CPUs with many-core GPGPUs. Such heterogeneous architec- such as GPGPUs with thousands of cores. As heterogeneous servers tures have the potential to improve the performance of data-intensive have become commonplace in modern data centres and cloud offer- stream processing applications, but they are not supported by cur- ings [24], researchers have proposed a range of parallel streaming al- rent relational stream processing engines. For an engine to exploit a gorithms for heterogeneous architectures, including for joins [36,51], heterogeneous architecture, it must execute streaming SQL queries sorting [28] and sequence alignment [42]. Yet, we lack the design with sufficient data-parallelism to fully utilise all available heteroge- of a general-purpose relational stream processing engine that can neous processors, and decide how to use each in the most effective transparently take advantage of accelerators such as GPGPUs while way. It must do this while respecting the semantics of streaming executing arbitrary streaming SQL queries with windowing [7]. SQL queries, in particular with regard to window handling. The design of such a streaming engine for heterogeneous archi- tectures raises three challenges, addressed in this paper: We describe SABER, a hybrid high-performance relational stream processing engine for CPUs and GPGPUs.
    [Show full text]
  • Analyzing Efficient Stream Processing on Modern Hardware
    Analyzing Efficient Stream Processing on Modern Hardware Steffen Zeuch 2, Bonaventura Del Monte 2, Jeyhun Karimov 2, Clemens Lutz 2, Manuel Renz 2, Jonas Traub 1, Sebastian Breß 1;2, Tilmann Rabl 1;2, Volker Markl 1;2 1Technische Universitat¨ Berlin, 2German Research Center for Artificial Intelligence fi[email protected] 384 Flink ABSTRACT 420 Memory Bandwidth 288 Spark Modern Stream Processing Engines (SPEs) process large 100 71 23:99 28 Storm data volumes under tight latency constraints. Many SPEs Java HC 10 6:25 execute processing pipelines using message passing on shared- 3:6 C++ HC Streambox Throughput nothing architectures and apply a partition-based scale-out [M records/s] 1 0:26 Saber strategy to handle high-velocity input streams. Further- Optimized more, many state-of-the-art SPEs rely on a Java Virtual Ma- Figure 1: Yahoo! Streaming Benchmark (1 Node). chine to achieve platform independence and speed up system development by abstracting from the underlying hardware. a large number of computing nodes in a cluster, i.e., scale- In this paper, we show that taking the underlying hard- out the processing. These systems trade single node perfor- ware into account is essential to exploit modern hardware mance for scalability to large clusters and use a Java Virtual efficiently. To this end, we conduct an extensive experimen- Machine (JVM) as the underlying processing environment tal analysis of current SPEs and SPE design alternatives for platform independence. While JVMs provide a high level optimized for modern hardware. Our analysis highlights po- of abstraction from the underlying hardware, they cannot tential bottlenecks and reveals that state-of-the-art SPEs are easily provide efficient data access due to processing over- not capable of fully exploiting current and emerging hard- heads induced by data (de-)serialization, objects scattering ware trends, such as multi-core processors and high-speed in main memory, virtual functions, and garbage collection.
    [Show full text]
  • Streambox: Modern Stream Processing on a Multicore Machine
    StreamBox: Modern Stream Processing on a Multicore Machine Hongyu Miao and Heejin Park, Purdue ECE; Myeongjae Jeon and Gennady Pekhimenko, Microsoft Research; Kathryn S. McKinley, Google; Felix Xiaozhu Lin, Purdue ECE https://www.usenix.org/conference/atc17/technical-sessions/presentation/miao This paper is included in the Proceedings of the 2017 USENIX Annual Technical Conference (USENIX ATC ’17). July 12–14, 2017 • Santa Clara, CA, USA ISBN 978-1-931971-38-6 Open access to the Proceedings of the 2017 USENIX Annual Technical Conference is sponsored by USENIX. StreamBox: Modern Stream Processing on a Multicore Machine Hongyu Miao1, Heejin Park1, Myeongjae Jeon2, Gennady Pekhimenko2, Kathryn S. McKinley3, and Felix Xiaozhu Lin1 1Purdue ECE 2Microsoft Research 3Google Abstract Most stream processing engines are distributed be- cause they assume processing requirements outstrip the Stream analytics on real-time events has an insatiable de- capabilities of a single machine [38, 28, 32]. How- mand for throughput and latency. Its performance on a ever, modern hardware advances make a single multi- single machine is central to meeting this demand, even in core machine an attractive streaming platform. These ad- a distributed system. This paper presents a novel stream vances include (i) high throughput I/O that significantly StreamBox processing engine called that exploits the improves ingress rate, e.g., Remote Direct Memory Ac- parallelism and memory hierarchy of modern multicore cess (RDMA) and 10Gb Ethernet; (ii) terabyte DRAMs StreamBox hardware. executes a pipeline of transforms that hold massive in-memory stream processing state; over records that may arrive out-of-order. As records ar- and (iii) a large number of cores.
    [Show full text]
  • A Media Enhanced Vector Architecture for Embedded Memory Systems
    A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis Report No. UCB/CSD-99-1059 July 1999 Computer Science Division (EECS) University of California Berkeley, California 94720 A Media-Enhanced Vector Architecture for Embedded Memory Systems by Christoforos Kozyrakis Research Project Submitted to the Department of Electrical Engineering and Computer Sciences, Uni- versity of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II. Approval for the Report and Comprehensive Examination: Committee: Professor David A. Patterson Research Advisor (Date) ******* Professor Katherine Yelick Second Reader (Date) A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis M.S. Report Abstract Next generation portable devices will require processors with both low energy consump- tion and high performance for media functions. At the same time, modern CMOS technology creates the need for highly scalable VLSI architectures. Conventional processor architec- tures fail to meet these requirements. This paper presents the architecture of Vector IRAM (VIRAM), a processor that combines vector processing with embedded DRAM technology. Vector processing achieves high multimedia performance with simple hardware, while em- bedded DRAM provides high memory bandwidth at low energy consumption. VIRAM pro- vides ¯exible support for media data types, short vectors, and DSP features. The vector pipeline is enhanced to hide DRAM latency without using caches. The peak performance is 3.2 GFLOPS (single precision) and maximum memory bandwidth is 25.6 GBytes/s. With a target power consumption of 2 Watts for the vector pipeline and the memory system, VIRAM supports 1.6 GFLOPS/Watt. For a set of representative media kernels, VIRAM sustains on average 88% of its peak performance, outperforming conventional SIMD media extensions and DSP processors by factors of 4.5 to 17.
    [Show full text]
  • Fine-Grained Real-Time Stream Processing with Cameo
    Move Fast and Meet Deadlines: Fine-grained Real-time Stream Processing with Cameo Le Xu, University of Illinois at Urbana-Champaign; Shivaram Venkataraman, UW-Madison; Indranil Gupta, University of Illinois at Urbana-Champaign; Luo Mai, University of Edinburgh; Rahul Potharaju, Microsoft https://www.usenix.org/conference/nsdi21/presentation/xu This paper is included in the Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation. April 12–14, 2021 978-1-939133-21-2 Open access to the Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation is sponsored by Move Fast and Meet Deadlines: Fine-grained Real-time Stream Processing with Cameo Le Xu1∗, Shivaram Venkataraman2, Indranil Gupta1, Luo Mai3, and Rahul Potharaju4 1University of Illinois at Urbana-Champaign, 2UW-Madison, 3University of Edinburgh, 4Microsoft Abstract Resource provisioning in multi-tenant stream processing sys- tems faces the dual challenges of keeping resource utilization high (without over-provisioning), and ensuring performance isolation. In our common production use cases, where stream- ing workloads have to meet latency targets and avoid breach- ing service-level agreements, existing solutions are incapable Figure 1: Slot-based system (Flink), Simple Actor system (Or- of handling the wide variability of user needs. Our framework leans), and our framework Cameo. called Cameo uses fine-grained stream processing (inspired by actor computation models), and is able to provide high latency. Others wish to maximize throughput under limited re- resource utilization while meeting latency targets. Cameo dy- sources, and yet others desire high resource utilization. Violat- namically calculates and propagates priorities of events based ing such user expectations is expensive, resulting in breaches on user latency targets and query semantics.
    [Show full text]