DOCSLIB.ORG

Mapping Streaming Applications to Opencl Abhishek Ray*1 *Student Author 1Nanyang Technological University

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Mapping Streaming Applications to Opencl Abhishek Ray*1 *Student Author 1Nanyang Technological University Mapping Streaming Applications to OpenCL Abhishek Ray*1 *Student Author 1Nanyang Technological University ABSTRACT 1.1 Motivation Graphic processing units (GPUs) have been gaining popularity in general purpose and high performance CUDA and OpenCL are two different programming computing. A GPU is made up of a number of frameworks for programming GPUs. CUDA is streaming multiprocessors (SM), each of which NVIDIA’s proprietary technology and is specific to consists of many processing cores. A large number of NVIDIA GPUs whereas OpenCL is an open and free general-purpose applications have been mapped onto standard managed by the Khronos Group [4] that can GPUs efficiently. Stream processing applications, be used to program different devices such as CPUs, however, exhibit properties such as unfavorable data GPUs and DSPs. Its portability is one of the prime movement patterns and low computation-to- motivations for porting framework to OpenCL. communication ratio that might lead to a poor performance on a GPU. We describe the automated 2. DESIGN mapping framework developed earlier that maps most The mapping framework is divided into two parts: stream processing applications onto NVIDIA GPUs StreamIT language – In StreamIt, the basic efficiently by taking into account its architectural programmable unit is called a Filter. It has a single characteristics. We then discuss the implementation input and a single output and its body is essentially details of porting the mapping framework to OpenCL Java-like code. StreamIt programs have a hierarchical running on AMD GPUs and evaluate the performance graph structure where a filter is represented by a leaf of the mapping framework by running several node. The flow of StreamIt programs can be further benchmarks. Performance between the generated distributed by placing filters into any of the composite CUDA and OpenCL code is compared based on blocks such as pipelines, splitters and joiners. different heuristics. 1. INTRODUCTION A GPU consists of a number of multi-threaded processors called streaming multiprocessors (SM). Each SM consists of execution cores, which execute in SIMD mode. On each SM, threads are grouped into scheduling units called wavefronts and warps, respectively, in AMD and NVIDIA terminology. Several warps/wavefronts can be supported on each Figure 1: Different Hierarchical Streams provided by SM at the same time. StreamIT Streaming applications are an important domain of Automated Mapping onto GPUs – applications. Streaming applications can be A filter executes in a sequence of steps. Firstly, it represented as graphs, which are composed of nodes reads the data from the memory. Secondly, it that communicate independently over data channels performs the computation on the data and lastly, it [1][6]. writes it back to the memory to pass it to the next processing filter. Usually the ratio between An automated mapping framework [2] was developed computation and memory access is small. Therefore, that maps stream processing applications onto GPUs if global memory is used to store the filter’s input and efficiently by taking into account architectural output data, most of the time will be spent on memory characteristics of NVIDIA GPUs. The mapping flow accesses. Thus, it is beneficial to bring this data onto captures the parallelism from the streaming language, the shared memory as the threads can access this models the parallel architecture of the GPU and uses a region of memory faster. novel execution model of heterogeneous threads, which is basically a mix of compute and memory In the framework two different types of threads are access threads. used: memory access (M) threads and compute (C) threads. M threads prefetch the data for the next C threads required for the execution of each stream stream execution while the C threads perform schedule, and the number of M threads accessing computation on the data fetched by M threads onto global memory are determined according to the the shared memory in the previous execution. stream schedule structure and specification of the As C threads are always ready for execution, they can target GPU. access the SM. Two components are built after this – A Kernel The automated mapping framework transforms the loader, which runs on the CPU and performs all the code in following ways: initializations and the GPU kernel code that executes on the device and performs the mapping and • Memory transfer operations with large latency are computation. clustered into dedicated threads. • The data flow is transformed based on the 3. MAPPING To OpenCL parallelism exhibited by StreamIt. Porting an application from CUDA to OpenCL is straightforward as both programming frameworks have similar syntax [3]. However, there are a few major differences. In CUDA, both the host code and the device code is compiled at the run time where as in OpenCL host code is compiled statically and the device code is compiled at run time. As a result, an additional header file is automatically generated in OpenCL, which stores all the macros, which are required, by both the host code and the device code. These macros were defined in the device code in CUDA. Another key difference is in the device initialization. Since OpenCL targets a lot of different platforms, it has a complicated initialization process as compared to CUDA. Table 1: Syntax Difference – Device Initialization CUDA OpenCL Figure 2: Automated Mapping Flow of the Framework Schedule<<<grid, status = clGetContextInfo(context, threads, CL_CONTEXT_DEVICES, ..); The mapping framework is implemented as an sharedSize>>>(in_stre commandQueue= am, out_stream, extension to the back-end of the StreamIt compiler. C thread_step, iterations) clCreateCommandQueue(context, code is generated by the application that can be devices[0], ..); compiled by the GPU compiler. The StreamIT compiler flattens the hierarchical stream graph and in_stream = clCreateBuffer(context, generates a schedule, which consists of the order and CL_MEM_READ_WRITE | CL_MEM_USE_HOST_PTR, .. ); the number of executions of each of these operators. After StreamIT generates the schedule, the mapping out_stream = clCreateBuffer(context, framework takes over as the generated schedule is CL_MEM_READ_WRITE | sequential and is meant for single-threaded execution. CL_MEM_USE_HOST_PTR,..); clBuildProgram(program, 1, devices, The requirements of each operator in the schedule are NULL, NULL, NULL); analyzed and a buffer layout is produced. After this various mapping parameters such as the number of stream schedules to execute in parallel, the number of kernel = clCreateKernel(program, “Schedule", &status); #Processing 1536 - Elements clSetKernelArg(kernel,0, #Core 800 1500 sizeof(cl_mem), (void *)&in_stream); clEnqueueNDRangeKernel(commandQ Clock ueue, kernel, .. ); (MHz) #Max BW 176 144 (GB/s) #Max 2703 1288 Table 2: Syntax Difference- Kernel Code GFLOPs CUDA OpenCL Global void Schedule kernel void Schedule( global Parameters used for the Graphs: (unsigned int *in_stream, unsigned int * in_stream, global unsigned int unsigned int * out_stream, const int S, the number of C threads per execution. *out_stream) { thread_step,const int iterations_total, • __local volatile unsigned int • F, the number of M threads that transfer data extern shared shared_mem) between global and SM memory. unsigned int • X – axis – number of parallel stream executions in volatile shared_mem[]; { each SM. • Performance is measured in FLOPS [5]. It is int iterations_start = int iterations_start = iterations_total calculated as the number of floating point iterations_total * *get_group_id(0) / operations / second. blockIdx.x / gridDim.x; get_num_groups(0); int • Performance is compared between OpenCL and int iterations_stop = iterations_stop = iterations_total * CUDA by taking into account their respective iterations_total * (get_group_id(0) + 1) / (blockIdx.x + 1) / get_num_groups(0); if FLOPS using the same parameters. It is calculated gridDim.x; if ((get_local_id(0) < WORKERS) && by FLOPSOPENCL / FLOPSCUDA * 100 ((threadIdx.x < (get_local_id(0) % 32 == 0)) WORKERS) && sync_work[get_local_id(0) / 32] = 0; 4.1 PERFORMANCE COMPARISON (threadIdx.x % 32 == BETWEEN GPU & CPU 0)) barrier(CLK_LOCAL_MEM_FE Performance between the GPU (Radeon HD 6970) sync_work[threadIdx.x / NCE); 32] = 0; and the CPU (Intel Xeon CPU E5540 @ 2.53 GHz) was compared. As expected, the GPU easily } syncthreads(); outperformed the CPU. } 40 35 30 GPU vs CPU 25 20 4. EXPERIMENTS Speedup 15 After mapping the streaming application to OpenCL, 10 different benchmarks were tested to check for 5 correctness of the generated code and to compare the 0 results of the OpenCL code with the CUDA code. The devices compared were AMD Radeon HD 6970 running OpenCL and NVIDIA Tesla C2050 running CUDA. Figure 3: Performance Comparison – GPU vs CPU Table 3: Architectural Differences between devices being compared AMD Radeon NVIDIA 4.2 PERFORMANCE COMPARISON HD 6970 Tesla C2050 BETWEEN OPENCL & CUDA #Compute 24 14 Unit Performance between OpenCL and CUDA was #Cores - 448 compared by taking into account the FLOPS (Floating Point Operations/Second). for our application. These factors are listed Memory Bandwidth, Floating Point Performance and 120 Architecture Related Differences. 100 80 Table 4: Comparison between the two devices based on 60 different heurestics for FFT benchmark 40 AMD Radeon NVIDIA Performance Performance 20 Comparison (%) OpenCL vs CUDA / S=1 / F=64 HD 6970 Tesla C2050 0 8 24 40 56 72 88 104 120 136 152 168 184 #BW 0.0105
Load more

Recommended publications
  • Parallel Patterns for Adaptive Data Stream Processing
    Università degli Studi di Pisa Dipartimento di Informatica Dottorato di Ricerca in Informatica Ph.D. Thesis Parallel Patterns for Adaptive Data Stream Processing Tiziano De Matteis Supervisor Supervisor Marco Danelutto Marco Vanneschi Abstract In recent years our ability to produce information has been growing steadily, driven by an ever increasing computing power, communication rates, hardware and software sensors diffusion. is data is often available in the form of continuous streams and the ability to gather and analyze it to extract insights and detect patterns is a valu- able opportunity for many businesses and scientific applications. e topic of Data Stream Processing (DaSP) is a recent and highly active research area dealing with the processing of this streaming data. e development of DaSP applications poses several challenges, from efficient algorithms for the computation to programming and runtime systems to support their execution. In this thesis two main problems will be tackled: • need for high performance: high throughput and low latency are critical re- quirements for DaSP problems. Applications necessitate taking advantage of parallel hardware and distributed systems, such as multi/manycores or cluster of multicores, in an effective way; • dynamicity: due to their long running nature (24hr/7d), DaSP applications are affected by highly variable arrival rates and changes in their workload charac- teristics. Adaptivity is a fundamental feature in this context: applications must be able to autonomously scale the used resources to accommodate dynamic requirements and workload while maintaining the desired Quality of Service (QoS) in a cost-effective manner. In the current approaches to the development of DaSP applications are still miss- ing efficient exploitation of intra-operator parallelism as well as adaptations strategies with well known properties of stability, QoS assurance and cost awareness.
    [Show full text]
  • A Middleware for Efficient Stream Processing in CUDA
    Noname manuscript No. (will be inserted by the editor) A Middleware for E±cient Stream Processing in CUDA Shinta Nakagawa ¢ Fumihiko Ino ¢ Kenichi Hagihara Received: date / Accepted: date Abstract This paper presents a middleware capable of which are expressed as kernels. On the other hand, in- out-of-order execution of kernels and data transfers for put/output data is organized as streams, namely se- e±cient stream processing in the compute uni¯ed de- quences of similar data records. Input streams are then vice architecture (CUDA). Our middleware runs on the passed through the chain of kernels in a pipelined fash- CUDA-compatible graphics processing unit (GPU). Us- ion, producing output streams. One advantage of stream ing the middleware, application developers are allowed processing is that it can exploit the parallelism inherent to easily overlap kernel computation with data trans- in the pipeline. For example, the execution of the stages fer between the main memory and the video memory. can be overlapped with each other to exploit task par- To maximize the e±ciency of this overlap, our middle- allelism. Furthermore, di®erent stream elements can be ware performs out-of-order execution of commands such simultaneously processed to exploit data parallelism. as kernel invocations and data transfers. This run-time One of the stream architecture that bene¯t from capability can be used by just replacing the original the advantages mentioned above is the graphics pro- CUDA API calls with our API calls. We have applied cessing unit (GPU), originally designed for acceleration the middleware to a practical application to understand of graphics applications.
    [Show full text]
  • AMD Accelerated Parallel Processing Opencl Programming Guide
    AMD Accelerated Parallel Processing OpenCL Programming Guide November 2013 rev2.7 © 2013 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD Arrow logo, AMD Accelerated Parallel Processing, the AMD Accelerated Parallel Processing logo, ATI, the ATI logo, Radeon, FireStream, FirePro, Catalyst, and combinations thereof are trade- marks of Advanced Micro Devices, Inc. Microsoft, Visual Studio, Windows, and Windows Vista are registered trademarks of Microsoft Corporation in the U.S. and/or other jurisdic- tions. Other names are for informational purposes only and may be trademarks of their respective owners. OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or other- wise, to any intellectual property rights is granted by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. AMD’s products are not designed, intended, authorized or warranted for use as compo- nents in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of AMD’s product could create a situation where personal injury, death, or severe property or envi- ronmental damage may occur.
    [Show full text]
  • Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated
    FineStream: Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated Architectures Feng Zhang and Lin Yang, Renmin University of China; Shuhao Zhang, Technische Universität Berlin and National University of Singapore; Bingsheng He, National University of Singapore; Wei Lu and Xiaoyong Du, Renmin University of China https://www.usenix.org/conference/atc20/presentation/zhang-feng This paper is included in the Proceedings of the 2020 USENIX Annual Technical Conference. July 15–17, 2020 978-1-939133-14-4 Open access to the Proceedings of the 2020 USENIX Annual Technical Conference is sponsored by USENIX. FineStream: Fine-Grained Window-Based Stream Processing on CPU-GPU Integrated Architectures Feng Zhang1, Lin Yang1, Shuhao Zhang2;3, Bingsheng He3, Wei Lu1, Xiaoyong Du1 1Key Laboratory of Data Engineering and Knowledge Engineering (MOE), and School of Information, Renmin University of China 2DIMA, Technische Universität Berlin 3School of Computing, National University of Singapore [email protected], [email protected], [email protected], [email protected], [email protected], [email protected] Abstract GPU memory via PCI-e before GPU processing, but the low Accelerating SQL queries on stream processing by utilizing bandwidth of PCI-e limits the performance of stream process- heterogeneous coprocessors, such as GPUs, has shown to be ing on GPUs. Hence, stream processing on GPUs needs to be an effective approach. Most works show that heterogeneous carefully designed to hide the PCI-e overhead. For example, coprocessors bring significant performance improvement be- prior works have explored pipelining the computation and cause of their high parallelism and computation capacity.
    [Show full text]
  • Lightsaber: Efficient Window Aggregation on Multi-Core Processors
    Research 28: Stream Processing SIGMOD ’20, June 14–19, 2020, Portland, OR, USA LightSaber: Efficient Window Aggregation on Multi-core Processors Georgios Theodorakis Alexandros Koliousis∗ Peter Pietzuch Imperial College London Graphcore Research Holger Pirk [email protected] [email protected] [email protected] [email protected] Imperial College London Abstract Invertible Aggregation (Sum) Non-Invertible Aggregation (Min) 200 Window aggregation queries are a core part of streaming ap- 140 150 Multiple TwoStacks 120 tuples/s) Multiple TwoStacks plications. To support window aggregation efficiently, stream 6 Multiple SoE 100 SlickDeque SlickDeque 80 100 SlideSide SlideSide processing engines face a trade-off between exploiting par- 60 allelism (at the instruction/multi-core levels) and incremen- 50 40 20 tal computation (across overlapping windows and queries). 0 0 Throughput (10 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 Existing engines implement ad-hoc aggregation and par- # Queries # Queries allelization strategies. As a result, they only achieve high Figure 1: Evaluating window aggregation queries performance for specific queries depending on the window definition and the type of aggregation function. an order of magnitude higher throughput compared to ex- We describe a general model for the design space of win- isting systems—on a 16-core server, it processes 470 million dow aggregation strategies. Based on this, we introduce records/s with 132 µs average latency. LightSaber, a new stream processing engine that balances parallelism and incremental processing when executing win- CCS Concepts dow aggregation queries on multi-core CPUs.
    [Show full text]
  • Parallel Stream Processing with MPI for Video Analytics and Data Visualization
    Parallel Stream Processing with MPI for Video Analytics and Data Visualization Adriano Vogel1 [0000−0003−3299−2641], Cassiano Rista1, Gabriel Justo1, Endrius Ewald1, Dalvan Griebler1;3[0000−0002−4690−3964], Gabriele Mencagli2, and Luiz Gustavo Fernandes1[0000−0002−7506−3685] 1 School of Technology, Pontifical Catholic University of Rio Grande do Sul, Porto Alegre - Brazil [email protected] 2 Department of Computer Science, University of Pisa, Pisa - Italy 3 Laboratory of Advanced Research on Cloud Computing (LARCC), Tr^esde Maio Faculty (SETREM), Tr^esde Maio - Brazil Abstract. The amount of data generated is increasing exponentially. However, processing data and producing fast results is a technological challenge. Parallel stream processing can be implemented for handling high frequency and big data flows. The MPI parallel programming model offers low-level and flexible mechanisms for dealing with distributed ar- chitectures such as clusters. This paper aims to use it to accelerate video analytics and data visualization applications so that insight can be ob- tained as soon as the data arrives. Experiments were conducted with a Domain-Specific Language for Geospatial Data Visualization and a Person Recognizer video application. We applied the same stream par- allelism strategy and two task distribution strategies. The dynamic task distribution achieved better performance than the static distribution in the HPC cluster. The data visualization achieved lower throughput with respect to the video analytics due to the I/O intensive operations. Also, the MPI programming model shows promising performance outcomes for stream processing applications. Keywords: parallel programming, stream parallelism, distributed pro- cessing, cluster 1 Introduction Nowadays, we are assisting to an explosion of devices producing data in the form of unbounded data streams that must be collected, stored, and processed in real-time [12].
    [Show full text]
  • Design and Implementation of an FPGA-Based Scalable Pipelined
    Design and Implementation of an FPGA-Based Scalable Pipelined Associative SIMD Processor Array with Specialized Variations for Sequence Comparison and MSIMD Operation A dissertation submitted to the Kent State University in partial fulfillment of the requirements for the degree of Doctor of Philosophy by Hong Wang November 2006 Dissertation written by Hong Wang B.A., Lanzhou University, 1990 M.A., Kent State University, 2002 Ph.D., Kent State University, 2006 Approved by ___Robert A. Walker ___________________, Chair, Doctoral Dissertation Committee ___Johnnie W. Baker ___________________, Members, Doctoral Dissertation Committee ___Kenneth E Batcher __________________ ___Eugene C. Gartland, Jr._______________ _____________________________________ Accepted by ___Robert A. Walker___________________, Chair, Department of Computer Science ___John R. D. Stalvey__________________, Dean, College of Arts and Sciences ii Table of Contents 1 INTRODUCTION........................................................................................................... 3 1.1 Overview of Associative Computing Research......................................................... 5 1.2 Associative Computing ............................................................................................... 7 1.2.1 Associative Search and Responder Processing......................................................... 7 1.2.2 Associative Reduction for Maximum / Minimum Value ......................................... 9 1.3 Applications of a Scalable Associative Processor..................................................
    [Show full text]
  • SABER: Window-Based Hybrid Stream Processing for Heterogeneous Architectures
    SABER: Window-Based Hybrid Stream Processing for Heterogeneous Architectures Alexandros Koliousis†, Matthias Weidlich†‡, Raul Castro Fernandez†, Alexander L. Wolf†, Paolo Costa], Peter Pietzuch† †Imperial College London ‡Humboldt-Universität zu Berlin ]Microsoft Research {akolious, mweidlic, rc3011, alw, costa, prp}@imperial.ac.uk ABSTRACT offered by heterogeneous servers: besides multi-core CPUs with Modern servers have become heterogeneous, often combining multi- dozens of processing cores, such servers also contain accelerators core CPUs with many-core GPGPUs. Such heterogeneous architec- such as GPGPUs with thousands of cores. As heterogeneous servers tures have the potential to improve the performance of data-intensive have become commonplace in modern data centres and cloud offer- stream processing applications, but they are not supported by cur- ings [24], researchers have proposed a range of parallel streaming al- rent relational stream processing engines. For an engine to exploit a gorithms for heterogeneous architectures, including for joins [36,51], heterogeneous architecture, it must execute streaming SQL queries sorting [28] and sequence alignment [42]. Yet, we lack the design with sufficient data-parallelism to fully utilise all available heteroge- of a general-purpose relational stream processing engine that can neous processors, and decide how to use each in the most effective transparently take advantage of accelerators such as GPGPUs while way. It must do this while respecting the semantics of streaming executing arbitrary streaming SQL queries with windowing [7]. SQL queries, in particular with regard to window handling. The design of such a streaming engine for heterogeneous archi- tectures raises three challenges, addressed in this paper: We describe SABER, a hybrid high-performance relational stream processing engine for CPUs and GPGPUs.
    [Show full text]
  • Analyzing Efficient Stream Processing on Modern Hardware
    Analyzing Efficient Stream Processing on Modern Hardware Steffen Zeuch 2, Bonaventura Del Monte 2, Jeyhun Karimov 2, Clemens Lutz 2, Manuel Renz 2, Jonas Traub 1, Sebastian Breß 1;2, Tilmann Rabl 1;2, Volker Markl 1;2 1Technische Universitat¨ Berlin, 2German Research Center for Artificial Intelligence fi[email protected] 384 Flink ABSTRACT 420 Memory Bandwidth 288 Spark Modern Stream Processing Engines (SPEs) process large 100 71 23:99 28 Storm data volumes under tight latency constraints. Many SPEs Java HC 10 6:25 execute processing pipelines using message passing on shared- 3:6 C++ HC Streambox Throughput nothing architectures and apply a partition-based scale-out [M records/s] 1 0:26 Saber strategy to handle high-velocity input streams. Further- Optimized more, many state-of-the-art SPEs rely on a Java Virtual Ma- Figure 1: Yahoo! Streaming Benchmark (1 Node). chine to achieve platform independence and speed up system development by abstracting from the underlying hardware. a large number of computing nodes in a cluster, i.e., scale- In this paper, we show that taking the underlying hard- out the processing. These systems trade single node perfor- ware into account is essential to exploit modern hardware mance for scalability to large clusters and use a Java Virtual efficiently. To this end, we conduct an extensive experimen- Machine (JVM) as the underlying processing environment tal analysis of current SPEs and SPE design alternatives for platform independence. While JVMs provide a high level optimized for modern hardware. Our analysis highlights po- of abstraction from the underlying hardware, they cannot tential bottlenecks and reveals that state-of-the-art SPEs are easily provide efficient data access due to processing over- not capable of fully exploiting current and emerging hard- heads induced by data (de-)serialization, objects scattering ware trends, such as multi-core processors and high-speed in main memory, virtual functions, and garbage collection.
    [Show full text]
  • Streambox: Modern Stream Processing on a Multicore Machine
    StreamBox: Modern Stream Processing on a Multicore Machine Hongyu Miao and Heejin Park, Purdue ECE; Myeongjae Jeon and Gennady Pekhimenko, Microsoft Research; Kathryn S. McKinley, Google; Felix Xiaozhu Lin, Purdue ECE https://www.usenix.org/conference/atc17/technical-sessions/presentation/miao This paper is included in the Proceedings of the 2017 USENIX Annual Technical Conference (USENIX ATC ’17). July 12–14, 2017 • Santa Clara, CA, USA ISBN 978-1-931971-38-6 Open access to the Proceedings of the 2017 USENIX Annual Technical Conference is sponsored by USENIX. StreamBox: Modern Stream Processing on a Multicore Machine Hongyu Miao1, Heejin Park1, Myeongjae Jeon2, Gennady Pekhimenko2, Kathryn S. McKinley3, and Felix Xiaozhu Lin1 1Purdue ECE 2Microsoft Research 3Google Abstract Most stream processing engines are distributed be- cause they assume processing requirements outstrip the Stream analytics on real-time events has an insatiable de- capabilities of a single machine [38, 28, 32]. How- mand for throughput and latency. Its performance on a ever, modern hardware advances make a single multi- single machine is central to meeting this demand, even in core machine an attractive streaming platform. These ad- a distributed system. This paper presents a novel stream vances include (i) high throughput I/O that significantly StreamBox processing engine called that exploits the improves ingress rate, e.g., Remote Direct Memory Ac- parallelism and memory hierarchy of modern multicore cess (RDMA) and 10Gb Ethernet; (ii) terabyte DRAMs StreamBox hardware. executes a pipeline of transforms that hold massive in-memory stream processing state; over records that may arrive out-of-order. As records ar- and (iii) a large number of cores.
    [Show full text]
  • A Media Enhanced Vector Architecture for Embedded Memory Systems
    A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis Report No. UCB/CSD-99-1059 July 1999 Computer Science Division (EECS) University of California Berkeley, California 94720 A Media-Enhanced Vector Architecture for Embedded Memory Systems by Christoforos Kozyrakis Research Project Submitted to the Department of Electrical Engineering and Computer Sciences, Uni- versity of California at Berkeley, in partial satisfaction of the requirements for the degree of Master of Science, Plan II. Approval for the Report and Comprehensive Examination: Committee: Professor David A. Patterson Research Advisor (Date) ******* Professor Katherine Yelick Second Reader (Date) A Media-Enhanced Vector Architecture for Embedded Memory Systems Christoforos Kozyrakis M.S. Report Abstract Next generation portable devices will require processors with both low energy consump- tion and high performance for media functions. At the same time, modern CMOS technology creates the need for highly scalable VLSI architectures. Conventional processor architec- tures fail to meet these requirements. This paper presents the architecture of Vector IRAM (VIRAM), a processor that combines vector processing with embedded DRAM technology. Vector processing achieves high multimedia performance with simple hardware, while em- bedded DRAM provides high memory bandwidth at low energy consumption. VIRAM pro- vides ¯exible support for media data types, short vectors, and DSP features. The vector pipeline is enhanced to hide DRAM latency without using caches. The peak performance is 3.2 GFLOPS (single precision) and maximum memory bandwidth is 25.6 GBytes/s. With a target power consumption of 2 Watts for the vector pipeline and the memory system, VIRAM supports 1.6 GFLOPS/Watt. For a set of representative media kernels, VIRAM sustains on average 88% of its peak performance, outperforming conventional SIMD media extensions and DSP processors by factors of 4.5 to 17.
    [Show full text]
  • Fine-Grained Real-Time Stream Processing with Cameo
    Move Fast and Meet Deadlines: Fine-grained Real-time Stream Processing with Cameo Le Xu, University of Illinois at Urbana-Champaign; Shivaram Venkataraman, UW-Madison; Indranil Gupta, University of Illinois at Urbana-Champaign; Luo Mai, University of Edinburgh; Rahul Potharaju, Microsoft https://www.usenix.org/conference/nsdi21/presentation/xu This paper is included in the Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation. April 12–14, 2021 978-1-939133-21-2 Open access to the Proceedings of the 18th USENIX Symposium on Networked Systems Design and Implementation is sponsored by Move Fast and Meet Deadlines: Fine-grained Real-time Stream Processing with Cameo Le Xu1∗, Shivaram Venkataraman2, Indranil Gupta1, Luo Mai3, and Rahul Potharaju4 1University of Illinois at Urbana-Champaign, 2UW-Madison, 3University of Edinburgh, 4Microsoft Abstract Resource provisioning in multi-tenant stream processing sys- tems faces the dual challenges of keeping resource utilization high (without over-provisioning), and ensuring performance isolation. In our common production use cases, where stream- ing workloads have to meet latency targets and avoid breach- ing service-level agreements, existing solutions are incapable Figure 1: Slot-based system (Flink), Simple Actor system (Or- of handling the wide variability of user needs. Our framework leans), and our framework Cameo. called Cameo uses fine-grained stream processing (inspired by actor computation models), and is able to provide high latency. Others wish to maximize throughput under limited re- resource utilization while meeting latency targets. Cameo dy- sources, and yet others desire high resource utilization. Violat- namically calculates and propagates priorities of events based ing such user expectations is expensive, resulting in breaches on user latency targets and query semantics.
    [Show full text]