Cover Feature Invited Paper Solid-State Transmitters for IFF and SSR Systems

John Walker and James Custer Integra Technologies Inc.

dentify Friend or Foe (IFF) and Secondary is at 1030 MHz, to the aircraft. On receipt of Surveillance Radar (SSR) systems are, from this pulse the aircraft on-board transponder Ia hardware point of view, essentially the sends back a reply at a different frequency of same system although the application is differ- 1090 MHz which, if it is a friendly aircraft, will ent. The radar systems developed in World War contain a coded message that identifies it as a II could determine the range and bearing of air- friendly aircraft. Thus IFF systems are basical- craft but could not distinguish between friendly ly military in nature. Further details about IFF and hostile planes. IFF systems were developed and SSR systems can be found in1-3. at the same time to solve that deficiency. Civil aviation has a different need to the The basic concept is illustrated in Figure military, requiring information such as the air- 1. Although today’s systems are digital rather craft’s flight number, its altitude etc. The basic than analog and the frequencies used are dif- difference between the military and civil uses ferent, the basic concept shown in Figure 1 of the IFF system is the information that is sent has not changed. A ground-based transmitter back to the ground station in the return pulse sends out an interrogating pulse, which today at 1090 MHz. Civil aviation labels this system a Secondary Surveillance Radar, but this is a misnomer since the returned pulse contains a IFF data stream containing information about the flight, so in reality it is a communication system Transponder Interrogator Pulse rather than a radar system. Nevertheless, it is IFF Transponder Pulse universally termed an SSR and so this nomen- Antenna clature will be used in this article. Figure 2 Radar Transmitter Pulse shows a typical SSR system co-located with the eturn Echo R S-Band primary radar system which is used to detect any object in the path of the radar beam. Antenna SSR message formats have evolved over the years and the system that is in the most wide- From spread use today is the Mode S version which Radar Radar XMTR Receiver transmits a train of 128 pulses of 0.5 µs on, 0.5 Responder µs off with a long term duty cycle of 1 percent. Interrogator As far as transistors are concerned, this is a very benign pulse train from a thermal point Radar “A” Scope Narrow Wide Emergency of view and any transistor technology can eas- ily withstand this. However, a newer version s Fig. 1 Principle of an IFF system. Source: Radar Bulletin 8A, U.S. Navy, 1950. of Mode S is being implemented called Ex- tended Length Message (ELM) which uses a Reprinted with permission of MICROWAVE JOURNAL® from the January 2016 issue. ©2016 Horizon House Publications, Inc. CoverFeature

transistors are often of transistors. It also only requires a operated at about 2 single positive supply voltage. dB into compression BJTs also have one other extremely which helps achieve important attribute that is not enjoyed high efficiency. by either GaN HEMTs or LDMOS The following transistors. BJTs are operated in Class is an assessment of C so that when there is no applied RF the merits and dis- pulse the transistor does not pass any advantages of sili- DC current. Consequently, BJT-based con bipolar, silicon SSRs inherently emit almost zero shot LDMOS and gal- noise in the off period. LDMOS and lium nitride HEMT GaN HEMTs, on the other hand, are technologies for this always biased Class A/B and so emit application. shot noise in the off-period which is s Fig. 2 Airport co-located primary and secondary radar system. injected into the receiver along with The SSR radar antenna is at the top with the S-Band antenna immediately beneath it. (Photo courtesy of Shutterstock.com). SILICON BIPOLAR the returned signal from the aircraft TRANSISTORS transponder causing receiver de-sen- Early solid-state sitization. Black SSR systems used The required quiescent current Red Si bipolar junction for LDMOS and GaN is roughly pro- transistors (BJT) portional to the output power of the C3 as this was the only transistor so it is more of an issue for transistor technol- the kW-level transistors used in SSR ogy available and systems than in low power systems. C2 BJT-based SSRs are The solution to this problem is to use still being manufac- more complex DC circuitry which IB1011S1500 LOT#-SER#

INTEGRA tured today. In fact, shuts down the transistor completely the standard mode in the off-period but which turns the S waveform3 suits gate bias on ahead of the RF pulse5. C1 the characteristics BJTs can also be designed for the of BJTs very well be- ELM version of mode S, but the maxi- cause the thermally mum output power drops to about 500 benign waveform W due to thermal limitations. This enables full advan- means that a minimum of 8 BJTs are needed for a complete SSR. This has s Fig. 3 Circuit for IB1011S1500 1.5 kW Si bipolar junction tage to be taken of transistor for SSR applications. the high power den- serious size and cost implications for sity capability of a the system. Thus, although BJT tech- 48 pulse burst of 32 µs on, 18 µs off BJT. With a requirement for around 4 nology is well-proven and extremely (i.e., 67 percent duty cycle within the kW of output power, the ‘holy grail’ for reliable it is unlikely that any new sys- pulse) with a long-term duty cycle of an SSR manufacturer has been a tran- tems will be designed using BJTs. 6.4 percent. sistor with an output power of at least BJTs also have three other disad- As far as the transistor is concerned 1 kW since then it is easy to combine vantages, namely they use environ- the off period during the pulse burst four of these devices to achieve 4 kW. mentally unfriendly BeO packages is not long enough for the transistor In fact, a little more than 1 kW is which are also expensive, and they to fully cool down so from a thermal needed to allow for losses in the com- have much lower gain than either perspective the ELM Mode S pulse biner and the insertion loss of the LDMOS or GaN HEMTs which train looks like a 2.4 ms pulse with isolator used at the output to protect means that more gain stages are need- an overall duty cycle of 6.4 percent. the transistor from a high VSWR mis- ed in the amplifier which, of course, This very long effective pulse means match. BJTs fulfill this requirement adds to size and cost. Finally, the that the transistor is running close to nicely with devices up to 1.5 kW4. BJTs VSWR withstand capability for a 1 CW conditions and many of the early for this application are always operated kW device is normally specified at 3:1 generations of high-power pulsed RF in Class C mode with no applied DC which means that the device needs to transistors cannot be run CW without voltage to the base-emitter junction be protected by a high power isolator substantial de-rating. and the typical efficiency is about 60 to which also adds to the overall cost. This has necessitated the redesign 65 percent for a 1 kW device. of many SSR systems. The typical BJTs have the simplest RF circuitry SILICON LDMOS output power of a SSR transmitter of any technology. Figure 3 shows the Silicon LDMOS became the main is around 4 kW for the ground sta- circuit for the 1.5 kW 1030 MHz BJT, technology for communications and tion while the airborne transponder is just two capacitors are used on the basestations in the mid 1990s, and lower power at 1 to 2 kW. There is no PCB plus a large external reservoir it has since become widely accepted requirement for linearity and so the capacitor that is common to all types for L-Band avionics and radar appli- CoverFeature cations, not least because it can be tion occurs, i.e., the manufactured in a standard 8" CMOS transistor has zero Gate Source Oxide Drain wafer fabrication facility resulting on-resistance or + – in lower cost than bipolar RF power knee voltage. Thus N N transistors. Also, kW-level LDMOS the transistor needs P* Sinker p Well transistors are readily available that to see a load of 1.25 p epi Layer can withstand a 20:1 VSWR mismatch V but the RF path and this leads to a further system-lev- from the plane of p* Substrate el cost reduction since the expensive the current genera- isolator that needs to be added at the tor to the external output of a bipolar transistor amplifier 50 V load is bound s Fig. 4 Parasitic bipolar transistor inside every LDMOS device. can be eliminated. to have some series A 1 kW LDMOS transistor typi- resistance, even 0.1 V would cause the di cally has about 10 dB more gain than efficiency to be reduced to 90 percent V = L the corresponding BJT device so fewer of its theoretical maximum value, for dt driver stages are needed leading to example, the ideal Class B efficiency further cost and size reduction. 1 kW would fall to 70 percent maximum. LDMOS transistors are available in both All of the above efficiency-reduc- single-ended and push-pull formats. Sin- tion mechanisms apply equally well gle-ended versions have simpler, smaller to both GaN and LDMOS, but the s Fig. 5 The drain bias inductor creates a and cheaper circuits than push-pull ver- next issue is more of a problem for voltage spike under pulsed operation. sions since no balun is needed. LDMOS than GaN. Real transistors While the above highlights the plus always have a finite on-resistance or, that the harmonics are shorted to points of LDMOS, there are also a equivalently, knee voltage. This pre- ground by the transistor’s own internal couple of negative features. Firstly, vents full voltage modulation from capacitance so that it isn’t possible to since LDMOS is always operated in occurring and leads to a further ef- present the required high impedance Class A/B rather than the Class C used ficiency reduction7. GaN HEMT needed for either Class F or Inverse by BJTs, the efficiency of an LDMOS devices have a lower on-resistance Class F operation. amplifier is typically 5 to 10 percent for the same output power than The second issue with LDMOS lower than is achieved with a bipolar- LDMOS, and so do not suffer from is that it has an inherent and unfor- based transmitter, usually in the mid this efficiency reduction mechanism tunate attribute, namely there is an 50 percent range. It is worth examin- to the same extent. Taken together, it unwanted parasitic bipolar transistor ing why the efficiency is much lower is easy to see why all these efficiency inside every LDMOS device. Figure than the theoretical 78.5 percent that degradation mechanisms result in 4 shows where this is formed in an an ideal Class B amplifier would have. LDMOS 1 kW transistors operated in LDMOS device. Early LDMOS de- Class A/B bias is used as a compromise Class A/B have typical efficiencies in vices had a checkered start when first between the best gain which occurs in the low to mid 50 percent range re- tested for high-power pulsed applica- Class A but which has the worst effi- gardless of whether they are push-pull tions with devices failing. The prob- ciency, and Class B which has the best or single-ended. lem was soon diagnosed8 as being efficiency but the lowest gain. This The obvious solution to achieve bet- caused by latch-up of the parasitic bi- fact alone accounts for a few percent- ter efficiency is to use one of the very polar transistor under fast rise and fall age points reduction in the maximum high efficiency modes such as Class E times associated with pulsed opera- efficiency from 78.5 percent which or F, but this is where LDMOS is at tion. Invariably, the drain bias to the would occur in an ideal class B ampli- a distinct disadvantage compared with transistor is applied via an inductor fier without any waveform clipping. GaN. These high efficiency modes as shown in Figure 5, but under fast However, it was mentioned ear- all involve non-sinusoidal waveforms rise and fall times a large enough volt- lier that the transistors in an SSR are which mean that the output matching age spike can be generated via L di/dt typically operated about 2 dB into circuit must present a specific imped- action to turn-on the parasitic bipolar compression. This is very beneficial ance to the transistor not just at the transistor and cause device failure. in terms of increasing the power out- fundamental frequency but at the har- The higher the power of the tran- put, if this didn’t happen then to get monics as well. In the case of Class F sistor, the higher is the value of the 1 kW would require an even larger it is required that the circuit presents di/dt term and so high power tran- and more expensive transistor but, a very high impedance to the transis- sistors are more prone to this prob- as Cripps6 has shown, this also gives tor’s internal current generator at odd- lem than low power devices. Manu- rise to another small reduction in ef- order harmonics and a short-circuit to facturers have devised proprietary ficiency. even-order harmonics. Conversely, for methods of reducing this effect, but A 1 kW transistor operated from Inverse Class F, a short-circuit to odd- in truth these techniques merely a 50 V supply requires that the cur- order harmonics and an open-circuit suppress the problem rather than rent generator in the transistor sees to even-order harmonics is needed. eliminate it. Device failures can a load resistance of 502/2*1000 V However, the output capacitance of still occur if the rise/fall time is fast 2 (Vrf /2PoutV) if full voltage modula- a 1 kW LDMOS transistor is so high enough. CoverFeature

GaN HEMT TRANSISTORS that each transistor can accommo- GaN HEMT devices use SiC date. However, all transistors have f = 1030 MHz, Idq = 150 mA ELM Mode S: substrates rather than Si substrates a finite output capacitance and this 48 × (32 µs On, 18 µs Off) 6.4% DC ( % ) D rain E fficiency which greatly add to their cost, and forms the first element in the output 20 80 the much smaller wafer size (4" ver- matching network. Hence the match- 18 70 sus 8") exacerbates the cost issue still ing network external to the transistor 16 60 14 50 further. Although GaN devices are has to transform not RL to 50 V, but 12 40

moving to 6" SiC substrates, there will RL in parallel with Cds to 50 V. The G ain ( d B ) 10 30 still be a cost penalty for using GaN. bandwidth over which it is possible to 8 20 6 10 However, there is a mitigating factor; match RL in parallel with Cds is limit- 49 51 53 55 57 59 61 9 GaN HEMT devices have a much ed by Fano’s law , RL becomes lower Pout (dBm) higher power density than LDMOS and Cds becomes higher as the power s Fig. 6 Gain and efficiency with harmonic and so the die size is a little smaller output increases and so the usable tuning for IGN1030L1000. for a given output power — but no- bandwidth of the transistor becomes where near enough to fully compen- smaller as the power increases. that terminology, which means that a sate the smaller size and higher cost The lower capacitance of GaN en- larger voltage modulation can be ob- of the substrate. Consequently, GaN ables much higher power transistors tained which directly aids the achieve- must offer substantial performance to be produced than is possible with ment of higher efficiency7. advantages compared with LDMOS LDMOS, 1 kW devices10 are already Finally, another aspect where GaN to justify its use in this application, so commercially available and 1.5 to 2 significantly differs from LDMOS is what are these advantages? kW devices will shortly be released. the ability to operate at voltages well Probably the single most signifi- In fact, the limit on the power output in excess of 50 V where state-of-the-art cant advantage is the much lower ca- from GaN under pulsed conditions is avionics LDMOS technology operates. pacitance per watt that GaN HEMTs set not by the impedance but on the For instance, UHF GaN radar tran- offer compared with LDMOS. This availability of a suitable package to fit sistors have recently been reported11 much lower capacitance is a conse- all the GaN die inside. successfully operating at 125 V drain quence of the much greater power The low capacitance per watt also bias, and there is no particular reason density (capacitance is proportional results in higher efficiency. It was men- why such capabilities could not be ex- to gate periphery so if the same power tioned in the LDMOS section that the tended to IFF and SSR applications is achieved from a smaller periphery high output capacitance of the device in L-Band. From the same equation it then you get lower capacitance). The results in all harmonics being termi- emerges that for the same load imped- greater power density of GaN is often nated in a short-circuit within the tran- ance RL, increasing the supply volt- cited as its greatest advantage, but this sistor die itself. This is just what one age to 100 V would allow a four-fold is a very debatable attribute. The high wants for Class B operation but not power output increase under pulsed power density creates thermal prob- what is needed if you want to use one conditions or, alternatively, keeping lems, especially in CW applications, of the higher efficiency modes such as the same output power would result in which is why the GaN epitaxial layer Class F. The recommended circuit for a four-fold reduction in the transistor has to be grown on SiC substrates the device shown in Figure 6, for ex- gate periphery leading to smaller die rather than Si for high power transis- ample, presents a specific impedance that would fit in a smaller package; this tors since SiC has a four-fold higher to the transistor at the second harmon- translates to lower weight for airborne thermal conductivity than Si. ic to increase the efficiency. systems. The higher impedance also Consequently, the higher power The fact that the efficiency can be facilitates harmonic tuning to boost ef- density attribute is actually a cost increased by altering the value of im- ficiency even further. driver. However, the low capacitance pedance at the second harmonic im- The reason why GaN is better suit- per watt has several very desirable plies that the capacitance within the ed than LDMOS for operation in the consequences. Firstly, it enables GaN chip is sufficiently low that the 100 V range is that GaN fundamen- higher power transistors to be pro- second harmonic is not being com- tal physics material properties allow duced. In pulsed applications, the pletely shorted within the die itself. higher breakdown voltage without a fundamental limit on how much pow- Figure 6 shows a graph of gain and significant increase of the on-resis- er a transistor can deliver is not set by efficiency versus output power from tance of the device, which is mostly thermal limitations but on the abil- which it can be seen that the typi- controlled by the gate-drain spacing ity of the output matching network cal efficiency during the pulse under or drift region of the transistor. to transform an ever-lower output Mode S ELM operation at 1 kW is impedance to 50 V. At first sight it 80 percent, about 25 percent higher CONCLUSION might be thought that GaN HEMTs than is achieved using LDMOS, and The upgrade of ATC systems to be have no advantage over LDMOS in better even than is achieved with a capable of operating under ELM mode 2 this regard since RL=Vrf /2PoutV is Class C BJT. The 1 kW output power has created the need for RF power identical for both types of transis- is achieved at 1 dB gain compression. transistors that can deliver >1 kW un- tor if operated from the same supply A further advantage of GaN HEMTs der almost CW conditions. BJT devic- voltage — ignoring any difference over LDMOS is the lower on-resis- es have been the dominant transistor in the maximum voltage modulation tance, or knee voltage if you prefer technology for previous generations of CoverFeature

ATC equipment but they are not the the thermal design of the transistor. 4. http://www.integratech.com/ProductDoc. best technology for new equipment. Finally, GaN offers the potential for ashx?Id=135. 5. Daniel Koyama, Apet Barsegyan and John LDMOS is the clear winner when it offering much higher power than is Walker, “Implications of Using kW-level comes to cost, not just because they are possible with LDMOS by using higher GaN Transistors in Radar Systems,” IEEE the cheapest but also because the very supply voltages, and this will help over- COMCAS Conference, Tel Aviv, Nov. 224, high VSWR ruggedness that they offer come the cost disadvantage. 2015. 6. S.C. Cripps, “RF Power Amplifiers for enables the expensive protection iso- Wireless Communications,” p. 142, Artech lator to be eliminated. However, they ACKNOWLEDGMENTS House. have the lowest efficiency of any of the The authors would like to acknowl- 7. S.C. Cripps, “RF Power Amplifiers for three transistor technologies, and care edge the contribution made by many Wireless Communications,” pp. 59261, needs to be taken to control the pulse other engineers at Integra without Artech House. 8. S.J.C.H. Theeuwen, J.A.M. de Boet, V.J. rise/fall times to prevent transistor fail- whom this article would not have Bloem and W.J.A.M Sneijers, “LDMOS ure due to latch-up of their inherent been possible, in particular Gabriele Ruggedness Reliability,” Microwave Jour- parasitic BJT. Formicone and Jeff Burger. n nal, April 2009. GaN HEMT devices have by far the 9. H.W. Bode, “Network Analysis and Feed- References back Amplifier Design,” Van Nostrand Re- highest efficiency but are more expen- inhold. sive than LDMOS, and current gen- 1. https://en.wikipedia.org/wiki/Identifica- tion_friend_or_foe. 10. http://www.integratech.com/ProductDoc. erations of 1 kW GaN do not have the 2. https://en.wikipedia.org/wiki/Secondary_ ashx?Id=1235. same VSWR ruggedness as LDMOS, surveillance_radar. 11. G. F. Formicone and J. Custer, “Analysis which means that the protection isola- 3. V.A. Orlando, “The Mode S Beacon Radar of a GaN/SiC UHF Radar Amplifier for Operation at 125V Bias,” Proceedings of tor cannot be eliminated. However, the System,” The Lincoln laboratory Journal, pp. 3452362, Vol. 2, No. 3, 1989. European Microwave Conference, 6-11 VSWR issue can be fixed by improving September 2015, Paris, France.