Indian Journal of Natural Sciences www.tnsroindia.org.in ©IJONS Vol.10 / Issue 57 / December / 2019 International Bimonthly ISSN: 0976 – 0997 RESEARCH ARTICLE Error Detection and Correction Method for Timing Errors in Registers M.Revathy1*, PN.Sundararajan1 and M.Kasthuri2 1Associate Professor, Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. 2Assistant Professor Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. Received: 31 Aug 2019 Revised: 02 Oct 2019 Accepted: 04 Nov 2019 *Address for Correspondence M.Revathy Associate Professor, Department of ECE, PSNA College of Engineering and Technology, Dindigul, Tamilnadu, India. Email:
[email protected] This is an Open Access Journal / article distributed under the terms of the Creative Commons Attribution License (CC BY-NC-ND 3.0) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. All rights reserved. ABSTRACT Timing errors are an important concern in nanometer CMOS technologies. A promising way to overcome the timing errors is the development of error detection and correction techniques in registers. Normally timing failures occur in high complexity and high frequency integrated circuits. The reason behind this timing failures are test escapes, environmental conditions, operating conditions and process variations. A local error detection and correction technique is done in this work. It is based on a new bit flipping flip flop. Whenever a timing error is detected, it is corrected by complementing the output of the corresponding flip flop. The addition of a multiplexer and a NOT gate replaces the need of an extra latch and an EX-OR gate in the modified EDC technique.